1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
56 #include "i915_params.h"
58 #include "i915_utils.h"
60 #include "intel_bios.h"
61 #include "intel_device_info.h"
62 #include "intel_display.h"
63 #include "intel_dpll_mgr.h"
64 #include "intel_lrc.h"
65 #include "intel_opregion.h"
66 #include "intel_ringbuffer.h"
67 #include "intel_uncore.h"
68 #include "intel_wopcm.h"
72 #include "i915_gem_context.h"
73 #include "i915_gem_fence_reg.h"
74 #include "i915_gem_object.h"
75 #include "i915_gem_gtt.h"
76 #include "i915_gpu_error.h"
77 #include "i915_request.h"
78 #include "i915_scheduler.h"
79 #include "i915_timeline.h"
82 #include "intel_gvt.h"
84 /* General customization:
87 #define DRIVER_NAME "i915"
88 #define DRIVER_DESC "Intel Graphics"
89 #define DRIVER_DATE "20180830"
90 #define DRIVER_TIMESTAMP 1535639183
92 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
93 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
94 * which may not necessarily be a user visible problem. This will either
95 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
96 * enable distros and users to tailor their preferred amount of i915 abrt
99 #define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915_modparams.verbose_state_checks, format)) \
104 unlikely(__ret_warn_on); \
107 #define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
112 bool __i915_inject_load_failure(const char *func, int line);
113 #define i915_inject_load_failure() \
114 __i915_inject_load_failure(__func__, __LINE__)
116 bool i915_error_injected(void);
120 #define i915_inject_load_failure() false
121 #define i915_error_injected() false
125 #define i915_load_error(i915, fmt, ...) \
126 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
131 } uint_fixed_16_16_t;
133 #define FP_16_16_MAX ({ \
134 uint_fixed_16_16_t fp; \
139 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
146 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
148 uint_fixed_16_16_t fp;
150 WARN_ON(val > U16_MAX);
156 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
158 return DIV_ROUND_UP(fp.val, 1 << 16);
161 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
166 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
167 uint_fixed_16_16_t min2)
169 uint_fixed_16_16_t min;
171 min.val = min(min1.val, min2.val);
175 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
176 uint_fixed_16_16_t max2)
178 uint_fixed_16_16_t max;
180 max.val = max(max1.val, max2.val);
184 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
186 uint_fixed_16_16_t fp;
187 WARN_ON(val > U32_MAX);
188 fp.val = (uint32_t) val;
192 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
193 uint_fixed_16_16_t d)
195 return DIV_ROUND_UP(val.val, d.val);
198 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
199 uint_fixed_16_16_t mul)
201 uint64_t intermediate_val;
203 intermediate_val = (uint64_t) val * mul.val;
204 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
205 WARN_ON(intermediate_val > U32_MAX);
206 return (uint32_t) intermediate_val;
209 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
210 uint_fixed_16_16_t mul)
212 uint64_t intermediate_val;
214 intermediate_val = (uint64_t) val.val * mul.val;
215 intermediate_val = intermediate_val >> 16;
216 return clamp_u64_to_fixed16(intermediate_val);
219 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
223 interm_val = (uint64_t)val << 16;
224 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
225 return clamp_u64_to_fixed16(interm_val);
228 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
229 uint_fixed_16_16_t d)
233 interm_val = (uint64_t)val << 16;
234 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
235 WARN_ON(interm_val > U32_MAX);
236 return (uint32_t) interm_val;
239 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
240 uint_fixed_16_16_t mul)
242 uint64_t intermediate_val;
244 intermediate_val = (uint64_t) val * mul.val;
245 return clamp_u64_to_fixed16(intermediate_val);
248 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
249 uint_fixed_16_16_t add2)
253 interm_sum = (uint64_t) add1.val + add2.val;
254 return clamp_u64_to_fixed16(interm_sum);
257 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
261 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
263 interm_sum = (uint64_t) add1.val + interm_add2.val;
264 return clamp_u64_to_fixed16(interm_sum);
269 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
282 #define for_each_hpd_pin(__pin) \
283 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
285 #define HPD_STORM_DEFAULT_THRESHOLD 5
287 struct i915_hotplug {
288 struct work_struct hotplug_work;
291 unsigned long last_jiffies;
296 HPD_MARK_DISABLED = 2
298 } stats[HPD_NUM_PINS];
300 struct delayed_work reenable_work;
304 struct work_struct dig_port_work;
306 struct work_struct poll_init_work;
309 unsigned int hpd_storm_threshold;
312 * if we get a HPD irq from DP and a HPD irq from non-DP
313 * the non-DP HPD could block the workqueue on a mode config
314 * mutex getting, that userspace may have taken. However
315 * userspace is waiting on the DP workqueue to run which is
316 * blocked behind the non-DP one.
318 struct workqueue_struct *dp_wq;
321 #define I915_GEM_GPU_DOMAINS \
322 (I915_GEM_DOMAIN_RENDER | \
323 I915_GEM_DOMAIN_SAMPLER | \
324 I915_GEM_DOMAIN_COMMAND | \
325 I915_GEM_DOMAIN_INSTRUCTION | \
326 I915_GEM_DOMAIN_VERTEX)
328 struct drm_i915_private;
329 struct i915_mm_struct;
330 struct i915_mmu_object;
332 struct drm_i915_file_private {
333 struct drm_i915_private *dev_priv;
334 struct drm_file *file;
338 struct list_head request_list;
339 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
340 * chosen to prevent the CPU getting more than a frame ahead of the GPU
341 * (when using lax throttling for the frontbuffer). We also use it to
342 * offer free GPU waitboosts for severely congested workloads.
344 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
346 struct idr context_idr;
348 struct intel_rps_client {
352 unsigned int bsd_engine;
355 * Every context ban increments per client ban score. Also
356 * hangs in short succession increments ban score. If ban threshold
357 * is reached, client is considered banned and submitting more work
358 * will fail. This is a stop gap measure to limit the badly behaving
359 * clients access to gpu. Note that unbannable contexts never increment
360 * the client ban score.
362 #define I915_CLIENT_SCORE_HANG_FAST 1
363 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
364 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
365 #define I915_CLIENT_SCORE_BANNED 9
366 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
368 unsigned long hang_timestamp;
371 /* Interface history:
374 * 1.2: Add Power Management
375 * 1.3: Add vblank support
376 * 1.4: Fix cmdbuffer path, add heap destroy
377 * 1.5: Add vblank pipe configuration
378 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
379 * - Support vertical blank on secondary display pipe
381 #define DRIVER_MAJOR 1
382 #define DRIVER_MINOR 6
383 #define DRIVER_PATCHLEVEL 0
385 struct intel_overlay;
386 struct intel_overlay_error_state;
388 struct sdvo_device_mapping {
397 struct intel_connector;
398 struct intel_encoder;
399 struct intel_atomic_state;
400 struct intel_crtc_state;
401 struct intel_initial_plane_config;
405 struct intel_cdclk_state;
407 struct drm_i915_display_funcs {
408 void (*get_cdclk)(struct drm_i915_private *dev_priv,
409 struct intel_cdclk_state *cdclk_state);
410 void (*set_cdclk)(struct drm_i915_private *dev_priv,
411 const struct intel_cdclk_state *cdclk_state);
412 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
413 enum i9xx_plane_id i9xx_plane);
414 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
415 int (*compute_intermediate_wm)(struct drm_device *dev,
416 struct intel_crtc *intel_crtc,
417 struct intel_crtc_state *newstate);
418 void (*initial_watermarks)(struct intel_atomic_state *state,
419 struct intel_crtc_state *cstate);
420 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
421 struct intel_crtc_state *cstate);
422 void (*optimize_watermarks)(struct intel_atomic_state *state,
423 struct intel_crtc_state *cstate);
424 int (*compute_global_watermarks)(struct drm_atomic_state *state);
425 void (*update_wm)(struct intel_crtc *crtc);
426 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
427 /* Returns the active state of the crtc, and if the crtc is active,
428 * fills out the pipe-config with the hw state. */
429 bool (*get_pipe_config)(struct intel_crtc *,
430 struct intel_crtc_state *);
431 void (*get_initial_plane_config)(struct intel_crtc *,
432 struct intel_initial_plane_config *);
433 int (*crtc_compute_clock)(struct intel_crtc *crtc,
434 struct intel_crtc_state *crtc_state);
435 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
436 struct drm_atomic_state *old_state);
437 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
438 struct drm_atomic_state *old_state);
439 void (*update_crtcs)(struct drm_atomic_state *state);
440 void (*audio_codec_enable)(struct intel_encoder *encoder,
441 const struct intel_crtc_state *crtc_state,
442 const struct drm_connector_state *conn_state);
443 void (*audio_codec_disable)(struct intel_encoder *encoder,
444 const struct intel_crtc_state *old_crtc_state,
445 const struct drm_connector_state *old_conn_state);
446 void (*fdi_link_train)(struct intel_crtc *crtc,
447 const struct intel_crtc_state *crtc_state);
448 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
449 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
450 /* clock updates for mode set */
452 /* render clock increase/decrease */
453 /* display clock increase/decrease */
454 /* pll clock increase/decrease */
456 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
457 void (*load_luts)(struct drm_crtc_state *crtc_state);
460 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
461 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
462 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
465 struct work_struct work;
467 uint32_t *dmc_payload;
468 uint32_t dmc_fw_size;
471 i915_reg_t mmioaddr[8];
472 uint32_t mmiodata[8];
474 uint32_t allowed_dc_mask;
477 enum i915_cache_level {
479 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
480 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
481 caches, eg sampler/render caches, and the
482 large Last-Level-Cache. LLC is coherent with
483 the CPU, but L3 is only visible to the GPU. */
484 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
487 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
498 /* This is always the inner lock when overlapping with struct_mutex and
499 * it's the outer lock when overlapping with stolen_lock. */
502 unsigned int possible_framebuffer_bits;
503 unsigned int busy_bits;
504 unsigned int visible_pipes_mask;
505 struct intel_crtc *crtc;
507 struct drm_mm_node compressed_fb;
508 struct drm_mm_node *compressed_llb;
516 bool underrun_detected;
517 struct work_struct underrun_work;
520 * Due to the atomic rules we can't access some structures without the
521 * appropriate locking, so we cache information here in order to avoid
524 struct intel_fbc_state_cache {
525 struct i915_vma *vma;
529 unsigned int mode_flags;
530 uint32_t hsw_bdw_pixel_rate;
534 unsigned int rotation;
539 * Display surface base address adjustement for
540 * pageflips. Note that on gen4+ this only adjusts up
541 * to a tile, offsets within a tile are handled in
542 * the hw itself (with the TILEOFF register).
551 const struct drm_format_info *format;
557 * This structure contains everything that's relevant to program the
558 * hardware registers. When we want to figure out if we need to disable
559 * and re-enable FBC for a new configuration we just check if there's
560 * something different in the struct. The genx_fbc_activate functions
561 * are supposed to read from it in order to program the registers.
563 struct intel_fbc_reg_params {
564 struct i915_vma *vma;
569 enum i9xx_plane_id i9xx_plane;
570 unsigned int fence_y_offset;
574 const struct drm_format_info *format;
579 unsigned int gen9_wa_cfb_stride;
582 const char *no_fbc_reason;
586 * HIGH_RR is the highest eDP panel refresh rate read from EDID
587 * LOW_RR is the lowest eDP panel refresh rate found from EDID
588 * parsing for same resolution.
590 enum drrs_refresh_rate_type {
593 DRRS_MAX_RR, /* RR count */
596 enum drrs_support_type {
597 DRRS_NOT_SUPPORTED = 0,
598 STATIC_DRRS_SUPPORT = 1,
599 SEAMLESS_DRRS_SUPPORT = 2
605 struct delayed_work work;
607 unsigned busy_frontbuffer_bits;
608 enum drrs_refresh_rate_type refresh_rate_type;
609 enum drrs_support_type type;
615 #define I915_PSR_DEBUG_MODE_MASK 0x0f
616 #define I915_PSR_DEBUG_DEFAULT 0x00
617 #define I915_PSR_DEBUG_DISABLE 0x01
618 #define I915_PSR_DEBUG_ENABLE 0x02
619 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
620 #define I915_PSR_DEBUG_IRQ 0x10
624 bool prepared, enabled;
627 struct work_struct work;
628 unsigned busy_frontbuffer_bits;
629 bool sink_psr2_support;
631 bool colorimetry_support;
634 u8 sink_sync_latency;
635 ktime_t last_entry_attempt;
640 PCH_NONE = 0, /* No PCH present */
641 PCH_IBX, /* Ibexpeak PCH */
642 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
643 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
644 PCH_SPT, /* Sunrisepoint PCH */
645 PCH_KBP, /* Kaby Lake PCH */
646 PCH_CNP, /* Cannon Lake PCH */
647 PCH_ICP, /* Ice Lake PCH */
648 PCH_NOP, /* PCH without south display */
651 enum intel_sbi_destination {
656 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
657 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
658 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
659 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
660 #define QUIRK_INCREASE_T12_DELAY (1<<6)
661 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
664 struct intel_fbc_work;
667 struct i2c_adapter adapter;
668 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
672 struct i2c_algo_bit_data bit_algo;
673 struct drm_i915_private *dev_priv;
676 struct i915_suspend_saved_registers {
679 u32 saveCACHE_MODE_0;
680 u32 saveMI_ARB_STATE;
684 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
685 u32 savePCH_PORT_HOTPLUG;
689 struct vlv_s0ix_state {
696 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
697 u32 media_max_req_count;
698 u32 gfx_max_req_count;
730 /* Display 1 CZ domain */
735 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
737 /* GT SA CZ domain */
744 /* Display 2 CZ domain */
751 struct intel_rps_ei {
759 * work, interrupts_enabled and pm_iir are protected by
762 struct work_struct work;
763 bool interrupts_enabled;
766 /* PM interrupt bits that should never be masked */
769 /* Frequencies are stored in potentially platform dependent multiples.
770 * In other words, *_freq needs to be multiplied by X to be interesting.
771 * Soft limits are those which are used for the dynamic reclocking done
772 * by the driver (raise frequencies under heavy loads, and lower for
773 * lighter loads). Hard limits are those imposed by the hardware.
775 * A distinction is made for overclocking, which is never enabled by
776 * default, and is considered to be above the hard limit if it's
779 u8 cur_freq; /* Current frequency (cached, may not == HW) */
780 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
781 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
782 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
783 u8 min_freq; /* AKA RPn. Minimum frequency */
784 u8 boost_freq; /* Frequency to request when wait boosting */
785 u8 idle_freq; /* Frequency to request when we are idle */
786 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
787 u8 rp1_freq; /* "less than" RP0 power/freqency */
788 u8 rp0_freq; /* Non-overclocked max frequency. */
789 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
796 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
797 unsigned int interactive;
799 u8 up_threshold; /* Current %busy required to uplock */
800 u8 down_threshold; /* Current %busy required to downclock */
804 atomic_t num_waiters;
807 /* manual wa residency calculations */
808 struct intel_rps_ei ei;
813 u64 prev_hw_residency[4];
814 u64 cur_residency[4];
817 struct intel_llc_pstate {
821 struct intel_gen6_power_mgmt {
822 struct intel_rps rps;
823 struct intel_rc6 rc6;
824 struct intel_llc_pstate llc_pstate;
827 /* defined intel_pm.c */
828 extern spinlock_t mchdev_lock;
830 struct intel_ilk_power_mgmt {
838 unsigned long last_time1;
839 unsigned long chipset_power;
842 unsigned long gfx_power;
849 struct drm_i915_private;
850 struct i915_power_well;
852 struct i915_power_well_ops {
854 * Synchronize the well's hw state to match the current sw state, for
855 * example enable/disable it based on the current refcount. Called
856 * during driver init and resume time, possibly after first calling
857 * the enable/disable handlers.
859 void (*sync_hw)(struct drm_i915_private *dev_priv,
860 struct i915_power_well *power_well);
862 * Enable the well and resources that depend on it (for example
863 * interrupts located on the well). Called after the 0->1 refcount
866 void (*enable)(struct drm_i915_private *dev_priv,
867 struct i915_power_well *power_well);
869 * Disable the well and resources that depend on it. Called after
870 * the 1->0 refcount transition.
872 void (*disable)(struct drm_i915_private *dev_priv,
873 struct i915_power_well *power_well);
874 /* Returns the hw enabled state. */
875 bool (*is_enabled)(struct drm_i915_private *dev_priv,
876 struct i915_power_well *power_well);
879 struct i915_power_well_regs {
886 /* Power well structure for haswell */
887 struct i915_power_well_desc {
891 /* unique identifier for this power well */
892 enum i915_power_well_id id;
894 * Arbitraty data associated with this power well. Platform and power
900 * request/status flag index in the PUNIT power well
901 * control/status registers.
909 const struct i915_power_well_regs *regs;
911 * request/status flag index in the power well
912 * constrol/status registers.
915 /* Mask of pipes whose IRQ logic is backed by the pw */
917 /* The pw is backing the VGA functionality */
922 const struct i915_power_well_ops *ops;
925 struct i915_power_well {
926 const struct i915_power_well_desc *desc;
927 /* power well enable/disable usage count */
929 /* cached hw enabled state */
933 struct i915_power_domains {
935 * Power wells needed for initialization at driver init and suspend
936 * time are on. They are kept on until after the first modeset.
939 bool display_core_suspended;
940 int power_well_count;
943 int domain_use_count[POWER_DOMAIN_NUM];
944 struct i915_power_well *power_wells;
947 #define MAX_L3_SLICES 2
948 struct intel_l3_parity {
949 u32 *remap_info[MAX_L3_SLICES];
950 struct work_struct error_work;
955 /** Memory allocator for GTT stolen memory */
956 struct drm_mm stolen;
957 /** Protects the usage of the GTT stolen memory allocator. This is
958 * always the inner lock when overlapping with struct_mutex. */
959 struct mutex stolen_lock;
961 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
964 /** List of all objects in gtt_space. Used to restore gtt
965 * mappings on resume */
966 struct list_head bound_list;
968 * List of objects which are not bound to the GTT (thus
969 * are idle and not used by the GPU). These objects may or may
970 * not actually have any pages attached.
972 struct list_head unbound_list;
974 /** List of all objects in gtt_space, currently mmaped by userspace.
975 * All objects within this list must also be on bound_list.
977 struct list_head userfault_list;
980 * List of objects which are pending destruction.
982 struct llist_head free_list;
983 struct work_struct free_work;
984 spinlock_t free_lock;
986 * Count of objects pending destructions. Used to skip needlessly
987 * waiting on an RCU barrier if no objects are waiting to be freed.
992 * Small stash of WC pages
994 struct pagestash wc_stash;
997 * tmpfs instance used for shmem backed objects
999 struct vfsmount *gemfs;
1001 /** PPGTT used for aliasing the PPGTT with the GTT */
1002 struct i915_hw_ppgtt *aliasing_ppgtt;
1004 struct notifier_block oom_notifier;
1005 struct notifier_block vmap_notifier;
1006 struct shrinker shrinker;
1008 /** LRU list of objects with fence regs on them. */
1009 struct list_head fence_list;
1012 * Workqueue to fault in userptr pages, flushed by the execbuf
1013 * when required but otherwise left to userspace to try again
1016 struct workqueue_struct *userptr_wq;
1018 u64 unordered_timeline;
1020 /* the indicator for dispatch video commands on two BSD rings */
1021 atomic_t bsd_engine_dispatch_index;
1023 /** Bit 6 swizzling required for X tiling */
1024 uint32_t bit_6_swizzle_x;
1025 /** Bit 6 swizzling required for Y tiling */
1026 uint32_t bit_6_swizzle_y;
1028 /* accounting, useful for userland debugging */
1029 spinlock_t object_stat_lock;
1034 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
1036 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1037 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1039 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1040 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1042 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
1044 #define DP_AUX_A 0x40
1045 #define DP_AUX_B 0x10
1046 #define DP_AUX_C 0x20
1047 #define DP_AUX_D 0x30
1048 #define DP_AUX_E 0x50
1049 #define DP_AUX_F 0x60
1051 #define DDC_PIN_B 0x05
1052 #define DDC_PIN_C 0x04
1053 #define DDC_PIN_D 0x06
1055 struct ddi_vbt_port_info {
1059 * This is an index in the HDMI/DVI DDI buffer translation table.
1060 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1061 * populate this field.
1063 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1064 uint8_t hdmi_level_shift;
1066 uint8_t supports_dvi:1;
1067 uint8_t supports_hdmi:1;
1068 uint8_t supports_dp:1;
1069 uint8_t supports_edp:1;
1071 uint8_t alternate_aux_channel;
1072 uint8_t alternate_ddc_pin;
1074 uint8_t dp_boost_level;
1075 uint8_t hdmi_boost_level;
1076 int dp_max_link_rate; /* 0 for not limited by VBT */
1079 enum psr_lines_to_wait {
1080 PSR_0_LINES_TO_WAIT = 0,
1082 PSR_4_LINES_TO_WAIT,
1086 struct intel_vbt_data {
1087 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1088 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1091 unsigned int int_tv_support:1;
1092 unsigned int lvds_dither:1;
1093 unsigned int int_crt_support:1;
1094 unsigned int lvds_use_ssc:1;
1095 unsigned int int_lvds_support:1;
1096 unsigned int display_clock_mode:1;
1097 unsigned int fdi_rx_polarity_inverted:1;
1098 unsigned int panel_type:4;
1100 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1102 enum drrs_support_type drrs_type;
1112 struct edp_power_seq pps;
1118 bool require_aux_wakeup;
1120 enum psr_lines_to_wait lines_to_wait;
1121 int tp1_wakeup_time_us;
1122 int tp2_tp3_wakeup_time_us;
1128 bool active_low_pwm;
1129 u8 min_brightness; /* min_brightness/255 of max */
1130 u8 controller; /* brightness controller number */
1131 enum intel_backlight_type type;
1137 struct mipi_config *config;
1138 struct mipi_pps_data *pps;
1144 const u8 *sequence[MIPI_SEQ_MAX];
1145 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1151 struct child_device_config *child_dev;
1153 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1154 struct sdvo_device_mapping sdvo_mappings[2];
1157 enum intel_ddb_partitioning {
1159 INTEL_DDB_PART_5_6, /* IVB+ */
1162 struct intel_wm_level {
1170 struct ilk_wm_values {
1171 uint32_t wm_pipe[3];
1173 uint32_t wm_lp_spr[3];
1174 uint32_t wm_linetime[3];
1176 enum intel_ddb_partitioning partitioning;
1179 struct g4x_pipe_wm {
1180 uint16_t plane[I915_MAX_PLANES];
1190 struct vlv_wm_ddl_values {
1191 uint8_t plane[I915_MAX_PLANES];
1194 struct vlv_wm_values {
1195 struct g4x_pipe_wm pipe[3];
1196 struct g4x_sr_wm sr;
1197 struct vlv_wm_ddl_values ddl[3];
1202 struct g4x_wm_values {
1203 struct g4x_pipe_wm pipe[2];
1204 struct g4x_sr_wm sr;
1205 struct g4x_sr_wm hpll;
1211 struct skl_ddb_entry {
1212 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1215 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1217 return entry->end - entry->start;
1220 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1221 const struct skl_ddb_entry *e2)
1223 if (e1->start == e2->start && e1->end == e2->end)
1229 struct skl_ddb_allocation {
1231 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1232 struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1233 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1236 struct skl_ddb_values {
1237 unsigned dirty_pipes;
1238 struct skl_ddb_allocation ddb;
1241 struct skl_wm_level {
1243 uint16_t plane_res_b;
1244 uint8_t plane_res_l;
1247 /* Stores plane specific WM parameters */
1248 struct skl_wm_params {
1249 bool x_tiled, y_tiled;
1254 uint32_t plane_pixel_rate;
1255 uint32_t y_min_scanlines;
1256 uint32_t plane_bytes_per_line;
1257 uint_fixed_16_16_t plane_blocks_per_line;
1258 uint_fixed_16_16_t y_tile_minimum;
1259 uint32_t linetime_us;
1260 uint32_t dbuf_block_size;
1264 * This struct helps tracking the state needed for runtime PM, which puts the
1265 * device in PCI D3 state. Notice that when this happens, nothing on the
1266 * graphics device works, even register access, so we don't get interrupts nor
1269 * Every piece of our code that needs to actually touch the hardware needs to
1270 * either call intel_runtime_pm_get or call intel_display_power_get with the
1271 * appropriate power domain.
1273 * Our driver uses the autosuspend delay feature, which means we'll only really
1274 * suspend if we stay with zero refcount for a certain amount of time. The
1275 * default value is currently very conservative (see intel_runtime_pm_enable), but
1276 * it can be changed with the standard runtime PM files from sysfs.
1278 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1279 * goes back to false exactly before we reenable the IRQs. We use this variable
1280 * to check if someone is trying to enable/disable IRQs while they're supposed
1281 * to be disabled. This shouldn't happen and we'll print some error messages in
1284 * For more, read the Documentation/power/runtime_pm.txt.
1286 struct i915_runtime_pm {
1287 atomic_t wakeref_count;
1292 enum intel_pipe_crc_source {
1293 INTEL_PIPE_CRC_SOURCE_NONE,
1294 INTEL_PIPE_CRC_SOURCE_PLANE1,
1295 INTEL_PIPE_CRC_SOURCE_PLANE2,
1296 INTEL_PIPE_CRC_SOURCE_PF,
1297 INTEL_PIPE_CRC_SOURCE_PIPE,
1298 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1299 INTEL_PIPE_CRC_SOURCE_TV,
1300 INTEL_PIPE_CRC_SOURCE_DP_B,
1301 INTEL_PIPE_CRC_SOURCE_DP_C,
1302 INTEL_PIPE_CRC_SOURCE_DP_D,
1303 INTEL_PIPE_CRC_SOURCE_AUTO,
1304 INTEL_PIPE_CRC_SOURCE_MAX,
1307 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1308 struct intel_pipe_crc {
1311 enum intel_pipe_crc_source source;
1314 struct i915_frontbuffer_tracking {
1318 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1325 struct i915_wa_reg {
1328 /* bitmask representing WA bits */
1332 #define I915_MAX_WA_REGS 16
1334 struct i915_workarounds {
1335 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1339 struct i915_virtual_gpu {
1344 /* used in computing the new watermarks state */
1345 struct intel_wm_config {
1346 unsigned int num_pipes_active;
1347 bool sprites_enabled;
1348 bool sprites_scaled;
1351 struct i915_oa_format {
1356 struct i915_oa_reg {
1361 struct i915_oa_config {
1362 char uuid[UUID_STRING_LEN + 1];
1365 const struct i915_oa_reg *mux_regs;
1367 const struct i915_oa_reg *b_counter_regs;
1368 u32 b_counter_regs_len;
1369 const struct i915_oa_reg *flex_regs;
1372 struct attribute_group sysfs_metric;
1373 struct attribute *attrs[2];
1374 struct device_attribute sysfs_metric_id;
1379 struct i915_perf_stream;
1382 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1384 struct i915_perf_stream_ops {
1386 * @enable: Enables the collection of HW samples, either in response to
1387 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1388 * without `I915_PERF_FLAG_DISABLED`.
1390 void (*enable)(struct i915_perf_stream *stream);
1393 * @disable: Disables the collection of HW samples, either in response
1394 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1397 void (*disable)(struct i915_perf_stream *stream);
1400 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1401 * once there is something ready to read() for the stream
1403 void (*poll_wait)(struct i915_perf_stream *stream,
1408 * @wait_unlocked: For handling a blocking read, wait until there is
1409 * something to ready to read() for the stream. E.g. wait on the same
1410 * wait queue that would be passed to poll_wait().
1412 int (*wait_unlocked)(struct i915_perf_stream *stream);
1415 * @read: Copy buffered metrics as records to userspace
1416 * **buf**: the userspace, destination buffer
1417 * **count**: the number of bytes to copy, requested by userspace
1418 * **offset**: zero at the start of the read, updated as the read
1419 * proceeds, it represents how many bytes have been copied so far and
1420 * the buffer offset for copying the next record.
1422 * Copy as many buffered i915 perf samples and records for this stream
1423 * to userspace as will fit in the given buffer.
1425 * Only write complete records; returning -%ENOSPC if there isn't room
1426 * for a complete record.
1428 * Return any error condition that results in a short read such as
1429 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1430 * returning to userspace.
1432 int (*read)(struct i915_perf_stream *stream,
1438 * @destroy: Cleanup any stream specific resources.
1440 * The stream will always be disabled before this is called.
1442 void (*destroy)(struct i915_perf_stream *stream);
1446 * struct i915_perf_stream - state for a single open stream FD
1448 struct i915_perf_stream {
1450 * @dev_priv: i915 drm device
1452 struct drm_i915_private *dev_priv;
1455 * @link: Links the stream into ``&drm_i915_private->streams``
1457 struct list_head link;
1460 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1461 * properties given when opening a stream, representing the contents
1462 * of a single sample as read() by userspace.
1467 * @sample_size: Considering the configured contents of a sample
1468 * combined with the required header size, this is the total size
1469 * of a single sample record.
1474 * @ctx: %NULL if measuring system-wide across all contexts or a
1475 * specific context that is being monitored.
1477 struct i915_gem_context *ctx;
1480 * @enabled: Whether the stream is currently enabled, considering
1481 * whether the stream was opened in a disabled state and based
1482 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1487 * @ops: The callbacks providing the implementation of this specific
1488 * type of configured stream.
1490 const struct i915_perf_stream_ops *ops;
1493 * @oa_config: The OA configuration used by the stream.
1495 struct i915_oa_config *oa_config;
1499 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1501 struct i915_oa_ops {
1503 * @is_valid_b_counter_reg: Validates register's address for
1504 * programming boolean counters for a particular platform.
1506 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1510 * @is_valid_mux_reg: Validates register's address for programming mux
1511 * for a particular platform.
1513 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1516 * @is_valid_flex_reg: Validates register's address for programming
1517 * flex EU filtering for a particular platform.
1519 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1522 * @init_oa_buffer: Resets the head and tail pointers of the
1523 * circular buffer for periodic OA reports.
1525 * Called when first opening a stream for OA metrics, but also may be
1526 * called in response to an OA buffer overflow or other error
1529 * Note it may be necessary to clear the full OA buffer here as part of
1530 * maintaining the invariable that new reports must be written to
1531 * zeroed memory for us to be able to reliable detect if an expected
1532 * report has not yet landed in memory. (At least on Haswell the OA
1533 * buffer tail pointer is not synchronized with reports being visible
1536 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1539 * @enable_metric_set: Selects and applies any MUX configuration to set
1540 * up the Boolean and Custom (B/C) counters that are part of the
1541 * counter reports being sampled. May apply system constraints such as
1542 * disabling EU clock gating as required.
1544 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1545 const struct i915_oa_config *oa_config);
1548 * @disable_metric_set: Remove system constraints associated with using
1551 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1554 * @oa_enable: Enable periodic sampling
1556 void (*oa_enable)(struct drm_i915_private *dev_priv);
1559 * @oa_disable: Disable periodic sampling
1561 void (*oa_disable)(struct drm_i915_private *dev_priv);
1564 * @read: Copy data from the circular OA buffer into a given userspace
1567 int (*read)(struct i915_perf_stream *stream,
1573 * @oa_hw_tail_read: read the OA tail pointer register
1575 * In particular this enables us to share all the fiddly code for
1576 * handling the OA unit tail pointer race that affects multiple
1579 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1582 struct intel_cdclk_state {
1583 unsigned int cdclk, vco, ref, bypass;
1587 struct drm_i915_private {
1588 struct drm_device drm;
1590 struct kmem_cache *objects;
1591 struct kmem_cache *vmas;
1592 struct kmem_cache *luts;
1593 struct kmem_cache *requests;
1594 struct kmem_cache *dependencies;
1595 struct kmem_cache *priorities;
1597 const struct intel_device_info info;
1598 struct intel_driver_caps caps;
1601 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1602 * end of stolen which we can optionally use to create GEM objects
1603 * backed by stolen memory. Note that stolen_usable_size tells us
1604 * exactly how much of this we are actually allowed to use, given that
1605 * some portion of it is in fact reserved for use by hardware functions.
1607 struct resource dsm;
1609 * Reseved portion of Data Stolen Memory
1611 struct resource dsm_reserved;
1614 * Stolen memory is segmented in hardware with different portions
1615 * offlimits to certain functions.
1617 * The drm_mm is initialised to the total accessible range, as found
1618 * from the PCI config. On Broadwell+, this is further restricted to
1619 * avoid the first page! The upper end of stolen memory is reserved for
1620 * hardware functions and similarly removed from the accessible range.
1622 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1626 struct intel_uncore uncore;
1628 struct i915_virtual_gpu vgpu;
1630 struct intel_gvt *gvt;
1632 struct intel_wopcm wopcm;
1634 struct intel_huc huc;
1635 struct intel_guc guc;
1637 struct intel_csr csr;
1639 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1641 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1642 * controller on different i2c buses. */
1643 struct mutex gmbus_mutex;
1646 * Base address of where the gmbus and gpio blocks are located (either
1647 * on PCH or on SoC for platforms without PCH).
1649 uint32_t gpio_mmio_base;
1651 /* MMIO base address for MIPI regs */
1652 uint32_t mipi_mmio_base;
1654 uint32_t psr_mmio_base;
1656 uint32_t pps_mmio_base;
1658 wait_queue_head_t gmbus_wait_queue;
1660 struct pci_dev *bridge_dev;
1661 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1662 /* Context used internally to idle the GPU and setup initial state */
1663 struct i915_gem_context *kernel_context;
1664 /* Context only to be used for injecting preemption commands */
1665 struct i915_gem_context *preempt_context;
1666 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1667 [MAX_ENGINE_INSTANCE + 1];
1669 struct drm_dma_handle *status_page_dmah;
1670 struct resource mch_res;
1672 /* protects the irq masks */
1673 spinlock_t irq_lock;
1675 bool display_irqs_enabled;
1677 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1678 struct pm_qos_request pm_qos;
1680 /* Sideband mailbox protection */
1681 struct mutex sb_lock;
1683 /** Cached value of IMR to avoid reads in updating the bitfield */
1686 u32 de_irq_mask[I915_MAX_PIPES];
1693 u32 pipestat_irq_mask[I915_MAX_PIPES];
1695 struct i915_hotplug hotplug;
1696 struct intel_fbc fbc;
1697 struct i915_drrs drrs;
1698 struct intel_opregion opregion;
1699 struct intel_vbt_data vbt;
1701 bool preserve_bios_swizzle;
1704 struct intel_overlay *overlay;
1706 /* backlight registers and fields in struct intel_panel */
1707 struct mutex backlight_lock;
1710 bool no_aux_handshake;
1712 /* protects panel power sequencer state */
1713 struct mutex pps_mutex;
1715 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1716 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1718 unsigned int fsb_freq, mem_freq, is_ddr3;
1719 unsigned int skl_preferred_vco_freq;
1720 unsigned int max_cdclk_freq;
1722 unsigned int max_dotclk_freq;
1723 unsigned int rawclk_freq;
1724 unsigned int hpll_freq;
1725 unsigned int fdi_pll_freq;
1726 unsigned int czclk_freq;
1730 * The current logical cdclk state.
1731 * See intel_atomic_state.cdclk.logical
1733 * For reading holding any crtc lock is sufficient,
1734 * for writing must hold all of them.
1736 struct intel_cdclk_state logical;
1738 * The current actual cdclk state.
1739 * See intel_atomic_state.cdclk.actual
1741 struct intel_cdclk_state actual;
1742 /* The current hardware cdclk state */
1743 struct intel_cdclk_state hw;
1747 * wq - Driver workqueue for GEM.
1749 * NOTE: Work items scheduled here are not allowed to grab any modeset
1750 * locks, for otherwise the flushing done in the pageflip code will
1751 * result in deadlocks.
1753 struct workqueue_struct *wq;
1755 /* ordered wq for modesets */
1756 struct workqueue_struct *modeset_wq;
1758 /* Display functions */
1759 struct drm_i915_display_funcs display;
1761 /* PCH chipset type */
1762 enum intel_pch pch_type;
1763 unsigned short pch_id;
1765 unsigned long quirks;
1767 struct drm_atomic_state *modeset_restore_state;
1768 struct drm_modeset_acquire_ctx reset_ctx;
1770 struct i915_ggtt ggtt; /* VM representing the global address space */
1772 struct i915_gem_mm mm;
1773 DECLARE_HASHTABLE(mm_structs, 7);
1774 struct mutex mm_lock;
1776 struct intel_ppat ppat;
1778 /* Kernel Modesetting */
1780 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1781 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1783 #ifdef CONFIG_DEBUG_FS
1784 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1787 /* dpll and cdclk state is protected by connection_mutex */
1788 int num_shared_dpll;
1789 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1790 const struct intel_dpll_mgr *dpll_mgr;
1793 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1794 * Must be global rather than per dpll, because on some platforms
1795 * plls share registers.
1797 struct mutex dpll_lock;
1799 unsigned int active_crtcs;
1800 /* minimum acceptable cdclk for each pipe */
1801 int min_cdclk[I915_MAX_PIPES];
1802 /* minimum acceptable voltage level for each pipe */
1803 u8 min_voltage_level[I915_MAX_PIPES];
1805 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1807 struct i915_workarounds workarounds;
1809 struct i915_frontbuffer_tracking fb_tracking;
1811 struct intel_atomic_helper {
1812 struct llist_head free_list;
1813 struct work_struct free_work;
1818 bool mchbar_need_disable;
1820 struct intel_l3_parity l3_parity;
1822 /* Cannot be determined by PCIID. You must always read a register. */
1826 * Protects RPS/RC6 register access and PCU communication.
1827 * Must be taken after struct_mutex if nested. Note that
1828 * this lock may be held for long periods of time when
1829 * talking to hw - so only take it when talking to hw!
1831 struct mutex pcu_lock;
1833 /* gen6+ GT PM state */
1834 struct intel_gen6_power_mgmt gt_pm;
1836 /* ilk-only ips/rps state. Everything in here is protected by the global
1837 * mchdev_lock in intel_pm.c */
1838 struct intel_ilk_power_mgmt ips;
1840 struct i915_power_domains power_domains;
1842 struct i915_psr psr;
1844 struct i915_gpu_error gpu_error;
1846 struct drm_i915_gem_object *vlv_pctx;
1848 /* list of fbdev register on this device */
1849 struct intel_fbdev *fbdev;
1850 struct work_struct fbdev_suspend_work;
1852 struct drm_property *broadcast_rgb_property;
1853 struct drm_property *force_audio_property;
1855 /* hda/i915 audio component */
1856 struct i915_audio_component *audio_component;
1857 bool audio_component_registered;
1859 * av_mutex - mutex for audio/video sync
1862 struct mutex av_mutex;
1865 struct list_head list;
1866 struct llist_head free_list;
1867 struct work_struct free_work;
1869 /* The hw wants to have a stable context identifier for the
1870 * lifetime of the context (for OA, PASID, faults, etc).
1871 * This is limited in execlists to 21 bits.
1874 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1875 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1876 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1881 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1882 u32 chv_phy_control;
1884 * Shadows for CHV DPLL_MD regs to keep the state
1885 * checker somewhat working in the presence hardware
1886 * crappiness (can't read out DPLL_MD for pipes B & C).
1888 u32 chv_dpll_md[I915_MAX_PIPES];
1892 bool power_domains_suspended;
1893 struct i915_suspend_saved_registers regfile;
1894 struct vlv_s0ix_state vlv_s0ix_state;
1897 I915_SAGV_UNKNOWN = 0,
1900 I915_SAGV_NOT_CONTROLLED
1905 * Raw watermark latency values:
1906 * in 0.1us units for WM0,
1907 * in 0.5us units for WM1+.
1910 uint16_t pri_latency[5];
1912 uint16_t spr_latency[5];
1914 uint16_t cur_latency[5];
1916 * Raw watermark memory latency values
1917 * for SKL for all 8 levels
1920 uint16_t skl_latency[8];
1922 /* current hardware state */
1924 struct ilk_wm_values hw;
1925 struct skl_ddb_values skl_hw;
1926 struct vlv_wm_values vlv;
1927 struct g4x_wm_values g4x;
1933 * Should be held around atomic WM register writing; also
1934 * protects * intel_crtc->wm.active and
1935 * cstate->wm.need_postvbl_update.
1937 struct mutex wm_mutex;
1940 * Set during HW readout of watermarks/DDB. Some platforms
1941 * need to know when we're still using BIOS-provided values
1942 * (which we don't fully trust).
1944 bool distrust_bios_wm;
1947 struct i915_runtime_pm runtime_pm;
1952 struct kobject *metrics_kobj;
1953 struct ctl_table_header *sysctl_header;
1956 * Lock associated with adding/modifying/removing OA configs
1957 * in dev_priv->perf.metrics_idr.
1959 struct mutex metrics_lock;
1962 * List of dynamic configurations, you need to hold
1963 * dev_priv->perf.metrics_lock to access it.
1965 struct idr metrics_idr;
1968 * Lock associated with anything below within this structure
1969 * except exclusive_stream.
1972 struct list_head streams;
1976 * The stream currently using the OA unit. If accessed
1977 * outside a syscall associated to its file
1978 * descriptor, you need to hold
1979 * dev_priv->drm.struct_mutex.
1981 struct i915_perf_stream *exclusive_stream;
1983 struct intel_context *pinned_ctx;
1984 u32 specific_ctx_id;
1985 u32 specific_ctx_id_mask;
1987 struct hrtimer poll_check_timer;
1988 wait_queue_head_t poll_wq;
1992 * For rate limiting any notifications of spurious
1993 * invalid OA reports
1995 struct ratelimit_state spurious_report_rs;
1998 int period_exponent;
2000 struct i915_oa_config test_config;
2003 struct i915_vma *vma;
2010 * Locks reads and writes to all head/tail state
2012 * Consider: the head and tail pointer state
2013 * needs to be read consistently from a hrtimer
2014 * callback (atomic context) and read() fop
2015 * (user context) with tail pointer updates
2016 * happening in atomic context and head updates
2017 * in user context and the (unlikely)
2018 * possibility of read() errors needing to
2019 * reset all head/tail state.
2021 * Note: Contention or performance aren't
2022 * currently a significant concern here
2023 * considering the relatively low frequency of
2024 * hrtimer callbacks (5ms period) and that
2025 * reads typically only happen in response to a
2026 * hrtimer event and likely complete before the
2029 * Note: This lock is not held *while* reading
2030 * and copying data to userspace so the value
2031 * of head observed in htrimer callbacks won't
2032 * represent any partial consumption of data.
2034 spinlock_t ptr_lock;
2037 * One 'aging' tail pointer and one 'aged'
2038 * tail pointer ready to used for reading.
2040 * Initial values of 0xffffffff are invalid
2041 * and imply that an update is required
2042 * (and should be ignored by an attempted
2050 * Index for the aged tail ready to read()
2053 unsigned int aged_tail_idx;
2056 * A monotonic timestamp for when the current
2057 * aging tail pointer was read; used to
2058 * determine when it is old enough to trust.
2060 u64 aging_timestamp;
2063 * Although we can always read back the head
2064 * pointer register, we prefer to avoid
2065 * trusting the HW state, just to avoid any
2066 * risk that some hardware condition could
2067 * somehow bump the head pointer unpredictably
2068 * and cause us to forward the wrong OA buffer
2069 * data to userspace.
2074 u32 gen7_latched_oastatus1;
2075 u32 ctx_oactxctrl_offset;
2076 u32 ctx_flexeu0_offset;
2079 * The RPT_ID/reason field for Gen8+ includes a bit
2080 * to determine if the CTX ID in the report is valid
2081 * but the specific bit differs between Gen 8 and 9
2083 u32 gen8_valid_ctx_bit;
2085 struct i915_oa_ops ops;
2086 const struct i915_oa_format *oa_formats;
2090 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2092 void (*resume)(struct drm_i915_private *);
2093 void (*cleanup_engine)(struct intel_engine_cs *engine);
2095 struct list_head timelines;
2097 struct list_head active_rings;
2098 struct list_head closed_vma;
2099 u32 active_requests;
2103 * Is the GPU currently considered idle, or busy executing
2104 * userspace requests? Whilst idle, we allow runtime power
2105 * management to power down the hardware and display clocks.
2106 * In order to reduce the effect on performance, there
2107 * is a slight delay before we do so.
2112 * The number of times we have woken up.
2115 #define I915_EPOCH_INVALID 0
2118 * We leave the user IRQ off as much as possible,
2119 * but this means that requests will finish and never
2120 * be retired once the system goes idle. Set a timer to
2121 * fire periodically while the ring is running. When it
2122 * fires, go retire requests.
2124 struct delayed_work retire_work;
2127 * When we detect an idle GPU, we want to turn on
2128 * powersaving features. So once we see that there
2129 * are no more requests outstanding and no more
2130 * arrive within a small period of time, we fire
2131 * off the idle_work.
2133 struct delayed_work idle_work;
2135 ktime_t last_init_time;
2138 /* perform PHY state sanity checks? */
2139 bool chv_phy_assert[2];
2143 /* Used to save the pipe-to-encoder mapping for audio */
2144 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2146 /* necessary resource sharing with HDMI LPE audio driver. */
2148 struct platform_device *platdev;
2152 struct i915_pmu pmu;
2155 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2156 * will be rejected. Instead look for a better place.
2160 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2162 return container_of(dev, struct drm_i915_private, drm);
2165 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2167 return to_i915(dev_get_drvdata(kdev));
2170 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2172 return container_of(wopcm, struct drm_i915_private, wopcm);
2175 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2177 return container_of(guc, struct drm_i915_private, guc);
2180 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2182 return container_of(huc, struct drm_i915_private, huc);
2185 /* Simple iterator over all initialised engines */
2186 #define for_each_engine(engine__, dev_priv__, id__) \
2188 (id__) < I915_NUM_ENGINES; \
2190 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2192 /* Iterator over subset of engines selected by mask */
2193 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2194 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2196 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2199 enum hdmi_force_audio {
2200 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2201 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2202 HDMI_AUDIO_AUTO, /* trust EDID */
2203 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2206 #define I915_GTT_OFFSET_NONE ((u32)-1)
2209 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2210 * considered to be the frontbuffer for the given plane interface-wise. This
2211 * doesn't mean that the hw necessarily already scans it out, but that any
2212 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2214 * We have one bit per pipe and per scanout plane type.
2216 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2217 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2218 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2219 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2220 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2222 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2223 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2224 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2225 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2226 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2229 * Optimised SGL iterator for GEM objects
2231 static __always_inline struct sgt_iter {
2232 struct scatterlist *sgp;
2239 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2240 struct sgt_iter s = { .sgp = sgl };
2243 s.max = s.curr = s.sgp->offset;
2244 s.max += s.sgp->length;
2246 s.dma = sg_dma_address(s.sgp);
2248 s.pfn = page_to_pfn(sg_page(s.sgp));
2254 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2257 if (unlikely(sg_is_chain(sg)))
2258 sg = sg_chain_ptr(sg);
2263 * __sg_next - return the next scatterlist entry in a list
2264 * @sg: The current sg entry
2267 * If the entry is the last, return NULL; otherwise, step to the next
2268 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2269 * otherwise just return the pointer to the current element.
2271 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2273 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2277 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2278 * @__dmap: DMA address (output)
2279 * @__iter: 'struct sgt_iter' (iterator state, internal)
2280 * @__sgt: sg_table to iterate over (input)
2282 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2283 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2284 ((__dmap) = (__iter).dma + (__iter).curr); \
2285 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2286 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2289 * for_each_sgt_page - iterate over the pages of the given sg_table
2290 * @__pp: page pointer (output)
2291 * @__iter: 'struct sgt_iter' (iterator state, internal)
2292 * @__sgt: sg_table to iterate over (input)
2294 #define for_each_sgt_page(__pp, __iter, __sgt) \
2295 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2296 ((__pp) = (__iter).pfn == 0 ? NULL : \
2297 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2298 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2299 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2301 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2303 unsigned int page_sizes;
2307 GEM_BUG_ON(sg->offset);
2308 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2309 page_sizes |= sg->length;
2316 static inline unsigned int i915_sg_segment_size(void)
2318 unsigned int size = swiotlb_max_segment();
2321 return SCATTERLIST_MAX_SEGMENT;
2323 size = rounddown(size, PAGE_SIZE);
2324 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2325 if (size < PAGE_SIZE)
2331 static inline const struct intel_device_info *
2332 intel_info(const struct drm_i915_private *dev_priv)
2334 return &dev_priv->info;
2337 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2338 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2340 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2341 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2343 #define REVID_FOREVER 0xff
2344 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2346 #define GEN_FOREVER (0)
2348 #define INTEL_GEN_MASK(s, e) ( \
2349 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2350 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2351 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2352 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2356 * Returns true if Gen is in inclusive range [Start, End].
2358 * Use GEN_FOREVER for unbound start and or end.
2360 #define IS_GEN(dev_priv, s, e) \
2361 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2364 * Return true if revision is in range [since,until] inclusive.
2366 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2368 #define IS_REVID(p, since, until) \
2369 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2371 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2373 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2374 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2375 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2376 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2377 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2378 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2379 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2380 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2381 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2382 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2383 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2384 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2385 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2386 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2387 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2388 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2389 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2390 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2391 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2392 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2393 (dev_priv)->info.gt == 1)
2394 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2395 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2396 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2397 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2398 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2399 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2400 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2401 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2402 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2403 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2404 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2405 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2406 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2407 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2408 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2409 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2410 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2411 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2412 /* ULX machines are also considered ULT. */
2413 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2414 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2415 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2416 (dev_priv)->info.gt == 3)
2417 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2418 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2419 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2420 (dev_priv)->info.gt == 3)
2421 /* ULX machines are also considered ULT. */
2422 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2423 INTEL_DEVID(dev_priv) == 0x0A1E)
2424 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2425 INTEL_DEVID(dev_priv) == 0x1913 || \
2426 INTEL_DEVID(dev_priv) == 0x1916 || \
2427 INTEL_DEVID(dev_priv) == 0x1921 || \
2428 INTEL_DEVID(dev_priv) == 0x1926)
2429 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2430 INTEL_DEVID(dev_priv) == 0x1915 || \
2431 INTEL_DEVID(dev_priv) == 0x191E)
2432 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2433 INTEL_DEVID(dev_priv) == 0x5913 || \
2434 INTEL_DEVID(dev_priv) == 0x5916 || \
2435 INTEL_DEVID(dev_priv) == 0x5921 || \
2436 INTEL_DEVID(dev_priv) == 0x5926)
2437 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2438 INTEL_DEVID(dev_priv) == 0x5915 || \
2439 INTEL_DEVID(dev_priv) == 0x591E)
2440 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2441 (dev_priv)->info.gt == 2)
2442 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2443 (dev_priv)->info.gt == 3)
2444 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2445 (dev_priv)->info.gt == 4)
2446 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2447 (dev_priv)->info.gt == 2)
2448 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2449 (dev_priv)->info.gt == 3)
2450 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2451 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2452 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2453 (dev_priv)->info.gt == 2)
2454 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2455 (dev_priv)->info.gt == 3)
2456 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2457 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2459 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2461 #define SKL_REVID_A0 0x0
2462 #define SKL_REVID_B0 0x1
2463 #define SKL_REVID_C0 0x2
2464 #define SKL_REVID_D0 0x3
2465 #define SKL_REVID_E0 0x4
2466 #define SKL_REVID_F0 0x5
2467 #define SKL_REVID_G0 0x6
2468 #define SKL_REVID_H0 0x7
2470 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2472 #define BXT_REVID_A0 0x0
2473 #define BXT_REVID_A1 0x1
2474 #define BXT_REVID_B0 0x3
2475 #define BXT_REVID_B_LAST 0x8
2476 #define BXT_REVID_C0 0x9
2478 #define IS_BXT_REVID(dev_priv, since, until) \
2479 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2481 #define KBL_REVID_A0 0x0
2482 #define KBL_REVID_B0 0x1
2483 #define KBL_REVID_C0 0x2
2484 #define KBL_REVID_D0 0x3
2485 #define KBL_REVID_E0 0x4
2487 #define IS_KBL_REVID(dev_priv, since, until) \
2488 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2490 #define GLK_REVID_A0 0x0
2491 #define GLK_REVID_A1 0x1
2493 #define IS_GLK_REVID(dev_priv, since, until) \
2494 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2496 #define CNL_REVID_A0 0x0
2497 #define CNL_REVID_B0 0x1
2498 #define CNL_REVID_C0 0x2
2500 #define IS_CNL_REVID(p, since, until) \
2501 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2503 #define ICL_REVID_A0 0x0
2504 #define ICL_REVID_A2 0x1
2505 #define ICL_REVID_B0 0x3
2506 #define ICL_REVID_B2 0x4
2507 #define ICL_REVID_C0 0x5
2509 #define IS_ICL_REVID(p, since, until) \
2510 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2513 * The genX designation typically refers to the render engine, so render
2514 * capability related checks should use IS_GEN, while display and other checks
2515 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2518 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2519 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2520 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2521 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2522 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2523 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2524 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2525 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2526 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2527 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2529 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2530 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2531 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2533 #define ENGINE_MASK(id) BIT(id)
2534 #define RENDER_RING ENGINE_MASK(RCS)
2535 #define BSD_RING ENGINE_MASK(VCS)
2536 #define BLT_RING ENGINE_MASK(BCS)
2537 #define VEBOX_RING ENGINE_MASK(VECS)
2538 #define BSD2_RING ENGINE_MASK(VCS2)
2539 #define BSD3_RING ENGINE_MASK(VCS3)
2540 #define BSD4_RING ENGINE_MASK(VCS4)
2541 #define VEBOX2_RING ENGINE_MASK(VECS2)
2542 #define ALL_ENGINES (~0)
2544 #define HAS_ENGINE(dev_priv, id) \
2545 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2547 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2548 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2549 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2550 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2552 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2554 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2555 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2556 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2557 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2558 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2560 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2562 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2563 ((dev_priv)->info.has_logical_ring_contexts)
2564 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2565 ((dev_priv)->info.has_logical_ring_elsq)
2566 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2567 ((dev_priv)->info.has_logical_ring_preemption)
2569 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2571 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2572 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2573 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2574 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2575 GEM_BUG_ON((sizes) == 0); \
2576 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2579 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2580 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2581 ((dev_priv)->info.overlay_needs_physical)
2583 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2584 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2586 /* WaRsDisableCoarsePowerGating:skl,cnl */
2587 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2588 (IS_CANNONLAKE(dev_priv) || \
2589 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2591 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2592 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2593 IS_GEMINILAKE(dev_priv) || \
2594 IS_KABYLAKE(dev_priv))
2596 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2597 * rows, which changed the alignment requirements and fence programming.
2599 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2600 !(IS_I915G(dev_priv) || \
2601 IS_I915GM(dev_priv)))
2602 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2603 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2605 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2606 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2607 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2609 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2611 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2613 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2614 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2615 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2617 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2618 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2619 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2621 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2623 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2624 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2626 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2629 * For now, anything with a GuC requires uCode loading, and then supports
2630 * command submission once loaded. But these are logically independent
2631 * properties, so we have separate macros to test them.
2633 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2634 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2635 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2636 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2638 /* For now, anything with a GuC has also HuC */
2639 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2640 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2642 /* Having a GuC is not the same as using a GuC */
2643 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2644 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2645 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2647 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2649 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2650 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2651 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2652 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2653 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2654 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2655 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2656 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2657 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2658 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2659 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2660 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2661 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2662 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2663 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2664 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2665 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2667 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2668 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2669 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2670 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2671 #define HAS_PCH_CNP_LP(dev_priv) \
2672 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2673 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2674 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2675 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2676 #define HAS_PCH_LPT_LP(dev_priv) \
2677 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2678 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2679 #define HAS_PCH_LPT_H(dev_priv) \
2680 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2681 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2682 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2683 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2684 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2685 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2687 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2689 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2691 /* DPF == dynamic parity feature */
2692 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2693 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2694 2 : HAS_L3_DPF(dev_priv))
2696 #define GT_FREQUENCY_MULTIPLIER 50
2697 #define GEN9_FREQ_SCALER 3
2699 #include "i915_trace.h"
2701 static inline bool intel_vtd_active(void)
2703 #ifdef CONFIG_INTEL_IOMMU
2704 if (intel_iommu_gfx_mapped)
2710 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2712 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2716 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2718 return IS_BROXTON(dev_priv) && intel_vtd_active();
2721 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2726 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2727 const char *fmt, ...);
2729 #define i915_report_error(dev_priv, fmt, ...) \
2730 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2732 #ifdef CONFIG_COMPAT
2733 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2736 #define i915_compat_ioctl NULL
2738 extern const struct dev_pm_ops i915_pm_ops;
2740 extern int i915_driver_load(struct pci_dev *pdev,
2741 const struct pci_device_id *ent);
2742 extern void i915_driver_unload(struct drm_device *dev);
2743 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2744 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2746 extern void i915_reset(struct drm_i915_private *i915,
2747 unsigned int stalled_mask,
2748 const char *reason);
2749 extern int i915_reset_engine(struct intel_engine_cs *engine,
2750 const char *reason);
2752 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2753 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2754 extern int intel_guc_reset_engine(struct intel_guc *guc,
2755 struct intel_engine_cs *engine);
2756 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2757 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2758 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2759 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2760 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2761 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2762 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2764 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2765 int intel_engines_init(struct drm_i915_private *dev_priv);
2767 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2769 /* intel_hotplug.c */
2770 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2771 u32 pin_mask, u32 long_mask);
2772 void intel_hpd_init(struct drm_i915_private *dev_priv);
2773 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2774 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2775 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2777 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2778 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2781 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2783 unsigned long delay;
2785 if (unlikely(!i915_modparams.enable_hangcheck))
2788 /* Don't continually defer the hangcheck so that it is always run at
2789 * least once after work has been scheduled on any ring. Otherwise,
2790 * we will ignore a hung ring if a second ring is kept busy.
2793 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2794 queue_delayed_work(system_long_wq,
2795 &dev_priv->gpu_error.hangcheck_work, delay);
2799 void i915_handle_error(struct drm_i915_private *dev_priv,
2801 unsigned long flags,
2802 const char *fmt, ...);
2803 #define I915_ERROR_CAPTURE BIT(0)
2805 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2806 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2807 int intel_irq_install(struct drm_i915_private *dev_priv);
2808 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2810 void i915_clear_error_registers(struct drm_i915_private *dev_priv);
2812 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2814 return dev_priv->gvt;
2817 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2819 return dev_priv->vgpu.active;
2822 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2825 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2829 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2832 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2833 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2834 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2837 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2838 uint32_t interrupt_mask,
2839 uint32_t enabled_irq_mask);
2841 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2843 ilk_update_display_irq(dev_priv, bits, bits);
2846 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2848 ilk_update_display_irq(dev_priv, bits, 0);
2850 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2852 uint32_t interrupt_mask,
2853 uint32_t enabled_irq_mask);
2854 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2855 enum pipe pipe, uint32_t bits)
2857 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2859 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2860 enum pipe pipe, uint32_t bits)
2862 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2864 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2865 uint32_t interrupt_mask,
2866 uint32_t enabled_irq_mask);
2868 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2870 ibx_display_interrupt_update(dev_priv, bits, bits);
2873 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2875 ibx_display_interrupt_update(dev_priv, bits, 0);
2879 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2880 struct drm_file *file_priv);
2881 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2882 struct drm_file *file_priv);
2883 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2884 struct drm_file *file_priv);
2885 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2886 struct drm_file *file_priv);
2887 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2888 struct drm_file *file_priv);
2889 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2890 struct drm_file *file_priv);
2891 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2892 struct drm_file *file_priv);
2893 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2894 struct drm_file *file_priv);
2895 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2896 struct drm_file *file_priv);
2897 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2898 struct drm_file *file_priv);
2899 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2900 struct drm_file *file);
2901 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2902 struct drm_file *file);
2903 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2904 struct drm_file *file_priv);
2905 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2906 struct drm_file *file_priv);
2907 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2908 struct drm_file *file_priv);
2909 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2910 struct drm_file *file_priv);
2911 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2912 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2913 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2914 struct drm_file *file);
2915 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2916 struct drm_file *file_priv);
2917 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2918 struct drm_file *file_priv);
2919 void i915_gem_sanitize(struct drm_i915_private *i915);
2920 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2921 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2922 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2923 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2924 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2926 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2927 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2928 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2929 const struct drm_i915_gem_object_ops *ops);
2930 struct drm_i915_gem_object *
2931 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2932 struct drm_i915_gem_object *
2933 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2934 const void *data, size_t size);
2935 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2936 void i915_gem_free_object(struct drm_gem_object *obj);
2938 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2940 if (!atomic_read(&i915->mm.free_count))
2943 /* A single pass should suffice to release all the freed objects (along
2944 * most call paths) , but be a little more paranoid in that freeing
2945 * the objects does take a little amount of time, during which the rcu
2946 * callbacks could have added new objects into the freed list, and
2947 * armed the work again.
2951 } while (flush_work(&i915->mm.free_work));
2954 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2957 * Similar to objects above (see i915_gem_drain_freed-objects), in
2958 * general we have workers that are armed by RCU and then rearm
2959 * themselves in their callbacks. To be paranoid, we need to
2960 * drain the workqueue a second time after waiting for the RCU
2961 * grace period so that we catch work queued via RCU from the first
2962 * pass. As neither drain_workqueue() nor flush_workqueue() report
2963 * a result, we make an assumption that we only don't require more
2964 * than 2 passes to catch all recursive RCU delayed work.
2970 drain_workqueue(i915->wq);
2974 struct i915_vma * __must_check
2975 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2976 const struct i915_ggtt_view *view,
2981 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2982 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2984 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2986 static inline int __sg_page_count(const struct scatterlist *sg)
2988 return sg->length >> PAGE_SHIFT;
2991 struct scatterlist *
2992 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2993 unsigned int n, unsigned int *offset);
2996 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3000 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3004 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3007 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3008 struct sg_table *pages,
3009 unsigned int sg_page_sizes);
3010 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3012 static inline int __must_check
3013 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3015 might_lock(&obj->mm.lock);
3017 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3020 return __i915_gem_object_get_pages(obj);
3024 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
3026 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
3030 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3032 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3034 atomic_inc(&obj->mm.pages_pin_count);
3038 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3040 return atomic_read(&obj->mm.pages_pin_count);
3044 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3046 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3047 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3049 atomic_dec(&obj->mm.pages_pin_count);
3053 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3055 __i915_gem_object_unpin_pages(obj);
3058 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3063 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3064 enum i915_mm_subclass subclass);
3065 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3067 enum i915_map_type {
3070 #define I915_MAP_OVERRIDE BIT(31)
3071 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3072 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3076 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3077 * @obj: the object to map into kernel address space
3078 * @type: the type of mapping, used to select pgprot_t
3080 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3081 * pages and then returns a contiguous mapping of the backing storage into
3082 * the kernel address space. Based on the @type of mapping, the PTE will be
3083 * set to either WriteBack or WriteCombine (via pgprot_t).
3085 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3086 * mapping is no longer required.
3088 * Returns the pointer through which to access the mapped object, or an
3089 * ERR_PTR() on error.
3091 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3092 enum i915_map_type type);
3095 * i915_gem_object_unpin_map - releases an earlier mapping
3096 * @obj: the object to unmap
3098 * After pinning the object and mapping its pages, once you are finished
3099 * with your access, call i915_gem_object_unpin_map() to release the pin
3100 * upon the mapping. Once the pin count reaches zero, that mapping may be
3103 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3105 i915_gem_object_unpin_pages(obj);
3108 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3109 unsigned int *needs_clflush);
3110 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3111 unsigned int *needs_clflush);
3112 #define CLFLUSH_BEFORE BIT(0)
3113 #define CLFLUSH_AFTER BIT(1)
3114 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3117 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3119 i915_gem_object_unpin_pages(obj);
3122 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3123 int i915_gem_dumb_create(struct drm_file *file_priv,
3124 struct drm_device *dev,
3125 struct drm_mode_create_dumb *args);
3126 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3127 uint32_t handle, uint64_t *offset);
3128 int i915_gem_mmap_gtt_version(void);
3130 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3131 struct drm_i915_gem_object *new,
3132 unsigned frontbuffer_bits);
3134 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3136 struct i915_request *
3137 i915_gem_find_active_request(struct intel_engine_cs *engine);
3139 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3141 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3144 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3146 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3149 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3151 return unlikely(test_bit(I915_WEDGED, &error->flags));
3154 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3156 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3159 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3161 return READ_ONCE(error->reset_count);
3164 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3165 struct intel_engine_cs *engine)
3167 return READ_ONCE(error->reset_engine_count[engine->id]);
3170 struct i915_request *
3171 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3172 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3173 void i915_gem_reset(struct drm_i915_private *dev_priv,
3174 unsigned int stalled_mask);
3175 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3176 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3177 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3178 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3179 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3180 struct i915_request *request,
3183 void i915_gem_init_mmio(struct drm_i915_private *i915);
3184 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3185 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3186 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3187 void i915_gem_fini(struct drm_i915_private *dev_priv);
3188 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3189 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3190 unsigned int flags, long timeout);
3191 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3192 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3193 void i915_gem_resume(struct drm_i915_private *dev_priv);
3194 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3195 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3198 struct intel_rps_client *rps);
3199 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3201 const struct i915_sched_attr *attr);
3202 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3205 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3207 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3209 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3210 struct i915_vma * __must_check
3211 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3213 const struct i915_ggtt_view *view,
3214 unsigned int flags);
3215 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3216 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3218 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3219 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3221 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3222 enum i915_cache_level cache_level);
3224 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3225 struct dma_buf *dma_buf);
3227 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3228 struct drm_gem_object *gem_obj, int flags);
3230 static inline struct i915_hw_ppgtt *
3231 i915_vm_to_ppgtt(struct i915_address_space *vm)
3233 return container_of(vm, struct i915_hw_ppgtt, vm);
3236 /* i915_gem_fence_reg.c */
3237 struct drm_i915_fence_reg *
3238 i915_reserve_fence(struct drm_i915_private *dev_priv);
3239 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3241 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3242 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3244 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3245 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3246 struct sg_table *pages);
3247 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3248 struct sg_table *pages);
3250 static inline struct i915_gem_context *
3251 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3253 return idr_find(&file_priv->context_idr, id);
3256 static inline struct i915_gem_context *
3257 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3259 struct i915_gem_context *ctx;
3262 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3263 if (ctx && !kref_get_unless_zero(&ctx->ref))
3270 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3271 struct drm_file *file);
3272 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3273 struct drm_file *file);
3274 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3275 struct drm_file *file);
3276 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3277 struct i915_gem_context *ctx,
3278 uint32_t *reg_state);
3280 /* i915_gem_evict.c */
3281 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3282 u64 min_size, u64 alignment,
3283 unsigned cache_level,
3286 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3287 struct drm_mm_node *node,
3288 unsigned int flags);
3289 int i915_gem_evict_vm(struct i915_address_space *vm);
3291 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3293 /* belongs in i915_gem_gtt.h */
3294 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3297 if (INTEL_GEN(dev_priv) < 6)
3298 intel_gtt_chipset_flush();
3301 /* i915_gem_stolen.c */
3302 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3303 struct drm_mm_node *node, u64 size,
3304 unsigned alignment);
3305 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3306 struct drm_mm_node *node, u64 size,
3307 unsigned alignment, u64 start,
3309 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3310 struct drm_mm_node *node);
3311 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3312 void i915_gem_cleanup_stolen(struct drm_device *dev);
3313 struct drm_i915_gem_object *
3314 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3315 resource_size_t size);
3316 struct drm_i915_gem_object *
3317 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3318 resource_size_t stolen_offset,
3319 resource_size_t gtt_offset,
3320 resource_size_t size);
3322 /* i915_gem_internal.c */
3323 struct drm_i915_gem_object *
3324 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3327 /* i915_gem_shrinker.c */
3328 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3329 unsigned long target,
3330 unsigned long *nr_scanned,
3332 #define I915_SHRINK_PURGEABLE 0x1
3333 #define I915_SHRINK_UNBOUND 0x2
3334 #define I915_SHRINK_BOUND 0x4
3335 #define I915_SHRINK_ACTIVE 0x8
3336 #define I915_SHRINK_VMAPS 0x10
3337 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3338 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3339 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3340 void i915_gem_shrinker_taints_mutex(struct mutex *mutex);
3342 /* i915_gem_tiling.c */
3343 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3345 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3347 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3348 i915_gem_object_is_tiled(obj);
3351 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3352 unsigned int tiling, unsigned int stride);
3353 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3354 unsigned int tiling, unsigned int stride);
3356 /* i915_debugfs.c */
3357 #ifdef CONFIG_DEBUG_FS
3358 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3359 int i915_debugfs_connector_add(struct drm_connector *connector);
3360 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3362 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3363 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3365 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3368 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3370 /* i915_cmd_parser.c */
3371 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3372 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3373 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3374 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3375 struct drm_i915_gem_object *batch_obj,
3376 struct drm_i915_gem_object *shadow_batch_obj,
3377 u32 batch_start_offset,
3382 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3383 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3384 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3385 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3387 /* i915_suspend.c */
3388 extern int i915_save_state(struct drm_i915_private *dev_priv);
3389 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3392 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3393 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3395 /* intel_lpe_audio.c */
3396 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3397 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3398 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3399 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3400 enum pipe pipe, enum port port,
3401 const void *eld, int ls_clock, bool dp_output);
3404 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3405 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3406 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3408 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3410 extern struct i2c_adapter *
3411 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3412 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3413 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3414 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3416 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3418 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3421 void intel_bios_init(struct drm_i915_private *dev_priv);
3422 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3423 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3424 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3425 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3426 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3427 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3428 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3429 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3430 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3432 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3437 extern void intel_register_dsm_handler(void);
3438 extern void intel_unregister_dsm_handler(void);
3440 static inline void intel_register_dsm_handler(void) { return; }
3441 static inline void intel_unregister_dsm_handler(void) { return; }
3442 #endif /* CONFIG_ACPI */
3444 /* intel_device_info.c */
3445 static inline struct intel_device_info *
3446 mkwrite_device_info(struct drm_i915_private *dev_priv)
3448 return (struct intel_device_info *)&dev_priv->info;
3452 extern void intel_modeset_init_hw(struct drm_device *dev);
3453 extern int intel_modeset_init(struct drm_device *dev);
3454 extern void intel_modeset_cleanup(struct drm_device *dev);
3455 extern int intel_connector_register(struct drm_connector *);
3456 extern void intel_connector_unregister(struct drm_connector *);
3457 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3459 extern void intel_display_resume(struct drm_device *dev);
3460 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3461 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3462 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3463 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3464 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3465 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3467 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3470 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3471 struct drm_file *file);
3474 extern struct intel_overlay_error_state *
3475 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3476 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3477 struct intel_overlay_error_state *error);
3479 extern struct intel_display_error_state *
3480 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3481 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3482 struct intel_display_error_state *error);
3484 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3485 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3486 u32 val, int fast_timeout_us,
3487 int slow_timeout_ms);
3488 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3489 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3491 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3492 u32 reply_mask, u32 reply, int timeout_base_ms);
3494 /* intel_sideband.c */
3495 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3496 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3497 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3498 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3499 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3500 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3501 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3502 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3503 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3504 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3505 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3506 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3507 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3508 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3509 enum intel_sbi_destination destination);
3510 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3511 enum intel_sbi_destination destination);
3512 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3513 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3515 /* intel_dpio_phy.c */
3516 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3517 enum dpio_phy *phy, enum dpio_channel *ch);
3518 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3519 enum port port, u32 margin, u32 scale,
3520 u32 enable, u32 deemphasis);
3521 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3522 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3523 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3525 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3527 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3528 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3529 uint8_t lane_lat_optim_mask);
3530 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3532 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3533 u32 deemph_reg_value, u32 margin_reg_value,
3534 bool uniq_trans_scale);
3535 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3536 const struct intel_crtc_state *crtc_state,
3538 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3539 const struct intel_crtc_state *crtc_state);
3540 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3541 const struct intel_crtc_state *crtc_state);
3542 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3543 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3544 const struct intel_crtc_state *old_crtc_state);
3546 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3547 u32 demph_reg_value, u32 preemph_reg_value,
3548 u32 uniqtranscale_reg_value, u32 tx3_demph);
3549 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3550 const struct intel_crtc_state *crtc_state);
3551 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3552 const struct intel_crtc_state *crtc_state);
3553 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3554 const struct intel_crtc_state *old_crtc_state);
3556 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3557 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3558 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3559 const i915_reg_t reg);
3561 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3563 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3564 const i915_reg_t reg)
3566 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3569 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3570 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3572 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3573 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3574 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3575 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3577 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3578 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3579 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3580 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3582 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3583 * will be implemented using 2 32-bit writes in an arbitrary order with
3584 * an arbitrary delay between them. This can cause the hardware to
3585 * act upon the intermediate value, possibly leading to corruption and
3586 * machine death. For this reason we do not support I915_WRITE64, or
3587 * dev_priv->uncore.funcs.mmio_writeq.
3589 * When reading a 64-bit value as two 32-bit values, the delay may cause
3590 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3591 * occasionally a 64-bit register does not actualy support a full readq
3592 * and must be read using two 32-bit reads.
3594 * You have been warned.
3596 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3598 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3599 u32 upper, lower, old_upper, loop = 0; \
3600 upper = I915_READ(upper_reg); \
3602 old_upper = upper; \
3603 lower = I915_READ(lower_reg); \
3604 upper = I915_READ(upper_reg); \
3605 } while (upper != old_upper && loop++ < 2); \
3606 (u64)upper << 32 | lower; })
3608 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3609 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3611 #define __raw_read(x, s) \
3612 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3615 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3618 #define __raw_write(x, s) \
3619 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3620 i915_reg_t reg, uint##x##_t val) \
3622 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3637 /* These are untraced mmio-accessors that are only valid to be used inside
3638 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3641 * Think twice, and think again, before using these.
3643 * As an example, these accessors can possibly be used between:
3645 * spin_lock_irq(&dev_priv->uncore.lock);
3646 * intel_uncore_forcewake_get__locked();
3650 * intel_uncore_forcewake_put__locked();
3651 * spin_unlock_irq(&dev_priv->uncore.lock);
3654 * Note: some registers may not need forcewake held, so
3655 * intel_uncore_forcewake_{get,put} can be omitted, see
3656 * intel_uncore_forcewake_for_reg().
3658 * Certain architectures will die if the same cacheline is concurrently accessed
3659 * by different clients (e.g. on Ivybridge). Access to registers should
3660 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3661 * a more localised lock guarding all access to that bank of registers.
3663 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3664 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3665 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3666 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3668 /* "Broadcast RGB" property */
3669 #define INTEL_BROADCAST_RGB_AUTO 0
3670 #define INTEL_BROADCAST_RGB_FULL 1
3671 #define INTEL_BROADCAST_RGB_LIMITED 2
3673 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3675 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3676 return VLV_VGACNTRL;
3677 else if (INTEL_GEN(dev_priv) >= 5)
3678 return CPU_VGACNTRL;
3683 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3685 unsigned long j = msecs_to_jiffies(m);
3687 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3690 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3692 /* nsecs_to_jiffies64() does not guard against overflow */
3693 if (NSEC_PER_SEC % HZ &&
3694 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3695 return MAX_JIFFY_OFFSET;
3697 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3701 * If you need to wait X milliseconds between events A and B, but event B
3702 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3703 * when event A happened, then just before event B you call this function and
3704 * pass the timestamp as the first argument, and X as the second argument.
3707 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3709 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3712 * Don't re-read the value of "jiffies" every time since it may change
3713 * behind our back and break the math.
3715 tmp_jiffies = jiffies;
3716 target_jiffies = timestamp_jiffies +
3717 msecs_to_jiffies_timeout(to_wait_ms);
3719 if (time_after(target_jiffies, tmp_jiffies)) {
3720 remaining_jiffies = target_jiffies - tmp_jiffies;
3721 while (remaining_jiffies)
3723 schedule_timeout_uninterruptible(remaining_jiffies);
3728 __i915_request_irq_complete(const struct i915_request *rq)
3730 struct intel_engine_cs *engine = rq->engine;
3733 /* Note that the engine may have wrapped around the seqno, and
3734 * so our request->global_seqno will be ahead of the hardware,
3735 * even though it completed the request before wrapping. We catch
3736 * this by kicking all the waiters before resetting the seqno
3737 * in hardware, and also signal the fence.
3739 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3742 /* The request was dequeued before we were awoken. We check after
3743 * inspecting the hw to confirm that this was the same request
3744 * that generated the HWS update. The memory barriers within
3745 * the request execution are sufficient to ensure that a check
3746 * after reading the value from hw matches this request.
3748 seqno = i915_request_global_seqno(rq);
3752 /* Before we do the heavier coherent read of the seqno,
3753 * check the value (hopefully) in the CPU cacheline.
3755 if (__i915_request_completed(rq, seqno))
3758 /* Ensure our read of the seqno is coherent so that we
3759 * do not "miss an interrupt" (i.e. if this is the last
3760 * request and the seqno write from the GPU is not visible
3761 * by the time the interrupt fires, we will see that the
3762 * request is incomplete and go back to sleep awaiting
3763 * another interrupt that will never come.)
3765 * Strictly, we only need to do this once after an interrupt,
3766 * but it is easier and safer to do it every time the waiter
3769 if (engine->irq_seqno_barrier &&
3770 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3771 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3773 /* The ordering of irq_posted versus applying the barrier
3774 * is crucial. The clearing of the current irq_posted must
3775 * be visible before we perform the barrier operation,
3776 * such that if a subsequent interrupt arrives, irq_posted
3777 * is reasserted and our task rewoken (which causes us to
3778 * do another __i915_request_irq_complete() immediately
3779 * and reapply the barrier). Conversely, if the clear
3780 * occurs after the barrier, then an interrupt that arrived
3781 * whilst we waited on the barrier would not trigger a
3782 * barrier on the next pass, and the read may not see the
3785 engine->irq_seqno_barrier(engine);
3787 /* If we consume the irq, but we are no longer the bottom-half,
3788 * the real bottom-half may not have serialised their own
3789 * seqno check with the irq-barrier (i.e. may have inspected
3790 * the seqno before we believe it coherent since they see
3791 * irq_posted == false but we are still running).
3793 spin_lock_irq(&b->irq_lock);
3794 if (b->irq_wait && b->irq_wait->tsk != current)
3795 /* Note that if the bottom-half is changed as we
3796 * are sending the wake-up, the new bottom-half will
3797 * be woken by whomever made the change. We only have
3798 * to worry about when we steal the irq-posted for
3801 wake_up_process(b->irq_wait->tsk);
3802 spin_unlock_irq(&b->irq_lock);
3804 if (__i915_request_completed(rq, seqno))
3811 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3812 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3814 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3815 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3816 * perform the operation. To check beforehand, pass in the parameters to
3817 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3818 * you only need to pass in the minor offsets, page-aligned pointers are
3821 * For just checking for SSE4.1, in the foreknowledge that the future use
3822 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3824 #define i915_can_memcpy_from_wc(dst, src, len) \
3825 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3827 #define i915_has_memcpy_from_wc() \
3828 i915_memcpy_from_wc(NULL, NULL, 0)
3831 int remap_io_mapping(struct vm_area_struct *vma,
3832 unsigned long addr, unsigned long pfn, unsigned long size,
3833 struct io_mapping *iomap);
3835 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3837 if (INTEL_GEN(i915) >= 10)
3838 return CNL_HWS_CSB_WRITE_INDEX;
3840 return I915_HWS_CSB_WRITE_INDEX;