2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
38 #define GMBUS1_TOTAL_BYTES_SHIFT 16
39 #define GMBUS1_TOTAL_BYTES_MASK 0x1ff
40 #define gmbus1_total_byte_count(v) (((v) >> \
41 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
42 #define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
43 #define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
44 #define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
46 /* GMBUS0 bits definitions */
47 #define _GMBUS_PIN_SEL_MASK (0x7)
49 static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
51 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
52 unsigned char chr = 0;
54 if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
55 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
58 if (edid->current_edid_read >= EDID_SIZE) {
59 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
63 if (!edid->edid_available) {
64 gvt_vgpu_err("Reading EDID but EDID is not available!\n");
68 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
69 struct intel_vgpu_edid_data *edid_data =
70 intel_vgpu_port(vgpu, edid->port)->edid;
72 chr = edid_data->edid_block[edid->current_edid_read];
73 edid->current_edid_read++;
75 gvt_vgpu_err("No EDID available during the reading?\n");
80 static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
82 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
87 else if (port_select == 2)
89 else if (port_select == 3)
94 static inline int get_port_from_gmbus0(u32 gmbus0)
96 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
101 else if (port_select == 4)
103 else if (port_select == 5)
105 else if (port_select == 6)
110 static void reset_gmbus_controller(struct intel_vgpu *vgpu)
112 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
113 if (!vgpu->display.i2c_edid.edid_available)
114 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
115 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
119 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
120 unsigned int offset, void *p_data, unsigned int bytes)
122 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
123 int port, pin_select;
125 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
127 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
129 intel_vgpu_init_i2c_edid(vgpu);
134 if (IS_BROXTON(dev_priv))
135 port = bxt_get_port_from_gmbus0(pin_select);
137 port = get_port_from_gmbus0(pin_select);
138 if (WARN_ON(port < 0))
141 vgpu->display.i2c_edid.state = I2C_GMBUS;
142 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
144 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
145 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
147 if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
148 !intel_vgpu_port_is_dp(vgpu, port)) {
149 vgpu->display.i2c_edid.port = port;
150 vgpu->display.i2c_edid.edid_available = true;
151 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
153 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
157 static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
158 void *p_data, unsigned int bytes)
160 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
162 u32 wvalue = *(u32 *)p_data;
164 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
165 if (!(wvalue & GMBUS_SW_CLR_INT)) {
166 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
167 reset_gmbus_controller(vgpu);
170 * TODO: "This bit is cleared to zero when an event
171 * causes the HW_RDY bit transition to occur "
175 * per bspec setting this bit can cause:
176 * 1) INT status bit cleared
177 * 2) HW_RDY bit asserted
179 if (wvalue & GMBUS_SW_CLR_INT) {
180 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
181 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
184 /* For virtualization, we suppose that HW is always ready,
185 * so GMBUS_SW_RDY should always be cleared
187 if (wvalue & GMBUS_SW_RDY)
188 wvalue &= ~GMBUS_SW_RDY;
190 i2c_edid->gmbus.total_byte_count =
191 gmbus1_total_byte_count(wvalue);
192 slave_addr = gmbus1_slave_addr(wvalue);
194 /* vgpu gmbus only support EDID */
195 if (slave_addr == EDID_ADDR) {
196 i2c_edid->slave_selected = true;
197 } else if (slave_addr != 0) {
199 "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
200 " gmbus operations will be ignored.\n",
201 vgpu->id, slave_addr);
204 if (wvalue & GMBUS_CYCLE_INDEX)
205 i2c_edid->current_edid_read =
206 gmbus1_slave_index(wvalue);
208 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
209 switch (gmbus1_bus_cycle(wvalue)) {
214 * This can only cause a STOP to be generated
215 * if a GMBUS cycle is generated, the GMBUS is
216 * currently in a data/wait/idle phase, or it is in a
219 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
221 intel_vgpu_init_i2c_edid(vgpu);
222 /* After the 'stop' cycle, hw state would become
223 * 'stop phase' and then 'idle phase' after a
224 * few milliseconds. In emulation, we just set
225 * it as 'idle phase' ('stop phase' is not
226 * visible in gmbus interface)
228 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
229 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
236 /* From hw spec the GMBUS phase
237 * transition like this:
238 * START (-->INDEX) -->DATA
240 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
241 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
244 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
248 * From hw spec the WAIT state will be
250 * (1) in a new GMBUS cycle
251 * (2) by generating a stop
253 vgpu_vreg(vgpu, offset) = wvalue;
258 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
259 void *p_data, unsigned int bytes)
265 static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
266 void *p_data, unsigned int bytes)
269 unsigned char byte_data;
270 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
271 int byte_left = i2c_edid->gmbus.total_byte_count -
272 i2c_edid->current_edid_read;
273 int byte_count = byte_left;
276 /* Data can only be recevied if previous settings correct */
277 if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
278 if (byte_left <= 0) {
279 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
285 for (i = 0; i < byte_count; i++) {
286 byte_data = edid_get_byte(vgpu);
287 reg_data |= (byte_data << (i << 3));
290 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count);
291 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
293 if (byte_left <= 4) {
294 switch (i2c_edid->gmbus.cycle_type) {
297 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
302 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
305 intel_vgpu_init_i2c_edid(vgpu);
308 * Read GMBUS3 during send operation,
309 * return the latest written value
312 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
313 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
318 static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
319 void *p_data, unsigned int bytes)
321 u32 value = vgpu_vreg(vgpu, offset);
323 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
324 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
325 memcpy(p_data, (void *)&value, bytes);
329 static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
330 void *p_data, unsigned int bytes)
332 u32 wvalue = *(u32 *)p_data;
334 if (wvalue & GMBUS_INUSE)
335 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
336 /* All other bits are read-only */
341 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
343 * @offset: reg offset
344 * @p_data: data return buffer
345 * @bytes: access data length
347 * This function is used to emulate gmbus register mmio read
350 * Zero on success, negative error code if failed.
353 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
354 unsigned int offset, void *p_data, unsigned int bytes)
356 if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
359 if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
360 return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
361 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
362 return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
364 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
369 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
371 * @offset: reg offset
372 * @p_data: data return buffer
373 * @bytes: access data length
375 * This function is used to emulate gmbus register mmio write
378 * Zero on success, negative error code if failed.
381 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
382 unsigned int offset, void *p_data, unsigned int bytes)
384 if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
387 if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
388 return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
389 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
390 return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
391 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
392 return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
393 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
394 return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
396 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
409 static inline int get_aux_ch_reg(unsigned int offset)
413 switch (offset & 0xff) {
439 #define AUX_CTL_MSG_LENGTH(reg) \
440 ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \
441 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
444 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
446 * @port_idx: port index
447 * @offset: reg offset
450 * This function is used to emulate AUX channel register write
453 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
458 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
459 int msg_length, ret_msg_size;
460 int msg, addr, ctrl, op;
461 u32 value = *(u32 *)p_data;
462 int aux_data_for_write = 0;
463 int reg = get_aux_ch_reg(offset);
465 if (reg != AUX_CH_CTL) {
466 vgpu_vreg(vgpu, offset) = value;
470 msg_length = AUX_CTL_MSG_LENGTH(value);
471 // check the msg in DATA register.
472 msg = vgpu_vreg(vgpu, offset + 4);
473 addr = (msg >> 8) & 0xffff;
474 ctrl = (msg >> 24) & 0xff;
476 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
477 /* The ctl write to clear some states */
481 /* Always set the wanted value for vms. */
482 ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
483 vgpu_vreg(vgpu, offset) =
485 ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) &
486 DP_AUX_CH_CTL_MESSAGE_SIZE_MASK);
488 if (msg_length == 3) {
489 if (!(op & GVT_AUX_I2C_MOT)) {
491 intel_vgpu_init_i2c_edid(vgpu);
493 /* start or restart */
494 i2c_edid->aux_ch.i2c_over_aux_ch = true;
495 i2c_edid->aux_ch.aux_ch_mot = true;
497 /* reset the address */
498 intel_vgpu_init_i2c_edid(vgpu);
499 } else if (addr == EDID_ADDR) {
500 i2c_edid->state = I2C_AUX_CH;
501 i2c_edid->port = port_idx;
502 i2c_edid->slave_selected = true;
503 if (intel_vgpu_has_monitor_on_port(vgpu,
505 intel_vgpu_port_is_dp(vgpu, port_idx))
506 i2c_edid->edid_available = true;
509 } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) {
511 * We only support EDID reading from I2C_over_AUX. And
512 * we do not expect the index mode to be used. Right now
513 * the WRITE operation is ignored. It is good enough to
514 * support the gfx driver to do EDID access.
517 if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
519 if (WARN_ON(msg_length != 4))
521 if (i2c_edid->edid_available && i2c_edid->slave_selected) {
522 unsigned char val = edid_get_byte(vgpu);
524 aux_data_for_write = (val << 16);
526 aux_data_for_write = (0xff << 16);
528 /* write the return value in AUX_CH_DATA reg which includes:
530 * returned byte if it is READ
532 aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24;
533 vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
537 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
540 * This function is used to initialize vGPU i2c edid emulation stuffs
543 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
545 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
547 edid->state = I2C_NOT_SPECIFIED;
550 edid->slave_selected = false;
551 edid->edid_available = false;
552 edid->current_edid_read = 0;
554 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
556 edid->aux_ch.i2c_over_aux_ch = false;
557 edid->aux_ch.aux_ch_mot = false;