1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2018 Intel Corporation
6 #include <linux/sort.h>
8 #include "intel_gpu_commands.h"
9 #include "intel_gt_pm.h"
10 #include "intel_rps.h"
12 #include "i915_selftest.h"
13 #include "selftests/igt_flush_test.h"
17 static int cmp_u32(const void *A, const void *B)
19 const u32 *a = A, *b = B;
24 static void perf_begin(struct intel_gt *gt)
28 /* Boost gpufreq to max [waitboost] and keep it fixed */
29 atomic_inc(>->rps.num_waiters);
30 queue_work(gt->i915->unordered_wq, >->rps.work);
31 flush_work(>->rps.work);
34 static int perf_end(struct intel_gt *gt)
36 atomic_dec(>->rps.num_waiters);
39 return igt_flush_test(gt->i915);
42 static i915_reg_t timestamp_reg(struct intel_engine_cs *engine)
44 struct drm_i915_private *i915 = engine->i915;
46 if (GRAPHICS_VER(i915) == 5 || IS_G4X(i915))
47 return RING_TIMESTAMP_UDW(engine->mmio_base);
49 return RING_TIMESTAMP(engine->mmio_base);
52 static int write_timestamp(struct i915_request *rq, int slot)
54 struct intel_timeline *tl =
55 rcu_dereference_protected(rq->timeline,
56 !i915_request_signaled(rq));
60 cs = intel_ring_begin(rq, 4);
64 cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
65 if (GRAPHICS_VER(rq->engine->i915) >= 8)
68 *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
69 *cs++ = tl->hwsp_offset + slot * sizeof(u32);
72 intel_ring_advance(rq, cs);
77 static struct i915_vma *create_empty_batch(struct intel_context *ce)
79 struct drm_i915_gem_object *obj;
84 obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE);
88 cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
94 cs[0] = MI_BATCH_BUFFER_END;
96 i915_gem_object_flush_map(obj);
98 vma = i915_vma_instance(obj, ce->vm, NULL);
104 err = i915_vma_pin(vma, 0, 0, PIN_USER);
108 i915_gem_object_unpin_map(obj);
112 i915_gem_object_unpin_map(obj);
114 i915_gem_object_put(obj);
118 static u32 trifilter(u32 *a)
122 sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
124 sum = mul_u32_u32(a[2], 2);
131 static int perf_mi_bb_start(void *arg)
133 struct intel_gt *gt = arg;
134 struct intel_engine_cs *engine;
135 enum intel_engine_id id;
138 if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
142 for_each_engine(engine, gt, id) {
143 struct intel_context *ce = engine->kernel_context;
144 struct i915_vma *batch;
148 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
151 intel_engine_pm_get(engine);
153 batch = create_empty_batch(ce);
155 err = PTR_ERR(batch);
156 intel_engine_pm_put(engine);
160 err = i915_vma_sync(batch);
162 intel_engine_pm_put(engine);
167 for (i = 0; i < ARRAY_SIZE(cycles); i++) {
168 struct i915_request *rq;
170 rq = i915_request_create(ce);
176 err = write_timestamp(rq, 2);
180 err = rq->engine->emit_bb_start(rq,
181 i915_vma_offset(batch), 8,
186 err = write_timestamp(rq, 3);
191 i915_request_get(rq);
192 i915_request_add(rq);
194 if (i915_request_wait(rq, 0, HZ / 5) < 0)
196 i915_request_put(rq);
200 cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
203 intel_engine_pm_put(engine);
207 pr_info("%s: MI_BB_START cycles: %u\n",
208 engine->name, trifilter(cycles));
216 static struct i915_vma *create_nop_batch(struct intel_context *ce)
218 struct drm_i915_gem_object *obj;
219 struct i915_vma *vma;
223 obj = i915_gem_object_create_internal(ce->engine->i915, SZ_64K);
225 return ERR_CAST(obj);
227 cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
233 memset(cs, 0, SZ_64K);
234 cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END;
236 i915_gem_object_flush_map(obj);
238 vma = i915_vma_instance(obj, ce->vm, NULL);
244 err = i915_vma_pin(vma, 0, 0, PIN_USER);
248 i915_gem_object_unpin_map(obj);
252 i915_gem_object_unpin_map(obj);
254 i915_gem_object_put(obj);
258 static int perf_mi_noop(void *arg)
260 struct intel_gt *gt = arg;
261 struct intel_engine_cs *engine;
262 enum intel_engine_id id;
265 if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
269 for_each_engine(engine, gt, id) {
270 struct intel_context *ce = engine->kernel_context;
271 struct i915_vma *base, *nop;
275 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
278 intel_engine_pm_get(engine);
280 base = create_empty_batch(ce);
283 intel_engine_pm_put(engine);
287 err = i915_vma_sync(base);
290 intel_engine_pm_put(engine);
294 nop = create_nop_batch(ce);
298 intel_engine_pm_put(engine);
302 err = i915_vma_sync(nop);
306 intel_engine_pm_put(engine);
310 for (i = 0; i < ARRAY_SIZE(cycles); i++) {
311 struct i915_request *rq;
313 rq = i915_request_create(ce);
319 err = write_timestamp(rq, 2);
323 err = rq->engine->emit_bb_start(rq,
324 i915_vma_offset(base), 8,
329 err = write_timestamp(rq, 3);
333 err = rq->engine->emit_bb_start(rq,
334 i915_vma_offset(nop),
340 err = write_timestamp(rq, 4);
345 i915_request_get(rq);
346 i915_request_add(rq);
348 if (i915_request_wait(rq, 0, HZ / 5) < 0)
350 i915_request_put(rq);
355 (rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) -
356 (rq->hwsp_seqno[3] - rq->hwsp_seqno[2]);
360 intel_engine_pm_put(engine);
364 pr_info("%s: 16K MI_NOOP cycles: %u\n",
365 engine->name, trifilter(cycles));
373 int intel_engine_cs_perf_selftests(struct drm_i915_private *i915)
375 static const struct i915_subtest tests[] = {
376 SUBTEST(perf_mi_bb_start),
377 SUBTEST(perf_mi_noop),
380 if (intel_gt_is_wedged(to_gt(i915)))
383 return intel_gt_live_subtests(tests, to_gt(i915));
386 static int intel_mmio_bases_check(void *arg)
390 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
391 const struct engine_info *info = &intel_engines[i];
394 for (j = 0; j < MAX_MMIO_BASES; j++) {
395 u8 ver = info->mmio_bases[j].graphics_ver;
396 u32 base = info->mmio_bases[j].base;
399 pr_err("%s(%s, class:%d, instance:%d): mmio base for graphics ver %u is before the one for ver %u\n",
401 intel_engine_class_repr(info->class),
402 info->class, info->instance,
411 pr_err("%s(%s, class:%d, instance:%d): invalid mmio base (%x) for graphics ver %u at entry %u\n",
413 intel_engine_class_repr(info->class),
414 info->class, info->instance,
422 pr_debug("%s: min graphics version supported for %s%d is %u\n",
424 intel_engine_class_repr(info->class),
432 int intel_engine_cs_mock_selftests(void)
434 static const struct i915_subtest tests[] = {
435 SUBTEST(intel_mmio_bases_check),
438 return i915_subtests(tests, NULL);