drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dp_tunnel.h>
  40 #include <drm/display/drm_dsc_helper.h>
  41 #include <drm/display/drm_hdmi_helper.h>
  42 #include <drm/drm_atomic_helper.h>
  43 #include <drm/drm_crtc.h>
  44 #include <drm/drm_edid.h>
  45 #include <drm/drm_probe_helper.h>
  46
  47 #include "g4x_dp.h"
  48 #include "i915_drv.h"
  49 #include "i915_irq.h"
  50 #include "i915_reg.h"
  51 #include "intel_atomic.h"
  52 #include "intel_audio.h"
  53 #include "intel_backlight.h"
  54 #include "intel_combo_phy_regs.h"
  55 #include "intel_connector.h"
  56 #include "intel_crtc.h"
  57 #include "intel_cx0_phy.h"
  58 #include "intel_ddi.h"
  59 #include "intel_de.h"
  60 #include "intel_display_driver.h"
  61 #include "intel_display_types.h"
  62 #include "intel_dp.h"
  63 #include "intel_dp_aux.h"
  64 #include "intel_dp_hdcp.h"
  65 #include "intel_dp_link_training.h"
  66 #include "intel_dp_mst.h"
  67 #include "intel_dp_tunnel.h"
  68 #include "intel_dpio_phy.h"
  69 #include "intel_dpll.h"
  70 #include "intel_drrs.h"
  71 #include "intel_fifo_underrun.h"
  72 #include "intel_hdcp.h"
  73 #include "intel_hdmi.h"
  74 #include "intel_hotplug.h"
  75 #include "intel_hotplug_irq.h"
  76 #include "intel_lspcon.h"
  77 #include "intel_lvds.h"
  78 #include "intel_panel.h"
  79 #include "intel_pch_display.h"
  80 #include "intel_pps.h"
  81 #include "intel_psr.h"
  82 #include "intel_tc.h"
  83 #include "intel_vdsc.h"
  84 #include "intel_vrr.h"
  85 #include "intel_crtc_state_dump.h"
  86
  87 /* DP DSC throughput values used for slice count calculations KPixels/s */
  88 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  89 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  90 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  91
  92 /* Max DSC line buffer depth supported by HW. */
  93 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH         13
  94
  95 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
  96 #define DP_DSC_FEC_OVERHEAD_FACTOR              1028530
  97
  98 /* Compliance test status bits  */
  99 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
 100 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 101 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 102 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 103
 104
 105 /* Constants for DP DSC configurations */
 106 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 107
 108 /* With Single pipe configuration, HW is capable of supporting maximum
 109  * of 4 slices per line.
 110  */
 111 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 112
 113 /**
 114  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 115  * @intel_dp: DP struct
 116  *
 117  * If a CPU or PCH DP output is attached to an eDP panel, this function
 118  * will return true, and false otherwise.
 119  *
 120  * This function is not safe to use prior to encoder type being set.
 121  */
 122 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 123 {
 124         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 125
 126         return dig_port->base.type == INTEL_OUTPUT_EDP;
 127 }
 128
 129 bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp)
 130 {
 131         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 132
 133         return HAS_AS_SDP(i915) &&
 134                 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
 135 }
 136
 137 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 138
 139 /* Is link rate UHBR and thus 128b/132b? */
 140 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 141 {
 142         return drm_dp_is_uhbr_rate(crtc_state->port_clock);
 143 }
 144
 145 /**
 146  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
 147  * @rate: link rate in 10kbit/s units
 148  *
 149  * Returns the link symbol size in bits/symbol units depending on the link
 150  * rate -> channel coding.
 151  */
 152 int intel_dp_link_symbol_size(int rate)
 153 {
 154         return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
 155 }
 156
 157 /**
 158  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
 159  * @rate: link rate in 10kbit/s units
 160  *
 161  * Returns the link symbol clock frequency in kHz units depending on the
 162  * link rate and channel coding.
 163  */
 164 int intel_dp_link_symbol_clock(int rate)
 165 {
 166         return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
 167 }
 168
 169 static int max_dprx_rate(struct intel_dp *intel_dp)
 170 {
 171         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 172                 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
 173
 174         return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 175 }
 176
 177 static int max_dprx_lane_count(struct intel_dp *intel_dp)
 178 {
 179         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 180                 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);
 181
 182         return drm_dp_max_lane_count(intel_dp->dpcd);
 183 }
 184
 185 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 186 {
 187         intel_dp->sink_rates[0] = 162000;
 188         intel_dp->num_sink_rates = 1;
 189 }
 190
 191 /* update sink rates from dpcd */
 192 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 193 {
 194         static const int dp_rates[] = {
 195                 162000, 270000, 540000, 810000
 196         };
 197         int i, max_rate;
 198         int max_lttpr_rate;
 199
 200         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 201                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 202                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 203
 204                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 205                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 206
 207                 return;
 208         }
 209
 210         /*
 211          * Sink rates for 8b/10b.
 212          */
 213         max_rate = max_dprx_rate(intel_dp);
 214         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 215         if (max_lttpr_rate)
 216                 max_rate = min(max_rate, max_lttpr_rate);
 217
 218         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 219                 if (dp_rates[i] > max_rate)
 220                         break;
 221                 intel_dp->sink_rates[i] = dp_rates[i];
 222         }
 223
 224         /*
 225          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 226          * rates and 10 Gbps.
 227          */
 228         if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
 229                 u8 uhbr_rates = 0;
 230
 231                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 232
 233                 drm_dp_dpcd_readb(&intel_dp->aux,
 234                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 235
 236                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 237                         /* We have a repeater */
 238                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 239                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 240                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 241                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 242                                 /* Repeater supports 128b/132b, valid UHBR rates */
 243                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 244                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 245                         } else {
 246                                 /* Does not support 128b/132b */
 247                                 uhbr_rates = 0;
 248                         }
 249                 }
 250
 251                 if (uhbr_rates & DP_UHBR10)
 252                         intel_dp->sink_rates[i++] = 1000000;
 253                 if (uhbr_rates & DP_UHBR13_5)
 254                         intel_dp->sink_rates[i++] = 1350000;
 255                 if (uhbr_rates & DP_UHBR20)
 256                         intel_dp->sink_rates[i++] = 2000000;
 257         }
 258
 259         intel_dp->num_sink_rates = i;
 260 }
 261
 262 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 263 {
 264         struct intel_connector *connector = intel_dp->attached_connector;
 265         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 266         struct intel_encoder *encoder = &intel_dig_port->base;
 267
 268         intel_dp_set_dpcd_sink_rates(intel_dp);
 269
 270         if (intel_dp->num_sink_rates)
 271                 return;
 272
 273         drm_err(&dp_to_i915(intel_dp)->drm,
 274                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 275                 connector->base.base.id, connector->base.name,
 276                 encoder->base.base.id, encoder->base.name);
 277
 278         intel_dp_set_default_sink_rates(intel_dp);
 279 }
 280
 281 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 282 {
 283         intel_dp->max_sink_lane_count = 1;
 284 }
 285
 286 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 287 {
 288         struct intel_connector *connector = intel_dp->attached_connector;
 289         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 290         struct intel_encoder *encoder = &intel_dig_port->base;
 291
 292         intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
 293
 294         switch (intel_dp->max_sink_lane_count) {
 295         case 1:
 296         case 2:
 297         case 4:
 298                 return;
 299         }
 300
 301         drm_err(&dp_to_i915(intel_dp)->drm,
 302                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 303                 connector->base.base.id, connector->base.name,
 304                 encoder->base.base.id, encoder->base.name,
 305                 intel_dp->max_sink_lane_count);
 306
 307         intel_dp_set_default_max_sink_lane_count(intel_dp);
 308 }
 309
 310 /* Get length of rates array potentially limited by max_rate. */
 311 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 312 {
 313         int i;
 314
 315         /* Limit results by potentially reduced max rate */
 316         for (i = 0; i < len; i++) {
 317                 if (rates[len - i - 1] <= max_rate)
 318                         return len - i;
 319         }
 320
 321         return 0;
 322 }
 323
 324 /* Get length of common rates array potentially limited by max_rate. */
 325 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 326                                           int max_rate)
 327 {
 328         return intel_dp_rate_limit_len(intel_dp->common_rates,
 329                                        intel_dp->num_common_rates, max_rate);
 330 }
 331
 332 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 333 {
 334         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 335                         index < 0 || index >= intel_dp->num_common_rates))
 336                 return 162000;
 337
 338         return intel_dp->common_rates[index];
 339 }
 340
 341 /* Theoretical max between source and sink */
 342 int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 343 {
 344         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 345 }
 346
 347 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 348 {
 349         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 350         int max_lanes = dig_port->max_lanes;
 351
 352         if (vbt_max_lanes)
 353                 max_lanes = min(max_lanes, vbt_max_lanes);
 354
 355         return max_lanes;
 356 }
 357
 358 /* Theoretical max between source and sink */
 359 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 360 {
 361         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 362         int source_max = intel_dp_max_source_lane_count(dig_port);
 363         int sink_max = intel_dp->max_sink_lane_count;
 364         int lane_max = intel_tc_port_max_lane_count(dig_port);
 365         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 366
 367         if (lttpr_max)
 368                 sink_max = min(sink_max, lttpr_max);
 369
 370         return min3(source_max, sink_max, lane_max);
 371 }
 372
 373 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 374 {
 375         switch (intel_dp->max_link_lane_count) {
 376         case 1:
 377         case 2:
 378         case 4:
 379                 return intel_dp->max_link_lane_count;
 380         default:
 381                 MISSING_CASE(intel_dp->max_link_lane_count);
 382                 return 1;
 383         }
 384 }
 385
 386 /*
 387  * The required data bandwidth for a mode with given pixel clock and bpp. This
 388  * is the required net bandwidth independent of the data bandwidth efficiency.
 389  *
 390  * TODO: check if callers of this functions should use
 391  * intel_dp_effective_data_rate() instead.
 392  */
 393 int
 394 intel_dp_link_required(int pixel_clock, int bpp)
 395 {
 396         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 397         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 398 }
 399
 400 /**
 401  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
 402  * @pixel_clock: pixel clock in kHz
 403  * @bpp_x16: bits per pixel .4 fixed point format
 404  * @bw_overhead: BW allocation overhead in 1ppm units
 405  *
 406  * Return the effective pixel data rate in kB/sec units taking into account
 407  * the provided SSC, FEC, DSC BW allocation overhead.
 408  */
 409 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
 410                                  int bw_overhead)
 411 {
 412         return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
 413                                 1000000 * 16 * 8);
 414 }
 415
 416 /**
 417  * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
 418  * @intel_dp: Intel DP object
 419  * @max_dprx_rate: Maximum data rate of the DPRX
 420  * @max_dprx_lanes: Maximum lane count of the DPRX
 421  *
 422  * Calculate the maximum data rate for the provided link parameters taking into
 423  * account any BW limitations by a DP tunnel attached to @intel_dp.
 424  *
 425  * Returns the maximum data rate in kBps units.
 426  */
 427 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
 428                                 int max_dprx_rate, int max_dprx_lanes)
 429 {
 430         int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);
 431
 432         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 433                 max_rate = min(max_rate,
 434                                drm_dp_tunnel_available_bw(intel_dp->tunnel));
 435
 436         return max_rate;
 437 }
 438
 439 bool intel_dp_has_bigjoiner(struct intel_dp *intel_dp)
 440 {
 441         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 442         struct intel_encoder *encoder = &intel_dig_port->base;
 443         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 444
 445         return DISPLAY_VER(dev_priv) >= 12 ||
 446                 (DISPLAY_VER(dev_priv) == 11 &&
 447                  encoder->port != PORT_A);
 448 }
 449
 450 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 451 {
 452         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 453 }
 454
 455 static int icl_max_source_rate(struct intel_dp *intel_dp)
 456 {
 457         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 458
 459         if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))
 460                 return 540000;
 461
 462         return 810000;
 463 }
 464
 465 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 466 {
 467         if (intel_dp_is_edp(intel_dp))
 468                 return 540000;
 469
 470         return 810000;
 471 }
 472
 473 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 474 {
 475         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 476
 477         if (intel_encoder_is_c10phy(encoder))
 478                 return 810000;
 479
 480         return 2000000;
 481 }
 482
 483 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 484 {
 485         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 486         int max_rate;
 487
 488         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 489
 490         if (intel_dp_is_edp(intel_dp)) {
 491                 struct intel_connector *connector = intel_dp->attached_connector;
 492                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 493
 494                 if (max_rate && edp_max_rate)
 495                         max_rate = min(max_rate, edp_max_rate);
 496                 else if (edp_max_rate)
 497                         max_rate = edp_max_rate;
 498         }
 499
 500         return max_rate;
 501 }
 502
 503 static void
 504 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 505 {
 506         /* The values must be in increasing order */
 507         static const int mtl_rates[] = {
 508                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 509                 810000, 1000000, 2000000,
 510         };
 511         static const int icl_rates[] = {
 512                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 513                 1000000, 1350000,
 514         };
 515         static const int bxt_rates[] = {
 516                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 517         };
 518         static const int skl_rates[] = {
 519                 162000, 216000, 270000, 324000, 432000, 540000
 520         };
 521         static const int hsw_rates[] = {
 522                 162000, 270000, 540000
 523         };
 524         static const int g4x_rates[] = {
 525                 162000, 270000
 526         };
 527         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 528         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 529         const int *source_rates;
 530         int size, max_rate = 0, vbt_max_rate;
 531
 532         /* This should only be done once */
 533         drm_WARN_ON(&dev_priv->drm,
 534                     intel_dp->source_rates || intel_dp->num_source_rates);
 535
 536         if (DISPLAY_VER(dev_priv) >= 14) {
 537                 source_rates = mtl_rates;
 538                 size = ARRAY_SIZE(mtl_rates);
 539                 max_rate = mtl_max_source_rate(intel_dp);
 540         } else if (DISPLAY_VER(dev_priv) >= 11) {
 541                 source_rates = icl_rates;
 542                 size = ARRAY_SIZE(icl_rates);
 543                 if (IS_DG2(dev_priv))
 544                         max_rate = dg2_max_source_rate(intel_dp);
 545                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 546                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 547                         max_rate = 810000;
 548                 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
 549                         max_rate = ehl_max_source_rate(intel_dp);
 550                 else
 551                         max_rate = icl_max_source_rate(intel_dp);
 552         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 553                 source_rates = bxt_rates;
 554                 size = ARRAY_SIZE(bxt_rates);
 555         } else if (DISPLAY_VER(dev_priv) == 9) {
 556                 source_rates = skl_rates;
 557                 size = ARRAY_SIZE(skl_rates);
 558         } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
 559                    IS_BROADWELL(dev_priv)) {
 560                 source_rates = hsw_rates;
 561                 size = ARRAY_SIZE(hsw_rates);
 562         } else {
 563                 source_rates = g4x_rates;
 564                 size = ARRAY_SIZE(g4x_rates);
 565         }
 566
 567         vbt_max_rate = vbt_max_link_rate(intel_dp);
 568         if (max_rate && vbt_max_rate)
 569                 max_rate = min(max_rate, vbt_max_rate);
 570         else if (vbt_max_rate)
 571                 max_rate = vbt_max_rate;
 572
 573         if (max_rate)
 574                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 575
 576         intel_dp->source_rates = source_rates;
 577         intel_dp->num_source_rates = size;
 578 }
 579
 580 static int intersect_rates(const int *source_rates, int source_len,
 581                            const int *sink_rates, int sink_len,
 582                            int *common_rates)
 583 {
 584         int i = 0, j = 0, k = 0;
 585
 586         while (i < source_len && j < sink_len) {
 587                 if (source_rates[i] == sink_rates[j]) {
 588                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 589                                 return k;
 590                         common_rates[k] = source_rates[i];
 591                         ++k;
 592                         ++i;
 593                         ++j;
 594                 } else if (source_rates[i] < sink_rates[j]) {
 595                         ++i;
 596                 } else {
 597                         ++j;
 598                 }
 599         }
 600         return k;
 601 }
 602
 603 /* return index of rate in rates array, or -1 if not found */
 604 static int intel_dp_rate_index(const int *rates, int len, int rate)
 605 {
 606         int i;
 607
 608         for (i = 0; i < len; i++)
 609                 if (rate == rates[i])
 610                         return i;
 611
 612         return -1;
 613 }
 614
 615 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 616 {
 617         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 618
 619         drm_WARN_ON(&i915->drm,
 620                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 621
 622         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 623                                                      intel_dp->num_source_rates,
 624                                                      intel_dp->sink_rates,
 625                                                      intel_dp->num_sink_rates,
 626                                                      intel_dp->common_rates);
 627
 628         /* Paranoia, there should always be something in common. */
 629         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 630                 intel_dp->common_rates[0] = 162000;
 631                 intel_dp->num_common_rates = 1;
 632         }
 633 }
 634
 635 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 636                                        u8 lane_count)
 637 {
 638         /*
 639          * FIXME: we need to synchronize the current link parameters with
 640          * hardware readout. Currently fast link training doesn't work on
 641          * boot-up.
 642          */
 643         if (link_rate == 0 ||
 644             link_rate > intel_dp->max_link_rate)
 645                 return false;
 646
 647         if (lane_count == 0 ||
 648             lane_count > intel_dp_max_lane_count(intel_dp))
 649                 return false;
 650
 651         return true;
 652 }
 653
 654 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 655                                                      int link_rate,
 656                                                      u8 lane_count)
 657 {
 658         /* FIXME figure out what we actually want here */
 659         const struct drm_display_mode *fixed_mode =
 660                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 661         int mode_rate, max_rate;
 662
 663         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 664         max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
 665         if (mode_rate > max_rate)
 666                 return false;
 667
 668         return true;
 669 }
 670
 671 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 672                                             int link_rate, u8 lane_count)
 673 {
 674         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 675         int index;
 676
 677         /*
 678          * TODO: Enable fallback on MST links once MST link compute can handle
 679          * the fallback params.
 680          */
 681         if (intel_dp->is_mst) {
 682                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 683                 return -1;
 684         }
 685
 686         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 687                 drm_dbg_kms(&i915->drm,
 688                             "Retrying Link training for eDP with max parameters\n");
 689                 intel_dp->use_max_params = true;
 690                 return 0;
 691         }
 692
 693         index = intel_dp_rate_index(intel_dp->common_rates,
 694                                     intel_dp->num_common_rates,
 695                                     link_rate);
 696         if (index > 0) {
 697                 if (intel_dp_is_edp(intel_dp) &&
 698                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 699                                                               intel_dp_common_rate(intel_dp, index - 1),
 700                                                               lane_count)) {
 701                         drm_dbg_kms(&i915->drm,
 702                                     "Retrying Link training for eDP with same parameters\n");
 703                         return 0;
 704                 }
 705                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 706                 intel_dp->max_link_lane_count = lane_count;
 707         } else if (lane_count > 1) {
 708                 if (intel_dp_is_edp(intel_dp) &&
 709                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 710                                                               intel_dp_max_common_rate(intel_dp),
 711                                                               lane_count >> 1)) {
 712                         drm_dbg_kms(&i915->drm,
 713                                     "Retrying Link training for eDP with same parameters\n");
 714                         return 0;
 715                 }
 716                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 717                 intel_dp->max_link_lane_count = lane_count >> 1;
 718         } else {
 719                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 720                 return -1;
 721         }
 722
 723         return 0;
 724 }
 725
 726 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 727 {
 728         return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
 729                        1000000U);
 730 }
 731
 732 int intel_dp_bw_fec_overhead(bool fec_enabled)
 733 {
 734         /*
 735          * TODO: Calculate the actual overhead for a given mode.
 736          * The hard-coded 1/0.972261=2.853% overhead factor
 737          * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
 738          * 0.453% DSC overhead. This is enough for a 3840 width mode,
 739          * which has a DSC overhead of up to ~0.2%, but may not be
 740          * enough for a 1024 width mode where this is ~0.8% (on a 4
 741          * lane DP link, with 2 DSC slices and 8 bpp color depth).
 742          */
 743         return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
 744 }
 745
 746 static int
 747 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 748 {
 749         if (DISPLAY_VER(i915) >= 13)
 750                 return 17280 * 8;
 751         else if (DISPLAY_VER(i915) >= 11)
 752                 return 7680 * 8;
 753         else
 754                 return 6144 * 8;
 755 }
 756
 757 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 758 {
 759         u32 bits_per_pixel = bpp;
 760         int i;
 761
 762         /* Error out if the max bpp is less than smallest allowed valid bpp */
 763         if (bits_per_pixel < valid_dsc_bpp[0]) {
 764                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 765                             bits_per_pixel, valid_dsc_bpp[0]);
 766                 return 0;
 767         }
 768
 769         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 770         if (DISPLAY_VER(i915) >= 13) {
 771                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 772
 773                 /*
 774                  * According to BSpec, 27 is the max DSC output bpp,
 775                  * 8 is the min DSC output bpp.
 776                  * While we can still clamp higher bpp values to 27, saving bandwidth,
 777                  * if it is required to oompress up to bpp < 8, means we can't do
 778                  * that and probably means we can't fit the required mode, even with
 779                  * DSC enabled.
 780                  */
 781                 if (bits_per_pixel < 8) {
 782                         drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
 783                                     bits_per_pixel);
 784                         return 0;
 785                 }
 786                 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
 787         } else {
 788                 /* Find the nearest match in the array of known BPPs from VESA */
 789                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 790                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 791                                 break;
 792                 }
 793                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 794                             bits_per_pixel, valid_dsc_bpp[i]);
 795
 796                 bits_per_pixel = valid_dsc_bpp[i];
 797         }
 798
 799         return bits_per_pixel;
 800 }
 801
 802 static
 803 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
 804                                        u32 mode_clock, u32 mode_hdisplay,
 805                                        bool bigjoiner)
 806 {
 807         u32 max_bpp_small_joiner_ram;
 808
 809         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 810         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
 811
 812         if (bigjoiner) {
 813                 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
 814                 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
 815                 int ppc = 2;
 816                 u32 max_bpp_bigjoiner =
 817                         i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
 818                         intel_dp_mode_to_fec_clock(mode_clock);
 819
 820                 max_bpp_small_joiner_ram *= 2;
 821
 822                 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
 823         }
 824
 825         return max_bpp_small_joiner_ram;
 826 }
 827
 828 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 829                                         u32 link_clock, u32 lane_count,
 830                                         u32 mode_clock, u32 mode_hdisplay,
 831                                         bool bigjoiner,
 832                                         enum intel_output_format output_format,
 833                                         u32 pipe_bpp,
 834                                         u32 timeslots)
 835 {
 836         u32 bits_per_pixel, joiner_max_bpp;
 837
 838         /*
 839          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 840          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 841          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 842          * for MST -> TimeSlots has to be calculated, based on mode requirements
 843          *
 844          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 845          * To support the given mode:
 846          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 847          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 848          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 849          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 850          *                     (ModeClock / FEC Overhead)
 851          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 852          *                     (ModeClock / FEC Overhead * 8)
 853          */
 854         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 855                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 856
 857         /* Bandwidth required for 420 is half, that of 444 format */
 858         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 859                 bits_per_pixel *= 2;
 860
 861         /*
 862          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
 863          * supported PPS value can be 63.9375 and with the further
 864          * mention that for 420, 422 formats, bpp should be programmed double
 865          * the target bpp restricting our target bpp to be 31.9375 at max.
 866          */
 867         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 868                 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
 869
 870         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 871                                 "total bw %u pixel clock %u\n",
 872                                 bits_per_pixel, timeslots,
 873                                 (link_clock * lane_count * 8),
 874                                 intel_dp_mode_to_fec_clock(mode_clock));
 875
 876         joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
 877                                                             mode_hdisplay, bigjoiner);
 878         bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
 879
 880         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 881
 882         return bits_per_pixel;
 883 }
 884
 885 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 886                                 int mode_clock, int mode_hdisplay,
 887                                 bool bigjoiner)
 888 {
 889         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 890         u8 min_slice_count, i;
 891         int max_slice_width;
 892
 893         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 894                 min_slice_count = DIV_ROUND_UP(mode_clock,
 895                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 896         else
 897                 min_slice_count = DIV_ROUND_UP(mode_clock,
 898                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 899
 900         /*
 901          * Due to some DSC engine BW limitations, we need to enable second
 902          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 903          */
 904         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 905                 min_slice_count = max_t(u8, min_slice_count, 2);
 906
 907         max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
 908         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 909                 drm_dbg_kms(&i915->drm,
 910                             "Unsupported slice width %d by DP DSC Sink device\n",
 911                             max_slice_width);
 912                 return 0;
 913         }
 914         /* Also take into account max slice width */
 915         min_slice_count = max_t(u8, min_slice_count,
 916                                 DIV_ROUND_UP(mode_hdisplay,
 917                                              max_slice_width));
 918
 919         /* Find the closest match to the valid slice count values */
 920         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 921                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 922
 923                 if (test_slice_count >
 924                     drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
 925                         break;
 926
 927                 /* big joiner needs small joiner to be enabled */
 928                 if (bigjoiner && test_slice_count < 4)
 929                         continue;
 930
 931                 if (min_slice_count <= test_slice_count)
 932                         return test_slice_count;
 933         }
 934
 935         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 936                     min_slice_count);
 937         return 0;
 938 }
 939
 940 static bool source_can_output(struct intel_dp *intel_dp,
 941                               enum intel_output_format format)
 942 {
 943         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 944
 945         switch (format) {
 946         case INTEL_OUTPUT_FORMAT_RGB:
 947                 return true;
 948
 949         case INTEL_OUTPUT_FORMAT_YCBCR444:
 950                 /*
 951                  * No YCbCr output support on gmch platforms.
 952                  * Also, ILK doesn't seem capable of DP YCbCr output.
 953                  * The displayed image is severly corrupted. SNB+ is fine.
 954                  */
 955                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
 956
 957         case INTEL_OUTPUT_FORMAT_YCBCR420:
 958                 /* Platform < Gen 11 cannot output YCbCr420 format */
 959                 return DISPLAY_VER(i915) >= 11;
 960
 961         default:
 962                 MISSING_CASE(format);
 963                 return false;
 964         }
 965 }
 966
 967 static bool
 968 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
 969                          enum intel_output_format sink_format)
 970 {
 971         if (!drm_dp_is_branch(intel_dp->dpcd))
 972                 return false;
 973
 974         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 975                 return intel_dp->dfp.rgb_to_ycbcr;
 976
 977         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 978                 return intel_dp->dfp.rgb_to_ycbcr &&
 979                         intel_dp->dfp.ycbcr_444_to_420;
 980
 981         return false;
 982 }
 983
 984 static bool
 985 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
 986                               enum intel_output_format sink_format)
 987 {
 988         if (!drm_dp_is_branch(intel_dp->dpcd))
 989                 return false;
 990
 991         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 992                 return intel_dp->dfp.ycbcr_444_to_420;
 993
 994         return false;
 995 }
 996
 997 static bool
 998 dfp_can_convert(struct intel_dp *intel_dp,
 999                 enum intel_output_format output_format,
1000                 enum intel_output_format sink_format)
1001 {
1002         switch (output_format) {
1003         case INTEL_OUTPUT_FORMAT_RGB:
1004                 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1005         case INTEL_OUTPUT_FORMAT_YCBCR444:
1006                 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1007         default:
1008                 MISSING_CASE(output_format);
1009                 return false;
1010         }
1011
1012         return false;
1013 }
1014
1015 static enum intel_output_format
1016 intel_dp_output_format(struct intel_connector *connector,
1017                        enum intel_output_format sink_format)
1018 {
1019         struct intel_dp *intel_dp = intel_attached_dp(connector);
1020         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1021         enum intel_output_format force_dsc_output_format =
1022                 intel_dp->force_dsc_output_format;
1023         enum intel_output_format output_format;
1024         if (force_dsc_output_format) {
1025                 if (source_can_output(intel_dp, force_dsc_output_format) &&
1026                     (!drm_dp_is_branch(intel_dp->dpcd) ||
1027                      sink_format != force_dsc_output_format ||
1028                      dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1029                         return force_dsc_output_format;
1030
1031                 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1032         }
1033
1034         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1035             dfp_can_convert_from_rgb(intel_dp, sink_format))
1036                 output_format = INTEL_OUTPUT_FORMAT_RGB;
1037
1038         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1039                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1040                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1041
1042         else
1043                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1044
1045         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1046
1047         return output_format;
1048 }
1049
1050 int intel_dp_min_bpp(enum intel_output_format output_format)
1051 {
1052         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1053                 return 6 * 3;
1054         else
1055                 return 8 * 3;
1056 }
1057
1058 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1059 {
1060         /*
1061          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1062          * format of the number of bytes per pixel will be half the number
1063          * of bytes of RGB pixel.
1064          */
1065         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1066                 bpp /= 2;
1067
1068         return bpp;
1069 }
1070
1071 static enum intel_output_format
1072 intel_dp_sink_format(struct intel_connector *connector,
1073                      const struct drm_display_mode *mode)
1074 {
1075         const struct drm_display_info *info = &connector->base.display_info;
1076
1077         if (drm_mode_is_420_only(info, mode))
1078                 return INTEL_OUTPUT_FORMAT_YCBCR420;
1079
1080         return INTEL_OUTPUT_FORMAT_RGB;
1081 }
1082
1083 static int
1084 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1085                              const struct drm_display_mode *mode)
1086 {
1087         enum intel_output_format output_format, sink_format;
1088
1089         sink_format = intel_dp_sink_format(connector, mode);
1090
1091         output_format = intel_dp_output_format(connector, sink_format);
1092
1093         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1094 }
1095
1096 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1097                                   int hdisplay)
1098 {
1099         /*
1100          * Older platforms don't like hdisplay==4096 with DP.
1101          *
1102          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1103          * and frame counter increment), but we don't get vblank interrupts,
1104          * and the pipe underruns immediately. The link also doesn't seem
1105          * to get trained properly.
1106          *
1107          * On CHV the vblank interrupts don't seem to disappear but
1108          * otherwise the symptoms are similar.
1109          *
1110          * TODO: confirm the behaviour on HSW+
1111          */
1112         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1113 }
1114
1115 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1116 {
1117         struct intel_connector *connector = intel_dp->attached_connector;
1118         const struct drm_display_info *info = &connector->base.display_info;
1119         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1120
1121         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1122         if (max_tmds_clock && info->max_tmds_clock)
1123                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1124
1125         return max_tmds_clock;
1126 }
1127
1128 static enum drm_mode_status
1129 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1130                           int clock, int bpc,
1131                           enum intel_output_format sink_format,
1132                           bool respect_downstream_limits)
1133 {
1134         int tmds_clock, min_tmds_clock, max_tmds_clock;
1135
1136         if (!respect_downstream_limits)
1137                 return MODE_OK;
1138
1139         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1140
1141         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1142         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1143
1144         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1145                 return MODE_CLOCK_LOW;
1146
1147         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1148                 return MODE_CLOCK_HIGH;
1149
1150         return MODE_OK;
1151 }
1152
1153 static enum drm_mode_status
1154 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1155                                const struct drm_display_mode *mode,
1156                                int target_clock)
1157 {
1158         struct intel_dp *intel_dp = intel_attached_dp(connector);
1159         const struct drm_display_info *info = &connector->base.display_info;
1160         enum drm_mode_status status;
1161         enum intel_output_format sink_format;
1162
1163         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1164         if (intel_dp->dfp.pcon_max_frl_bw) {
1165                 int target_bw;
1166                 int max_frl_bw;
1167                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1168
1169                 target_bw = bpp * target_clock;
1170
1171                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1172
1173                 /* converting bw from Gbps to Kbps*/
1174                 max_frl_bw = max_frl_bw * 1000000;
1175
1176                 if (target_bw > max_frl_bw)
1177                         return MODE_CLOCK_HIGH;
1178
1179                 return MODE_OK;
1180         }
1181
1182         if (intel_dp->dfp.max_dotclock &&
1183             target_clock > intel_dp->dfp.max_dotclock)
1184                 return MODE_CLOCK_HIGH;
1185
1186         sink_format = intel_dp_sink_format(connector, mode);
1187
1188         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1189         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1190                                            8, sink_format, true);
1191
1192         if (status != MODE_OK) {
1193                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1194                     !connector->base.ycbcr_420_allowed ||
1195                     !drm_mode_is_420_also(info, mode))
1196                         return status;
1197                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1198                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1199                                                    8, sink_format, true);
1200                 if (status != MODE_OK)
1201                         return status;
1202         }
1203
1204         return MODE_OK;
1205 }
1206
1207 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1208                              struct intel_connector *connector,
1209                              int hdisplay, int clock)
1210 {
1211         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1212
1213         if (!intel_dp_has_bigjoiner(intel_dp))
1214                 return false;
1215
1216         return clock > i915->display.cdclk.max_dotclk_freq || hdisplay > 5120 ||
1217                connector->force_bigjoiner_enable;
1218 }
1219
1220 static enum drm_mode_status
1221 intel_dp_mode_valid(struct drm_connector *_connector,
1222                     struct drm_display_mode *mode)
1223 {
1224         struct intel_connector *connector = to_intel_connector(_connector);
1225         struct intel_dp *intel_dp = intel_attached_dp(connector);
1226         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1227         const struct drm_display_mode *fixed_mode;
1228         int target_clock = mode->clock;
1229         int max_rate, mode_rate, max_lanes, max_link_clock;
1230         int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
1231         u16 dsc_max_compressed_bpp = 0;
1232         u8 dsc_slice_count = 0;
1233         enum drm_mode_status status;
1234         bool dsc = false, bigjoiner = false;
1235
1236         status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1237         if (status != MODE_OK)
1238                 return status;
1239
1240         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1241                 return MODE_H_ILLEGAL;
1242
1243         if (mode->clock < 10000)
1244                 return MODE_CLOCK_LOW;
1245
1246         fixed_mode = intel_panel_fixed_mode(connector, mode);
1247         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1248                 status = intel_panel_mode_valid(connector, mode);
1249                 if (status != MODE_OK)
1250                         return status;
1251
1252                 target_clock = fixed_mode->clock;
1253         }
1254
1255         if (intel_dp_need_bigjoiner(intel_dp, connector,
1256                                     mode->hdisplay, target_clock)) {
1257                 bigjoiner = true;
1258                 max_dotclk *= 2;
1259         }
1260         if (target_clock > max_dotclk)
1261                 return MODE_CLOCK_HIGH;
1262
1263         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1264                 return MODE_H_ILLEGAL;
1265
1266         max_link_clock = intel_dp_max_link_rate(intel_dp);
1267         max_lanes = intel_dp_max_lane_count(intel_dp);
1268
1269         max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
1270
1271         mode_rate = intel_dp_link_required(target_clock,
1272                                            intel_dp_mode_min_output_bpp(connector, mode));
1273
1274         if (HAS_DSC(dev_priv) &&
1275             drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
1276                 enum intel_output_format sink_format, output_format;
1277                 int pipe_bpp;
1278
1279                 sink_format = intel_dp_sink_format(connector, mode);
1280                 output_format = intel_dp_output_format(connector, sink_format);
1281                 /*
1282                  * TBD pass the connector BPC,
1283                  * for now U8_MAX so that max BPC on that platform would be picked
1284                  */
1285                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1286
1287                 /*
1288                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1289                  * integer value since we support only integer values of bpp.
1290                  */
1291                 if (intel_dp_is_edp(intel_dp)) {
1292                         dsc_max_compressed_bpp =
1293                                 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1294                         dsc_slice_count =
1295                                 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1296                                                                 true);
1297                 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1298                         dsc_max_compressed_bpp =
1299                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1300                                                                     max_link_clock,
1301                                                                     max_lanes,
1302                                                                     target_clock,
1303                                                                     mode->hdisplay,
1304                                                                     bigjoiner,
1305                                                                     output_format,
1306                                                                     pipe_bpp, 64);
1307                         dsc_slice_count =
1308                                 intel_dp_dsc_get_slice_count(connector,
1309                                                              target_clock,
1310                                                              mode->hdisplay,
1311                                                              bigjoiner);
1312                 }
1313
1314                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1315         }
1316
1317         if (intel_dp_joiner_needs_dsc(dev_priv, bigjoiner) && !dsc)
1318                 return MODE_CLOCK_HIGH;
1319
1320         if (mode_rate > max_rate && !dsc)
1321                 return MODE_CLOCK_HIGH;
1322
1323         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1324         if (status != MODE_OK)
1325                 return status;
1326
1327         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1328 }
1329
1330 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1331 {
1332         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1333 }
1334
1335 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1336 {
1337         return DISPLAY_VER(i915) >= 10;
1338 }
1339
1340 static void snprintf_int_array(char *str, size_t len,
1341                                const int *array, int nelem)
1342 {
1343         int i;
1344
1345         str[0] = '\0';
1346
1347         for (i = 0; i < nelem; i++) {
1348                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1349                 if (r >= len)
1350                         return;
1351                 str += r;
1352                 len -= r;
1353         }
1354 }
1355
1356 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1357 {
1358         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1359         char str[128]; /* FIXME: too big for stack? */
1360
1361         if (!drm_debug_enabled(DRM_UT_KMS))
1362                 return;
1363
1364         snprintf_int_array(str, sizeof(str),
1365                            intel_dp->source_rates, intel_dp->num_source_rates);
1366         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1367
1368         snprintf_int_array(str, sizeof(str),
1369                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1370         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1371
1372         snprintf_int_array(str, sizeof(str),
1373                            intel_dp->common_rates, intel_dp->num_common_rates);
1374         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1375 }
1376
1377 int
1378 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1379 {
1380         int len;
1381
1382         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1383
1384         return intel_dp_common_rate(intel_dp, len - 1);
1385 }
1386
1387 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1388 {
1389         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1390         int i = intel_dp_rate_index(intel_dp->sink_rates,
1391                                     intel_dp->num_sink_rates, rate);
1392
1393         if (drm_WARN_ON(&i915->drm, i < 0))
1394                 i = 0;
1395
1396         return i;
1397 }
1398
1399 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1400                            u8 *link_bw, u8 *rate_select)
1401 {
1402         /* eDP 1.4 rate select method. */
1403         if (intel_dp->use_rate_select) {
1404                 *link_bw = 0;
1405                 *rate_select =
1406                         intel_dp_rate_select(intel_dp, port_clock);
1407         } else {
1408                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1409                 *rate_select = 0;
1410         }
1411 }
1412
1413 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1414 {
1415         struct intel_connector *connector = intel_dp->attached_connector;
1416
1417         return connector->base.display_info.is_hdmi;
1418 }
1419
1420 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1421                                          const struct intel_crtc_state *pipe_config)
1422 {
1423         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1424         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1425
1426         if (DISPLAY_VER(dev_priv) >= 12)
1427                 return true;
1428
1429         if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1430             !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1431                 return true;
1432
1433         return false;
1434 }
1435
1436 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1437                            const struct intel_connector *connector,
1438                            const struct intel_crtc_state *pipe_config)
1439 {
1440         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1441                 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1442 }
1443
1444 static bool intel_dp_supports_dsc(const struct intel_connector *connector,
1445                                   const struct intel_crtc_state *crtc_state)
1446 {
1447         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1448                 return false;
1449
1450         return intel_dsc_source_support(crtc_state) &&
1451                 connector->dp.dsc_decompression_aux &&
1452                 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
1453 }
1454
1455 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1456                                      const struct intel_crtc_state *crtc_state,
1457                                      int bpc, bool respect_downstream_limits)
1458 {
1459         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1460
1461         /*
1462          * Current bpc could already be below 8bpc due to
1463          * FDI bandwidth constraints or other limits.
1464          * HDMI minimum is 8bpc however.
1465          */
1466         bpc = max(bpc, 8);
1467
1468         /*
1469          * We will never exceed downstream TMDS clock limits while
1470          * attempting deep color. If the user insists on forcing an
1471          * out of spec mode they will have to be satisfied with 8bpc.
1472          */
1473         if (!respect_downstream_limits)
1474                 bpc = 8;
1475
1476         for (; bpc >= 8; bpc -= 2) {
1477                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1478                                             intel_dp_has_hdmi_sink(intel_dp)) &&
1479                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1480                                               respect_downstream_limits) == MODE_OK)
1481                         return bpc;
1482         }
1483
1484         return -EINVAL;
1485 }
1486
1487 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1488                             const struct intel_crtc_state *crtc_state,
1489                             bool respect_downstream_limits)
1490 {
1491         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1492         struct intel_connector *intel_connector = intel_dp->attached_connector;
1493         int bpp, bpc;
1494
1495         bpc = crtc_state->pipe_bpp / 3;
1496
1497         if (intel_dp->dfp.max_bpc)
1498                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1499
1500         if (intel_dp->dfp.min_tmds_clock) {
1501                 int max_hdmi_bpc;
1502
1503                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1504                                                          respect_downstream_limits);
1505                 if (max_hdmi_bpc < 0)
1506                         return 0;
1507
1508                 bpc = min(bpc, max_hdmi_bpc);
1509         }
1510
1511         bpp = bpc * 3;
1512         if (intel_dp_is_edp(intel_dp)) {
1513                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1514                 if (intel_connector->base.display_info.bpc == 0 &&
1515                     intel_connector->panel.vbt.edp.bpp &&
1516                     intel_connector->panel.vbt.edp.bpp < bpp) {
1517                         drm_dbg_kms(&dev_priv->drm,
1518                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1519                                     intel_connector->panel.vbt.edp.bpp);
1520                         bpp = intel_connector->panel.vbt.edp.bpp;
1521                 }
1522         }
1523
1524         return bpp;
1525 }
1526
1527 /* Adjust link config limits based on compliance test requests. */
1528 void
1529 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1530                                   struct intel_crtc_state *pipe_config,
1531                                   struct link_config_limits *limits)
1532 {
1533         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1534
1535         /* For DP Compliance we override the computed bpp for the pipe */
1536         if (intel_dp->compliance.test_data.bpc != 0) {
1537                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1538
1539                 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
1540                 pipe_config->dither_force_disable = bpp == 6 * 3;
1541
1542                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1543         }
1544
1545         /* Use values requested by Compliance Test Request */
1546         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1547                 int index;
1548
1549                 /* Validate the compliance test data since max values
1550                  * might have changed due to link train fallback.
1551                  */
1552                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1553                                                intel_dp->compliance.test_lane_count)) {
1554                         index = intel_dp_rate_index(intel_dp->common_rates,
1555                                                     intel_dp->num_common_rates,
1556                                                     intel_dp->compliance.test_link_rate);
1557                         if (index >= 0)
1558                                 limits->min_rate = limits->max_rate =
1559                                         intel_dp->compliance.test_link_rate;
1560                         limits->min_lane_count = limits->max_lane_count =
1561                                 intel_dp->compliance.test_lane_count;
1562                 }
1563         }
1564 }
1565
1566 static bool has_seamless_m_n(struct intel_connector *connector)
1567 {
1568         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1569
1570         /*
1571          * Seamless M/N reprogramming only implemented
1572          * for BDW+ double buffered M/N registers so far.
1573          */
1574         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1575                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1576 }
1577
1578 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1579                                const struct drm_connector_state *conn_state)
1580 {
1581         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1582         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1583
1584         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1585         if (has_seamless_m_n(connector))
1586                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1587         else
1588                 return adjusted_mode->crtc_clock;
1589 }
1590
1591 /* Optimize link config in order: max bpp, min clock, min lanes */
1592 static int
1593 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1594                                   struct intel_crtc_state *pipe_config,
1595                                   const struct drm_connector_state *conn_state,
1596                                   const struct link_config_limits *limits)
1597 {
1598         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1599         int mode_rate, link_rate, link_avail;
1600
1601         for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1602              bpp >= to_bpp_int(limits->link.min_bpp_x16);
1603              bpp -= 2 * 3) {
1604                 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1605
1606                 mode_rate = intel_dp_link_required(clock, link_bpp);
1607
1608                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1609                         link_rate = intel_dp_common_rate(intel_dp, i);
1610                         if (link_rate < limits->min_rate ||
1611                             link_rate > limits->max_rate)
1612                                 continue;
1613
1614                         for (lane_count = limits->min_lane_count;
1615                              lane_count <= limits->max_lane_count;
1616                              lane_count <<= 1) {
1617                                 link_avail = intel_dp_max_link_data_rate(intel_dp,
1618                                                                          link_rate,
1619                                                                          lane_count);
1620
1621
1622                                 if (mode_rate <= link_avail) {
1623                                         pipe_config->lane_count = lane_count;
1624                                         pipe_config->pipe_bpp = bpp;
1625                                         pipe_config->port_clock = link_rate;
1626
1627                                         return 0;
1628                                 }
1629                         }
1630                 }
1631         }
1632
1633         return -EINVAL;
1634 }
1635
1636 static
1637 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1638 {
1639         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1640         if (DISPLAY_VER(i915) >= 12)
1641                 return 12;
1642         if (DISPLAY_VER(i915) == 11)
1643                 return 10;
1644
1645         return 0;
1646 }
1647
1648 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1649                                  u8 max_req_bpc)
1650 {
1651         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1652         int i, num_bpc;
1653         u8 dsc_bpc[3] = {};
1654         u8 dsc_max_bpc;
1655
1656         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1657
1658         if (!dsc_max_bpc)
1659                 return dsc_max_bpc;
1660
1661         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1662
1663         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1664                                                        dsc_bpc);
1665         for (i = 0; i < num_bpc; i++) {
1666                 if (dsc_max_bpc >= dsc_bpc[i])
1667                         return dsc_bpc[i] * 3;
1668         }
1669
1670         return 0;
1671 }
1672
1673 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1674 {
1675         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1676 }
1677
1678 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1679 {
1680         return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1681                 DP_DSC_MINOR_SHIFT;
1682 }
1683
1684 static int intel_dp_get_slice_height(int vactive)
1685 {
1686         int slice_height;
1687
1688         /*
1689          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1690          * lines is an optimal slice height, but any size can be used as long as
1691          * vertical active integer multiple and maximum vertical slice count
1692          * requirements are met.
1693          */
1694         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1695                 if (vactive % slice_height == 0)
1696                         return slice_height;
1697
1698         /*
1699          * Highly unlikely we reach here as most of the resolutions will end up
1700          * finding appropriate slice_height in above loop but returning
1701          * slice_height as 2 here as it should work with all resolutions.
1702          */
1703         return 2;
1704 }
1705
1706 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1707                                        struct intel_crtc_state *crtc_state)
1708 {
1709         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1710         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1711         int ret;
1712
1713         /*
1714          * RC_MODEL_SIZE is currently a constant across all configurations.
1715          *
1716          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1717          * DP_DSC_RC_BUF_SIZE for this.
1718          */
1719         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1720         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1721
1722         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1723
1724         ret = intel_dsc_compute_params(crtc_state);
1725         if (ret)
1726                 return ret;
1727
1728         vdsc_cfg->dsc_version_major =
1729                 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1730                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1731         vdsc_cfg->dsc_version_minor =
1732                 min(intel_dp_source_dsc_version_minor(i915),
1733                     intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1734         if (vdsc_cfg->convert_rgb)
1735                 vdsc_cfg->convert_rgb =
1736                         connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1737                         DP_DSC_RGB;
1738
1739         vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1740                                        drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1741         if (!vdsc_cfg->line_buf_depth) {
1742                 drm_dbg_kms(&i915->drm,
1743                             "DSC Sink Line Buffer Depth invalid\n");
1744                 return -EINVAL;
1745         }
1746
1747         vdsc_cfg->block_pred_enable =
1748                 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1749                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1750
1751         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1752 }
1753
1754 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1755                                          enum intel_output_format output_format)
1756 {
1757         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1758         u8 sink_dsc_format;
1759
1760         switch (output_format) {
1761         case INTEL_OUTPUT_FORMAT_RGB:
1762                 sink_dsc_format = DP_DSC_RGB;
1763                 break;
1764         case INTEL_OUTPUT_FORMAT_YCBCR444:
1765                 sink_dsc_format = DP_DSC_YCbCr444;
1766                 break;
1767         case INTEL_OUTPUT_FORMAT_YCBCR420:
1768                 if (min(intel_dp_source_dsc_version_minor(i915),
1769                         intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1770                         return false;
1771                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1772                 break;
1773         default:
1774                 return false;
1775         }
1776
1777         return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1778 }
1779
1780 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1781                                             u32 lane_count, u32 mode_clock,
1782                                             enum intel_output_format output_format,
1783                                             int timeslots)
1784 {
1785         u32 available_bw, required_bw;
1786
1787         available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
1788         required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1789
1790         return available_bw > required_bw;
1791 }
1792
1793 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1794                                    struct intel_crtc_state *pipe_config,
1795                                    struct link_config_limits *limits,
1796                                    u16 compressed_bppx16,
1797                                    int timeslots)
1798 {
1799         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1800         int link_rate, lane_count;
1801         int i;
1802
1803         for (i = 0; i < intel_dp->num_common_rates; i++) {
1804                 link_rate = intel_dp_common_rate(intel_dp, i);
1805                 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1806                         continue;
1807
1808                 for (lane_count = limits->min_lane_count;
1809                      lane_count <= limits->max_lane_count;
1810                      lane_count <<= 1) {
1811                         if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1812                                                              lane_count, adjusted_mode->clock,
1813                                                              pipe_config->output_format,
1814                                                              timeslots))
1815                                 continue;
1816
1817                         pipe_config->lane_count = lane_count;
1818                         pipe_config->port_clock = link_rate;
1819
1820                         return 0;
1821                 }
1822         }
1823
1824         return -EINVAL;
1825 }
1826
1827 static
1828 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1829                                             struct intel_crtc_state *pipe_config,
1830                                             int bpc)
1831 {
1832         u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1833
1834         if (max_bppx16)
1835                 return max_bppx16;
1836         /*
1837          * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1838          * values as given in spec Table 2-157 DP v2.0
1839          */
1840         switch (pipe_config->output_format) {
1841         case INTEL_OUTPUT_FORMAT_RGB:
1842         case INTEL_OUTPUT_FORMAT_YCBCR444:
1843                 return (3 * bpc) << 4;
1844         case INTEL_OUTPUT_FORMAT_YCBCR420:
1845                 return (3 * (bpc / 2)) << 4;
1846         default:
1847                 MISSING_CASE(pipe_config->output_format);
1848                 break;
1849         }
1850
1851         return 0;
1852 }
1853
1854 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1855 {
1856         /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1857         switch (pipe_config->output_format) {
1858         case INTEL_OUTPUT_FORMAT_RGB:
1859         case INTEL_OUTPUT_FORMAT_YCBCR444:
1860                 return 8;
1861         case INTEL_OUTPUT_FORMAT_YCBCR420:
1862                 return 6;
1863         default:
1864                 MISSING_CASE(pipe_config->output_format);
1865                 break;
1866         }
1867
1868         return 0;
1869 }
1870
1871 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
1872                                          struct intel_crtc_state *pipe_config,
1873                                          int bpc)
1874 {
1875         return intel_dp_dsc_max_sink_compressed_bppx16(connector,
1876                                                        pipe_config, bpc) >> 4;
1877 }
1878
1879 static int dsc_src_min_compressed_bpp(void)
1880 {
1881         /* Min Compressed bpp supported by source is 8 */
1882         return 8;
1883 }
1884
1885 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1886 {
1887         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1888
1889         /*
1890          * Max Compressed bpp for Gen 13+ is 27bpp.
1891          * For earlier platform is 23bpp. (Bspec:49259).
1892          */
1893         if (DISPLAY_VER(i915) < 13)
1894                 return 23;
1895         else
1896                 return 27;
1897 }
1898
1899 /*
1900  * From a list of valid compressed bpps try different compressed bpp and find a
1901  * suitable link configuration that can support it.
1902  */
1903 static int
1904 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1905                             struct intel_crtc_state *pipe_config,
1906                             struct link_config_limits *limits,
1907                             int dsc_max_bpp,
1908                             int dsc_min_bpp,
1909                             int pipe_bpp,
1910                             int timeslots)
1911 {
1912         int i, ret;
1913
1914         /* Compressed BPP should be less than the Input DSC bpp */
1915         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1916
1917         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1918                 if (valid_dsc_bpp[i] < dsc_min_bpp)
1919                         continue;
1920                 if (valid_dsc_bpp[i] > dsc_max_bpp)
1921                         break;
1922
1923                 ret = dsc_compute_link_config(intel_dp,
1924                                               pipe_config,
1925                                               limits,
1926                                               valid_dsc_bpp[i] << 4,
1927                                               timeslots);
1928                 if (ret == 0) {
1929                         pipe_config->dsc.compressed_bpp_x16 =
1930                                 to_bpp_x16(valid_dsc_bpp[i]);
1931                         return 0;
1932                 }
1933         }
1934
1935         return -EINVAL;
1936 }
1937
1938 /*
1939  * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1940  * uncompressed bpp-1. So we start from max compressed bpp and see if any
1941  * link configuration is able to support that compressed bpp, if not we
1942  * step down and check for lower compressed bpp.
1943  */
1944 static int
1945 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1946                               const struct intel_connector *connector,
1947                               struct intel_crtc_state *pipe_config,
1948                               struct link_config_limits *limits,
1949                               int dsc_max_bpp,
1950                               int dsc_min_bpp,
1951                               int pipe_bpp,
1952                               int timeslots)
1953 {
1954         u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
1955         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1956         u16 compressed_bppx16;
1957         u8 bppx16_step;
1958         int ret;
1959
1960         if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
1961                 bppx16_step = 16;
1962         else
1963                 bppx16_step = 16 / bppx16_incr;
1964
1965         /* Compressed BPP should be less than the Input DSC bpp */
1966         dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
1967         dsc_min_bpp = dsc_min_bpp << 4;
1968
1969         for (compressed_bppx16 = dsc_max_bpp;
1970              compressed_bppx16 >= dsc_min_bpp;
1971              compressed_bppx16 -= bppx16_step) {
1972                 if (intel_dp->force_dsc_fractional_bpp_en &&
1973                     !to_bpp_frac(compressed_bppx16))
1974                         continue;
1975                 ret = dsc_compute_link_config(intel_dp,
1976                                               pipe_config,
1977                                               limits,
1978                                               compressed_bppx16,
1979                                               timeslots);
1980                 if (ret == 0) {
1981                         pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
1982                         if (intel_dp->force_dsc_fractional_bpp_en &&
1983                             to_bpp_frac(compressed_bppx16))
1984                                 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
1985
1986                         return 0;
1987                 }
1988         }
1989         return -EINVAL;
1990 }
1991
1992 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1993                                       const struct intel_connector *connector,
1994                                       struct intel_crtc_state *pipe_config,
1995                                       struct link_config_limits *limits,
1996                                       int pipe_bpp,
1997                                       int timeslots)
1998 {
1999         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2000         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2001         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2002         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2003         int dsc_joiner_max_bpp;
2004
2005         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2006         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2007         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2008         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2009
2010         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2011         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2012                                                                 pipe_config,
2013                                                                 pipe_bpp / 3);
2014         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2015
2016         dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2017                                                                 adjusted_mode->hdisplay,
2018                                                                 pipe_config->bigjoiner_pipes);
2019         dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2020         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2021
2022         if (DISPLAY_VER(i915) >= 13)
2023                 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2024                                                      dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2025         return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2026                                            dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2027 }
2028
2029 static
2030 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2031 {
2032         /* Min DSC Input BPC for ICL+ is 8 */
2033         return HAS_DSC(i915) ? 8 : 0;
2034 }
2035
2036 static
2037 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2038                                 struct drm_connector_state *conn_state,
2039                                 struct link_config_limits *limits,
2040                                 int pipe_bpp)
2041 {
2042         u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2043
2044         dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2045         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2046
2047         dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2048         dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2049
2050         return pipe_bpp >= dsc_min_pipe_bpp &&
2051                pipe_bpp <= dsc_max_pipe_bpp;
2052 }
2053
2054 static
2055 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2056                                 struct drm_connector_state *conn_state,
2057                                 struct link_config_limits *limits)
2058 {
2059         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2060         int forced_bpp;
2061
2062         if (!intel_dp->force_dsc_bpc)
2063                 return 0;
2064
2065         forced_bpp = intel_dp->force_dsc_bpc * 3;
2066
2067         if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2068                 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2069                 return forced_bpp;
2070         }
2071
2072         drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2073                     intel_dp->force_dsc_bpc);
2074
2075         return 0;
2076 }
2077
2078 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2079                                          struct intel_crtc_state *pipe_config,
2080                                          struct drm_connector_state *conn_state,
2081                                          struct link_config_limits *limits,
2082                                          int timeslots)
2083 {
2084         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2085         const struct intel_connector *connector =
2086                 to_intel_connector(conn_state->connector);
2087         u8 max_req_bpc = conn_state->max_requested_bpc;
2088         u8 dsc_max_bpc, dsc_max_bpp;
2089         u8 dsc_min_bpc, dsc_min_bpp;
2090         u8 dsc_bpc[3] = {};
2091         int forced_bpp, pipe_bpp;
2092         int num_bpc, i, ret;
2093
2094         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2095
2096         if (forced_bpp) {
2097                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2098                                                  limits, forced_bpp, timeslots);
2099                 if (ret == 0) {
2100                         pipe_config->pipe_bpp = forced_bpp;
2101                         return 0;
2102                 }
2103         }
2104
2105         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2106         if (!dsc_max_bpc)
2107                 return -EINVAL;
2108
2109         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2110         dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2111
2112         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2113         dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2114
2115         /*
2116          * Get the maximum DSC bpc that will be supported by any valid
2117          * link configuration and compressed bpp.
2118          */
2119         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2120         for (i = 0; i < num_bpc; i++) {
2121                 pipe_bpp = dsc_bpc[i] * 3;
2122                 if (pipe_bpp < dsc_min_bpp)
2123                         break;
2124                 if (pipe_bpp > dsc_max_bpp)
2125                         continue;
2126                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2127                                                  limits, pipe_bpp, timeslots);
2128                 if (ret == 0) {
2129                         pipe_config->pipe_bpp = pipe_bpp;
2130                         return 0;
2131                 }
2132         }
2133
2134         return -EINVAL;
2135 }
2136
2137 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2138                                           struct intel_crtc_state *pipe_config,
2139                                           struct drm_connector_state *conn_state,
2140                                           struct link_config_limits *limits)
2141 {
2142         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2143         struct intel_connector *connector =
2144                 to_intel_connector(conn_state->connector);
2145         int pipe_bpp, forced_bpp;
2146         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2147         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2148
2149         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2150
2151         if (forced_bpp) {
2152                 pipe_bpp = forced_bpp;
2153         } else {
2154                 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2155
2156                 /* For eDP use max bpp that can be supported with DSC. */
2157                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2158                 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2159                         drm_dbg_kms(&i915->drm,
2160                                     "Computed BPC is not in DSC BPC limits\n");
2161                         return -EINVAL;
2162                 }
2163         }
2164         pipe_config->port_clock = limits->max_rate;
2165         pipe_config->lane_count = limits->max_lane_count;
2166
2167         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2168         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2169         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2170         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2171
2172         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2173         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2174                                                                 pipe_config,
2175                                                                 pipe_bpp / 3);
2176         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2177         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2178
2179         /* Compressed BPP should be less than the Input DSC bpp */
2180         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2181
2182         pipe_config->dsc.compressed_bpp_x16 =
2183                 to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
2184
2185         pipe_config->pipe_bpp = pipe_bpp;
2186
2187         return 0;
2188 }
2189
2190 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2191                                 struct intel_crtc_state *pipe_config,
2192                                 struct drm_connector_state *conn_state,
2193                                 struct link_config_limits *limits,
2194                                 int timeslots,
2195                                 bool compute_pipe_bpp)
2196 {
2197         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2198         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2199         const struct intel_connector *connector =
2200                 to_intel_connector(conn_state->connector);
2201         const struct drm_display_mode *adjusted_mode =
2202                 &pipe_config->hw.adjusted_mode;
2203         int ret;
2204
2205         pipe_config->fec_enable = pipe_config->fec_enable ||
2206                 (!intel_dp_is_edp(intel_dp) &&
2207                  intel_dp_supports_fec(intel_dp, connector, pipe_config));
2208
2209         if (!intel_dp_supports_dsc(connector, pipe_config))
2210                 return -EINVAL;
2211
2212         if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2213                 return -EINVAL;
2214
2215         /*
2216          * compute pipe bpp is set to false for DP MST DSC case
2217          * and compressed_bpp is calculated same time once
2218          * vpci timeslots are allocated, because overall bpp
2219          * calculation procedure is bit different for MST case.
2220          */
2221         if (compute_pipe_bpp) {
2222                 if (intel_dp_is_edp(intel_dp))
2223                         ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2224                                                              conn_state, limits);
2225                 else
2226                         ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2227                                                             conn_state, limits, timeslots);
2228                 if (ret) {
2229                         drm_dbg_kms(&dev_priv->drm,
2230                                     "No Valid pipe bpp for given mode ret = %d\n", ret);
2231                         return ret;
2232                 }
2233         }
2234
2235         /* Calculate Slice count */
2236         if (intel_dp_is_edp(intel_dp)) {
2237                 pipe_config->dsc.slice_count =
2238                         drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2239                                                         true);
2240                 if (!pipe_config->dsc.slice_count) {
2241                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2242                                     pipe_config->dsc.slice_count);
2243                         return -EINVAL;
2244                 }
2245         } else {
2246                 u8 dsc_dp_slice_count;
2247
2248                 dsc_dp_slice_count =
2249                         intel_dp_dsc_get_slice_count(connector,
2250                                                      adjusted_mode->crtc_clock,
2251                                                      adjusted_mode->crtc_hdisplay,
2252                                                      pipe_config->bigjoiner_pipes);
2253                 if (!dsc_dp_slice_count) {
2254                         drm_dbg_kms(&dev_priv->drm,
2255                                     "Compressed Slice Count not supported\n");
2256                         return -EINVAL;
2257                 }
2258
2259                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2260         }
2261         /*
2262          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2263          * is greater than the maximum Cdclock and if slice count is even
2264          * then we need to use 2 VDSC instances.
2265          */
2266         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
2267                 pipe_config->dsc.dsc_split = true;
2268
2269         ret = intel_dp_dsc_compute_params(connector, pipe_config);
2270         if (ret < 0) {
2271                 drm_dbg_kms(&dev_priv->drm,
2272                             "Cannot compute valid DSC parameters for Input Bpp = %d"
2273                             "Compressed BPP = " BPP_X16_FMT "\n",
2274                             pipe_config->pipe_bpp,
2275                             BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2276                 return ret;
2277         }
2278
2279         pipe_config->dsc.compression_enable = true;
2280         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2281                     "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
2282                     pipe_config->pipe_bpp,
2283                     BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2284                     pipe_config->dsc.slice_count);
2285
2286         return 0;
2287 }
2288
2289 /**
2290  * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2291  * @intel_dp: intel DP
2292  * @crtc_state: crtc state
2293  * @dsc: DSC compression mode
2294  * @limits: link configuration limits
2295  *
2296  * Calculates the output link min, max bpp values in @limits based on the
2297  * pipe bpp range, @crtc_state and @dsc mode.
2298  *
2299  * Returns %true in case of success.
2300  */
2301 bool
2302 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2303                                         const struct intel_crtc_state *crtc_state,
2304                                         bool dsc,
2305                                         struct link_config_limits *limits)
2306 {
2307         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2308         const struct drm_display_mode *adjusted_mode =
2309                 &crtc_state->hw.adjusted_mode;
2310         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2311         const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2312         int max_link_bpp_x16;
2313
2314         max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2315                                to_bpp_x16(limits->pipe.max_bpp));
2316
2317         if (!dsc) {
2318                 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2319
2320                 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2321                         return false;
2322
2323                 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2324         } else {
2325                 /*
2326                  * TODO: set the DSC link limits already here, atm these are
2327                  * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2328                  * intel_dp_dsc_compute_pipe_bpp()
2329                  */
2330                 limits->link.min_bpp_x16 = 0;
2331         }
2332
2333         limits->link.max_bpp_x16 = max_link_bpp_x16;
2334
2335         drm_dbg_kms(&i915->drm,
2336                     "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2337                     encoder->base.base.id, encoder->base.name,
2338                     crtc->base.base.id, crtc->base.name,
2339                     adjusted_mode->crtc_clock,
2340                     dsc ? "on" : "off",
2341                     limits->max_lane_count,
2342                     limits->max_rate,
2343                     limits->pipe.max_bpp,
2344                     BPP_X16_ARGS(limits->link.max_bpp_x16));
2345
2346         return true;
2347 }
2348
2349 static bool
2350 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2351                                struct intel_crtc_state *crtc_state,
2352                                bool respect_downstream_limits,
2353                                bool dsc,
2354                                struct link_config_limits *limits)
2355 {
2356         limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2357         limits->max_rate = intel_dp_max_link_rate(intel_dp);
2358
2359         /* FIXME 128b/132b SST support missing */
2360         limits->max_rate = min(limits->max_rate, 810000);
2361
2362         limits->min_lane_count = 1;
2363         limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2364
2365         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2366         limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2367                                                      respect_downstream_limits);
2368
2369         if (intel_dp->use_max_params) {
2370                 /*
2371                  * Use the maximum clock and number of lanes the eDP panel
2372                  * advertizes being capable of in case the initial fast
2373                  * optimal params failed us. The panels are generally
2374                  * designed to support only a single clock and lane
2375                  * configuration, and typically on older panels these
2376                  * values correspond to the native resolution of the panel.
2377                  */
2378                 limits->min_lane_count = limits->max_lane_count;
2379                 limits->min_rate = limits->max_rate;
2380         }
2381
2382         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
2383
2384         return intel_dp_compute_config_link_bpp_limits(intel_dp,
2385                                                        crtc_state,
2386                                                        dsc,
2387                                                        limits);
2388 }
2389
2390 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2391 {
2392         const struct drm_display_mode *adjusted_mode =
2393                 &crtc_state->hw.adjusted_mode;
2394         int bpp = crtc_state->dsc.compression_enable ?
2395                 to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
2396                 crtc_state->pipe_bpp;
2397
2398         return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2399 }
2400
2401 bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915, bool use_joiner)
2402 {
2403         /*
2404          * Pipe joiner needs compression up to display 12 due to bandwidth
2405          * limitation. DG2 onwards pipe joiner can be enabled without
2406          * compression.
2407          */
2408         return DISPLAY_VER(i915) < 13 && use_joiner;
2409 }
2410
2411 static int
2412 intel_dp_compute_link_config(struct intel_encoder *encoder,
2413                              struct intel_crtc_state *pipe_config,
2414                              struct drm_connector_state *conn_state,
2415                              bool respect_downstream_limits)
2416 {
2417         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2418         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2419         struct intel_connector *connector =
2420                 to_intel_connector(conn_state->connector);
2421         const struct drm_display_mode *adjusted_mode =
2422                 &pipe_config->hw.adjusted_mode;
2423         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2424         struct link_config_limits limits;
2425         bool dsc_needed, joiner_needs_dsc;
2426         int ret = 0;
2427
2428         if (pipe_config->fec_enable &&
2429             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2430                 return -EINVAL;
2431
2432         if (intel_dp_need_bigjoiner(intel_dp, connector,
2433                                     adjusted_mode->crtc_hdisplay,
2434                                     adjusted_mode->crtc_clock))
2435                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
2436
2437         joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, pipe_config->bigjoiner_pipes);
2438
2439         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2440                      !intel_dp_compute_config_limits(intel_dp, pipe_config,
2441                                                      respect_downstream_limits,
2442                                                      false,
2443                                                      &limits);
2444
2445         if (!dsc_needed) {
2446                 /*
2447                  * Optimize for slow and wide for everything, because there are some
2448                  * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2449                  */
2450                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2451                                                         conn_state, &limits);
2452                 if (ret)
2453                         dsc_needed = true;
2454         }
2455
2456         if (dsc_needed) {
2457                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2458                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2459                             str_yes_no(intel_dp->force_dsc_en));
2460
2461                 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2462                                                     respect_downstream_limits,
2463                                                     true,
2464                                                     &limits))
2465                         return -EINVAL;
2466
2467                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2468                                                   conn_state, &limits, 64, true);
2469                 if (ret < 0)
2470                         return ret;
2471         }
2472
2473         drm_dbg_kms(&i915->drm,
2474                     "DP lane count %d clock %d bpp input %d compressed " BPP_X16_FMT " link rate required %d available %d\n",
2475                     pipe_config->lane_count, pipe_config->port_clock,
2476                     pipe_config->pipe_bpp,
2477                     BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2478                     intel_dp_config_required_rate(pipe_config),
2479                     intel_dp_max_link_data_rate(intel_dp,
2480                                                 pipe_config->port_clock,
2481                                                 pipe_config->lane_count));
2482
2483         return 0;
2484 }
2485
2486 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2487                                   const struct drm_connector_state *conn_state)
2488 {
2489         const struct intel_digital_connector_state *intel_conn_state =
2490                 to_intel_digital_connector_state(conn_state);
2491         const struct drm_display_mode *adjusted_mode =
2492                 &crtc_state->hw.adjusted_mode;
2493
2494         /*
2495          * Our YCbCr output is always limited range.
2496          * crtc_state->limited_color_range only applies to RGB,
2497          * and it must never be set for YCbCr or we risk setting
2498          * some conflicting bits in TRANSCONF which will mess up
2499          * the colors on the monitor.
2500          */
2501         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2502                 return false;
2503
2504         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2505                 /*
2506                  * See:
2507                  * CEA-861-E - 5.1 Default Encoding Parameters
2508                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2509                  */
2510                 return crtc_state->pipe_bpp != 18 &&
2511                         drm_default_rgb_quant_range(adjusted_mode) ==
2512                         HDMI_QUANTIZATION_RANGE_LIMITED;
2513         } else {
2514                 return intel_conn_state->broadcast_rgb ==
2515                         INTEL_BROADCAST_RGB_LIMITED;
2516         }
2517 }
2518
2519 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2520                                     enum port port)
2521 {
2522         if (IS_G4X(dev_priv))
2523                 return false;
2524         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2525                 return false;
2526
2527         return true;
2528 }
2529
2530 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2531                                              const struct drm_connector_state *conn_state,
2532                                              struct drm_dp_vsc_sdp *vsc)
2533 {
2534         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2535         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2536
2537         if (crtc_state->has_panel_replay) {
2538                 /*
2539                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2540                  * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2541                  * Encoding/Colorimetry Format indication.
2542                  */
2543                 vsc->revision = 0x7;
2544         } else {
2545                 /*
2546                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2547                  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2548                  * Colorimetry Format indication.
2549                  */
2550                 vsc->revision = 0x5;
2551         }
2552
2553         vsc->length = 0x13;
2554
2555         /* DP 1.4a spec, Table 2-120 */
2556         switch (crtc_state->output_format) {
2557         case INTEL_OUTPUT_FORMAT_YCBCR444:
2558                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2559                 break;
2560         case INTEL_OUTPUT_FORMAT_YCBCR420:
2561                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2562                 break;
2563         case INTEL_OUTPUT_FORMAT_RGB:
2564         default:
2565                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2566         }
2567
2568         switch (conn_state->colorspace) {
2569         case DRM_MODE_COLORIMETRY_BT709_YCC:
2570                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2571                 break;
2572         case DRM_MODE_COLORIMETRY_XVYCC_601:
2573                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2574                 break;
2575         case DRM_MODE_COLORIMETRY_XVYCC_709:
2576                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2577                 break;
2578         case DRM_MODE_COLORIMETRY_SYCC_601:
2579                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2580                 break;
2581         case DRM_MODE_COLORIMETRY_OPYCC_601:
2582                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2583                 break;
2584         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2585                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2586                 break;
2587         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2588                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2589                 break;
2590         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2591                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2592                 break;
2593         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2594         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2595                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2596                 break;
2597         default:
2598                 /*
2599                  * RGB->YCBCR color conversion uses the BT.709
2600                  * color space.
2601                  */
2602                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2603                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2604                 else
2605                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2606                 break;
2607         }
2608
2609         vsc->bpc = crtc_state->pipe_bpp / 3;
2610
2611         /* only RGB pixelformat supports 6 bpc */
2612         drm_WARN_ON(&dev_priv->drm,
2613                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2614
2615         /* all YCbCr are always limited range */
2616         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2617         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2618 }
2619
2620 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
2621                                     struct intel_crtc_state *crtc_state)
2622 {
2623         struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
2624         const struct drm_display_mode *adjusted_mode =
2625                 &crtc_state->hw.adjusted_mode;
2626
2627         if (!crtc_state->vrr.enable ||
2628             !intel_dp_as_sdp_supported(intel_dp))
2629                 return;
2630
2631         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
2632
2633         /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
2634         as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
2635         as_sdp->length = 0x9;
2636         as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
2637         as_sdp->vtotal = adjusted_mode->vtotal;
2638         as_sdp->target_rr = 0;
2639         as_sdp->duration_incr_ms = 0;
2640         as_sdp->duration_incr_ms = 0;
2641 }
2642
2643 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2644                                      struct intel_crtc_state *crtc_state,
2645                                      const struct drm_connector_state *conn_state)
2646 {
2647         struct drm_dp_vsc_sdp *vsc;
2648
2649         if ((!intel_dp->colorimetry_support ||
2650              !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2651             !crtc_state->has_psr)
2652                 return;
2653
2654         vsc = &crtc_state->infoframes.vsc;
2655
2656         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2657         vsc->sdp_type = DP_SDP_VSC;
2658
2659         /* Needs colorimetry */
2660         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2661                 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2662                                                  vsc);
2663         } else if (crtc_state->has_psr2) {
2664                 /*
2665                  * [PSR2 without colorimetry]
2666                  * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2667                  * 3D stereo + PSR/PSR2 + Y-coordinate.
2668                  */
2669                 vsc->revision = 0x4;
2670                 vsc->length = 0xe;
2671         } else if (crtc_state->has_panel_replay) {
2672                 /*
2673                  * [Panel Replay without colorimetry info]
2674                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2675                  * VSC SDP supporting 3D stereo + Panel Replay.
2676                  */
2677                 vsc->revision = 0x6;
2678                 vsc->length = 0x10;
2679         } else {
2680                 /*
2681                  * [PSR1]
2682                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2683                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2684                  * higher).
2685                  */
2686                 vsc->revision = 0x2;
2687                 vsc->length = 0x8;
2688         }
2689 }
2690
2691 static void
2692 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2693                                             struct intel_crtc_state *crtc_state,
2694                                             const struct drm_connector_state *conn_state)
2695 {
2696         int ret;
2697         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2698         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2699
2700         if (!conn_state->hdr_output_metadata)
2701                 return;
2702
2703         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2704
2705         if (ret) {
2706                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2707                 return;
2708         }
2709
2710         crtc_state->infoframes.enable |=
2711                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2712 }
2713
2714 static bool can_enable_drrs(struct intel_connector *connector,
2715                             const struct intel_crtc_state *pipe_config,
2716                             const struct drm_display_mode *downclock_mode)
2717 {
2718         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2719
2720         if (pipe_config->vrr.enable)
2721                 return false;
2722
2723         /*
2724          * DRRS and PSR can't be enable together, so giving preference to PSR
2725          * as it allows more power-savings by complete shutting down display,
2726          * so to guarantee this, intel_drrs_compute_config() must be called
2727          * after intel_psr_compute_config().
2728          */
2729         if (pipe_config->has_psr)
2730                 return false;
2731
2732         /* FIXME missing FDI M2/N2 etc. */
2733         if (pipe_config->has_pch_encoder)
2734                 return false;
2735
2736         if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2737                 return false;
2738
2739         return downclock_mode &&
2740                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2741 }
2742
2743 static void
2744 intel_dp_drrs_compute_config(struct intel_connector *connector,
2745                              struct intel_crtc_state *pipe_config,
2746                              int link_bpp_x16)
2747 {
2748         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2749         const struct drm_display_mode *downclock_mode =
2750                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2751         int pixel_clock;
2752
2753         /*
2754          * FIXME all joined pipes share the same transcoder.
2755          * Need to account for that when updating M/N live.
2756          */
2757         if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes)
2758                 pipe_config->update_m_n = true;
2759
2760         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2761                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2762                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2763                 return;
2764         }
2765
2766         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2767                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2768
2769         pipe_config->has_drrs = true;
2770
2771         pixel_clock = downclock_mode->clock;
2772         if (pipe_config->splitter.enable)
2773                 pixel_clock /= pipe_config->splitter.link_count;
2774
2775         intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2776                                pipe_config->port_clock,
2777                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2778                                &pipe_config->dp_m2_n2);
2779
2780         /* FIXME: abstract this better */
2781         if (pipe_config->splitter.enable)
2782                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2783 }
2784
2785 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2786                                struct intel_crtc_state *crtc_state,
2787                                const struct drm_connector_state *conn_state)
2788 {
2789         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2790         const struct intel_digital_connector_state *intel_conn_state =
2791                 to_intel_digital_connector_state(conn_state);
2792         struct intel_connector *connector =
2793                 to_intel_connector(conn_state->connector);
2794
2795         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2796             !intel_dp_port_has_audio(i915, encoder->port))
2797                 return false;
2798
2799         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2800                 return connector->base.display_info.has_audio;
2801         else
2802                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2803 }
2804
2805 static int
2806 intel_dp_compute_output_format(struct intel_encoder *encoder,
2807                                struct intel_crtc_state *crtc_state,
2808                                struct drm_connector_state *conn_state,
2809                                bool respect_downstream_limits)
2810 {
2811         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2812         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2813         struct intel_connector *connector = intel_dp->attached_connector;
2814         const struct drm_display_info *info = &connector->base.display_info;
2815         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2816         bool ycbcr_420_only;
2817         int ret;
2818
2819         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2820
2821         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2822                 drm_dbg_kms(&i915->drm,
2823                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2824                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2825         } else {
2826                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2827         }
2828
2829         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2830
2831         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2832                                            respect_downstream_limits);
2833         if (ret) {
2834                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2835                     !connector->base.ycbcr_420_allowed ||
2836                     !drm_mode_is_420_also(info, adjusted_mode))
2837                         return ret;
2838
2839                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2840                 crtc_state->output_format = intel_dp_output_format(connector,
2841                                                                    crtc_state->sink_format);
2842                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2843                                                    respect_downstream_limits);
2844         }
2845
2846         return ret;
2847 }
2848
2849 void
2850 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2851                               struct intel_crtc_state *pipe_config,
2852                               struct drm_connector_state *conn_state)
2853 {
2854         pipe_config->has_audio =
2855                 intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2856                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2857
2858         pipe_config->sdp_split_enable = pipe_config->has_audio &&
2859                                         intel_dp_is_uhbr(pipe_config);
2860 }
2861
2862 void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
2863 {
2864         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2865
2866         drm_connector_get(&connector->base);
2867         if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))
2868                 drm_connector_put(&connector->base);
2869 }
2870
2871 void
2872 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
2873                                       struct intel_encoder *encoder,
2874                                       const struct intel_crtc_state *crtc_state)
2875 {
2876         struct intel_connector *connector;
2877         struct intel_digital_connector_state *conn_state;
2878         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2879         int i;
2880
2881         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2882                 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);
2883
2884                 return;
2885         }
2886
2887         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
2888                 if (!conn_state->base.crtc)
2889                         continue;
2890
2891                 if (connector->mst_port == intel_dp)
2892                         intel_dp_queue_modeset_retry_work(connector);
2893         }
2894 }
2895
2896 int
2897 intel_dp_compute_config(struct intel_encoder *encoder,
2898                         struct intel_crtc_state *pipe_config,
2899                         struct drm_connector_state *conn_state)
2900 {
2901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2902         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
2903         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2904         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2905         const struct drm_display_mode *fixed_mode;
2906         struct intel_connector *connector = intel_dp->attached_connector;
2907         int ret = 0, link_bpp_x16;
2908
2909         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2910                 pipe_config->has_pch_encoder = true;
2911
2912         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2913         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2914                 ret = intel_panel_compute_config(connector, adjusted_mode);
2915                 if (ret)
2916                         return ret;
2917         }
2918
2919         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2920                 return -EINVAL;
2921
2922         if (!connector->base.interlace_allowed &&
2923             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2924                 return -EINVAL;
2925
2926         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2927                 return -EINVAL;
2928
2929         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2930                 return -EINVAL;
2931
2932         /*
2933          * Try to respect downstream TMDS clock limits first, if
2934          * that fails assume the user might know something we don't.
2935          */
2936         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2937         if (ret)
2938                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2939         if (ret)
2940                 return ret;
2941
2942         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2943             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2944                 ret = intel_panel_fitting(pipe_config, conn_state);
2945                 if (ret)
2946                         return ret;
2947         }
2948
2949         pipe_config->limited_color_range =
2950                 intel_dp_limited_color_range(pipe_config, conn_state);
2951
2952         pipe_config->enhanced_framing =
2953                 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2954
2955         if (pipe_config->dsc.compression_enable)
2956                 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
2957         else
2958                 link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
2959                                                               pipe_config->pipe_bpp));
2960
2961         if (intel_dp->mso_link_count) {
2962                 int n = intel_dp->mso_link_count;
2963                 int overlap = intel_dp->mso_pixel_overlap;
2964
2965                 pipe_config->splitter.enable = true;
2966                 pipe_config->splitter.link_count = n;
2967                 pipe_config->splitter.pixel_overlap = overlap;
2968
2969                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2970                             n, overlap);
2971
2972                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2973                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2974                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2975                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2976                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2977                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2978                 adjusted_mode->crtc_clock /= n;
2979         }
2980
2981         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2982
2983         intel_link_compute_m_n(link_bpp_x16,
2984                                pipe_config->lane_count,
2985                                adjusted_mode->crtc_clock,
2986                                pipe_config->port_clock,
2987                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2988                                &pipe_config->dp_m_n);
2989
2990         /* FIXME: abstract this better */
2991         if (pipe_config->splitter.enable)
2992                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2993
2994         if (!HAS_DDI(dev_priv))
2995                 g4x_dp_set_clock(encoder, pipe_config);
2996
2997         intel_vrr_compute_config(pipe_config, conn_state);
2998         intel_dp_compute_as_sdp(intel_dp, pipe_config);
2999         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
3000         intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
3001         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
3002         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
3003
3004         return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
3005                                                         pipe_config);
3006 }
3007
3008 void intel_dp_set_link_params(struct intel_dp *intel_dp,
3009                               int link_rate, int lane_count)
3010 {
3011         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3012         intel_dp->link_trained = false;
3013         intel_dp->link_rate = link_rate;
3014         intel_dp->lane_count = lane_count;
3015 }
3016
3017 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
3018 {
3019         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
3020         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
3021 }
3022
3023 /* Enable backlight PWM and backlight PP control. */
3024 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3025                             const struct drm_connector_state *conn_state)
3026 {
3027         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3028         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3029
3030         if (!intel_dp_is_edp(intel_dp))
3031                 return;
3032
3033         drm_dbg_kms(&i915->drm, "\n");
3034
3035         intel_backlight_enable(crtc_state, conn_state);
3036         intel_pps_backlight_on(intel_dp);
3037 }
3038
3039 /* Disable backlight PP control and backlight PWM. */
3040 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3041 {
3042         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3043         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3044
3045         if (!intel_dp_is_edp(intel_dp))
3046                 return;
3047
3048         drm_dbg_kms(&i915->drm, "\n");
3049
3050         intel_pps_backlight_off(intel_dp);
3051         intel_backlight_disable(old_conn_state);
3052 }
3053
3054 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3055 {
3056         /*
3057          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3058          * be capable of signalling downstream hpd with a long pulse.
3059          * Whether or not that means D3 is safe to use is not clear,
3060          * but let's assume so until proven otherwise.
3061          *
3062          * FIXME should really check all downstream ports...
3063          */
3064         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3065                 drm_dp_is_branch(intel_dp->dpcd) &&
3066                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3067 }
3068
3069 static int
3070 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3071 {
3072         int err;
3073         u8 val;
3074
3075         err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3076         if (err < 0)
3077                 return err;
3078
3079         if (set)
3080                 val |= flag;
3081         else
3082                 val &= ~flag;
3083
3084         return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3085 }
3086
3087 static void
3088 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3089                                     bool enable)
3090 {
3091         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3092
3093         if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3094                                          DP_DECOMPRESSION_EN, enable) < 0)
3095                 drm_dbg_kms(&i915->drm,
3096                             "Failed to %s sink decompression state\n",
3097                             str_enable_disable(enable));
3098 }
3099
3100 static void
3101 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3102                                   bool enable)
3103 {
3104         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3105         struct drm_dp_aux *aux = connector->port ?
3106                                  connector->port->passthrough_aux : NULL;
3107
3108         if (!aux)
3109                 return;
3110
3111         if (write_dsc_decompression_flag(aux,
3112                                          DP_DSC_PASSTHROUGH_EN, enable) < 0)
3113                 drm_dbg_kms(&i915->drm,
3114                             "Failed to %s sink compression passthrough state\n",
3115                             str_enable_disable(enable));
3116 }
3117
3118 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3119                                       const struct intel_connector *connector,
3120                                       bool for_get_ref)
3121 {
3122         struct drm_i915_private *i915 = to_i915(state->base.dev);
3123         struct drm_connector *_connector_iter;
3124         struct drm_connector_state *old_conn_state;
3125         struct drm_connector_state *new_conn_state;
3126         int ref_count = 0;
3127         int i;
3128
3129         /*
3130          * On SST the decompression AUX device won't be shared, each connector
3131          * uses for this its own AUX targeting the sink device.
3132          */
3133         if (!connector->mst_port)
3134                 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3135
3136         for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3137                                            old_conn_state, new_conn_state, i) {
3138                 const struct intel_connector *
3139                         connector_iter = to_intel_connector(_connector_iter);
3140
3141                 if (connector_iter->mst_port != connector->mst_port)
3142                         continue;
3143
3144                 if (!connector_iter->dp.dsc_decompression_enabled)
3145                         continue;
3146
3147                 drm_WARN_ON(&i915->drm,
3148                             (for_get_ref && !new_conn_state->crtc) ||
3149                             (!for_get_ref && !old_conn_state->crtc));
3150
3151                 if (connector_iter->dp.dsc_decompression_aux ==
3152                     connector->dp.dsc_decompression_aux)
3153                         ref_count++;
3154         }
3155
3156         return ref_count;
3157 }
3158
3159 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3160                                      struct intel_connector *connector)
3161 {
3162         bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3163
3164         connector->dp.dsc_decompression_enabled = true;
3165
3166         return ret;
3167 }
3168
3169 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3170                                      struct intel_connector *connector)
3171 {
3172         connector->dp.dsc_decompression_enabled = false;
3173
3174         return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3175 }
3176
3177 /**
3178  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3179  * @state: atomic state
3180  * @connector: connector to enable the decompression for
3181  * @new_crtc_state: new state for the CRTC driving @connector
3182  *
3183  * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3184  * register of the appropriate sink/branch device. On SST this is always the
3185  * sink device, whereas on MST based on each device's DSC capabilities it's
3186  * either the last branch device (enabling decompression in it) or both the
3187  * last branch device (enabling passthrough in it) and the sink device
3188  * (enabling decompression in it).
3189  */
3190 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3191                                         struct intel_connector *connector,
3192                                         const struct intel_crtc_state *new_crtc_state)
3193 {
3194         struct drm_i915_private *i915 = to_i915(state->base.dev);
3195
3196         if (!new_crtc_state->dsc.compression_enable)
3197                 return;
3198
3199         if (drm_WARN_ON(&i915->drm,
3200                         !connector->dp.dsc_decompression_aux ||
3201                         connector->dp.dsc_decompression_enabled))
3202                 return;
3203
3204         if (!intel_dp_dsc_aux_get_ref(state, connector))
3205                 return;
3206
3207         intel_dp_sink_set_dsc_passthrough(connector, true);
3208         intel_dp_sink_set_dsc_decompression(connector, true);
3209 }
3210
3211 /**
3212  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3213  * @state: atomic state
3214  * @connector: connector to disable the decompression for
3215  * @old_crtc_state: old state for the CRTC driving @connector
3216  *
3217  * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3218  * register of the appropriate sink/branch device, corresponding to the
3219  * sequence in intel_dp_sink_enable_decompression().
3220  */
3221 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3222                                          struct intel_connector *connector,
3223                                          const struct intel_crtc_state *old_crtc_state)
3224 {
3225         struct drm_i915_private *i915 = to_i915(state->base.dev);
3226
3227         if (!old_crtc_state->dsc.compression_enable)
3228                 return;
3229
3230         if (drm_WARN_ON(&i915->drm,
3231                         !connector->dp.dsc_decompression_aux ||
3232                         !connector->dp.dsc_decompression_enabled))
3233                 return;
3234
3235         if (!intel_dp_dsc_aux_put_ref(state, connector))
3236                 return;
3237
3238         intel_dp_sink_set_dsc_decompression(connector, false);
3239         intel_dp_sink_set_dsc_passthrough(connector, false);
3240 }
3241
3242 static void
3243 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
3244 {
3245         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3246         u8 oui[] = { 0x00, 0xaa, 0x01 };
3247         u8 buf[3] = {};
3248
3249         /*
3250          * During driver init, we want to be careful and avoid changing the source OUI if it's
3251          * already set to what we want, so as to avoid clearing any state by accident
3252          */
3253         if (careful) {
3254                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3255                         drm_err(&i915->drm, "Failed to read source OUI\n");
3256
3257                 if (memcmp(oui, buf, sizeof(oui)) == 0)
3258                         return;
3259         }
3260
3261         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
3262                 drm_err(&i915->drm, "Failed to write source OUI\n");
3263
3264         intel_dp->last_oui_write = jiffies;
3265 }
3266
3267 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3268 {
3269         struct intel_connector *connector = intel_dp->attached_connector;
3270         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3271
3272         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3273                     connector->base.base.id, connector->base.name,
3274                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3275
3276         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3277                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3278 }
3279
3280 /* If the device supports it, try to set the power state appropriately */
3281 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3282 {
3283         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3284         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3285         int ret, i;
3286
3287         /* Should have a valid DPCD by this point */
3288         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3289                 return;
3290
3291         if (mode != DP_SET_POWER_D0) {
3292                 if (downstream_hpd_needs_d0(intel_dp))
3293                         return;
3294
3295                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3296         } else {
3297                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3298
3299                 lspcon_resume(dp_to_dig_port(intel_dp));
3300
3301                 /* Write the source OUI as early as possible */
3302                 if (intel_dp_is_edp(intel_dp))
3303                         intel_edp_init_source_oui(intel_dp, false);
3304
3305                 /*
3306                  * When turning on, we need to retry for 1ms to give the sink
3307                  * time to wake up.
3308                  */
3309                 for (i = 0; i < 3; i++) {
3310                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3311                         if (ret == 1)
3312                                 break;
3313                         msleep(1);
3314                 }
3315
3316                 if (ret == 1 && lspcon->active)
3317                         lspcon_wait_pcon_mode(lspcon);
3318         }
3319
3320         if (ret != 1)
3321                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3322                             encoder->base.base.id, encoder->base.name,
3323                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3324 }
3325
3326 static bool
3327 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3328
3329 /**
3330  * intel_dp_sync_state - sync the encoder state during init/resume
3331  * @encoder: intel encoder to sync
3332  * @crtc_state: state for the CRTC connected to the encoder
3333  *
3334  * Sync any state stored in the encoder wrt. HW state during driver init
3335  * and system resume.
3336  */
3337 void intel_dp_sync_state(struct intel_encoder *encoder,
3338                          const struct intel_crtc_state *crtc_state)
3339 {
3340         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3341         bool dpcd_updated = false;
3342
3343         /*
3344          * Don't clobber DPCD if it's been already read out during output
3345          * setup (eDP) or detect.
3346          */
3347         if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3348                 intel_dp_get_dpcd(intel_dp);
3349                 dpcd_updated = true;
3350         }
3351
3352         intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3353
3354         if (crtc_state)
3355                 intel_dp_reset_max_link_params(intel_dp);
3356 }
3357
3358 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3359                                     struct intel_crtc_state *crtc_state)
3360 {
3361         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3362         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3363         bool fastset = true;
3364
3365         /*
3366          * If BIOS has set an unsupported or non-standard link rate for some
3367          * reason force an encoder recompute and full modeset.
3368          */
3369         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3370                                 crtc_state->port_clock) < 0) {
3371                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3372                             encoder->base.base.id, encoder->base.name);
3373                 crtc_state->uapi.connectors_changed = true;
3374                 fastset = false;
3375         }
3376
3377         /*
3378          * FIXME hack to force full modeset when DSC is being used.
3379          *
3380          * As long as we do not have full state readout and config comparison
3381          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3382          * Remove once we have readout for DSC.
3383          */
3384         if (crtc_state->dsc.compression_enable) {
3385                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3386                             encoder->base.base.id, encoder->base.name);
3387                 crtc_state->uapi.mode_changed = true;
3388                 fastset = false;
3389         }
3390
3391         if (CAN_PANEL_REPLAY(intel_dp)) {
3392                 drm_dbg_kms(&i915->drm,
3393                             "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3394                             encoder->base.base.id, encoder->base.name);
3395                 crtc_state->uapi.mode_changed = true;
3396                 fastset = false;
3397         }
3398
3399         return fastset;
3400 }
3401
3402 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3403 {
3404         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3405
3406         /* Clear the cached register set to avoid using stale values */
3407
3408         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3409
3410         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3411                              intel_dp->pcon_dsc_dpcd,
3412                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3413                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3414                         DP_PCON_DSC_ENCODER);
3415
3416         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3417                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3418 }
3419
3420 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3421 {
3422         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3423         int i;
3424
3425         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3426                 if (frl_bw_mask & (1 << i))
3427                         return bw_gbps[i];
3428         }
3429         return 0;
3430 }
3431
3432 static int intel_dp_pcon_set_frl_mask(int max_frl)
3433 {
3434         switch (max_frl) {
3435         case 48:
3436                 return DP_PCON_FRL_BW_MASK_48GBPS;
3437         case 40:
3438                 return DP_PCON_FRL_BW_MASK_40GBPS;
3439         case 32:
3440                 return DP_PCON_FRL_BW_MASK_32GBPS;
3441         case 24:
3442                 return DP_PCON_FRL_BW_MASK_24GBPS;
3443         case 18:
3444                 return DP_PCON_FRL_BW_MASK_18GBPS;
3445         case 9:
3446                 return DP_PCON_FRL_BW_MASK_9GBPS;
3447         }
3448
3449         return 0;
3450 }
3451
3452 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3453 {
3454         struct intel_connector *intel_connector = intel_dp->attached_connector;
3455         struct drm_connector *connector = &intel_connector->base;
3456         int max_frl_rate;
3457         int max_lanes, rate_per_lane;
3458         int max_dsc_lanes, dsc_rate_per_lane;
3459
3460         max_lanes = connector->display_info.hdmi.max_lanes;
3461         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3462         max_frl_rate = max_lanes * rate_per_lane;
3463
3464         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3465                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3466                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3467                 if (max_dsc_lanes && dsc_rate_per_lane)
3468                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3469         }
3470
3471         return max_frl_rate;
3472 }
3473
3474 static bool
3475 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3476                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
3477 {
3478         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3479             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3480             *frl_trained_mask >= max_frl_bw_mask)
3481                 return true;
3482
3483         return false;
3484 }
3485
3486 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3487 {
3488 #define TIMEOUT_FRL_READY_MS 500
3489 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3490
3491         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3492         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3493         u8 max_frl_bw_mask = 0, frl_trained_mask;
3494         bool is_active;
3495
3496         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3497         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3498
3499         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3500         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3501
3502         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3503
3504         if (max_frl_bw <= 0)
3505                 return -EINVAL;
3506
3507         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3508         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3509
3510         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3511                 goto frl_trained;
3512
3513         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3514         if (ret < 0)
3515                 return ret;
3516         /* Wait for PCON to be FRL Ready */
3517         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3518
3519         if (!is_active)
3520                 return -ETIMEDOUT;
3521
3522         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3523                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
3524         if (ret < 0)
3525                 return ret;
3526         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3527                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
3528         if (ret < 0)
3529                 return ret;
3530         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3531         if (ret < 0)
3532                 return ret;
3533         /*
3534          * Wait for FRL to be completed
3535          * Check if the HDMI Link is up and active.
3536          */
3537         wait_for(is_active =
3538                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3539                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
3540
3541         if (!is_active)
3542                 return -ETIMEDOUT;
3543
3544 frl_trained:
3545         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3546         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3547         intel_dp->frl.is_trained = true;
3548         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3549
3550         return 0;
3551 }
3552
3553 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3554 {
3555         if (drm_dp_is_branch(intel_dp->dpcd) &&
3556             intel_dp_has_hdmi_sink(intel_dp) &&
3557             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3558                 return true;
3559
3560         return false;
3561 }
3562
3563 static
3564 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3565 {
3566         int ret;
3567         u8 buf = 0;
3568
3569         /* Set PCON source control mode */
3570         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3571
3572         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3573         if (ret < 0)
3574                 return ret;
3575
3576         /* Set HDMI LINK ENABLE */
3577         buf |= DP_PCON_ENABLE_HDMI_LINK;
3578         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3579         if (ret < 0)
3580                 return ret;
3581
3582         return 0;
3583 }
3584
3585 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3586 {
3587         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3588
3589         /*
3590          * Always go for FRL training if:
3591          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3592          * -sink is HDMI2.1
3593          */
3594         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3595             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3596             intel_dp->frl.is_trained)
3597                 return;
3598
3599         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3600                 int ret, mode;
3601
3602                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3603                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3604                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3605
3606                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3607                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3608         } else {
3609                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3610         }
3611 }
3612
3613 static int
3614 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3615 {
3616         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3617
3618         return intel_hdmi_dsc_get_slice_height(vactive);
3619 }
3620
3621 static int
3622 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3623                              const struct intel_crtc_state *crtc_state)
3624 {
3625         struct intel_connector *intel_connector = intel_dp->attached_connector;
3626         struct drm_connector *connector = &intel_connector->base;
3627         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3628         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3629         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3630         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3631
3632         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3633                                              pcon_max_slice_width,
3634                                              hdmi_max_slices, hdmi_throughput);
3635 }
3636
3637 static int
3638 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3639                           const struct intel_crtc_state *crtc_state,
3640                           int num_slices, int slice_width)
3641 {
3642         struct intel_connector *intel_connector = intel_dp->attached_connector;
3643         struct drm_connector *connector = &intel_connector->base;
3644         int output_format = crtc_state->output_format;
3645         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3646         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3647         int hdmi_max_chunk_bytes =
3648                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3649
3650         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3651                                       num_slices, output_format, hdmi_all_bpp,
3652                                       hdmi_max_chunk_bytes);
3653 }
3654
3655 void
3656 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3657                             const struct intel_crtc_state *crtc_state)
3658 {
3659         u8 pps_param[6];
3660         int slice_height;
3661         int slice_width;
3662         int num_slices;
3663         int bits_per_pixel;
3664         int ret;
3665         struct intel_connector *intel_connector = intel_dp->attached_connector;
3666         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3667         struct drm_connector *connector;
3668         bool hdmi_is_dsc_1_2;
3669
3670         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3671                 return;
3672
3673         if (!intel_connector)
3674                 return;
3675         connector = &intel_connector->base;
3676         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3677
3678         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3679             !hdmi_is_dsc_1_2)
3680                 return;
3681
3682         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3683         if (!slice_height)
3684                 return;
3685
3686         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3687         if (!num_slices)
3688                 return;
3689
3690         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3691                                    num_slices);
3692
3693         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3694                                                    num_slices, slice_width);
3695         if (!bits_per_pixel)
3696                 return;
3697
3698         pps_param[0] = slice_height & 0xFF;
3699         pps_param[1] = slice_height >> 8;
3700         pps_param[2] = slice_width & 0xFF;
3701         pps_param[3] = slice_width >> 8;
3702         pps_param[4] = bits_per_pixel & 0xFF;
3703         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3704
3705         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3706         if (ret < 0)
3707                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3708 }
3709
3710 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3711                                            const struct intel_crtc_state *crtc_state)
3712 {
3713         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3714         bool ycbcr444_to_420 = false;
3715         bool rgb_to_ycbcr = false;
3716         u8 tmp;
3717
3718         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3719                 return;
3720
3721         if (!drm_dp_is_branch(intel_dp->dpcd))
3722                 return;
3723
3724         tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3725
3726         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3727                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3728                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3729                             str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3730
3731         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3732                 switch (crtc_state->output_format) {
3733                 case INTEL_OUTPUT_FORMAT_YCBCR420:
3734                         break;
3735                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3736                         ycbcr444_to_420 = true;
3737                         break;
3738                 case INTEL_OUTPUT_FORMAT_RGB:
3739                         rgb_to_ycbcr = true;
3740                         ycbcr444_to_420 = true;
3741                         break;
3742                 default:
3743                         MISSING_CASE(crtc_state->output_format);
3744                         break;
3745                 }
3746         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3747                 switch (crtc_state->output_format) {
3748                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3749                         break;
3750                 case INTEL_OUTPUT_FORMAT_RGB:
3751                         rgb_to_ycbcr = true;
3752                         break;
3753                 default:
3754                         MISSING_CASE(crtc_state->output_format);
3755                         break;
3756                 }
3757         }
3758
3759         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3760
3761         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3762                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3763                 drm_dbg_kms(&i915->drm,
3764                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3765                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3766
3767         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3768
3769         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3770                 drm_dbg_kms(&i915->drm,
3771                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3772                             str_enable_disable(tmp));
3773 }
3774
3775 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3776 {
3777         u8 dprx = 0;
3778
3779         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3780                               &dprx) != 1)
3781                 return false;
3782         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3783 }
3784
3785 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3786                                    u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3787 {
3788         if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3789                              DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3790                 drm_err(aux->drm_dev,
3791                         "Failed to read DPCD register 0x%x\n",
3792                         DP_DSC_SUPPORT);
3793                 return;
3794         }
3795
3796         drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3797                     DP_DSC_RECEIVER_CAP_SIZE,
3798                     dsc_dpcd);
3799 }
3800
3801 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3802 {
3803         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3804
3805         /*
3806          * Clear the cached register set to avoid using stale values
3807          * for the sinks that do not support DSC.
3808          */
3809         memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3810
3811         /* Clear fec_capable to avoid using stale values */
3812         connector->dp.fec_capability = 0;
3813
3814         if (dpcd_rev < DP_DPCD_REV_14)
3815                 return;
3816
3817         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3818                                connector->dp.dsc_dpcd);
3819
3820         if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3821                               &connector->dp.fec_capability) < 0) {
3822                 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
3823                 return;
3824         }
3825
3826         drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3827                     connector->dp.fec_capability);
3828 }
3829
3830 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
3831 {
3832         if (edp_dpcd_rev < DP_EDP_14)
3833                 return;
3834
3835         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
3836 }
3837
3838 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3839                                      struct drm_display_mode *mode)
3840 {
3841         struct intel_dp *intel_dp = intel_attached_dp(connector);
3842         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3843         int n = intel_dp->mso_link_count;
3844         int overlap = intel_dp->mso_pixel_overlap;
3845
3846         if (!mode || !n)
3847                 return;
3848
3849         mode->hdisplay = (mode->hdisplay - overlap) * n;
3850         mode->hsync_start = (mode->hsync_start - overlap) * n;
3851         mode->hsync_end = (mode->hsync_end - overlap) * n;
3852         mode->htotal = (mode->htotal - overlap) * n;
3853         mode->clock *= n;
3854
3855         drm_mode_set_name(mode);
3856
3857         drm_dbg_kms(&i915->drm,
3858                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3859                     connector->base.base.id, connector->base.name,
3860                     DRM_MODE_ARG(mode));
3861 }
3862
3863 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3864 {
3865         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3866         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3867         struct intel_connector *connector = intel_dp->attached_connector;
3868
3869         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3870                 /*
3871                  * This is a big fat ugly hack.
3872                  *
3873                  * Some machines in UEFI boot mode provide us a VBT that has 18
3874                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3875                  * unknown we fail to light up. Yet the same BIOS boots up with
3876                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3877                  * max, not what it tells us to use.
3878                  *
3879                  * Note: This will still be broken if the eDP panel is not lit
3880                  * up by the BIOS, and thus we can't get the mode at module
3881                  * load.
3882                  */
3883                 drm_dbg_kms(&dev_priv->drm,
3884                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3885                             pipe_bpp, connector->panel.vbt.edp.bpp);
3886                 connector->panel.vbt.edp.bpp = pipe_bpp;
3887         }
3888 }
3889
3890 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3891 {
3892         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3893         struct intel_connector *connector = intel_dp->attached_connector;
3894         struct drm_display_info *info = &connector->base.display_info;
3895         u8 mso;
3896
3897         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3898                 return;
3899
3900         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3901                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3902                 return;
3903         }
3904
3905         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3906         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3907         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3908                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3909                 mso = 0;
3910         }
3911
3912         if (mso) {
3913                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3914                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3915                             info->mso_pixel_overlap);
3916                 if (!HAS_MSO(i915)) {
3917                         drm_err(&i915->drm, "No source MSO support, disabling\n");
3918                         mso = 0;
3919                 }
3920         }
3921
3922         intel_dp->mso_link_count = mso;
3923         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3924 }
3925
3926 static bool
3927 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
3928 {
3929         struct drm_i915_private *dev_priv =
3930                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3931
3932         /* this function is meant to be called only once */
3933         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3934
3935         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3936                 return false;
3937
3938         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3939                          drm_dp_is_branch(intel_dp->dpcd));
3940
3941         /*
3942          * Read the eDP display control registers.
3943          *
3944          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3945          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3946          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3947          * method). The display control registers should read zero if they're
3948          * not supported anyway.
3949          */
3950         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3951                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3952                              sizeof(intel_dp->edp_dpcd)) {
3953                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3954                             (int)sizeof(intel_dp->edp_dpcd),
3955                             intel_dp->edp_dpcd);
3956
3957                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3958         }
3959
3960         /*
3961          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3962          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3963          */
3964         intel_psr_init_dpcd(intel_dp);
3965
3966         /* Clear the default sink rates */
3967         intel_dp->num_sink_rates = 0;
3968
3969         /* Read the eDP 1.4+ supported link rates. */
3970         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3971                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3972                 int i;
3973
3974                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3975                                 sink_rates, sizeof(sink_rates));
3976
3977                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3978                         int val = le16_to_cpu(sink_rates[i]);
3979
3980                         if (val == 0)
3981                                 break;
3982
3983                         /* Value read multiplied by 200kHz gives the per-lane
3984                          * link rate in kHz. The source rates are, however,
3985                          * stored in terms of LS_Clk kHz. The full conversion
3986                          * back to symbols is
3987                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3988                          */
3989                         intel_dp->sink_rates[i] = (val * 200) / 10;
3990                 }
3991                 intel_dp->num_sink_rates = i;
3992         }
3993
3994         /*
3995          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3996          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3997          */
3998         if (intel_dp->num_sink_rates)
3999                 intel_dp->use_rate_select = true;
4000         else
4001                 intel_dp_set_sink_rates(intel_dp);
4002         intel_dp_set_max_sink_lane_count(intel_dp);
4003
4004         /* Read the eDP DSC DPCD registers */
4005         if (HAS_DSC(dev_priv))
4006                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
4007                                            connector);
4008
4009         /*
4010          * If needed, program our source OUI so we can make various Intel-specific AUX services
4011          * available (such as HDR backlight controls)
4012          */
4013         intel_edp_init_source_oui(intel_dp, true);
4014
4015         return true;
4016 }
4017
4018 static bool
4019 intel_dp_has_sink_count(struct intel_dp *intel_dp)
4020 {
4021         if (!intel_dp->attached_connector)
4022                 return false;
4023
4024         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
4025                                           intel_dp->dpcd,
4026                                           &intel_dp->desc);
4027 }
4028
4029 void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
4030 {
4031         intel_dp_set_sink_rates(intel_dp);
4032         intel_dp_set_max_sink_lane_count(intel_dp);
4033         intel_dp_set_common_rates(intel_dp);
4034 }
4035
4036 static bool
4037 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4038 {
4039         int ret;
4040
4041         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4042                 return false;
4043
4044         /*
4045          * Don't clobber cached eDP rates. Also skip re-reading
4046          * the OUI/ID since we know it won't change.
4047          */
4048         if (!intel_dp_is_edp(intel_dp)) {
4049                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4050                                  drm_dp_is_branch(intel_dp->dpcd));
4051
4052                 intel_dp_update_sink_caps(intel_dp);
4053         }
4054
4055         if (intel_dp_has_sink_count(intel_dp)) {
4056                 ret = drm_dp_read_sink_count(&intel_dp->aux);
4057                 if (ret < 0)
4058                         return false;
4059
4060                 /*
4061                  * Sink count can change between short pulse hpd hence
4062                  * a member variable in intel_dp will track any changes
4063                  * between short pulse interrupts.
4064                  */
4065                 intel_dp->sink_count = ret;
4066
4067                 /*
4068                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4069                  * a dongle is present but no display. Unless we require to know
4070                  * if a dongle is present or not, we don't need to update
4071                  * downstream port information. So, an early return here saves
4072                  * time from performing other operations which are not required.
4073                  */
4074                 if (!intel_dp->sink_count)
4075                         return false;
4076         }
4077
4078         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4079                                            intel_dp->downstream_ports) == 0;
4080 }
4081
4082 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)
4083 {
4084         if (mst_mode == DRM_DP_MST)
4085                 return "MST";
4086         else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG)
4087                 return "SST w/ sideband messaging";
4088         else
4089                 return "SST";
4090 }
4091
4092 static enum drm_dp_mst_mode
4093 intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4094                          enum drm_dp_mst_mode sink_mst_mode)
4095 {
4096         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4097
4098         if (!i915->display.params.enable_dp_mst)
4099                 return DRM_DP_SST;
4100
4101         if (!intel_dp_mst_source_support(intel_dp))
4102                 return DRM_DP_SST;
4103
4104         if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG &&
4105             !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))
4106                 return DRM_DP_SST;
4107
4108         return sink_mst_mode;
4109 }
4110
4111 static enum drm_dp_mst_mode
4112 intel_dp_mst_detect(struct intel_dp *intel_dp)
4113 {
4114         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4115         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4116         enum drm_dp_mst_mode sink_mst_mode;
4117         enum drm_dp_mst_mode mst_detect;
4118
4119         sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4120
4121         mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4122
4123         drm_dbg_kms(&i915->drm,
4124                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4125                     encoder->base.base.id, encoder->base.name,
4126                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
4127                     intel_dp_mst_mode_str(sink_mst_mode),
4128                     str_yes_no(i915->display.params.enable_dp_mst),
4129                     intel_dp_mst_mode_str(mst_detect));
4130
4131         return mst_detect;
4132 }
4133
4134 static void
4135 intel_dp_mst_configure(struct intel_dp *intel_dp)
4136 {
4137         if (!intel_dp_mst_source_support(intel_dp))
4138                 return;
4139
4140         intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
4141
4142         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4143
4144         /* Avoid stale info on the next detect cycle. */
4145         intel_dp->mst_detect = DRM_DP_SST;
4146 }
4147
4148 static void
4149 intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4150 {
4151         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4152
4153         if (!intel_dp->is_mst)
4154                 return;
4155
4156         drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n",
4157                     intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4158         intel_dp->is_mst = false;
4159         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4160 }
4161
4162 static bool
4163 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4164 {
4165         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4166 }
4167
4168 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4169 {
4170         int retry;
4171
4172         for (retry = 0; retry < 3; retry++) {
4173                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4174                                       &esi[1], 3) == 3)
4175                         return true;
4176         }
4177
4178         return false;
4179 }
4180
4181 bool
4182 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4183                        const struct drm_connector_state *conn_state)
4184 {
4185         /*
4186          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4187          * of Color Encoding Format and Content Color Gamut], in order to
4188          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4189          */
4190         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4191                 return true;
4192
4193         switch (conn_state->colorspace) {
4194         case DRM_MODE_COLORIMETRY_SYCC_601:
4195         case DRM_MODE_COLORIMETRY_OPYCC_601:
4196         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4197         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4198         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4199                 return true;
4200         default:
4201                 break;
4202         }
4203
4204         return false;
4205 }
4206
4207 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
4208                                     struct dp_sdp *sdp, size_t size)
4209 {
4210         size_t length = sizeof(struct dp_sdp);
4211
4212         if (size < length)
4213                 return -ENOSPC;
4214
4215         memset(sdp, 0, size);
4216
4217         /* Prepare AS (Adaptive Sync) SDP Header */
4218         sdp->sdp_header.HB0 = 0;
4219         sdp->sdp_header.HB1 = as_sdp->sdp_type;
4220         sdp->sdp_header.HB2 = 0x02;
4221         sdp->sdp_header.HB3 = as_sdp->length;
4222
4223         /* Fill AS (Adaptive Sync) SDP Payload */
4224         sdp->db[0] = as_sdp->mode;
4225         sdp->db[1] = as_sdp->vtotal & 0xFF;
4226         sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
4227         sdp->db[3] = as_sdp->target_rr & 0xFF;
4228         sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
4229
4230         return length;
4231 }
4232
4233 static ssize_t
4234 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4235                                          const struct hdmi_drm_infoframe *drm_infoframe,
4236                                          struct dp_sdp *sdp,
4237                                          size_t size)
4238 {
4239         size_t length = sizeof(struct dp_sdp);
4240         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4241         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4242         ssize_t len;
4243
4244         if (size < length)
4245                 return -ENOSPC;
4246
4247         memset(sdp, 0, size);
4248
4249         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4250         if (len < 0) {
4251                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4252                 return -ENOSPC;
4253         }
4254
4255         if (len != infoframe_size) {
4256                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4257                 return -ENOSPC;
4258         }
4259
4260         /*
4261          * Set up the infoframe sdp packet for HDR static metadata.
4262          * Prepare VSC Header for SU as per DP 1.4a spec,
4263          * Table 2-100 and Table 2-101
4264          */
4265
4266         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4267         sdp->sdp_header.HB0 = 0;
4268         /*
4269          * Packet Type 80h + Non-audio INFOFRAME Type value
4270          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4271          * - 80h + Non-audio INFOFRAME Type value
4272          * - InfoFrame Type: 0x07
4273          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4274          */
4275         sdp->sdp_header.HB1 = drm_infoframe->type;
4276         /*
4277          * Least Significant Eight Bits of (Data Byte Count – 1)
4278          * infoframe_size - 1
4279          */
4280         sdp->sdp_header.HB2 = 0x1D;
4281         /* INFOFRAME SDP Version Number */
4282         sdp->sdp_header.HB3 = (0x13 << 2);
4283         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4284         sdp->db[0] = drm_infoframe->version;
4285         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4286         sdp->db[1] = drm_infoframe->length;
4287         /*
4288          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4289          * HDMI_INFOFRAME_HEADER_SIZE
4290          */
4291         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4292         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4293                HDMI_DRM_INFOFRAME_SIZE);
4294
4295         /*
4296          * Size of DP infoframe sdp packet for HDR static metadata consists of
4297          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4298          * - Two Data Blocks: 2 bytes
4299          *    CTA Header Byte2 (INFOFRAME Version Number)
4300          *    CTA Header Byte3 (Length of INFOFRAME)
4301          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4302          *
4303          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4304          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4305          * will pad rest of the size.
4306          */
4307         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4308 }
4309
4310 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4311                                const struct intel_crtc_state *crtc_state,
4312                                unsigned int type)
4313 {
4314         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4315         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4316         struct dp_sdp sdp = {};
4317         ssize_t len;
4318
4319         if ((crtc_state->infoframes.enable &
4320              intel_hdmi_infoframe_enable(type)) == 0)
4321                 return;
4322
4323         switch (type) {
4324         case DP_SDP_VSC:
4325                 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4326                 break;
4327         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4328                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4329                                                                &crtc_state->infoframes.drm.drm,
4330                                                                &sdp, sizeof(sdp));
4331                 break;
4332         case DP_SDP_ADAPTIVE_SYNC:
4333                 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
4334                                            sizeof(sdp));
4335                 break;
4336         default:
4337                 MISSING_CASE(type);
4338                 return;
4339         }
4340
4341         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4342                 return;
4343
4344         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4345 }
4346
4347 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4348                              bool enable,
4349                              const struct intel_crtc_state *crtc_state,
4350                              const struct drm_connector_state *conn_state)
4351 {
4352         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4353         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4354         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4355                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4356                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4357
4358         if (HAS_AS_SDP(dev_priv))
4359                 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4360
4361         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4362
4363         /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4364         if (!enable && HAS_DSC(dev_priv))
4365                 val &= ~VDIP_ENABLE_PPS;
4366
4367         /* When PSR is enabled, this routine doesn't disable VSC DIP */
4368         if (!crtc_state->has_psr)
4369                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4370
4371         intel_de_write(dev_priv, reg, val);
4372         intel_de_posting_read(dev_priv, reg);
4373
4374         if (!enable)
4375                 return;
4376
4377         intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4378         intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
4379
4380         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4381 }
4382
4383 static
4384 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
4385                            const void *buffer, size_t size)
4386 {
4387         const struct dp_sdp *sdp = buffer;
4388
4389         if (size < sizeof(struct dp_sdp))
4390                 return -EINVAL;
4391
4392         memset(as_sdp, 0, sizeof(*as_sdp));
4393
4394         if (sdp->sdp_header.HB0 != 0)
4395                 return -EINVAL;
4396
4397         if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
4398                 return -EINVAL;
4399
4400         if (sdp->sdp_header.HB2 != 0x02)
4401                 return -EINVAL;
4402
4403         if ((sdp->sdp_header.HB3 & 0x3F) != 9)
4404                 return -EINVAL;
4405
4406         as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
4407         as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
4408         as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
4409         as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
4410
4411         return 0;
4412 }
4413
4414 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4415                                    const void *buffer, size_t size)
4416 {
4417         const struct dp_sdp *sdp = buffer;
4418
4419         if (size < sizeof(struct dp_sdp))
4420                 return -EINVAL;
4421
4422         memset(vsc, 0, sizeof(*vsc));
4423
4424         if (sdp->sdp_header.HB0 != 0)
4425                 return -EINVAL;
4426
4427         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4428                 return -EINVAL;
4429
4430         vsc->sdp_type = sdp->sdp_header.HB1;
4431         vsc->revision = sdp->sdp_header.HB2;
4432         vsc->length = sdp->sdp_header.HB3;
4433
4434         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4435             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4436                 /*
4437                  * - HB2 = 0x2, HB3 = 0x8
4438                  *   VSC SDP supporting 3D stereo + PSR
4439                  * - HB2 = 0x4, HB3 = 0xe
4440                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4441                  *   first scan line of the SU region (applies to eDP v1.4b
4442                  *   and higher).
4443                  */
4444                 return 0;
4445         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4446                 /*
4447                  * - HB2 = 0x5, HB3 = 0x13
4448                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4449                  *   Format.
4450                  */
4451                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4452                 vsc->colorimetry = sdp->db[16] & 0xf;
4453                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4454
4455                 switch (sdp->db[17] & 0x7) {
4456                 case 0x0:
4457                         vsc->bpc = 6;
4458                         break;
4459                 case 0x1:
4460                         vsc->bpc = 8;
4461                         break;
4462                 case 0x2:
4463                         vsc->bpc = 10;
4464                         break;
4465                 case 0x3:
4466                         vsc->bpc = 12;
4467                         break;
4468                 case 0x4:
4469                         vsc->bpc = 16;
4470                         break;
4471                 default:
4472                         MISSING_CASE(sdp->db[17] & 0x7);
4473                         return -EINVAL;
4474                 }
4475
4476                 vsc->content_type = sdp->db[18] & 0x7;
4477         } else {
4478                 return -EINVAL;
4479         }
4480
4481         return 0;
4482 }
4483
4484 static void
4485 intel_read_dp_as_sdp(struct intel_encoder *encoder,
4486                      struct intel_crtc_state *crtc_state,
4487                      struct drm_dp_as_sdp *as_sdp)
4488 {
4489         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4490         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4491         unsigned int type = DP_SDP_ADAPTIVE_SYNC;
4492         struct dp_sdp sdp = {};
4493         int ret;
4494
4495         if ((crtc_state->infoframes.enable &
4496              intel_hdmi_infoframe_enable(type)) == 0)
4497                 return;
4498
4499         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4500                                  sizeof(sdp));
4501
4502         ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
4503         if (ret)
4504                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
4505 }
4506
4507 static int
4508 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4509                                            const void *buffer, size_t size)
4510 {
4511         int ret;
4512
4513         const struct dp_sdp *sdp = buffer;
4514
4515         if (size < sizeof(struct dp_sdp))
4516                 return -EINVAL;
4517
4518         if (sdp->sdp_header.HB0 != 0)
4519                 return -EINVAL;
4520
4521         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4522                 return -EINVAL;
4523
4524         /*
4525          * Least Significant Eight Bits of (Data Byte Count – 1)
4526          * 1Dh (i.e., Data Byte Count = 30 bytes).
4527          */
4528         if (sdp->sdp_header.HB2 != 0x1D)
4529                 return -EINVAL;
4530
4531         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4532         if ((sdp->sdp_header.HB3 & 0x3) != 0)
4533                 return -EINVAL;
4534
4535         /* INFOFRAME SDP Version Number */
4536         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4537                 return -EINVAL;
4538
4539         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4540         if (sdp->db[0] != 1)
4541                 return -EINVAL;
4542
4543         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4544         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4545                 return -EINVAL;
4546
4547         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4548                                              HDMI_DRM_INFOFRAME_SIZE);
4549
4550         return ret;
4551 }
4552
4553 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4554                                   struct intel_crtc_state *crtc_state,
4555                                   struct drm_dp_vsc_sdp *vsc)
4556 {
4557         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4559         unsigned int type = DP_SDP_VSC;
4560         struct dp_sdp sdp = {};
4561         int ret;
4562
4563         if ((crtc_state->infoframes.enable &
4564              intel_hdmi_infoframe_enable(type)) == 0)
4565                 return;
4566
4567         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4568
4569         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4570
4571         if (ret)
4572                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4573 }
4574
4575 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4576                                                      struct intel_crtc_state *crtc_state,
4577                                                      struct hdmi_drm_infoframe *drm_infoframe)
4578 {
4579         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4580         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4581         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4582         struct dp_sdp sdp = {};
4583         int ret;
4584
4585         if ((crtc_state->infoframes.enable &
4586             intel_hdmi_infoframe_enable(type)) == 0)
4587                 return;
4588
4589         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4590                                  sizeof(sdp));
4591
4592         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4593                                                          sizeof(sdp));
4594
4595         if (ret)
4596                 drm_dbg_kms(&dev_priv->drm,
4597                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4598 }
4599
4600 void intel_read_dp_sdp(struct intel_encoder *encoder,
4601                        struct intel_crtc_state *crtc_state,
4602                        unsigned int type)
4603 {
4604         switch (type) {
4605         case DP_SDP_VSC:
4606                 intel_read_dp_vsc_sdp(encoder, crtc_state,
4607                                       &crtc_state->infoframes.vsc);
4608                 break;
4609         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4610                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4611                                                          &crtc_state->infoframes.drm.drm);
4612                 break;
4613         case DP_SDP_ADAPTIVE_SYNC:
4614                 intel_read_dp_as_sdp(encoder, crtc_state,
4615                                      &crtc_state->infoframes.as_sdp);
4616                 break;
4617         default:
4618                 MISSING_CASE(type);
4619                 break;
4620         }
4621 }
4622
4623 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4624 {
4625         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4626         int status = 0;
4627         int test_link_rate;
4628         u8 test_lane_count, test_link_bw;
4629         /* (DP CTS 1.2)
4630          * 4.3.1.11
4631          */
4632         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4633         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4634                                    &test_lane_count);
4635
4636         if (status <= 0) {
4637                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4638                 return DP_TEST_NAK;
4639         }
4640         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4641
4642         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4643                                    &test_link_bw);
4644         if (status <= 0) {
4645                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4646                 return DP_TEST_NAK;
4647         }
4648         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4649
4650         /* Validate the requested link rate and lane count */
4651         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4652                                         test_lane_count))
4653                 return DP_TEST_NAK;
4654
4655         intel_dp->compliance.test_lane_count = test_lane_count;
4656         intel_dp->compliance.test_link_rate = test_link_rate;
4657
4658         return DP_TEST_ACK;
4659 }
4660
4661 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4662 {
4663         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4664         u8 test_pattern;
4665         u8 test_misc;
4666         __be16 h_width, v_height;
4667         int status = 0;
4668
4669         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4670         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4671                                    &test_pattern);
4672         if (status <= 0) {
4673                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4674                 return DP_TEST_NAK;
4675         }
4676         if (test_pattern != DP_COLOR_RAMP)
4677                 return DP_TEST_NAK;
4678
4679         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4680                                   &h_width, 2);
4681         if (status <= 0) {
4682                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4683                 return DP_TEST_NAK;
4684         }
4685
4686         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4687                                   &v_height, 2);
4688         if (status <= 0) {
4689                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4690                 return DP_TEST_NAK;
4691         }
4692
4693         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4694                                    &test_misc);
4695         if (status <= 0) {
4696                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4697                 return DP_TEST_NAK;
4698         }
4699         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4700                 return DP_TEST_NAK;
4701         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4702                 return DP_TEST_NAK;
4703         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4704         case DP_TEST_BIT_DEPTH_6:
4705                 intel_dp->compliance.test_data.bpc = 6;
4706                 break;
4707         case DP_TEST_BIT_DEPTH_8:
4708                 intel_dp->compliance.test_data.bpc = 8;
4709                 break;
4710         default:
4711                 return DP_TEST_NAK;
4712         }
4713
4714         intel_dp->compliance.test_data.video_pattern = test_pattern;
4715         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4716         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4717         /* Set test active flag here so userspace doesn't interrupt things */
4718         intel_dp->compliance.test_active = true;
4719
4720         return DP_TEST_ACK;
4721 }
4722
4723 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4724 {
4725         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4726         u8 test_result = DP_TEST_ACK;
4727         struct intel_connector *intel_connector = intel_dp->attached_connector;
4728         struct drm_connector *connector = &intel_connector->base;
4729
4730         if (intel_connector->detect_edid == NULL ||
4731             connector->edid_corrupt ||
4732             intel_dp->aux.i2c_defer_count > 6) {
4733                 /* Check EDID read for NACKs, DEFERs and corruption
4734                  * (DP CTS 1.2 Core r1.1)
4735                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4736                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4737                  *    4.2.2.6 : EDID corruption detected
4738                  * Use failsafe mode for all cases
4739                  */
4740                 if (intel_dp->aux.i2c_nack_count > 0 ||
4741                         intel_dp->aux.i2c_defer_count > 0)
4742                         drm_dbg_kms(&i915->drm,
4743                                     "EDID read had %d NACKs, %d DEFERs\n",
4744                                     intel_dp->aux.i2c_nack_count,
4745                                     intel_dp->aux.i2c_defer_count);
4746                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4747         } else {
4748                 /* FIXME: Get rid of drm_edid_raw() */
4749                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
4750
4751                 /* We have to write the checksum of the last block read */
4752                 block += block->extensions;
4753
4754                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4755                                        block->checksum) <= 0)
4756                         drm_dbg_kms(&i915->drm,
4757                                     "Failed to write EDID checksum\n");
4758
4759                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4760                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4761         }
4762
4763         /* Set test active flag here so userspace doesn't interrupt things */
4764         intel_dp->compliance.test_active = true;
4765
4766         return test_result;
4767 }
4768
4769 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4770                                         const struct intel_crtc_state *crtc_state)
4771 {
4772         struct drm_i915_private *dev_priv =
4773                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4774         struct drm_dp_phy_test_params *data =
4775                         &intel_dp->compliance.test_data.phytest;
4776         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4777         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4778         enum pipe pipe = crtc->pipe;
4779         u32 pattern_val;
4780
4781         switch (data->phy_pattern) {
4782         case DP_LINK_QUAL_PATTERN_DISABLE:
4783                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4784                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4785                 if (DISPLAY_VER(dev_priv) >= 10)
4786                         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4787                                      DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4788                                      DP_TP_CTL_LINK_TRAIN_NORMAL);
4789                 break;
4790         case DP_LINK_QUAL_PATTERN_D10_2:
4791                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4792                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4793                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4794                 break;
4795         case DP_LINK_QUAL_PATTERN_ERROR_RATE:
4796                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4797                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4798                                DDI_DP_COMP_CTL_ENABLE |
4799                                DDI_DP_COMP_CTL_SCRAMBLED_0);
4800                 break;
4801         case DP_LINK_QUAL_PATTERN_PRBS7:
4802                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4803                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4804                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4805                 break;
4806         case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM:
4807                 /*
4808                  * FIXME: Ideally pattern should come from DPCD 0x250. As
4809                  * current firmware of DPR-100 could not set it, so hardcoding
4810                  * now for complaince test.
4811                  */
4812                 drm_dbg_kms(&dev_priv->drm,
4813                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4814                 pattern_val = 0x3e0f83e0;
4815                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4816                 pattern_val = 0x0f83e0f8;
4817                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4818                 pattern_val = 0x0000f83e;
4819                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4820                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4821                                DDI_DP_COMP_CTL_ENABLE |
4822                                DDI_DP_COMP_CTL_CUSTOM80);
4823                 break;
4824         case DP_LINK_QUAL_PATTERN_CP2520_PAT_1:
4825                 /*
4826                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
4827                  * current firmware of DPR-100 could not set it, so hardcoding
4828                  * now for complaince test.
4829                  */
4830                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4831                 pattern_val = 0xFB;
4832                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4833                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4834                                pattern_val);
4835                 break;
4836         case DP_LINK_QUAL_PATTERN_CP2520_PAT_3:
4837                 if (DISPLAY_VER(dev_priv) < 10)  {
4838                         drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");
4839                         break;
4840                 }
4841                 drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");
4842                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4843                 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4844                              DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4845                              DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4);
4846                 break;
4847         default:
4848                 drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");
4849         }
4850 }
4851
4852 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4853                                          const struct intel_crtc_state *crtc_state)
4854 {
4855         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4856         struct drm_dp_phy_test_params *data =
4857                 &intel_dp->compliance.test_data.phytest;
4858         u8 link_status[DP_LINK_STATUS_SIZE];
4859
4860         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4861                                              link_status) < 0) {
4862                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
4863                 return;
4864         }
4865
4866         /* retrieve vswing & pre-emphasis setting */
4867         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4868                                   link_status);
4869
4870         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4871
4872         intel_dp_phy_pattern_update(intel_dp, crtc_state);
4873
4874         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
4875                           intel_dp->train_set, crtc_state->lane_count);
4876
4877         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4878                                     intel_dp->dpcd[DP_DPCD_REV]);
4879 }
4880
4881 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4882 {
4883         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4884         struct drm_dp_phy_test_params *data =
4885                 &intel_dp->compliance.test_data.phytest;
4886
4887         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4888                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4889                 return DP_TEST_NAK;
4890         }
4891
4892         /* Set test active flag here so userspace doesn't interrupt things */
4893         intel_dp->compliance.test_active = true;
4894
4895         return DP_TEST_ACK;
4896 }
4897
4898 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4899 {
4900         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4901         u8 response = DP_TEST_NAK;
4902         u8 request = 0;
4903         int status;
4904
4905         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4906         if (status <= 0) {
4907                 drm_dbg_kms(&i915->drm,
4908                             "Could not read test request from sink\n");
4909                 goto update_status;
4910         }
4911
4912         switch (request) {
4913         case DP_TEST_LINK_TRAINING:
4914                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4915                 response = intel_dp_autotest_link_training(intel_dp);
4916                 break;
4917         case DP_TEST_LINK_VIDEO_PATTERN:
4918                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4919                 response = intel_dp_autotest_video_pattern(intel_dp);
4920                 break;
4921         case DP_TEST_LINK_EDID_READ:
4922                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4923                 response = intel_dp_autotest_edid(intel_dp);
4924                 break;
4925         case DP_TEST_LINK_PHY_TEST_PATTERN:
4926                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4927                 response = intel_dp_autotest_phy_pattern(intel_dp);
4928                 break;
4929         default:
4930                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4931                             request);
4932                 break;
4933         }
4934
4935         if (response & DP_TEST_ACK)
4936                 intel_dp->compliance.test_type = request;
4937
4938 update_status:
4939         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4940         if (status <= 0)
4941                 drm_dbg_kms(&i915->drm,
4942                             "Could not write test response to sink\n");
4943 }
4944
4945 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4946                              u8 link_status[DP_LINK_STATUS_SIZE])
4947 {
4948         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4949         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4950         bool uhbr = intel_dp->link_rate >= 1000000;
4951         bool ok;
4952
4953         if (uhbr)
4954                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4955                                                           intel_dp->lane_count);
4956         else
4957                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4958
4959         if (ok)
4960                 return true;
4961
4962         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4963         drm_dbg_kms(&i915->drm,
4964                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4965                     encoder->base.base.id, encoder->base.name,
4966                     uhbr ? "128b/132b" : "8b/10b");
4967
4968         return false;
4969 }
4970
4971 static void
4972 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4973 {
4974         bool handled = false;
4975
4976         drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4977
4978         if (esi[1] & DP_CP_IRQ) {
4979                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4980                 ack[1] |= DP_CP_IRQ;
4981         }
4982 }
4983
4984 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4985 {
4986         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4987         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4988         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4989         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4990
4991         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4992                              esi_link_status_size) != esi_link_status_size) {
4993                 drm_err(&i915->drm,
4994                         "[ENCODER:%d:%s] Failed to read link status\n",
4995                         encoder->base.base.id, encoder->base.name);
4996                 return false;
4997         }
4998
4999         return intel_dp_link_ok(intel_dp, link_status);
5000 }
5001
5002 /**
5003  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
5004  * @intel_dp: Intel DP struct
5005  *
5006  * Read any pending MST interrupts, call MST core to handle these and ack the
5007  * interrupts. Check if the main and AUX link state is ok.
5008  *
5009  * Returns:
5010  * - %true if pending interrupts were serviced (or no interrupts were
5011  *   pending) w/o detecting an error condition.
5012  * - %false if an error condition - like AUX failure or a loss of link - is
5013  *   detected, or another condition - like a DP tunnel BW state change - needs
5014  *   servicing from the hotplug work.
5015  */
5016 static bool
5017 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5018 {
5019         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5020         bool link_ok = true;
5021         bool reprobe_needed = false;
5022
5023         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
5024
5025         for (;;) {
5026                 u8 esi[4] = {};
5027                 u8 ack[4] = {};
5028
5029                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
5030                         drm_dbg_kms(&i915->drm,
5031                                     "failed to get ESI - device may have failed\n");
5032                         link_ok = false;
5033
5034                         break;
5035                 }
5036
5037                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
5038
5039                 if (intel_dp->active_mst_links > 0 && link_ok &&
5040                     esi[3] & LINK_STATUS_CHANGED) {
5041                         if (!intel_dp_mst_link_status(intel_dp))
5042                                 link_ok = false;
5043                         ack[3] |= LINK_STATUS_CHANGED;
5044                 }
5045
5046                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
5047
5048                 if (esi[3] & DP_TUNNELING_IRQ) {
5049                         if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
5050                                                      &intel_dp->aux))
5051                                 reprobe_needed = true;
5052                         ack[3] |= DP_TUNNELING_IRQ;
5053                 }
5054
5055                 if (!memchr_inv(ack, 0, sizeof(ack)))
5056                         break;
5057
5058                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
5059                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
5060
5061                 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
5062                         drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
5063         }
5064
5065         return link_ok && !reprobe_needed;
5066 }
5067
5068 static void
5069 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
5070 {
5071         bool is_active;
5072         u8 buf = 0;
5073
5074         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
5075         if (intel_dp->frl.is_trained && !is_active) {
5076                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
5077                         return;
5078
5079                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
5080                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
5081                         return;
5082
5083                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
5084
5085                 intel_dp->frl.is_trained = false;
5086
5087                 /* Restart FRL training or fall back to TMDS mode */
5088                 intel_dp_check_frl_training(intel_dp);
5089         }
5090 }
5091
5092 static bool
5093 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5094 {
5095         u8 link_status[DP_LINK_STATUS_SIZE];
5096
5097         if (!intel_dp->link_trained)
5098                 return false;
5099
5100         /*
5101          * While PSR source HW is enabled, it will control main-link sending
5102          * frames, enabling and disabling it so trying to do a retrain will fail
5103          * as the link would or not be on or it could mix training patterns
5104          * and frame data at the same time causing retrain to fail.
5105          * Also when exiting PSR, HW will retrain the link anyways fixing
5106          * any link status error.
5107          */
5108         if (intel_psr_enabled(intel_dp))
5109                 return false;
5110
5111         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5112                                              link_status) < 0)
5113                 return false;
5114
5115         /*
5116          * Validate the cached values of intel_dp->link_rate and
5117          * intel_dp->lane_count before attempting to retrain.
5118          *
5119          * FIXME would be nice to user the crtc state here, but since
5120          * we need to call this from the short HPD handler that seems
5121          * a bit hard.
5122          */
5123         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5124                                         intel_dp->lane_count))
5125                 return false;
5126
5127         /* Retrain if link not ok */
5128         return !intel_dp_link_ok(intel_dp, link_status);
5129 }
5130
5131 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5132                                    const struct drm_connector_state *conn_state)
5133 {
5134         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5135         struct intel_encoder *encoder;
5136         enum pipe pipe;
5137
5138         if (!conn_state->best_encoder)
5139                 return false;
5140
5141         /* SST */
5142         encoder = &dp_to_dig_port(intel_dp)->base;
5143         if (conn_state->best_encoder == &encoder->base)
5144                 return true;
5145
5146         /* MST */
5147         for_each_pipe(i915, pipe) {
5148                 encoder = &intel_dp->mst_encoders[pipe]->base;
5149                 if (conn_state->best_encoder == &encoder->base)
5150                         return true;
5151         }
5152
5153         return false;
5154 }
5155
5156 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5157                               struct drm_modeset_acquire_ctx *ctx,
5158                               u8 *pipe_mask)
5159 {
5160         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5161         struct drm_connector_list_iter conn_iter;
5162         struct intel_connector *connector;
5163         int ret = 0;
5164
5165         *pipe_mask = 0;
5166
5167         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5168         for_each_intel_connector_iter(connector, &conn_iter) {
5169                 struct drm_connector_state *conn_state =
5170                         connector->base.state;
5171                 struct intel_crtc_state *crtc_state;
5172                 struct intel_crtc *crtc;
5173
5174                 if (!intel_dp_has_connector(intel_dp, conn_state))
5175                         continue;
5176
5177                 crtc = to_intel_crtc(conn_state->crtc);
5178                 if (!crtc)
5179                         continue;
5180
5181                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5182                 if (ret)
5183                         break;
5184
5185                 crtc_state = to_intel_crtc_state(crtc->base.state);
5186
5187                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5188
5189                 if (!crtc_state->hw.active)
5190                         continue;
5191
5192                 if (conn_state->commit)
5193                         drm_WARN_ON(&i915->drm,
5194                                     !wait_for_completion_timeout(&conn_state->commit->hw_done,
5195                                                                  msecs_to_jiffies(5000)));
5196
5197                 *pipe_mask |= BIT(crtc->pipe);
5198         }
5199         drm_connector_list_iter_end(&conn_iter);
5200
5201         return ret;
5202 }
5203
5204 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5205 {
5206         struct intel_connector *connector = intel_dp->attached_connector;
5207
5208         return connector->base.status == connector_status_connected ||
5209                 intel_dp->is_mst;
5210 }
5211
5212 int intel_dp_retrain_link(struct intel_encoder *encoder,
5213                           struct drm_modeset_acquire_ctx *ctx)
5214 {
5215         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5216         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5217         struct intel_crtc *crtc;
5218         u8 pipe_mask;
5219         int ret;
5220
5221         if (!intel_dp_is_connected(intel_dp))
5222                 return 0;
5223
5224         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5225                                ctx);
5226         if (ret)
5227                 return ret;
5228
5229         if (!intel_dp_needs_link_retrain(intel_dp))
5230                 return 0;
5231
5232         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5233         if (ret)
5234                 return ret;
5235
5236         if (pipe_mask == 0)
5237                 return 0;
5238
5239         if (!intel_dp_needs_link_retrain(intel_dp))
5240                 return 0;
5241
5242         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5243                     encoder->base.base.id, encoder->base.name);
5244
5245         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5246                 const struct intel_crtc_state *crtc_state =
5247                         to_intel_crtc_state(crtc->base.state);
5248
5249                 /* Suppress underruns caused by re-training */
5250                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5251                 if (crtc_state->has_pch_encoder)
5252                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5253                                                               intel_crtc_pch_transcoder(crtc), false);
5254         }
5255
5256         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5257                 const struct intel_crtc_state *crtc_state =
5258                         to_intel_crtc_state(crtc->base.state);
5259
5260                 /* retrain on the MST master transcoder */
5261                 if (DISPLAY_VER(dev_priv) >= 12 &&
5262                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5263                     !intel_dp_mst_is_master_trans(crtc_state))
5264                         continue;
5265
5266                 intel_dp_check_frl_training(intel_dp);
5267                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
5268                 intel_dp_start_link_train(intel_dp, crtc_state);
5269                 intel_dp_stop_link_train(intel_dp, crtc_state);
5270                 break;
5271         }
5272
5273         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5274                 const struct intel_crtc_state *crtc_state =
5275                         to_intel_crtc_state(crtc->base.state);
5276
5277                 /* Keep underrun reporting disabled until things are stable */
5278                 intel_crtc_wait_for_next_vblank(crtc);
5279
5280                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5281                 if (crtc_state->has_pch_encoder)
5282                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5283                                                               intel_crtc_pch_transcoder(crtc), true);
5284         }
5285
5286         return 0;
5287 }
5288
5289 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
5290                                   struct drm_modeset_acquire_ctx *ctx,
5291                                   u8 *pipe_mask)
5292 {
5293         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5294         struct drm_connector_list_iter conn_iter;
5295         struct intel_connector *connector;
5296         int ret = 0;
5297
5298         *pipe_mask = 0;
5299
5300         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5301         for_each_intel_connector_iter(connector, &conn_iter) {
5302                 struct drm_connector_state *conn_state =
5303                         connector->base.state;
5304                 struct intel_crtc_state *crtc_state;
5305                 struct intel_crtc *crtc;
5306
5307                 if (!intel_dp_has_connector(intel_dp, conn_state))
5308                         continue;
5309
5310                 crtc = to_intel_crtc(conn_state->crtc);
5311                 if (!crtc)
5312                         continue;
5313
5314                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5315                 if (ret)
5316                         break;
5317
5318                 crtc_state = to_intel_crtc_state(crtc->base.state);
5319
5320                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5321
5322                 if (!crtc_state->hw.active)
5323                         continue;
5324
5325                 if (conn_state->commit &&
5326                     !try_wait_for_completion(&conn_state->commit->hw_done))
5327                         continue;
5328
5329                 *pipe_mask |= BIT(crtc->pipe);
5330         }
5331         drm_connector_list_iter_end(&conn_iter);
5332
5333         return ret;
5334 }
5335
5336 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
5337                                 struct drm_modeset_acquire_ctx *ctx)
5338 {
5339         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5340         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5341         struct intel_crtc *crtc;
5342         u8 pipe_mask;
5343         int ret;
5344
5345         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5346                                ctx);
5347         if (ret)
5348                 return ret;
5349
5350         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
5351         if (ret)
5352                 return ret;
5353
5354         if (pipe_mask == 0)
5355                 return 0;
5356
5357         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
5358                     encoder->base.base.id, encoder->base.name);
5359
5360         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5361                 const struct intel_crtc_state *crtc_state =
5362                         to_intel_crtc_state(crtc->base.state);
5363
5364                 /* test on the MST master transcoder */
5365                 if (DISPLAY_VER(dev_priv) >= 12 &&
5366                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5367                     !intel_dp_mst_is_master_trans(crtc_state))
5368                         continue;
5369
5370                 intel_dp_process_phy_request(intel_dp, crtc_state);
5371                 break;
5372         }
5373
5374         return 0;
5375 }
5376
5377 void intel_dp_phy_test(struct intel_encoder *encoder)
5378 {
5379         struct drm_modeset_acquire_ctx ctx;
5380         int ret;
5381
5382         drm_modeset_acquire_init(&ctx, 0);
5383
5384         for (;;) {
5385                 ret = intel_dp_do_phy_test(encoder, &ctx);
5386
5387                 if (ret == -EDEADLK) {
5388                         drm_modeset_backoff(&ctx);
5389                         continue;
5390                 }
5391
5392                 break;
5393         }
5394
5395         drm_modeset_drop_locks(&ctx);
5396         drm_modeset_acquire_fini(&ctx);
5397         drm_WARN(encoder->base.dev, ret,
5398                  "Acquiring modeset locks failed with %i\n", ret);
5399 }
5400
5401 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5402 {
5403         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5404         u8 val;
5405
5406         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5407                 return;
5408
5409         if (drm_dp_dpcd_readb(&intel_dp->aux,
5410                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5411                 return;
5412
5413         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5414
5415         if (val & DP_AUTOMATED_TEST_REQUEST)
5416                 intel_dp_handle_test_request(intel_dp);
5417
5418         if (val & DP_CP_IRQ)
5419                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5420
5421         if (val & DP_SINK_SPECIFIC_IRQ)
5422                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5423 }
5424
5425 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5426 {
5427         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5428         bool reprobe_needed = false;
5429         u8 val;
5430
5431         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5432                 return false;
5433
5434         if (drm_dp_dpcd_readb(&intel_dp->aux,
5435                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5436                 return false;
5437
5438         if ((val & DP_TUNNELING_IRQ) &&
5439             drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
5440                                      &intel_dp->aux))
5441                 reprobe_needed = true;
5442
5443         if (drm_dp_dpcd_writeb(&intel_dp->aux,
5444                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5445                 return reprobe_needed;
5446
5447         if (val & HDMI_LINK_STATUS_CHANGED)
5448                 intel_dp_handle_hdmi_link_status_change(intel_dp);
5449
5450         return reprobe_needed;
5451 }
5452
5453 /*
5454  * According to DP spec
5455  * 5.1.2:
5456  *  1. Read DPCD
5457  *  2. Configure link according to Receiver Capabilities
5458  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5459  *  4. Check link status on receipt of hot-plug interrupt
5460  *
5461  * intel_dp_short_pulse -  handles short pulse interrupts
5462  * when full detection is not required.
5463  * Returns %true if short pulse is handled and full detection
5464  * is NOT required and %false otherwise.
5465  */
5466 static bool
5467 intel_dp_short_pulse(struct intel_dp *intel_dp)
5468 {
5469         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5470         u8 old_sink_count = intel_dp->sink_count;
5471         bool reprobe_needed = false;
5472         bool ret;
5473
5474         /*
5475          * Clearing compliance test variables to allow capturing
5476          * of values for next automated test request.
5477          */
5478         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5479
5480         /*
5481          * Now read the DPCD to see if it's actually running
5482          * If the current value of sink count doesn't match with
5483          * the value that was stored earlier or dpcd read failed
5484          * we need to do full detection
5485          */
5486         ret = intel_dp_get_dpcd(intel_dp);
5487
5488         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5489                 /* No need to proceed if we are going to do full detect */
5490                 return false;
5491         }
5492
5493         intel_dp_check_device_service_irq(intel_dp);
5494         reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5495
5496         /* Handle CEC interrupts, if any */
5497         drm_dp_cec_irq(&intel_dp->aux);
5498
5499         /* defer to the hotplug work for link retraining if needed */
5500         if (intel_dp_needs_link_retrain(intel_dp))
5501                 return false;
5502
5503         intel_psr_short_pulse(intel_dp);
5504
5505         switch (intel_dp->compliance.test_type) {
5506         case DP_TEST_LINK_TRAINING:
5507                 drm_dbg_kms(&dev_priv->drm,
5508                             "Link Training Compliance Test requested\n");
5509                 /* Send a Hotplug Uevent to userspace to start modeset */
5510                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5511                 break;
5512         case DP_TEST_LINK_PHY_TEST_PATTERN:
5513                 drm_dbg_kms(&dev_priv->drm,
5514                             "PHY test pattern Compliance Test requested\n");
5515                 /*
5516                  * Schedule long hpd to do the test
5517                  *
5518                  * FIXME get rid of the ad-hoc phy test modeset code
5519                  * and properly incorporate it into the normal modeset.
5520                  */
5521                 reprobe_needed = true;
5522         }
5523
5524         return !reprobe_needed;
5525 }
5526
5527 /* XXX this is probably wrong for multiple downstream ports */
5528 static enum drm_connector_status
5529 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5530 {
5531         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5532         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5533         u8 *dpcd = intel_dp->dpcd;
5534         u8 type;
5535
5536         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5537                 return connector_status_connected;
5538
5539         lspcon_resume(dig_port);
5540
5541         if (!intel_dp_get_dpcd(intel_dp))
5542                 return connector_status_disconnected;
5543
5544         intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);
5545
5546         /* if there's no downstream port, we're done */
5547         if (!drm_dp_is_branch(dpcd))
5548                 return connector_status_connected;
5549
5550         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5551         if (intel_dp_has_sink_count(intel_dp) &&
5552             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5553                 return intel_dp->sink_count ?
5554                 connector_status_connected : connector_status_disconnected;
5555         }
5556
5557         if (intel_dp->mst_detect == DRM_DP_MST)
5558                 return connector_status_connected;
5559
5560         /* If no HPD, poke DDC gently */
5561         if (drm_probe_ddc(&intel_dp->aux.ddc))
5562                 return connector_status_connected;
5563
5564         /* Well we tried, say unknown for unreliable port types */
5565         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5566                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5567                 if (type == DP_DS_PORT_TYPE_VGA ||
5568                     type == DP_DS_PORT_TYPE_NON_EDID)
5569                         return connector_status_unknown;
5570         } else {
5571                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5572                         DP_DWN_STRM_PORT_TYPE_MASK;
5573                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5574                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5575                         return connector_status_unknown;
5576         }
5577
5578         /* Anything else is out of spec, warn and ignore */
5579         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5580         return connector_status_disconnected;
5581 }
5582
5583 static enum drm_connector_status
5584 edp_detect(struct intel_dp *intel_dp)
5585 {
5586         return connector_status_connected;
5587 }
5588
5589 void intel_digital_port_lock(struct intel_encoder *encoder)
5590 {
5591         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5592
5593         if (dig_port->lock)
5594                 dig_port->lock(dig_port);
5595 }
5596
5597 void intel_digital_port_unlock(struct intel_encoder *encoder)
5598 {
5599         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5600
5601         if (dig_port->unlock)
5602                 dig_port->unlock(dig_port);
5603 }
5604
5605 /*
5606  * intel_digital_port_connected_locked - is the specified port connected?
5607  * @encoder: intel_encoder
5608  *
5609  * In cases where there's a connector physically connected but it can't be used
5610  * by our hardware we also return false, since the rest of the driver should
5611  * pretty much treat the port as disconnected. This is relevant for type-C
5612  * (starting on ICL) where there's ownership involved.
5613  *
5614  * The caller must hold the lock acquired by calling intel_digital_port_lock()
5615  * when calling this function.
5616  *
5617  * Return %true if port is connected, %false otherwise.
5618  */
5619 bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5620 {
5621         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5622         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5623         bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5624         bool is_connected = false;
5625         intel_wakeref_t wakeref;
5626
5627         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5628                 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5629
5630                 do {
5631                         is_connected = dig_port->connected(encoder);
5632                         if (is_connected || is_glitch_free)
5633                                 break;
5634                         usleep_range(10, 30);
5635                 } while (time_before(jiffies, wait_expires));
5636         }
5637
5638         return is_connected;
5639 }
5640
5641 bool intel_digital_port_connected(struct intel_encoder *encoder)
5642 {
5643         bool ret;
5644
5645         intel_digital_port_lock(encoder);
5646         ret = intel_digital_port_connected_locked(encoder);
5647         intel_digital_port_unlock(encoder);
5648
5649         return ret;
5650 }
5651
5652 static const struct drm_edid *
5653 intel_dp_get_edid(struct intel_dp *intel_dp)
5654 {
5655         struct intel_connector *connector = intel_dp->attached_connector;
5656         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5657
5658         /* Use panel fixed edid if we have one */
5659         if (fixed_edid) {
5660                 /* invalid edid */
5661                 if (IS_ERR(fixed_edid))
5662                         return NULL;
5663
5664                 return drm_edid_dup(fixed_edid);
5665         }
5666
5667         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5668 }
5669
5670 static void
5671 intel_dp_update_dfp(struct intel_dp *intel_dp,
5672                     const struct drm_edid *drm_edid)
5673 {
5674         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5675         struct intel_connector *connector = intel_dp->attached_connector;
5676
5677         intel_dp->dfp.max_bpc =
5678                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5679                                           intel_dp->downstream_ports, drm_edid);
5680
5681         intel_dp->dfp.max_dotclock =
5682                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5683                                                intel_dp->downstream_ports);
5684
5685         intel_dp->dfp.min_tmds_clock =
5686                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5687                                                  intel_dp->downstream_ports,
5688                                                  drm_edid);
5689         intel_dp->dfp.max_tmds_clock =
5690                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5691                                                  intel_dp->downstream_ports,
5692                                                  drm_edid);
5693
5694         intel_dp->dfp.pcon_max_frl_bw =
5695                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5696                                            intel_dp->downstream_ports);
5697
5698         drm_dbg_kms(&i915->drm,
5699                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5700                     connector->base.base.id, connector->base.name,
5701                     intel_dp->dfp.max_bpc,
5702                     intel_dp->dfp.max_dotclock,
5703                     intel_dp->dfp.min_tmds_clock,
5704                     intel_dp->dfp.max_tmds_clock,
5705                     intel_dp->dfp.pcon_max_frl_bw);
5706
5707         intel_dp_get_pcon_dsc_cap(intel_dp);
5708 }
5709
5710 static bool
5711 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5712 {
5713         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5714             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5715                 return true;
5716
5717         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5718             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5719                 return true;
5720
5721         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5722             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5723                 return true;
5724
5725         return false;
5726 }
5727
5728 static void
5729 intel_dp_update_420(struct intel_dp *intel_dp)
5730 {
5731         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5732         struct intel_connector *connector = intel_dp->attached_connector;
5733
5734         intel_dp->dfp.ycbcr420_passthrough =
5735                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5736                                                   intel_dp->downstream_ports);
5737         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5738         intel_dp->dfp.ycbcr_444_to_420 =
5739                 dp_to_dig_port(intel_dp)->lspcon.active ||
5740                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5741                                                         intel_dp->downstream_ports);
5742         intel_dp->dfp.rgb_to_ycbcr =
5743                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5744                                                           intel_dp->downstream_ports,
5745                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5746
5747         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5748
5749         drm_dbg_kms(&i915->drm,
5750                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5751                     connector->base.base.id, connector->base.name,
5752                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5753                     str_yes_no(connector->base.ycbcr_420_allowed),
5754                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5755 }
5756
5757 static void
5758 intel_dp_set_edid(struct intel_dp *intel_dp)
5759 {
5760         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5761         struct intel_connector *connector = intel_dp->attached_connector;
5762         const struct drm_edid *drm_edid;
5763         bool vrr_capable;
5764
5765         intel_dp_unset_edid(intel_dp);
5766         drm_edid = intel_dp_get_edid(intel_dp);
5767         connector->detect_edid = drm_edid;
5768
5769         /* Below we depend on display info having been updated */
5770         drm_edid_connector_update(&connector->base, drm_edid);
5771
5772         vrr_capable = intel_vrr_is_capable(connector);
5773         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5774                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5775         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5776
5777         intel_dp_update_dfp(intel_dp, drm_edid);
5778         intel_dp_update_420(intel_dp);
5779
5780         drm_dp_cec_attach(&intel_dp->aux,
5781                           connector->base.display_info.source_physical_address);
5782 }
5783
5784 static void
5785 intel_dp_unset_edid(struct intel_dp *intel_dp)
5786 {
5787         struct intel_connector *connector = intel_dp->attached_connector;
5788
5789         drm_dp_cec_unset_edid(&intel_dp->aux);
5790         drm_edid_free(connector->detect_edid);
5791         connector->detect_edid = NULL;
5792
5793         intel_dp->dfp.max_bpc = 0;
5794         intel_dp->dfp.max_dotclock = 0;
5795         intel_dp->dfp.min_tmds_clock = 0;
5796         intel_dp->dfp.max_tmds_clock = 0;
5797
5798         intel_dp->dfp.pcon_max_frl_bw = 0;
5799
5800         intel_dp->dfp.ycbcr_444_to_420 = false;
5801         connector->base.ycbcr_420_allowed = false;
5802
5803         drm_connector_set_vrr_capable_property(&connector->base,
5804                                                false);
5805 }
5806
5807 static void
5808 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5809 {
5810         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5811
5812         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5813         if (!HAS_DSC(i915))
5814                 return;
5815
5816         if (intel_dp_is_edp(intel_dp))
5817                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5818                                            connector);
5819         else
5820                 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5821                                           connector);
5822 }
5823
5824 static int
5825 intel_dp_detect(struct drm_connector *connector,
5826                 struct drm_modeset_acquire_ctx *ctx,
5827                 bool force)
5828 {
5829         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5830         struct intel_connector *intel_connector =
5831                 to_intel_connector(connector);
5832         struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5833         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5834         struct intel_encoder *encoder = &dig_port->base;
5835         enum drm_connector_status status;
5836         int ret;
5837
5838         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5839                     connector->base.id, connector->name);
5840         drm_WARN_ON(&dev_priv->drm,
5841                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5842
5843         if (!intel_display_device_enabled(dev_priv))
5844                 return connector_status_disconnected;
5845
5846         if (!intel_display_driver_check_access(dev_priv))
5847                 return connector->status;
5848
5849         /* Can't disconnect eDP */
5850         if (intel_dp_is_edp(intel_dp))
5851                 status = edp_detect(intel_dp);
5852         else if (intel_digital_port_connected(encoder))
5853                 status = intel_dp_detect_dpcd(intel_dp);
5854         else
5855                 status = connector_status_disconnected;
5856
5857         if (status == connector_status_disconnected) {
5858                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5859                 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5860                 intel_dp->psr.sink_panel_replay_support = false;
5861
5862                 intel_dp_mst_disconnect(intel_dp);
5863
5864                 intel_dp_tunnel_disconnect(intel_dp);
5865
5866                 goto out;
5867         }
5868
5869         ret = intel_dp_tunnel_detect(intel_dp, ctx);
5870         if (ret == -EDEADLK)
5871                 return ret;
5872
5873         if (ret == 1)
5874                 intel_connector->base.epoch_counter++;
5875
5876         if (!intel_dp_is_edp(intel_dp))
5877                 intel_psr_init_dpcd(intel_dp);
5878
5879         intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5880
5881         intel_dp_mst_configure(intel_dp);
5882
5883         /*
5884          * TODO: Reset link params when switching to MST mode, until MST
5885          * supports link training fallback params.
5886          */
5887         if (intel_dp->reset_link_params || intel_dp->is_mst) {
5888                 intel_dp_reset_max_link_params(intel_dp);
5889                 intel_dp->reset_link_params = false;
5890         }
5891
5892         intel_dp_print_rates(intel_dp);
5893
5894         if (intel_dp->is_mst) {
5895                 /*
5896                  * If we are in MST mode then this connector
5897                  * won't appear connected or have anything
5898                  * with EDID on it
5899                  */
5900                 status = connector_status_disconnected;
5901                 goto out;
5902         }
5903
5904         /*
5905          * Some external monitors do not signal loss of link synchronization
5906          * with an IRQ_HPD, so force a link status check.
5907          */
5908         if (!intel_dp_is_edp(intel_dp)) {
5909                 ret = intel_dp_retrain_link(encoder, ctx);
5910                 if (ret)
5911                         return ret;
5912         }
5913
5914         /*
5915          * Clearing NACK and defer counts to get their exact values
5916          * while reading EDID which are required by Compliance tests
5917          * 4.2.2.4 and 4.2.2.5
5918          */
5919         intel_dp->aux.i2c_nack_count = 0;
5920         intel_dp->aux.i2c_defer_count = 0;
5921
5922         intel_dp_set_edid(intel_dp);
5923         if (intel_dp_is_edp(intel_dp) ||
5924             to_intel_connector(connector)->detect_edid)
5925                 status = connector_status_connected;
5926
5927         intel_dp_check_device_service_irq(intel_dp);
5928
5929 out:
5930         if (status != connector_status_connected && !intel_dp->is_mst)
5931                 intel_dp_unset_edid(intel_dp);
5932
5933         if (!intel_dp_is_edp(intel_dp))
5934                 drm_dp_set_subconnector_property(connector,
5935                                                  status,
5936                                                  intel_dp->dpcd,
5937                                                  intel_dp->downstream_ports);
5938         return status;
5939 }
5940
5941 static void
5942 intel_dp_force(struct drm_connector *connector)
5943 {
5944         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5945         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5946         struct intel_encoder *intel_encoder = &dig_port->base;
5947         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5948
5949         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5950                     connector->base.id, connector->name);
5951
5952         if (!intel_display_driver_check_access(dev_priv))
5953                 return;
5954
5955         intel_dp_unset_edid(intel_dp);
5956
5957         if (connector->status != connector_status_connected)
5958                 return;
5959
5960         intel_dp_set_edid(intel_dp);
5961 }
5962
5963 static int intel_dp_get_modes(struct drm_connector *connector)
5964 {
5965         struct intel_connector *intel_connector = to_intel_connector(connector);
5966         int num_modes;
5967
5968         /* drm_edid_connector_update() done in ->detect() or ->force() */
5969         num_modes = drm_edid_connector_add_modes(connector);
5970
5971         /* Also add fixed mode, which may or may not be present in EDID */
5972         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5973                 num_modes += intel_panel_get_modes(intel_connector);
5974
5975         if (num_modes)
5976                 return num_modes;
5977
5978         if (!intel_connector->detect_edid) {
5979                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5980                 struct drm_display_mode *mode;
5981
5982                 mode = drm_dp_downstream_mode(connector->dev,
5983                                               intel_dp->dpcd,
5984                                               intel_dp->downstream_ports);
5985                 if (mode) {
5986                         drm_mode_probed_add(connector, mode);
5987                         num_modes++;
5988                 }
5989         }
5990
5991         return num_modes;
5992 }
5993
5994 static int
5995 intel_dp_connector_register(struct drm_connector *connector)
5996 {
5997         struct drm_i915_private *i915 = to_i915(connector->dev);
5998         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5999         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6000         struct intel_lspcon *lspcon = &dig_port->lspcon;
6001         int ret;
6002
6003         ret = intel_connector_register(connector);
6004         if (ret)
6005                 return ret;
6006
6007         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6008                     intel_dp->aux.name, connector->kdev->kobj.name);
6009
6010         intel_dp->aux.dev = connector->kdev;
6011         ret = drm_dp_aux_register(&intel_dp->aux);
6012         if (!ret)
6013                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6014
6015         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
6016                 return ret;
6017
6018         /*
6019          * ToDo: Clean this up to handle lspcon init and resume more
6020          * efficiently and streamlined.
6021          */
6022         if (lspcon_init(dig_port)) {
6023                 lspcon_detect_hdr_capability(lspcon);
6024                 if (lspcon->hdr_supported)
6025                         drm_connector_attach_hdr_output_metadata_property(connector);
6026         }
6027
6028         return ret;
6029 }
6030
6031 static void
6032 intel_dp_connector_unregister(struct drm_connector *connector)
6033 {
6034         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6035
6036         drm_dp_cec_unregister_connector(&intel_dp->aux);
6037         drm_dp_aux_unregister(&intel_dp->aux);
6038         intel_connector_unregister(connector);
6039 }
6040
6041 void intel_dp_connector_sync_state(struct intel_connector *connector,
6042                                    const struct intel_crtc_state *crtc_state)
6043 {
6044         struct drm_i915_private *i915 = to_i915(connector->base.dev);
6045
6046         if (crtc_state && crtc_state->dsc.compression_enable) {
6047                 drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
6048                 connector->dp.dsc_decompression_enabled = true;
6049         } else {
6050                 connector->dp.dsc_decompression_enabled = false;
6051         }
6052 }
6053
6054 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6055 {
6056         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6057         struct intel_dp *intel_dp = &dig_port->dp;
6058
6059         intel_dp_mst_encoder_cleanup(dig_port);
6060
6061         intel_dp_tunnel_destroy(intel_dp);
6062
6063         intel_pps_vdd_off_sync(intel_dp);
6064
6065         /*
6066          * Ensure power off delay is respected on module remove, so that we can
6067          * reduce delays at driver probe. See pps_init_timestamps().
6068          */
6069         intel_pps_wait_power_cycle(intel_dp);
6070
6071         intel_dp_aux_fini(intel_dp);
6072 }
6073
6074 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6075 {
6076         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6077
6078         intel_pps_vdd_off_sync(intel_dp);
6079
6080         intel_dp_tunnel_suspend(intel_dp);
6081 }
6082
6083 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
6084 {
6085         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6086
6087         intel_pps_wait_power_cycle(intel_dp);
6088 }
6089
6090 static int intel_modeset_tile_group(struct intel_atomic_state *state,
6091                                     int tile_group_id)
6092 {
6093         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6094         struct drm_connector_list_iter conn_iter;
6095         struct drm_connector *connector;
6096         int ret = 0;
6097
6098         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
6099         drm_for_each_connector_iter(connector, &conn_iter) {
6100                 struct drm_connector_state *conn_state;
6101                 struct intel_crtc_state *crtc_state;
6102                 struct intel_crtc *crtc;
6103
6104                 if (!connector->has_tile ||
6105                     connector->tile_group->id != tile_group_id)
6106                         continue;
6107
6108                 conn_state = drm_atomic_get_connector_state(&state->base,
6109                                                             connector);
6110                 if (IS_ERR(conn_state)) {
6111                         ret = PTR_ERR(conn_state);
6112                         break;
6113                 }
6114
6115                 crtc = to_intel_crtc(conn_state->crtc);
6116
6117                 if (!crtc)
6118                         continue;
6119
6120                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6121                 crtc_state->uapi.mode_changed = true;
6122
6123                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6124                 if (ret)
6125                         break;
6126         }
6127         drm_connector_list_iter_end(&conn_iter);
6128
6129         return ret;
6130 }
6131
6132 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6133 {
6134         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6135         struct intel_crtc *crtc;
6136
6137         if (transcoders == 0)
6138                 return 0;
6139
6140         for_each_intel_crtc(&dev_priv->drm, crtc) {
6141                 struct intel_crtc_state *crtc_state;
6142                 int ret;
6143
6144                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6145                 if (IS_ERR(crtc_state))
6146                         return PTR_ERR(crtc_state);
6147
6148                 if (!crtc_state->hw.enable)
6149                         continue;
6150
6151                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6152                         continue;
6153
6154                 crtc_state->uapi.mode_changed = true;
6155
6156                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6157                 if (ret)
6158                         return ret;
6159
6160                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6161                 if (ret)
6162                         return ret;
6163
6164                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
6165         }
6166
6167         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
6168
6169         return 0;
6170 }
6171
6172 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6173                                       struct drm_connector *connector)
6174 {
6175         const struct drm_connector_state *old_conn_state =
6176                 drm_atomic_get_old_connector_state(&state->base, connector);
6177         const struct intel_crtc_state *old_crtc_state;
6178         struct intel_crtc *crtc;
6179         u8 transcoders;
6180
6181         crtc = to_intel_crtc(old_conn_state->crtc);
6182         if (!crtc)
6183                 return 0;
6184
6185         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6186
6187         if (!old_crtc_state->hw.active)
6188                 return 0;
6189
6190         transcoders = old_crtc_state->sync_mode_slaves_mask;
6191         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6192                 transcoders |= BIT(old_crtc_state->master_transcoder);
6193
6194         return intel_modeset_affected_transcoders(state,
6195                                                   transcoders);
6196 }
6197
6198 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6199                                            struct drm_atomic_state *_state)
6200 {
6201         struct drm_i915_private *dev_priv = to_i915(conn->dev);
6202         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6203         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6204         struct intel_connector *intel_conn = to_intel_connector(conn);
6205         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6206         int ret;
6207
6208         ret = intel_digital_connector_atomic_check(conn, &state->base);
6209         if (ret)
6210                 return ret;
6211
6212         if (intel_dp_mst_source_support(intel_dp)) {
6213                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6214                 if (ret)
6215                         return ret;
6216         }
6217
6218         if (!intel_connector_needs_modeset(state, conn))
6219                 return 0;
6220
6221         ret = intel_dp_tunnel_atomic_check_state(state,
6222                                                  intel_dp,
6223                                                  intel_conn);
6224         if (ret)
6225                 return ret;
6226
6227         /*
6228          * We don't enable port sync on BDW due to missing w/as and
6229          * due to not having adjusted the modeset sequence appropriately.
6230          */
6231         if (DISPLAY_VER(dev_priv) < 9)
6232                 return 0;
6233
6234         if (conn->has_tile) {
6235                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6236                 if (ret)
6237                         return ret;
6238         }
6239
6240         return intel_modeset_synced_crtcs(state, conn);
6241 }
6242
6243 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6244                                        enum drm_connector_status hpd_state)
6245 {
6246         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6247         struct drm_i915_private *i915 = to_i915(connector->dev);
6248         bool hpd_high = hpd_state == connector_status_connected;
6249         unsigned int hpd_pin = encoder->hpd_pin;
6250         bool need_work = false;
6251
6252         spin_lock_irq(&i915->irq_lock);
6253         if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6254                 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6255
6256                 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6257                 need_work = true;
6258         }
6259         spin_unlock_irq(&i915->irq_lock);
6260
6261         if (need_work)
6262                 intel_hpd_schedule_detection(i915);
6263 }
6264
6265 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6266         .force = intel_dp_force,
6267         .fill_modes = drm_helper_probe_single_connector_modes,
6268         .atomic_get_property = intel_digital_connector_atomic_get_property,
6269         .atomic_set_property = intel_digital_connector_atomic_set_property,
6270         .late_register = intel_dp_connector_register,
6271         .early_unregister = intel_dp_connector_unregister,
6272         .destroy = intel_connector_destroy,
6273         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6274         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6275         .oob_hotplug_event = intel_dp_oob_hotplug_event,
6276 };
6277
6278 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6279         .detect_ctx = intel_dp_detect,
6280         .get_modes = intel_dp_get_modes,
6281         .mode_valid = intel_dp_mode_valid,
6282         .atomic_check = intel_dp_connector_atomic_check,
6283 };
6284
6285 enum irqreturn
6286 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6287 {
6288         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6289         struct intel_dp *intel_dp = &dig_port->dp;
6290         u8 dpcd[DP_RECEIVER_CAP_SIZE];
6291
6292         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6293             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6294                 /*
6295                  * vdd off can generate a long/short pulse on eDP which
6296                  * would require vdd on to handle it, and thus we
6297                  * would end up in an endless cycle of
6298                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6299                  */
6300                 drm_dbg_kms(&i915->drm,
6301                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6302                             long_hpd ? "long" : "short",
6303                             dig_port->base.base.base.id,
6304                             dig_port->base.base.name);
6305                 return IRQ_HANDLED;
6306         }
6307
6308         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6309                     dig_port->base.base.base.id,
6310                     dig_port->base.base.name,
6311                     long_hpd ? "long" : "short");
6312
6313         /*
6314          * TBT DP tunnels require the GFX driver to read out the DPRX caps in
6315          * response to long HPD pulses. The DP hotplug handler does that,
6316          * however the hotplug handler may be blocked by another
6317          * connector's/encoder's hotplug handler. Since the TBT CM may not
6318          * complete the DP tunnel BW request for the latter connector/encoder
6319          * waiting for this encoder's DPRX read, perform a dummy read here.
6320          */
6321         if (long_hpd)
6322                 intel_dp_read_dprx_caps(intel_dp, dpcd);
6323
6324         if (long_hpd) {
6325                 intel_dp->reset_link_params = true;
6326                 return IRQ_NONE;
6327         }
6328
6329         if (intel_dp->is_mst) {
6330                 if (!intel_dp_check_mst_status(intel_dp))
6331                         return IRQ_NONE;
6332         } else if (!intel_dp_short_pulse(intel_dp)) {
6333                 return IRQ_NONE;
6334         }
6335
6336         return IRQ_HANDLED;
6337 }
6338
6339 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6340                                   const struct intel_bios_encoder_data *devdata,
6341                                   enum port port)
6342 {
6343         /*
6344          * eDP not supported on g4x. so bail out early just
6345          * for a bit extra safety in case the VBT is bonkers.
6346          */
6347         if (DISPLAY_VER(dev_priv) < 5)
6348                 return false;
6349
6350         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6351                 return true;
6352
6353         return devdata && intel_bios_encoder_supports_edp(devdata);
6354 }
6355
6356 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6357 {
6358         const struct intel_bios_encoder_data *devdata =
6359                 intel_bios_encoder_data_lookup(i915, port);
6360
6361         return _intel_dp_is_port_edp(i915, devdata, port);
6362 }
6363
6364 static bool
6365 has_gamut_metadata_dip(struct intel_encoder *encoder)
6366 {
6367         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6368         enum port port = encoder->port;
6369
6370         if (intel_bios_encoder_is_lspcon(encoder->devdata))
6371                 return false;
6372
6373         if (DISPLAY_VER(i915) >= 11)
6374                 return true;
6375
6376         if (port == PORT_A)
6377                 return false;
6378
6379         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6380             DISPLAY_VER(i915) >= 9)
6381                 return true;
6382
6383         return false;
6384 }
6385
6386 static void
6387 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6388 {
6389         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6390         enum port port = dp_to_dig_port(intel_dp)->base.port;
6391
6392         if (!intel_dp_is_edp(intel_dp))
6393                 drm_connector_attach_dp_subconnector_property(connector);
6394
6395         if (!IS_G4X(dev_priv) && port != PORT_A)
6396                 intel_attach_force_audio_property(connector);
6397
6398         intel_attach_broadcast_rgb_property(connector);
6399         if (HAS_GMCH(dev_priv))
6400                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6401         else if (DISPLAY_VER(dev_priv) >= 5)
6402                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6403
6404         /* Register HDMI colorspace for case of lspcon */
6405         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6406                 drm_connector_attach_content_type_property(connector);
6407                 intel_attach_hdmi_colorspace_property(connector);
6408         } else {
6409                 intel_attach_dp_colorspace_property(connector);
6410         }
6411
6412         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6413                 drm_connector_attach_hdr_output_metadata_property(connector);
6414
6415         if (HAS_VRR(dev_priv))
6416                 drm_connector_attach_vrr_capable_property(connector);
6417 }
6418
6419 static void
6420 intel_edp_add_properties(struct intel_dp *intel_dp)
6421 {
6422         struct intel_connector *connector = intel_dp->attached_connector;
6423         struct drm_i915_private *i915 = to_i915(connector->base.dev);
6424         const struct drm_display_mode *fixed_mode =
6425                 intel_panel_preferred_fixed_mode(connector);
6426
6427         intel_attach_scaling_mode_property(&connector->base);
6428
6429         drm_connector_set_panel_orientation_with_quirk(&connector->base,
6430                                                        i915->display.vbt.orientation,
6431                                                        fixed_mode->hdisplay,
6432                                                        fixed_mode->vdisplay);
6433 }
6434
6435 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6436                                       struct intel_connector *connector)
6437 {
6438         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6439         enum pipe pipe = INVALID_PIPE;
6440
6441         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
6442                 /*
6443                  * Figure out the current pipe for the initial backlight setup.
6444                  * If the current pipe isn't valid, try the PPS pipe, and if that
6445                  * fails just assume pipe A.
6446                  */
6447                 pipe = vlv_active_pipe(intel_dp);
6448
6449                 if (pipe != PIPE_A && pipe != PIPE_B)
6450                         pipe = intel_dp->pps.pps_pipe;
6451
6452                 if (pipe != PIPE_A && pipe != PIPE_B)
6453                         pipe = PIPE_A;
6454         }
6455
6456         intel_backlight_setup(connector, pipe);
6457 }
6458
6459 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6460                                      struct intel_connector *intel_connector)
6461 {
6462         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6463         struct drm_connector *connector = &intel_connector->base;
6464         struct drm_display_mode *fixed_mode;
6465         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6466         bool has_dpcd;
6467         const struct drm_edid *drm_edid;
6468
6469         if (!intel_dp_is_edp(intel_dp))
6470                 return true;
6471
6472         /*
6473          * On IBX/CPT we may get here with LVDS already registered. Since the
6474          * driver uses the only internal power sequencer available for both
6475          * eDP and LVDS bail out early in this case to prevent interfering
6476          * with an already powered-on LVDS power sequencer.
6477          */
6478         if (intel_get_lvds_encoder(dev_priv)) {
6479                 drm_WARN_ON(&dev_priv->drm,
6480                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6481                 drm_info(&dev_priv->drm,
6482                          "LVDS was detected, not registering eDP\n");
6483
6484                 return false;
6485         }
6486
6487         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
6488                                     encoder->devdata);
6489
6490         if (!intel_pps_init(intel_dp)) {
6491                 drm_info(&dev_priv->drm,
6492                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6493                          encoder->base.base.id, encoder->base.name);
6494                 /*
6495                  * The BIOS may have still enabled VDD on the PPS even
6496                  * though it's unusable. Make sure we turn it back off
6497                  * and to release the power domain references/etc.
6498                  */
6499                 goto out_vdd_off;
6500         }
6501
6502         /*
6503          * Enable HPD sense for live status check.
6504          * intel_hpd_irq_setup() will turn it off again
6505          * if it's no longer needed later.
6506          *
6507          * The DPCD probe below will make sure VDD is on.
6508          */
6509         intel_hpd_enable_detection(encoder);
6510
6511         /* Cache DPCD and EDID for edp. */
6512         has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6513
6514         if (!has_dpcd) {
6515                 /* if this fails, presume the device is a ghost */
6516                 drm_info(&dev_priv->drm,
6517                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6518                          encoder->base.base.id, encoder->base.name);
6519                 goto out_vdd_off;
6520         }
6521
6522         /*
6523          * VBT and straps are liars. Also check HPD as that seems
6524          * to be the most reliable piece of information available.
6525          *
6526          * ... expect on devices that forgot to hook HPD up for eDP
6527          * (eg. Acer Chromebook C710), so we'll check it only if multiple
6528          * ports are attempting to use the same AUX CH, according to VBT.
6529          */
6530         if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6531                 /*
6532                  * If this fails, presume the DPCD answer came
6533                  * from some other port using the same AUX CH.
6534                  *
6535                  * FIXME maybe cleaner to check this before the
6536                  * DPCD read? Would need sort out the VDD handling...
6537                  */
6538                 if (!intel_digital_port_connected(encoder)) {
6539                         drm_info(&dev_priv->drm,
6540                                  "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6541                                  encoder->base.base.id, encoder->base.name);
6542                         goto out_vdd_off;
6543                 }
6544
6545                 /*
6546                  * Unfortunately even the HPD based detection fails on
6547                  * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6548                  * back to checking for a VGA branch device. Only do this
6549                  * on known affected platforms to minimize false positives.
6550                  */
6551                 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6552                     (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6553                     DP_DWN_STRM_PORT_TYPE_ANALOG) {
6554                         drm_info(&dev_priv->drm,
6555                                  "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6556                                  encoder->base.base.id, encoder->base.name);
6557                         goto out_vdd_off;
6558                 }
6559         }
6560
6561         mutex_lock(&dev_priv->drm.mode_config.mutex);
6562         drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6563         if (!drm_edid) {
6564                 /* Fallback to EDID from ACPI OpRegion, if any */
6565                 drm_edid = intel_opregion_get_edid(intel_connector);
6566                 if (drm_edid)
6567                         drm_dbg_kms(&dev_priv->drm,
6568                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6569                                     connector->base.id, connector->name);
6570         }
6571         if (drm_edid) {
6572                 if (drm_edid_connector_update(connector, drm_edid) ||
6573                     !drm_edid_connector_add_modes(connector)) {
6574                         drm_edid_connector_update(connector, NULL);
6575                         drm_edid_free(drm_edid);
6576                         drm_edid = ERR_PTR(-EINVAL);
6577                 }
6578         } else {
6579                 drm_edid = ERR_PTR(-ENOENT);
6580         }
6581
6582         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6583                                    IS_ERR(drm_edid) ? NULL : drm_edid);
6584
6585         intel_panel_add_edid_fixed_modes(intel_connector, true);
6586
6587         /* MSO requires information from the EDID */
6588         intel_edp_mso_init(intel_dp);
6589
6590         /* multiply the mode clock and horizontal timings for MSO */
6591         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6592                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6593
6594         /* fallback to VBT if available for eDP */
6595         if (!intel_panel_preferred_fixed_mode(intel_connector))
6596                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6597
6598         mutex_unlock(&dev_priv->drm.mode_config.mutex);
6599
6600         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6601                 drm_info(&dev_priv->drm,
6602                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6603                          encoder->base.base.id, encoder->base.name);
6604                 goto out_vdd_off;
6605         }
6606
6607         intel_panel_init(intel_connector, drm_edid);
6608
6609         intel_edp_backlight_setup(intel_dp, intel_connector);
6610
6611         intel_edp_add_properties(intel_dp);
6612
6613         intel_pps_init_late(intel_dp);
6614
6615         return true;
6616
6617 out_vdd_off:
6618         intel_pps_vdd_off_sync(intel_dp);
6619
6620         return false;
6621 }
6622
6623 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6624 {
6625         struct intel_connector *intel_connector;
6626         struct drm_connector *connector;
6627
6628         intel_connector = container_of(work, typeof(*intel_connector),
6629                                        modeset_retry_work);
6630         connector = &intel_connector->base;
6631         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6632                     connector->name);
6633
6634         /* Grab the locks before changing connector property*/
6635         mutex_lock(&connector->dev->mode_config.mutex);
6636         /* Set connector link status to BAD and send a Uevent to notify
6637          * userspace to do a modeset.
6638          */
6639         drm_connector_set_link_status_property(connector,
6640                                                DRM_MODE_LINK_STATUS_BAD);
6641         mutex_unlock(&connector->dev->mode_config.mutex);
6642         /* Send Hotplug uevent so userspace can reprobe */
6643         drm_kms_helper_connector_hotplug_event(connector);
6644
6645         drm_connector_put(connector);
6646 }
6647
6648 void intel_dp_init_modeset_retry_work(struct intel_connector *connector)
6649 {
6650         INIT_WORK(&connector->modeset_retry_work,
6651                   intel_dp_modeset_retry_work_fn);
6652 }
6653
6654 bool
6655 intel_dp_init_connector(struct intel_digital_port *dig_port,
6656                         struct intel_connector *intel_connector)
6657 {
6658         struct drm_connector *connector = &intel_connector->base;
6659         struct intel_dp *intel_dp = &dig_port->dp;
6660         struct intel_encoder *intel_encoder = &dig_port->base;
6661         struct drm_device *dev = intel_encoder->base.dev;
6662         struct drm_i915_private *dev_priv = to_i915(dev);
6663         enum port port = intel_encoder->port;
6664         int type;
6665
6666         /* Initialize the work for modeset in case of link train failure */
6667         intel_dp_init_modeset_retry_work(intel_connector);
6668
6669         if (drm_WARN(dev, dig_port->max_lanes < 1,
6670                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6671                      dig_port->max_lanes, intel_encoder->base.base.id,
6672                      intel_encoder->base.name))
6673                 return false;
6674
6675         intel_dp->reset_link_params = true;
6676         intel_dp->pps.pps_pipe = INVALID_PIPE;
6677         intel_dp->pps.active_pipe = INVALID_PIPE;
6678
6679         /* Preserve the current hw state. */
6680         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6681         intel_dp->attached_connector = intel_connector;
6682
6683         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6684                 /*
6685                  * Currently we don't support eDP on TypeC ports, although in
6686                  * theory it could work on TypeC legacy ports.
6687                  */
6688                 drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder));
6689                 type = DRM_MODE_CONNECTOR_eDP;
6690                 intel_encoder->type = INTEL_OUTPUT_EDP;
6691
6692                 /* eDP only on port B and/or C on vlv/chv */
6693                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6694                                       IS_CHERRYVIEW(dev_priv)) &&
6695                                 port != PORT_B && port != PORT_C))
6696                         return false;
6697         } else {
6698                 type = DRM_MODE_CONNECTOR_DisplayPort;
6699         }
6700
6701         intel_dp_set_default_sink_rates(intel_dp);
6702         intel_dp_set_default_max_sink_lane_count(intel_dp);
6703
6704         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6705                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6706
6707         intel_dp_aux_init(intel_dp);
6708         intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6709
6710         drm_dbg_kms(&dev_priv->drm,
6711                     "Adding %s connector on [ENCODER:%d:%s]\n",
6712                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6713                     intel_encoder->base.base.id, intel_encoder->base.name);
6714
6715         drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6716                                     type, &intel_dp->aux.ddc);
6717         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6718
6719         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6720                 connector->interlace_allowed = true;
6721
6722         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6723         intel_connector->base.polled = intel_connector->polled;
6724
6725         intel_connector_attach_encoder(intel_connector, intel_encoder);
6726
6727         if (HAS_DDI(dev_priv))
6728                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6729         else
6730                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6731         intel_connector->sync_state = intel_dp_connector_sync_state;
6732
6733         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6734                 intel_dp_aux_fini(intel_dp);
6735                 goto fail;
6736         }
6737
6738         intel_dp_set_source_rates(intel_dp);
6739         intel_dp_set_common_rates(intel_dp);
6740         intel_dp_reset_max_link_params(intel_dp);
6741
6742         /* init MST on ports that can support it */
6743         intel_dp_mst_encoder_init(dig_port,
6744                                   intel_connector->base.base.id);
6745
6746         intel_dp_add_properties(intel_dp, connector);
6747
6748         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6749                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6750                 if (ret)
6751                         drm_dbg_kms(&dev_priv->drm,
6752                                     "HDCP init failed, skipping.\n");
6753         }
6754
6755         intel_dp->colorimetry_support =
6756                 intel_dp_get_colorimetry_status(intel_dp);
6757
6758         intel_dp->frl.is_trained = false;
6759         intel_dp->frl.trained_rate_gbps = 0;
6760
6761         intel_psr_init(intel_dp);
6762
6763         return true;
6764
6765 fail:
6766         intel_display_power_flush_work(dev_priv);
6767         drm_connector_cleanup(connector);
6768
6769         return false;
6770 }
6771
6772 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6773 {
6774         struct intel_encoder *encoder;
6775
6776         if (!HAS_DISPLAY(dev_priv))
6777                 return;
6778
6779         for_each_intel_encoder(&dev_priv->drm, encoder) {
6780                 struct intel_dp *intel_dp;
6781
6782                 if (encoder->type != INTEL_OUTPUT_DDI)
6783                         continue;
6784
6785                 intel_dp = enc_to_intel_dp(encoder);
6786
6787                 if (!intel_dp_mst_source_support(intel_dp))
6788                         continue;
6789
6790                 if (intel_dp->is_mst)
6791                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6792         }
6793 }
6794
6795 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6796 {
6797         struct intel_encoder *encoder;
6798
6799         if (!HAS_DISPLAY(dev_priv))
6800                 return;
6801
6802         for_each_intel_encoder(&dev_priv->drm, encoder) {
6803                 struct intel_dp *intel_dp;
6804                 int ret;
6805
6806                 if (encoder->type != INTEL_OUTPUT_DDI)
6807                         continue;
6808
6809                 intel_dp = enc_to_intel_dp(encoder);
6810
6811                 if (!intel_dp_mst_source_support(intel_dp))
6812                         continue;
6813
6814                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6815                                                      true);
6816                 if (ret) {
6817                         intel_dp->is_mst = false;
6818                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6819                                                         false);
6820                 }
6821         }
6822 }