2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/i2c.h>
30 #include <linux/pm_qos.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
34 #include <drm/display/drm_dp_dual_mode_helper.h>
35 #include <drm/display/drm_dp_mst_helper.h>
36 #include <drm/display/drm_dsc.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_encoder.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_framebuffer.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_rect.h>
44 #include <drm/drm_vblank.h>
45 #include <drm/drm_vblank_work.h>
46 #include <drm/i915_mei_hdcp_interface.h>
47 #include <media/cec-notifier.h>
50 #include "i915_vma_types.h"
51 #include "intel_bios.h"
52 #include "intel_display.h"
53 #include "intel_display_power.h"
54 #include "intel_dpll_mgr.h"
55 #include "intel_pm_types.h"
58 struct __intel_global_objs_state;
59 struct intel_ddi_buf_trans;
61 struct intel_connector;
64 * Display related stuff
67 /* these are outputs from the chip - integrated only
68 external chips are via DVO or SDVO output */
69 enum intel_output_type {
70 INTEL_OUTPUT_UNUSED = 0,
71 INTEL_OUTPUT_ANALOG = 1,
73 INTEL_OUTPUT_SDVO = 3,
74 INTEL_OUTPUT_LVDS = 4,
75 INTEL_OUTPUT_TVOUT = 5,
76 INTEL_OUTPUT_HDMI = 6,
80 INTEL_OUTPUT_DDI = 10,
81 INTEL_OUTPUT_DP_MST = 11,
84 enum hdmi_force_audio {
85 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
86 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
87 HDMI_AUDIO_AUTO, /* trust EDID */
88 HDMI_AUDIO_ON, /* force turn on HDMI audio */
91 /* "Broadcast RGB" property */
92 enum intel_broadcast_rgb {
93 INTEL_BROADCAST_RGB_AUTO,
94 INTEL_BROADCAST_RGB_FULL,
95 INTEL_BROADCAST_RGB_LIMITED,
98 struct intel_fb_view {
100 * The remap information used in the remapped and rotated views to
101 * create the DMA scatter-gather list for each FB color plane. This sg
102 * list is created along with the view type (gtt.type) specific
103 * i915_vma object and contains the list of FB object pages (reordered
104 * in the rotated view) that are visible in the view.
105 * In the normal view the FB object's backing store sg list is used
106 * directly and hence the remap information here is not used.
108 struct i915_ggtt_view gtt;
111 * The GTT view (gtt.type) specific information for each FB color
112 * plane. In the normal GTT view all formats (up to 4 color planes),
113 * in the rotated and remapped GTT view all no-CCS formats (up to 2
114 * color planes) are supported.
116 * The view information shared by all FB color planes in the FB,
117 * like dst x/y and src/dst width, is stored separately in
120 struct i915_color_plane_view {
125 * bytes for 0/180 degree rotation
126 * pixels for 90/270 degree rotation
128 unsigned int mapping_stride;
129 unsigned int scanout_stride;
133 struct intel_framebuffer {
134 struct drm_framebuffer base;
135 struct intel_frontbuffer *frontbuffer;
137 /* Params to remap the FB pages and program the plane registers in each view. */
138 struct intel_fb_view normal_view;
140 struct intel_fb_view rotated_view;
141 struct intel_fb_view remapped_view;
144 struct i915_address_space *dpt_vm;
147 enum intel_hotplug_state {
148 INTEL_HOTPLUG_UNCHANGED,
149 INTEL_HOTPLUG_CHANGED,
153 struct intel_encoder {
154 struct drm_encoder base;
156 enum intel_output_type type;
160 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
161 struct intel_connector *connector);
162 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
163 struct intel_crtc_state *,
164 struct drm_connector_state *);
165 int (*compute_config)(struct intel_encoder *,
166 struct intel_crtc_state *,
167 struct drm_connector_state *);
168 int (*compute_config_late)(struct intel_encoder *,
169 struct intel_crtc_state *,
170 struct drm_connector_state *);
171 void (*update_prepare)(struct intel_atomic_state *,
172 struct intel_encoder *,
173 struct intel_crtc *);
174 void (*pre_pll_enable)(struct intel_atomic_state *,
175 struct intel_encoder *,
176 const struct intel_crtc_state *,
177 const struct drm_connector_state *);
178 void (*pre_enable)(struct intel_atomic_state *,
179 struct intel_encoder *,
180 const struct intel_crtc_state *,
181 const struct drm_connector_state *);
182 void (*enable)(struct intel_atomic_state *,
183 struct intel_encoder *,
184 const struct intel_crtc_state *,
185 const struct drm_connector_state *);
186 void (*update_complete)(struct intel_atomic_state *,
187 struct intel_encoder *,
188 struct intel_crtc *);
189 void (*disable)(struct intel_atomic_state *,
190 struct intel_encoder *,
191 const struct intel_crtc_state *,
192 const struct drm_connector_state *);
193 void (*post_disable)(struct intel_atomic_state *,
194 struct intel_encoder *,
195 const struct intel_crtc_state *,
196 const struct drm_connector_state *);
197 void (*post_pll_disable)(struct intel_atomic_state *,
198 struct intel_encoder *,
199 const struct intel_crtc_state *,
200 const struct drm_connector_state *);
201 void (*update_pipe)(struct intel_atomic_state *,
202 struct intel_encoder *,
203 const struct intel_crtc_state *,
204 const struct drm_connector_state *);
205 /* Read out the current hw state of this connector, returning true if
206 * the encoder is active. If the encoder is enabled it also set the pipe
207 * it is connected to in the pipe parameter. */
208 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
209 /* Reconstructs the equivalent mode flags for the current hardware
210 * state. This must be called _after_ display->get_pipe_config has
211 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
212 * be set correctly before calling this function. */
213 void (*get_config)(struct intel_encoder *,
214 struct intel_crtc_state *pipe_config);
217 * Optional hook called during init/resume to sync any state
218 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
220 void (*sync_state)(struct intel_encoder *encoder,
221 const struct intel_crtc_state *crtc_state);
224 * Optional hook, returning true if this encoder allows a fastset
225 * during the initial commit, false otherwise.
227 bool (*initial_fastset_check)(struct intel_encoder *encoder,
228 struct intel_crtc_state *crtc_state);
231 * Acquires the power domains needed for an active encoder during
232 * hardware state readout.
234 void (*get_power_domains)(struct intel_encoder *encoder,
235 struct intel_crtc_state *crtc_state);
237 * Called during system suspend after all pending requests for the
238 * encoder are flushed (for example for DP AUX transactions) and
239 * device interrupts are disabled.
241 void (*suspend)(struct intel_encoder *);
243 * Called during system reboot/shutdown after all the
244 * encoders have been disabled and suspended.
246 void (*shutdown)(struct intel_encoder *encoder);
248 * Enable/disable the clock to the port.
250 void (*enable_clock)(struct intel_encoder *encoder,
251 const struct intel_crtc_state *crtc_state);
252 void (*disable_clock)(struct intel_encoder *encoder);
254 * Returns whether the port clock is enabled or not.
256 bool (*is_clock_enabled)(struct intel_encoder *encoder);
257 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
258 const struct intel_crtc_state *crtc_state,
260 void (*set_signal_levels)(struct intel_encoder *encoder,
261 const struct intel_crtc_state *crtc_state);
263 enum hpd_pin hpd_pin;
264 enum intel_display_power_domain power_domain;
265 /* for communication with audio component; protected by av_mutex */
266 const struct drm_connector *audio_connector;
268 /* VBT information for this encoder (may be NULL for older platforms) */
269 const struct intel_bios_encoder_data *devdata;
272 struct intel_panel_bl_funcs {
273 /* Connector and platform specific backlight functions */
274 int (*setup)(struct intel_connector *connector, enum pipe pipe);
275 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
276 void (*set)(const struct drm_connector_state *conn_state, u32 level);
277 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
278 void (*enable)(const struct intel_crtc_state *crtc_state,
279 const struct drm_connector_state *conn_state, u32 level);
280 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
289 struct intel_vbt_panel_data {
290 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
291 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
294 unsigned int panel_type:4;
295 unsigned int lvds_dither:1;
296 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
300 u8 seamless_drrs_min_refresh_rate;
301 enum drrs_type drrs_type;
310 struct edp_power_seq pps;
311 u8 drrs_msa_timing_delay;
320 bool require_aux_wakeup;
322 int tp1_wakeup_time_us;
323 int tp2_tp3_wakeup_time_us;
324 int psr2_tp2_tp3_wakeup_time_us;
329 u16 brightness_precision_bits;
332 u8 min_brightness; /* min_brightness/255 of max */
333 u8 controller; /* brightness controller number */
334 enum intel_backlight_type type;
340 struct mipi_config *config;
341 struct mipi_pps_data *pps;
347 const u8 *sequence[MIPI_SEQ_MAX];
348 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
349 enum drm_panel_orientation orientation;
354 struct list_head fixed_modes;
363 bool combination_mode; /* gen 2/4 only */
365 bool alternate_pwm_increment; /* lpt+ */
371 bool util_pin_active_low; /* bxt+ */
372 u8 controller; /* bxt+ only */
373 struct pwm_device *pwm;
374 struct pwm_state pwm_state;
379 struct drm_edp_backlight_info info;
386 struct backlight_device *device;
388 const struct intel_panel_bl_funcs *funcs;
389 const struct intel_panel_bl_funcs *pwm_funcs;
390 void (*power)(struct intel_connector *, bool enable);
393 struct intel_vbt_panel_data vbt;
396 struct intel_digital_port;
398 enum check_link_response {
399 HDCP_LINK_PROTECTED = 0,
400 HDCP_TOPOLOGY_CHANGE,
401 HDCP_LINK_INTEGRITY_FAILURE,
406 * This structure serves as a translation layer between the generic HDCP code
407 * and the bus-specific code. What that means is that HDCP over HDMI differs
408 * from HDCP over DP, so to account for these differences, we need to
409 * communicate with the receiver through this shim.
411 * For completeness, the 2 buses differ in the following ways:
413 * HDCP registers on the receiver are set via DP AUX for DP, and
414 * they are set via DDC for HDMI.
415 * - Receiver register offsets
416 * The offsets of the registers are different for DP vs. HDMI
417 * - Receiver register masks/offsets
418 * For instance, the ready bit for the KSV fifo is in a different
419 * place on DP vs HDMI
420 * - Receiver register names
421 * Seriously. In the DP spec, the 16-bit register containing
422 * downstream information is called BINFO, on HDMI it's called
423 * BSTATUS. To confuse matters further, DP has a BSTATUS register
424 * with a completely different definition.
426 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
427 * be read 3 keys at a time
429 * Since Aksv is hidden in hardware, there's different procedures
430 * to send it over DP AUX vs DDC
432 struct intel_hdcp_shim {
433 /* Outputs the transmitter's An and Aksv values to the receiver. */
434 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
436 /* Reads the receiver's key selection vector */
437 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
440 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
441 * definitions are the same in the respective specs, but the names are
442 * different. Call it BSTATUS since that's the name the HDMI spec
443 * uses and it was there first.
445 int (*read_bstatus)(struct intel_digital_port *dig_port,
448 /* Determines whether a repeater is present downstream */
449 int (*repeater_present)(struct intel_digital_port *dig_port,
450 bool *repeater_present);
452 /* Reads the receiver's Ri' value */
453 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
455 /* Determines if the receiver's KSV FIFO is ready for consumption */
456 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
459 /* Reads the ksv fifo for num_downstream devices */
460 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
461 int num_downstream, u8 *ksv_fifo);
463 /* Reads a 32-bit part of V' from the receiver */
464 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
467 /* Enables HDCP signalling on the port */
468 int (*toggle_signalling)(struct intel_digital_port *dig_port,
469 enum transcoder cpu_transcoder,
472 /* Enable/Disable stream encryption on DP MST Transport Link */
473 int (*stream_encryption)(struct intel_connector *connector,
476 /* Ensures the link is still protected */
477 bool (*check_link)(struct intel_digital_port *dig_port,
478 struct intel_connector *connector);
480 /* Detects panel's hdcp capability. This is optional for HDMI. */
481 int (*hdcp_capable)(struct intel_digital_port *dig_port,
484 /* HDCP adaptation(DP/HDMI) required on the port */
485 enum hdcp_wired_protocol protocol;
487 /* Detects whether sink is HDCP2.2 capable */
488 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
491 /* Write HDCP2.2 messages */
492 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
493 void *buf, size_t size);
495 /* Read HDCP2.2 messages */
496 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
497 u8 msg_id, void *buf, size_t size);
500 * Implementation of DP HDCP2.2 Errata for the communication of stream
501 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
502 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
504 int (*config_stream_type)(struct intel_digital_port *dig_port,
505 bool is_repeater, u8 type);
507 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
508 int (*stream_2_2_encryption)(struct intel_connector *connector,
511 /* HDCP2.2 Link Integrity Check */
512 int (*check_2_2_link)(struct intel_digital_port *dig_port,
513 struct intel_connector *connector);
517 const struct intel_hdcp_shim *shim;
518 /* Mutex for hdcp state of the connector */
521 struct delayed_work check_work;
522 struct work_struct prop_work;
524 /* HDCP1.4 Encryption status */
527 /* HDCP2.2 related definitions */
528 /* Flag indicates whether this connector supports HDCP2.2 or not. */
529 bool hdcp2_supported;
531 /* HDCP2.2 Encryption status */
532 bool hdcp2_encrypted;
535 * Content Stream Type defined by content owner. TYPE0(0x0) content can
536 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
537 * content can flow only through a link protected by HDCP2.2.
545 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
546 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
547 * When it rolls over re-auth has to be triggered.
552 * Count of RepeaterAuth_Stream_Manage msg propagated.
553 * Initialized to 0 on AKE_INIT. Incremented after every successful
554 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
555 * over re-Auth has to be triggered.
560 * Work queue to signal the CP_IRQ. Used for the waiters to read the
561 * available information from HDCP DP sink.
563 wait_queue_head_t cp_irq_queue;
564 atomic_t cp_irq_count;
565 int cp_irq_count_cached;
568 * HDCP register access for gen12+ need the transcoder associated.
569 * Transcoder attached to the connector could be changed at modeset.
570 * Hence caching the transcoder here.
572 enum transcoder cpu_transcoder;
573 /* Only used for DP MST stream encryption */
574 enum transcoder stream_transcoder;
577 struct intel_connector {
578 struct drm_connector base;
580 * The fixed encoder this connector is connected to.
582 struct intel_encoder *encoder;
584 /* ACPI device id for ACPI and driver cooperation */
587 /* Reads out the current hw, returning true if the connector is enabled
588 * and active (i.e. dpms ON state). */
589 bool (*get_hw_state)(struct intel_connector *);
591 /* Panel info for eDP and LVDS */
592 struct intel_panel panel;
594 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
596 struct edid *detect_edid;
598 /* Number of times hotplug detection was tried after an HPD interrupt */
601 /* since POLL and HPD connectors may use the same HPD line keep the native
602 state of connector->polled in case hotplug storm detection changes it */
605 struct drm_dp_mst_port *port;
607 struct intel_dp *mst_port;
609 /* Work struct to schedule a uevent on link train failure */
610 struct work_struct modeset_retry_work;
612 struct intel_hdcp hdcp;
615 struct intel_digital_connector_state {
616 struct drm_connector_state base;
618 enum hdmi_force_audio force_audio;
622 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
636 struct intel_atomic_state {
637 struct drm_atomic_state base;
639 intel_wakeref_t wakeref;
641 struct __intel_global_objs_state *global_objs;
644 bool dpll_set, modeset;
646 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
649 * Current watermarks can't be trusted during hardware readout, so
650 * don't bother calculating intermediate watermarks.
652 bool skip_intermediate_wm;
654 bool rps_interactive;
656 struct i915_sw_fence commit_ready;
658 struct llist_node freed;
661 struct intel_plane_state {
662 struct drm_plane_state uapi;
665 * actual hardware state, the state we program to the hardware.
666 * The following members are used to verify the hardware state:
667 * During initial hw readout, they need to be copied from uapi.
670 struct drm_crtc *crtc;
671 struct drm_framebuffer *fb;
674 u16 pixel_blend_mode;
675 unsigned int rotation;
676 enum drm_color_encoding color_encoding;
677 enum drm_color_range color_range;
678 enum drm_scaling_filter scaling_filter;
681 struct i915_vma *ggtt_vma;
682 struct i915_vma *dpt_vma;
684 #define PLANE_HAS_FENCE BIT(0)
686 struct intel_fb_view view;
688 /* Plane pxp decryption state */
691 /* Plane state to display black pixels when pxp is borked */
694 /* plane control register */
697 /* plane color control register */
700 /* chroma upsampler control register */
705 * = -1 : not using a scaler
706 * >= 0 : using a scalers
708 * plane requiring a scaler:
709 * - During check_plane, its bit is set in
710 * crtc_state->scaler_state.scaler_users by calling helper function
711 * update_scaler_plane.
712 * - scaler_id indicates the scaler it got assigned.
714 * plane doesn't require a scaler:
715 * - this can happen when scaling is no more required or plane simply
717 * - During check_plane, corresponding bit is reset in
718 * crtc_state->scaler_state.scaler_users by calling helper function
719 * update_scaler_plane.
724 * planar_linked_plane:
726 * ICL planar formats require 2 planes that are updated as pairs.
727 * This member is used to make sure the other plane is also updated
728 * when required, and for update_slave() to find the correct
729 * plane_state to pass as argument.
731 struct intel_plane *planar_linked_plane;
735 * If set don't update use the linked plane's state for updating
736 * this plane during atomic commit with the update_slave() callback.
738 * It's also used by the watermark code to ignore wm calculations on
739 * this plane. They're calculated by the linked plane's wm code.
743 struct drm_intel_sprite_colorkey ckey;
745 struct drm_rect psr2_sel_fetch_area;
747 /* Clear Color Value */
750 const char *no_fbc_reason;
753 struct intel_initial_plane_config {
754 struct intel_framebuffer *fb;
755 struct i915_vma *vma;
762 struct intel_scaler {
767 struct intel_crtc_scaler_state {
768 #define SKL_NUM_SCALERS 2
769 struct intel_scaler scalers[SKL_NUM_SCALERS];
772 * scaler_users: keeps track of users requesting scalers on this crtc.
774 * If a bit is set, a user is using a scaler.
775 * Here user can be a plane or crtc as defined below:
776 * bits 0-30 - plane (bit position is index from drm_plane_index)
779 * Instead of creating a new index to cover planes and crtc, using
780 * existing drm_plane_index for planes which is well less than 31
781 * planes and bit 31 for crtc. This should be fine to cover all
784 * intel_atomic_setup_scalers will setup available scalers to users
785 * requesting scalers. It will gracefully fail if request exceeds
788 #define SKL_CRTC_INDEX 31
789 unsigned scaler_users;
791 /* scaler used by crtc for panel fitting purpose */
795 /* {crtc,crtc_state}->mode_flags */
796 /* Flag to get scanline using frame time stamps */
797 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
798 /* Flag to use the scanline counter instead of the pixel counter */
799 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
801 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
802 * is operating in command mode.
803 * Flag to use TE from DSI0 instead of VBI in command mode
805 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
806 /* Flag to use TE from DSI1 instead of VBI in command mode */
807 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
808 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
809 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
810 /* Do tricks to make vblank timestamps sane with VRR? */
811 #define I915_MODE_FLAG_VRR (1<<6)
813 struct intel_wm_level {
821 struct intel_pipe_wm {
822 struct intel_wm_level wm[5];
825 bool sprites_enabled;
829 struct skl_wm_level {
838 struct skl_plane_wm {
839 struct skl_wm_level wm[8];
840 struct skl_wm_level uv_wm[8];
841 struct skl_wm_level trans_wm;
843 struct skl_wm_level wm0;
844 struct skl_wm_level trans_wm;
850 struct skl_plane_wm planes[I915_MAX_PLANES];
857 VLV_WM_LEVEL_DDR_DVFS,
861 struct vlv_wm_state {
862 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
863 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
868 struct vlv_fifo_state {
869 u16 plane[I915_MAX_PLANES];
879 struct g4x_wm_state {
880 struct g4x_pipe_wm wm;
882 struct g4x_sr_wm hpll;
888 struct intel_crtc_wm_state {
892 * The "raw" watermark values produced by the formula
893 * given the plane's current state. They do not consider
894 * how much FIFO is actually allocated for each plane.
897 * The "optimal" watermark values given the current
898 * state of the planes and the amount of FIFO
899 * allocated to each, ignoring any previous state
903 * The "intermediate" watermark values when transitioning
904 * between the old and new "optimal" values. Used when
905 * the watermark registers are single buffered and hence
906 * their state changes asynchronously with regards to the
907 * actual plane registers. These are essentially the
908 * worst case combination of the old and new "optimal"
909 * watermarks, which are therefore safe to use when the
910 * plane is in either its old or new state.
913 struct intel_pipe_wm intermediate;
914 struct intel_pipe_wm optimal;
918 struct skl_pipe_wm raw;
919 /* gen9+ only needs 1-step wm programming */
920 struct skl_pipe_wm optimal;
921 struct skl_ddb_entry ddb;
923 * pre-icl: for packed/planar CbCr
924 * icl+: for everything
926 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
927 /* pre-icl: for planar Y */
928 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
932 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
933 struct vlv_wm_state intermediate; /* inverted */
934 struct vlv_wm_state optimal; /* inverted */
935 struct vlv_fifo_state fifo_state;
939 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
940 struct g4x_wm_state intermediate;
941 struct g4x_wm_state optimal;
946 * Platforms with two-step watermark programming will need to
947 * update watermark programming post-vblank to switch from the
948 * safe intermediate watermarks to the optimal final
951 bool need_postvbl_update;
954 enum intel_output_format {
955 INTEL_OUTPUT_FORMAT_RGB,
956 INTEL_OUTPUT_FORMAT_YCBCR420,
957 INTEL_OUTPUT_FORMAT_YCBCR444,
960 struct intel_mpllb_state {
961 u32 clock; /* in KHz */
972 struct intel_crtc_state {
974 * uapi (drm) state. This is the software state shown to userspace.
975 * In particular, the following members are used for bookkeeping:
983 struct drm_crtc_state uapi;
986 * actual hardware state, the state we program to the hardware.
987 * The following members are used to verify the hardware state:
990 * - mode / pipe_mode / adjusted_mode
991 * - color property blobs.
993 * During initial hw readout, they need to be copied to uapi.
995 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
996 * Use the pipe_mode for calculations like watermarks, pipe
997 * scaler, and bandwidth.
999 * Use adjusted_mode for things that need to know the full
1000 * mode on the transcoder, which spans all pipes.
1003 bool active, enable;
1004 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
1005 struct drm_display_mode mode, pipe_mode, adjusted_mode;
1006 enum drm_scaling_filter scaling_filter;
1010 * quirks - bitfield with hw state readout quirks
1012 * For various reasons the hw state readout code might not be able to
1013 * completely faithfully read out the current state. These cases are
1014 * tracked with quirk flags so that fastboot and state checker can act
1017 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
1018 unsigned long quirks;
1020 unsigned fb_bits; /* framebuffers to flip */
1021 bool update_pipe; /* can a fast modeset be performed? */
1023 bool update_wm_pre, update_wm_post; /* watermarks are updated */
1024 bool fifo_changed; /* FIFO split is changed */
1026 bool inherited; /* state inherited from BIOS? */
1028 /* Ask the hardware to actually async flip? */
1031 /* Pipe source size (ie. panel fitter input size)
1032 * All planes will be positioned inside this space,
1033 * and get clipped at the edges. */
1034 struct drm_rect pipe_src;
1037 * Pipe pixel rate, adjusted for
1038 * panel fitter/pipe scaler downscaling.
1040 unsigned int pixel_rate;
1042 /* Whether to set up the PCH/FDI. Note that we never allow sharing
1043 * between pch encoders and cpu encoders. */
1044 bool has_pch_encoder;
1046 /* Are we sending infoframes on the attached port */
1049 /* CPU Transcoder for the pipe. Currently this can only differ from the
1050 * pipe on Haswell and later (where we have a special eDP transcoder)
1051 * and Broxton (where we have special DSI transcoders). */
1052 enum transcoder cpu_transcoder;
1055 * Use reduced/limited/broadcast rbg range, compressing from the full
1056 * range fed into the crtcs.
1058 bool limited_color_range;
1060 /* Bitmask of encoder types (enum intel_output_type)
1061 * driven by the pipe.
1063 unsigned int output_types;
1065 /* Whether we should send NULL infoframes. Required for audio. */
1068 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1069 * has_dp_encoder is set. */
1073 * Enable dithering, used when the selected pipe bpp doesn't match the
1079 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1080 * compliance video pattern tests.
1081 * Disable dither only if it is a compliance test request for
1084 bool dither_force_disable;
1086 /* Controls for the clock computation, to override various stages. */
1089 /* SDVO TV has a bunch of special case. To make multifunction encoders
1090 * work correctly, we need to track this at runtime.*/
1094 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1095 * required. This is set in the 2nd loop of calling encoder's
1096 * ->compute_config if the first pick doesn't work out.
1098 bool bw_constrained;
1100 /* Settings for the intel dpll used on pretty much everything but
1104 /* Selected dpll when shared or NULL. */
1105 struct intel_shared_dpll *shared_dpll;
1107 /* Actual register state of the dpll, for shared dpll cross-checking. */
1109 struct intel_dpll_hw_state dpll_hw_state;
1110 struct intel_mpllb_state mpllb_state;
1114 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1115 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1117 struct icl_port_dpll {
1118 struct intel_shared_dpll *pll;
1119 struct intel_dpll_hw_state hw_state;
1120 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1122 /* DSI PLL registers */
1128 struct intel_link_m_n dp_m_n;
1130 /* m2_n2 for eDP downclock */
1131 struct intel_link_m_n dp_m2_n2;
1134 /* PSR is supported but might not be enabled due the lack of enabled planes */
1137 bool enable_psr2_sel_fetch;
1138 bool req_psr2_sdp_prior_scanline;
1140 u16 su_y_granularity;
1141 struct drm_dp_vsc_sdp psr_vsc;
1144 * Frequence the dpll for the port should run at. Differs from the
1145 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1146 * already multiplied by pixel_multiplier.
1150 /* Used by SDVO (and if we ever fix it, HDMI). */
1151 unsigned pixel_multiplier;
1153 /* I915_MODE_FLAG_* */
1159 * Used by platforms having DP/HDMI PHY with programmable lane
1160 * latency optimization.
1162 u8 lane_lat_optim_mask;
1164 /* minimum acceptable voltage level */
1165 u8 min_voltage_level;
1167 /* Panel fitter controls for gen2-gen4 + VLV */
1171 u32 lvds_border_bits;
1174 /* Panel fitter placement and size for Ironlake+ */
1176 struct drm_rect dst;
1181 /* FDI configuration, only valid if has_pch_encoder is set. */
1183 struct intel_link_m_n fdi_m_n;
1193 struct intel_crtc_scaler_state scaler_state;
1195 /* w/a for waiting 2 vblanks during crtc enable */
1196 enum pipe hsw_workaround_pipe;
1198 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1201 struct intel_crtc_wm_state wm;
1203 int min_cdclk[I915_MAX_PLANES];
1205 /* for packed/planar CbCr */
1206 u32 data_rate[I915_MAX_PLANES];
1208 u32 data_rate_y[I915_MAX_PLANES];
1210 /* FIXME unify with data_rate[]? */
1211 u64 rel_data_rate[I915_MAX_PLANES];
1212 u64 rel_data_rate_y[I915_MAX_PLANES];
1214 /* Gamma mode programmed on the pipe */
1218 /* CSC mode programmed on the pipe */
1225 /* bitmask of logically enabled planes (enum plane_id) */
1228 /* bitmask of actually visible planes (enum plane_id) */
1234 /* bitmask of planes that will be updated during the commit */
1237 u8 framestart_delay; /* 1-4 */
1238 u8 msa_timing_delay; /* 0-3 */
1243 union hdmi_infoframe avi;
1244 union hdmi_infoframe spd;
1245 union hdmi_infoframe hdmi;
1246 union hdmi_infoframe drm;
1247 struct drm_dp_vsc_sdp vsc;
1250 /* HDMI scrambling status */
1251 bool hdmi_scrambling;
1253 /* HDMI High TMDS char rate ratio */
1254 bool hdmi_high_tmds_clock_ratio;
1256 /* Output format RGB/YCBCR etc */
1257 enum intel_output_format output_format;
1259 /* enable pipe gamma? */
1262 /* enable pipe csc? */
1265 /* big joiner pipe bitmask */
1268 /* Display Stream compression state */
1270 bool compression_enable;
1274 struct drm_dsc_config config;
1277 /* HSW+ linetime watermarks */
1281 /* Forward Error correction State */
1284 /* Pointer to master transcoder in case of tiled displays */
1285 enum transcoder master_transcoder;
1287 /* Bitmask to indicate slaves attached */
1288 u8 sync_mode_slaves_mask;
1290 /* Only valid on TGL+ */
1291 enum transcoder mst_master_transcoder;
1293 /* For DSB related info */
1294 struct intel_dsb *dsb;
1296 u32 psr2_man_track_ctl;
1298 /* Variable Refresh Rate state */
1302 u16 flipline, vmin, vmax, guardband;
1305 /* Stream Splitter for eDP MSO */
1312 /* for loading single buffered registers during vblank */
1313 struct drm_vblank_work vblank_work;
1316 enum intel_pipe_crc_source {
1317 INTEL_PIPE_CRC_SOURCE_NONE,
1318 INTEL_PIPE_CRC_SOURCE_PLANE1,
1319 INTEL_PIPE_CRC_SOURCE_PLANE2,
1320 INTEL_PIPE_CRC_SOURCE_PLANE3,
1321 INTEL_PIPE_CRC_SOURCE_PLANE4,
1322 INTEL_PIPE_CRC_SOURCE_PLANE5,
1323 INTEL_PIPE_CRC_SOURCE_PLANE6,
1324 INTEL_PIPE_CRC_SOURCE_PLANE7,
1325 INTEL_PIPE_CRC_SOURCE_PIPE,
1326 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1327 INTEL_PIPE_CRC_SOURCE_TV,
1328 INTEL_PIPE_CRC_SOURCE_DP_B,
1329 INTEL_PIPE_CRC_SOURCE_DP_C,
1330 INTEL_PIPE_CRC_SOURCE_DP_D,
1331 INTEL_PIPE_CRC_SOURCE_AUTO,
1332 INTEL_PIPE_CRC_SOURCE_MAX,
1335 enum drrs_refresh_rate {
1336 DRRS_REFRESH_RATE_HIGH,
1337 DRRS_REFRESH_RATE_LOW,
1340 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1341 struct intel_pipe_crc {
1344 enum intel_pipe_crc_source source;
1348 struct drm_crtc base;
1351 * Whether the crtc and the connected output pipeline is active. Implies
1352 * that crtc->enabled is set, i.e. the current mode configuration has
1353 * some outputs connected to this crtc.
1358 /* I915_MODE_FLAG_* */
1361 u16 vmax_vblank_start;
1363 struct intel_display_power_domain_set enabled_power_domains;
1364 struct intel_overlay *overlay;
1366 struct intel_crtc_state *config;
1368 /* Access to these should be protected by dev_priv->irq_lock. */
1369 bool cpu_fifo_underrun_disabled;
1370 bool pch_fifo_underrun_disabled;
1372 /* per-pipe watermark state */
1374 /* watermarks currently being used */
1376 struct intel_pipe_wm ilk;
1377 struct vlv_wm_state vlv;
1378 struct g4x_wm_state g4x;
1384 struct delayed_work work;
1385 enum drrs_refresh_rate refresh_rate;
1386 unsigned int frontbuffer_bits;
1387 unsigned int busy_frontbuffer_bits;
1388 enum transcoder cpu_transcoder;
1389 struct intel_link_m_n m_n, m2_n2;
1392 int scanline_offset;
1395 unsigned start_vbl_count;
1396 ktime_t start_vbl_time;
1397 int min_vbl, max_vbl;
1399 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1405 unsigned int times[17]; /* [1us, 16ms] */
1410 /* scalers available on this crtc */
1413 /* for loading single buffered registers during vblank */
1414 struct pm_qos_request vblank_pm_qos;
1416 #ifdef CONFIG_DEBUG_FS
1417 struct intel_pipe_crc pipe_crc;
1421 struct intel_plane {
1422 struct drm_plane base;
1423 enum i9xx_plane_id i9xx_plane;
1426 bool need_async_flip_disable_wa;
1427 u32 frontbuffer_bit;
1430 u32 base, cntl, size;
1433 struct intel_fbc *fbc;
1436 * NOTE: Do not place new plane state fields here (e.g., when adding
1437 * new plane properties). New runtime state should now be placed in
1438 * the intel_plane_state structure and accessed via plane_state.
1441 int (*min_width)(const struct drm_framebuffer *fb,
1443 unsigned int rotation);
1444 int (*max_width)(const struct drm_framebuffer *fb,
1446 unsigned int rotation);
1447 int (*max_height)(const struct drm_framebuffer *fb,
1449 unsigned int rotation);
1450 unsigned int (*max_stride)(struct intel_plane *plane,
1451 u32 pixel_format, u64 modifier,
1452 unsigned int rotation);
1453 /* Write all non-self arming plane registers */
1454 void (*update_noarm)(struct intel_plane *plane,
1455 const struct intel_crtc_state *crtc_state,
1456 const struct intel_plane_state *plane_state);
1457 /* Write all self-arming plane registers */
1458 void (*update_arm)(struct intel_plane *plane,
1459 const struct intel_crtc_state *crtc_state,
1460 const struct intel_plane_state *plane_state);
1461 /* Disable the plane, must arm */
1462 void (*disable_arm)(struct intel_plane *plane,
1463 const struct intel_crtc_state *crtc_state);
1464 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1465 int (*check_plane)(struct intel_crtc_state *crtc_state,
1466 struct intel_plane_state *plane_state);
1467 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1468 const struct intel_plane_state *plane_state);
1469 void (*async_flip)(struct intel_plane *plane,
1470 const struct intel_crtc_state *crtc_state,
1471 const struct intel_plane_state *plane_state,
1473 void (*enable_flip_done)(struct intel_plane *plane);
1474 void (*disable_flip_done)(struct intel_plane *plane);
1477 struct intel_watermark_params {
1485 struct cxsr_latency {
1486 bool is_desktop : 1;
1491 u16 display_hpll_disable;
1493 u16 cursor_hpll_disable;
1496 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1497 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1498 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1499 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1500 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1501 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1502 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1503 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1504 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1507 i915_reg_t hdmi_reg;
1510 enum drm_dp_dual_mode_type type;
1515 struct intel_connector *attached_connector;
1516 struct cec_notifier *cec_notifier;
1519 struct intel_dp_mst_encoder;
1521 struct intel_dp_compliance_data {
1524 u16 hdisplay, vdisplay;
1526 struct drm_dp_phy_test_params phytest;
1529 struct intel_dp_compliance {
1530 unsigned long test_type;
1531 struct intel_dp_compliance_data test_data;
1537 struct intel_dp_pcon_frl {
1539 int trained_rate_gbps;
1543 int panel_power_up_delay;
1544 int panel_power_down_delay;
1545 int panel_power_cycle_delay;
1546 int backlight_on_delay;
1547 int backlight_off_delay;
1548 struct delayed_work panel_vdd_work;
1549 bool want_panel_vdd;
1551 unsigned long last_power_on;
1552 unsigned long last_backlight_off;
1553 ktime_t panel_power_off_time;
1554 intel_wakeref_t vdd_wakeref;
1557 * Pipe whose power sequencer is currently locked into
1558 * this port. Only relevant on VLV/CHV.
1562 * Pipe currently driving the port. Used for preventing
1563 * the use of the PPS for any pipe currentrly driving
1564 * external DP as that will mess things up on VLV.
1566 enum pipe active_pipe;
1568 * Set if the sequencer may be reset due to a power transition,
1569 * requiring a reinitialization. Only relevant on BXT.
1572 struct edp_power_seq pps_delays;
1573 struct edp_power_seq bios_pps_delays;
1577 /* Mutex for PSR state of the transcoder */
1580 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1581 #define I915_PSR_DEBUG_DEFAULT 0x00
1582 #define I915_PSR_DEBUG_DISABLE 0x01
1583 #define I915_PSR_DEBUG_ENABLE 0x02
1584 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1585 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1586 #define I915_PSR_DEBUG_IRQ 0x10
1590 bool source_support;
1594 enum transcoder transcoder;
1596 struct work_struct work;
1597 unsigned int busy_frontbuffer_bits;
1598 bool sink_psr2_support;
1600 bool colorimetry_support;
1602 bool psr2_sel_fetch_enabled;
1603 bool psr2_sel_fetch_cff_enabled;
1604 bool req_psr2_sdp_prior_scanline;
1605 u8 sink_sync_latency;
1606 ktime_t last_entry_attempt;
1608 bool sink_not_reliable;
1610 u16 su_w_granularity;
1611 u16 su_y_granularity;
1613 u32 dc3co_exit_delay;
1614 struct delayed_work dc3co_work;
1618 i915_reg_t output_reg;
1626 bool reset_link_params;
1627 bool use_max_params;
1628 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1629 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1630 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1631 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1632 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1633 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1634 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1636 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1638 int num_source_rates;
1639 const int *source_rates;
1640 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1642 int sink_rates[DP_MAX_SUPPORTED_RATES];
1643 bool use_rate_select;
1644 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1645 int max_sink_lane_count;
1646 /* intersection of source and sink rates */
1647 int num_common_rates;
1648 int common_rates[DP_MAX_SUPPORTED_RATES];
1649 /* Max lane count for the current link */
1650 int max_link_lane_count;
1651 /* Max rate for the current link */
1654 int mso_pixel_overlap;
1655 /* sink or branch descriptor */
1656 struct drm_dp_desc desc;
1657 struct drm_dp_aux aux;
1658 u32 aux_busy_last_status;
1661 struct intel_pps pps;
1664 int active_mst_links;
1666 /* connector directly attached - won't be use for modeset in mst world */
1667 struct intel_connector *attached_connector;
1669 /* mst connector list */
1670 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1671 struct drm_dp_mst_topology_mgr mst_mgr;
1673 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1675 * This function returns the value we have to program the AUX_CTL
1676 * register with to kick off an AUX transaction.
1678 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1679 u32 aux_clock_divider);
1681 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1682 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1684 /* This is called before a link training is starterd */
1685 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1686 const struct intel_crtc_state *crtc_state);
1687 void (*set_link_train)(struct intel_dp *intel_dp,
1688 const struct intel_crtc_state *crtc_state,
1690 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1691 const struct intel_crtc_state *crtc_state);
1693 u8 (*preemph_max)(struct intel_dp *intel_dp);
1694 u8 (*voltage_max)(struct intel_dp *intel_dp,
1695 const struct intel_crtc_state *crtc_state);
1697 /* Displayport compliance testing */
1698 struct intel_dp_compliance compliance;
1700 /* Downstream facing port caps */
1702 int min_tmds_clock, max_tmds_clock;
1704 int pcon_max_frl_bw;
1706 bool ycbcr_444_to_420;
1710 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1711 struct pm_qos_request pm_qos;
1713 /* Display stream compression testing */
1720 struct intel_dp_pcon_frl frl;
1722 struct intel_psr psr;
1724 /* When we last wrote the OUI for eDP */
1725 unsigned long last_oui_write;
1728 enum lspcon_vendor {
1730 LSPCON_VENDOR_PARADE
1733 struct intel_lspcon {
1736 enum drm_lspcon_mode mode;
1737 enum lspcon_vendor vendor;
1740 struct intel_digital_port {
1741 struct intel_encoder base;
1742 u32 saved_port_bits;
1744 struct intel_hdmi hdmi;
1745 struct intel_lspcon lspcon;
1746 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1747 bool release_cl2_override;
1749 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1751 enum intel_display_power_domain ddi_io_power_domain;
1752 intel_wakeref_t ddi_io_wakeref;
1753 intel_wakeref_t aux_wakeref;
1755 struct mutex tc_lock; /* protects the TypeC port mode */
1756 intel_wakeref_t tc_lock_wakeref;
1757 enum intel_display_power_domain tc_lock_power_domain;
1758 struct delayed_work tc_disconnect_phy_work;
1759 int tc_link_refcount;
1760 bool tc_legacy_port:1;
1761 char tc_port_name[8];
1762 enum tc_port_mode tc_mode;
1763 enum phy_fia tc_phy_fia;
1766 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1767 struct mutex hdcp_mutex;
1768 /* the number of pipes using HDCP signalling out of this port */
1769 unsigned int num_hdcp_streams;
1770 /* port HDCP auth status */
1771 bool hdcp_auth_status;
1772 /* HDCP port data need to pass to security f/w */
1773 struct hdcp_port_data hdcp_port_data;
1774 /* Whether the MST topology supports HDCP Type 1 Content */
1775 bool hdcp_mst_type1_capable;
1777 void (*write_infoframe)(struct intel_encoder *encoder,
1778 const struct intel_crtc_state *crtc_state,
1780 const void *frame, ssize_t len);
1781 void (*read_infoframe)(struct intel_encoder *encoder,
1782 const struct intel_crtc_state *crtc_state,
1784 void *frame, ssize_t len);
1785 void (*set_infoframes)(struct intel_encoder *encoder,
1787 const struct intel_crtc_state *crtc_state,
1788 const struct drm_connector_state *conn_state);
1789 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1790 const struct intel_crtc_state *pipe_config);
1791 bool (*connected)(struct intel_encoder *encoder);
1794 struct intel_dp_mst_encoder {
1795 struct intel_encoder base;
1797 struct intel_digital_port *primary;
1798 struct intel_connector *connector;
1801 static inline enum dpio_channel
1802 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1804 switch (dig_port->base.port) {
1806 MISSING_CASE(dig_port->base.port);
1816 static inline enum dpio_phy
1817 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1819 switch (dig_port->base.port) {
1821 MISSING_CASE(dig_port->base.port);
1831 static inline enum dpio_channel
1832 vlv_pipe_to_channel(enum pipe pipe)
1846 struct intel_load_detect_pipe {
1847 struct drm_atomic_state *restore_state;
1850 static inline struct intel_encoder *
1851 intel_attached_encoder(struct intel_connector *connector)
1853 return connector->encoder;
1856 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1858 switch (encoder->type) {
1859 case INTEL_OUTPUT_DDI:
1860 case INTEL_OUTPUT_DP:
1861 case INTEL_OUTPUT_EDP:
1862 case INTEL_OUTPUT_HDMI:
1869 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1871 return encoder->type == INTEL_OUTPUT_DP_MST;
1874 static inline struct intel_dp_mst_encoder *
1875 enc_to_mst(struct intel_encoder *encoder)
1877 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1881 static inline struct intel_digital_port *
1882 enc_to_dig_port(struct intel_encoder *encoder)
1884 struct intel_encoder *intel_encoder = encoder;
1886 if (intel_encoder_is_dig_port(intel_encoder))
1887 return container_of(&encoder->base, struct intel_digital_port,
1889 else if (intel_encoder_is_mst(intel_encoder))
1890 return enc_to_mst(encoder)->primary;
1895 static inline struct intel_digital_port *
1896 intel_attached_dig_port(struct intel_connector *connector)
1898 return enc_to_dig_port(intel_attached_encoder(connector));
1901 static inline struct intel_hdmi *
1902 enc_to_intel_hdmi(struct intel_encoder *encoder)
1904 return &enc_to_dig_port(encoder)->hdmi;
1907 static inline struct intel_hdmi *
1908 intel_attached_hdmi(struct intel_connector *connector)
1910 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1913 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1915 return &enc_to_dig_port(encoder)->dp;
1918 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1920 return enc_to_intel_dp(intel_attached_encoder(connector));
1923 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1925 switch (encoder->type) {
1926 case INTEL_OUTPUT_DP:
1927 case INTEL_OUTPUT_EDP:
1929 case INTEL_OUTPUT_DDI:
1930 /* Skip pure HDMI/DVI DDI encoders */
1931 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1937 static inline struct intel_lspcon *
1938 enc_to_intel_lspcon(struct intel_encoder *encoder)
1940 return &enc_to_dig_port(encoder)->lspcon;
1943 static inline struct intel_digital_port *
1944 dp_to_dig_port(struct intel_dp *intel_dp)
1946 return container_of(intel_dp, struct intel_digital_port, dp);
1949 static inline struct intel_lspcon *
1950 dp_to_lspcon(struct intel_dp *intel_dp)
1952 return &dp_to_dig_port(intel_dp)->lspcon;
1955 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
1957 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1958 (intel_dp)->psr.source_support)
1960 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
1962 if (!intel_encoder_is_dp(encoder))
1965 return CAN_PSR(enc_to_intel_dp(encoder));
1968 static inline struct intel_digital_port *
1969 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1971 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1974 static inline struct intel_plane_state *
1975 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1976 struct intel_plane *plane)
1978 struct drm_plane_state *ret =
1979 drm_atomic_get_plane_state(&state->base, &plane->base);
1982 return ERR_CAST(ret);
1984 return to_intel_plane_state(ret);
1987 static inline struct intel_plane_state *
1988 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1989 struct intel_plane *plane)
1991 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1995 static inline struct intel_plane_state *
1996 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1997 struct intel_plane *plane)
1999 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2003 static inline struct intel_crtc_state *
2004 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2005 struct intel_crtc *crtc)
2007 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2011 static inline struct intel_crtc_state *
2012 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2013 struct intel_crtc *crtc)
2015 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2019 static inline struct intel_digital_connector_state *
2020 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2021 struct intel_connector *connector)
2023 return to_intel_digital_connector_state(
2024 drm_atomic_get_new_connector_state(&state->base,
2028 static inline struct intel_digital_connector_state *
2029 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2030 struct intel_connector *connector)
2032 return to_intel_digital_connector_state(
2033 drm_atomic_get_old_connector_state(&state->base,
2037 /* intel_display.c */
2039 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2040 enum intel_output_type type)
2042 return crtc_state->output_types & (1 << type);
2045 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2047 return crtc_state->output_types &
2048 ((1 << INTEL_OUTPUT_DP) |
2049 (1 << INTEL_OUTPUT_DP_MST) |
2050 (1 << INTEL_OUTPUT_EDP));
2054 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2056 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2059 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2061 return i915_ggtt_offset(plane_state->ggtt_vma);
2064 static inline struct intel_frontbuffer *
2065 to_intel_frontbuffer(struct drm_framebuffer *fb)
2067 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2070 #endif /* __INTEL_DISPLAY_TYPES_H__ */