drivers/gpu/drm/i2c/tda998x_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Texas Instruments
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6
   7 #include <linux/component.h>
   8 #include <linux/gpio/consumer.h>
   9 #include <linux/hdmi.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_data/tda9950.h>
  12 #include <linux/irq.h>
  13 #include <sound/asoundef.h>
  14 #include <sound/hdmi-codec.h>
  15
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_bridge.h>
  18 #include <drm/drm_edid.h>
  19 #include <drm/drm_of.h>
  20 #include <drm/drm_print.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/i2c/tda998x.h>
  23
  24 #include <media/cec-notifier.h>
  25
  26 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  27
  28 enum {
  29         AUDIO_ROUTE_I2S,
  30         AUDIO_ROUTE_SPDIF,
  31         AUDIO_ROUTE_NUM
  32 };
  33
  34 struct tda998x_audio_route {
  35         u8 ena_aclk;
  36         u8 mux_ap;
  37         u8 aip_clksel;
  38 };
  39
  40 struct tda998x_audio_settings {
  41         const struct tda998x_audio_route *route;
  42         struct hdmi_audio_infoframe cea;
  43         unsigned int sample_rate;
  44         u8 status[5];
  45         u8 ena_ap;
  46         u8 i2s_format;
  47         u8 cts_n;
  48 };
  49
  50 struct tda998x_priv {
  51         struct i2c_client *cec;
  52         struct i2c_client *hdmi;
  53         struct mutex mutex;
  54         u16 rev;
  55         u8 cec_addr;
  56         u8 current_page;
  57         bool is_on;
  58         bool supports_infoframes;
  59         bool sink_has_audio;
  60         enum hdmi_quantization_range rgb_quant_range;
  61         u8 vip_cntrl_0;
  62         u8 vip_cntrl_1;
  63         u8 vip_cntrl_2;
  64         unsigned long tmds_clock;
  65         struct tda998x_audio_settings audio;
  66
  67         struct platform_device *audio_pdev;
  68         struct mutex audio_mutex;
  69
  70         struct mutex edid_mutex;
  71         wait_queue_head_t wq_edid;
  72         volatile int wq_edid_wait;
  73
  74         struct work_struct detect_work;
  75         struct timer_list edid_delay_timer;
  76         wait_queue_head_t edid_delay_waitq;
  77         bool edid_delay_active;
  78
  79         struct drm_encoder encoder;
  80         struct drm_bridge bridge;
  81         struct drm_connector connector;
  82
  83         u8 audio_port_enable[AUDIO_ROUTE_NUM];
  84         struct tda9950_glue cec_glue;
  85         struct gpio_desc *calib;
  86         struct cec_notifier *cec_notify;
  87 };
  88
  89 #define conn_to_tda998x_priv(x) \
  90         container_of(x, struct tda998x_priv, connector)
  91 #define enc_to_tda998x_priv(x) \
  92         container_of(x, struct tda998x_priv, encoder)
  93 #define bridge_to_tda998x_priv(x) \
  94         container_of(x, struct tda998x_priv, bridge)
  95
  96 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  97  * things we encode the page # in upper bits of the register #.  To read/
  98  * write a given register, we need to make sure CURPAGE register is set
  99  * appropriately.  Which implies reads/writes are not atomic.  Fun!
 100  */
 101
 102 #define REG(page, addr) (((page) << 8) | (addr))
 103 #define REG2ADDR(reg)   ((reg) & 0xff)
 104 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
 105
 106 #define REG_CURPAGE               0xff                /* write */
 107
 108
 109 /* Page 00h: General Control */
 110 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
 111 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
 112 # define MAIN_CNTRL0_SR           (1 << 0)
 113 # define MAIN_CNTRL0_DECS         (1 << 1)
 114 # define MAIN_CNTRL0_DEHS         (1 << 2)
 115 # define MAIN_CNTRL0_CECS         (1 << 3)
 116 # define MAIN_CNTRL0_CEHS         (1 << 4)
 117 # define MAIN_CNTRL0_SCALER       (1 << 7)
 118 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
 119 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
 120 # define SOFTRESET_AUDIO          (1 << 0)
 121 # define SOFTRESET_I2C_MASTER     (1 << 1)
 122 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
 123 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
 124 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
 125 # define I2C_MASTER_DIS_MM        (1 << 0)
 126 # define I2C_MASTER_DIS_FILT      (1 << 1)
 127 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
 128 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
 129 # define FEAT_POWERDOWN_PREFILT   BIT(0)
 130 # define FEAT_POWERDOWN_CSC       BIT(1)
 131 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
 132 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
 133 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
 134 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
 135 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
 136 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
 137 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
 138 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
 139 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 140 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 141 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 142 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 143 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 144 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 145 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 146 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 147 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 148 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 149 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 150 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 151 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 152 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 153 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 154 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 155 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 156 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 157 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 158 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 159 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 160 # define VIP_CNTRL_3_EMB          (1 << 3)
 161 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 162 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 163 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 164 # define VIP_CNTRL_3_EDGE         (1 << 7)
 165 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 166 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 167 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 168 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 169 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 170 # define VIP_CNTRL_4_TST_656      (1 << 6)
 171 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 172 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 173 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 174 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 175 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 176 # define MUX_AP_SELECT_I2S        0x64
 177 # define MUX_AP_SELECT_SPDIF      0x40
 178 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 179 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 180 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 181 # define MAT_CONTRL_MAT_BP        (1 << 2)
 182 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 183 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 184 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 185 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 186 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 187 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 188 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 189 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 190 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 191 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 192 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 193 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 194 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 195 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 196 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 197 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 198 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 199 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 200 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 201 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 202 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 203 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 204 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 205 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 206 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 207 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 208 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 209 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 210 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 211 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 212 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 213 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 214 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 215 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 216 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 217 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 218 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 219 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 220 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 221 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 222 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 223 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 224 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 225 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 226 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 227 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 228 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 229 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 230 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 231 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 232 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 233 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 234 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 235 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 236 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 237 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 238 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 239 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 240 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 241 # define HVF_CNTRL_0_SM           (1 << 7)
 242 # define HVF_CNTRL_0_RWB          (1 << 6)
 243 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 244 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 245 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 246 # define HVF_CNTRL_1_FOR          (1 << 0)
 247 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 248 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 249 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 250 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 251 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 252 # define RPT_CNTRL_REPEAT(x)      ((x) & 15)
 253 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 254 # define I2S_FORMAT_PHILIPS       (0 << 0)
 255 # define I2S_FORMAT_LEFT_J        (2 << 0)
 256 # define I2S_FORMAT_RIGHT_J       (3 << 0)
 257 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 258 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 259 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 260 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 261 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 262 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 263
 264 /* Page 02h: PLL settings */
 265 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 266 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 267 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 268 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 269 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 270 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 271 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 272 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 273 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 274 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 275 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 276 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 277 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 278 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 279 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 280 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 281 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 282 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 283 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 284 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 285 # define AUDIO_DIV_SERCLK_1       0
 286 # define AUDIO_DIV_SERCLK_2       1
 287 # define AUDIO_DIV_SERCLK_4       2
 288 # define AUDIO_DIV_SERCLK_8       3
 289 # define AUDIO_DIV_SERCLK_16      4
 290 # define AUDIO_DIV_SERCLK_32      5
 291 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 292 # define SEL_CLK_SEL_CLK1         (1 << 0)
 293 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 294 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 295 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 296
 297
 298 /* Page 09h: EDID Control */
 299 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 300 /* next 127 successive registers are the EDID block */
 301 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 302 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 303 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 304 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 305 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 306
 307
 308 /* Page 10h: information frames and packets */
 309 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 310 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 311 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 312 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 313 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 314
 315
 316 /* Page 11h: audio settings and content info packets */
 317 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 318 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 319 # define AIP_CNTRL_0_SWAP         (1 << 1)
 320 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 321 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 322 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 323 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 324 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 325 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 326 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 327 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 328 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 329 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 330 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 331 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 332 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 333 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 334 # define CTS_N_K(x)               (((x) & 7) << 0)
 335 # define CTS_N_M(x)               (((x) & 3) << 4)
 336 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 337 # define ENC_CNTRL_RST_ENC        (1 << 0)
 338 # define ENC_CNTRL_RST_SEL        (1 << 1)
 339 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 340 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 341 # define DIP_FLAGS_ACR            (1 << 0)
 342 # define DIP_FLAGS_GC             (1 << 1)
 343 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 344 # define DIP_IF_FLAGS_IF1         (1 << 1)
 345 # define DIP_IF_FLAGS_IF2         (1 << 2)
 346 # define DIP_IF_FLAGS_IF3         (1 << 3)
 347 # define DIP_IF_FLAGS_IF4         (1 << 4)
 348 # define DIP_IF_FLAGS_IF5         (1 << 5)
 349 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 350
 351
 352 /* Page 12h: HDCP and OTP */
 353 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 354 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 355 # define TX4_PD_RAM               (1 << 1)
 356 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 357 # define TX33_HDMI                (1 << 1)
 358
 359
 360 /* Page 13h: Gamut related metadata packets */
 361
 362
 363
 364 /* CEC registers: (not paged)
 365  */
 366 #define REG_CEC_INTSTATUS         0xee                /* read */
 367 # define CEC_INTSTATUS_CEC        (1 << 0)
 368 # define CEC_INTSTATUS_HDMI       (1 << 1)
 369 #define REG_CEC_CAL_XOSC_CTRL1    0xf2
 370 # define CEC_CAL_XOSC_CTRL1_ENA_CAL     BIT(0)
 371 #define REG_CEC_DES_FREQ2         0xf5
 372 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
 373 #define REG_CEC_CLK               0xf6
 374 # define CEC_CLK_FRO              0x11
 375 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 376 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 377 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 378 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 379 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 380 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 381 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 382 # define CEC_RXSHPDINT_RXSENS     BIT(0)
 383 # define CEC_RXSHPDINT_HPD        BIT(1)
 384 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 385 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 386 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 387
 388 #define REG_CEC_ENAMODS           0xff                /* read/write */
 389 # define CEC_ENAMODS_EN_CEC_CLK   (1 << 7)
 390 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 391 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 392 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 393 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 394 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 395
 396
 397 /* Device versions: */
 398 #define TDA9989N2                 0x0101
 399 #define TDA19989                  0x0201
 400 #define TDA19989N2                0x0202
 401 #define TDA19988                  0x0301
 402
 403 static void
 404 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 405 {
 406         u8 buf[] = {addr, val};
 407         struct i2c_msg msg = {
 408                 .addr = priv->cec_addr,
 409                 .len = 2,
 410                 .buf = buf,
 411         };
 412         int ret;
 413
 414         ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
 415         if (ret < 0)
 416                 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
 417                         ret, addr);
 418 }
 419
 420 static u8
 421 cec_read(struct tda998x_priv *priv, u8 addr)
 422 {
 423         u8 val;
 424         struct i2c_msg msg[2] = {
 425                 {
 426                         .addr = priv->cec_addr,
 427                         .len = 1,
 428                         .buf = &addr,
 429                 }, {
 430                         .addr = priv->cec_addr,
 431                         .flags = I2C_M_RD,
 432                         .len = 1,
 433                         .buf = &val,
 434                 },
 435         };
 436         int ret;
 437
 438         ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
 439         if (ret < 0) {
 440                 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
 441                         ret, addr);
 442                 val = 0;
 443         }
 444
 445         return val;
 446 }
 447
 448 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
 449 {
 450         int val = cec_read(priv, REG_CEC_ENAMODS);
 451
 452         if (val < 0)
 453                 return;
 454
 455         if (enable)
 456                 val |= mods;
 457         else
 458                 val &= ~mods;
 459
 460         cec_write(priv, REG_CEC_ENAMODS, val);
 461 }
 462
 463 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
 464 {
 465         if (enable) {
 466                 u8 val;
 467
 468                 cec_write(priv, 0xf3, 0xc0);
 469                 cec_write(priv, 0xf4, 0xd4);
 470
 471                 /* Enable automatic calibration mode */
 472                 val = cec_read(priv, REG_CEC_DES_FREQ2);
 473                 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
 474                 cec_write(priv, REG_CEC_DES_FREQ2, val);
 475
 476                 /* Enable free running oscillator */
 477                 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
 478                 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
 479
 480                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
 481                           CEC_CAL_XOSC_CTRL1_ENA_CAL);
 482         } else {
 483                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
 484         }
 485 }
 486
 487 /*
 488  * Calibration for the internal oscillator: we need to set calibration mode,
 489  * and then pulse the IRQ line low for a 10ms ± 1% period.
 490  */
 491 static void tda998x_cec_calibration(struct tda998x_priv *priv)
 492 {
 493         struct gpio_desc *calib = priv->calib;
 494
 495         mutex_lock(&priv->edid_mutex);
 496         if (priv->hdmi->irq > 0)
 497                 disable_irq(priv->hdmi->irq);
 498         gpiod_direction_output(calib, 1);
 499         tda998x_cec_set_calibration(priv, true);
 500
 501         local_irq_disable();
 502         gpiod_set_value(calib, 0);
 503         mdelay(10);
 504         gpiod_set_value(calib, 1);
 505         local_irq_enable();
 506
 507         tda998x_cec_set_calibration(priv, false);
 508         gpiod_direction_input(calib);
 509         if (priv->hdmi->irq > 0)
 510                 enable_irq(priv->hdmi->irq);
 511         mutex_unlock(&priv->edid_mutex);
 512 }
 513
 514 static int tda998x_cec_hook_init(void *data)
 515 {
 516         struct tda998x_priv *priv = data;
 517         struct gpio_desc *calib;
 518
 519         calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
 520         if (IS_ERR(calib)) {
 521                 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
 522                          PTR_ERR(calib));
 523                 return PTR_ERR(calib);
 524         }
 525
 526         priv->calib = calib;
 527
 528         return 0;
 529 }
 530
 531 static void tda998x_cec_hook_exit(void *data)
 532 {
 533         struct tda998x_priv *priv = data;
 534
 535         gpiod_put(priv->calib);
 536         priv->calib = NULL;
 537 }
 538
 539 static int tda998x_cec_hook_open(void *data)
 540 {
 541         struct tda998x_priv *priv = data;
 542
 543         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
 544         tda998x_cec_calibration(priv);
 545
 546         return 0;
 547 }
 548
 549 static void tda998x_cec_hook_release(void *data)
 550 {
 551         struct tda998x_priv *priv = data;
 552
 553         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
 554 }
 555
 556 static int
 557 set_page(struct tda998x_priv *priv, u16 reg)
 558 {
 559         if (REG2PAGE(reg) != priv->current_page) {
 560                 struct i2c_client *client = priv->hdmi;
 561                 u8 buf[] = {
 562                                 REG_CURPAGE, REG2PAGE(reg)
 563                 };
 564                 int ret = i2c_master_send(client, buf, sizeof(buf));
 565                 if (ret < 0) {
 566                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 567                                         reg, ret);
 568                         return ret;
 569                 }
 570
 571                 priv->current_page = REG2PAGE(reg);
 572         }
 573         return 0;
 574 }
 575
 576 static int
 577 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 578 {
 579         struct i2c_client *client = priv->hdmi;
 580         u8 addr = REG2ADDR(reg);
 581         int ret;
 582
 583         mutex_lock(&priv->mutex);
 584         ret = set_page(priv, reg);
 585         if (ret < 0)
 586                 goto out;
 587
 588         ret = i2c_master_send(client, &addr, sizeof(addr));
 589         if (ret < 0)
 590                 goto fail;
 591
 592         ret = i2c_master_recv(client, buf, cnt);
 593         if (ret < 0)
 594                 goto fail;
 595
 596         goto out;
 597
 598 fail:
 599         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 600 out:
 601         mutex_unlock(&priv->mutex);
 602         return ret;
 603 }
 604
 605 #define MAX_WRITE_RANGE_BUF 32
 606
 607 static void
 608 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 609 {
 610         struct i2c_client *client = priv->hdmi;
 611         /* This is the maximum size of the buffer passed in */
 612         u8 buf[MAX_WRITE_RANGE_BUF + 1];
 613         int ret;
 614
 615         if (cnt > MAX_WRITE_RANGE_BUF) {
 616                 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
 617                                 MAX_WRITE_RANGE_BUF);
 618                 return;
 619         }
 620
 621         buf[0] = REG2ADDR(reg);
 622         memcpy(&buf[1], p, cnt);
 623
 624         mutex_lock(&priv->mutex);
 625         ret = set_page(priv, reg);
 626         if (ret < 0)
 627                 goto out;
 628
 629         ret = i2c_master_send(client, buf, cnt + 1);
 630         if (ret < 0)
 631                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 632 out:
 633         mutex_unlock(&priv->mutex);
 634 }
 635
 636 static int
 637 reg_read(struct tda998x_priv *priv, u16 reg)
 638 {
 639         u8 val = 0;
 640         int ret;
 641
 642         ret = reg_read_range(priv, reg, &val, sizeof(val));
 643         if (ret < 0)
 644                 return ret;
 645         return val;
 646 }
 647
 648 static void
 649 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 650 {
 651         struct i2c_client *client = priv->hdmi;
 652         u8 buf[] = {REG2ADDR(reg), val};
 653         int ret;
 654
 655         mutex_lock(&priv->mutex);
 656         ret = set_page(priv, reg);
 657         if (ret < 0)
 658                 goto out;
 659
 660         ret = i2c_master_send(client, buf, sizeof(buf));
 661         if (ret < 0)
 662                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 663 out:
 664         mutex_unlock(&priv->mutex);
 665 }
 666
 667 static void
 668 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 669 {
 670         struct i2c_client *client = priv->hdmi;
 671         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 672         int ret;
 673
 674         mutex_lock(&priv->mutex);
 675         ret = set_page(priv, reg);
 676         if (ret < 0)
 677                 goto out;
 678
 679         ret = i2c_master_send(client, buf, sizeof(buf));
 680         if (ret < 0)
 681                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 682 out:
 683         mutex_unlock(&priv->mutex);
 684 }
 685
 686 static void
 687 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 688 {
 689         int old_val;
 690
 691         old_val = reg_read(priv, reg);
 692         if (old_val >= 0)
 693                 reg_write(priv, reg, old_val | val);
 694 }
 695
 696 static void
 697 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 698 {
 699         int old_val;
 700
 701         old_val = reg_read(priv, reg);
 702         if (old_val >= 0)
 703                 reg_write(priv, reg, old_val & ~val);
 704 }
 705
 706 static void
 707 tda998x_reset(struct tda998x_priv *priv)
 708 {
 709         /* reset audio and i2c master: */
 710         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 711         msleep(50);
 712         reg_write(priv, REG_SOFTRESET, 0);
 713         msleep(50);
 714
 715         /* reset transmitter: */
 716         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 717         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 718
 719         /* PLL registers common configuration */
 720         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 721         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 722         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 723         reg_write(priv, REG_SERIALIZER,   0x00);
 724         reg_write(priv, REG_BUFFER_OUT,   0x00);
 725         reg_write(priv, REG_PLL_SCG1,     0x00);
 726         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 727         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 728         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 729         reg_write(priv, REG_PLL_SCGN2,    0x00);
 730         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 731         reg_write(priv, REG_PLL_SCGR2,    0x00);
 732         reg_write(priv, REG_PLL_SCG2,     0x10);
 733
 734         /* Write the default value MUX register */
 735         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 736 }
 737
 738 /*
 739  * The TDA998x has a problem when trying to read the EDID close to a
 740  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 741  * trying to read EDID data.
 742  *
 743  * However, tda998x_connector_get_modes() may be called at any moment
 744  * after tda998x_connector_detect() indicates that we are connected, so
 745  * we need to delay probing modes in tda998x_connector_get_modes() after
 746  * we have seen a HPD inactive->active transition.  This code implements
 747  * that delay.
 748  */
 749 static void tda998x_edid_delay_done(struct timer_list *t)
 750 {
 751         struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
 752
 753         priv->edid_delay_active = false;
 754         wake_up(&priv->edid_delay_waitq);
 755         schedule_work(&priv->detect_work);
 756 }
 757
 758 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 759 {
 760         priv->edid_delay_active = true;
 761         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 762 }
 763
 764 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 765 {
 766         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 767 }
 768
 769 /*
 770  * We need to run the KMS hotplug event helper outside of our threaded
 771  * interrupt routine as this can call back into our get_modes method,
 772  * which will want to make use of interrupts.
 773  */
 774 static void tda998x_detect_work(struct work_struct *work)
 775 {
 776         struct tda998x_priv *priv =
 777                 container_of(work, struct tda998x_priv, detect_work);
 778         struct drm_device *dev = priv->connector.dev;
 779
 780         if (dev)
 781                 drm_kms_helper_hotplug_event(dev);
 782 }
 783
 784 /*
 785  * only 2 interrupts may occur: screen plug/unplug and EDID read
 786  */
 787 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 788 {
 789         struct tda998x_priv *priv = data;
 790         u8 sta, cec, lvl, flag0, flag1, flag2;
 791         bool handled = false;
 792
 793         sta = cec_read(priv, REG_CEC_INTSTATUS);
 794         if (sta & CEC_INTSTATUS_HDMI) {
 795                 cec = cec_read(priv, REG_CEC_RXSHPDINT);
 796                 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 797                 flag0 = reg_read(priv, REG_INT_FLAGS_0);
 798                 flag1 = reg_read(priv, REG_INT_FLAGS_1);
 799                 flag2 = reg_read(priv, REG_INT_FLAGS_2);
 800                 DRM_DEBUG_DRIVER(
 801                         "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 802                         sta, cec, lvl, flag0, flag1, flag2);
 803
 804                 if (cec & CEC_RXSHPDINT_HPD) {
 805                         if (lvl & CEC_RXSHPDLEV_HPD) {
 806                                 tda998x_edid_delay_start(priv);
 807                         } else {
 808                                 schedule_work(&priv->detect_work);
 809                                 cec_notifier_set_phys_addr(priv->cec_notify,
 810                                                    CEC_PHYS_ADDR_INVALID);
 811                         }
 812
 813                         handled = true;
 814                 }
 815
 816                 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 817                         priv->wq_edid_wait = 0;
 818                         wake_up(&priv->wq_edid);
 819                         handled = true;
 820                 }
 821         }
 822
 823         return IRQ_RETVAL(handled);
 824 }
 825
 826 static void
 827 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 828                  union hdmi_infoframe *frame)
 829 {
 830         u8 buf[MAX_WRITE_RANGE_BUF];
 831         ssize_t len;
 832
 833         len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 834         if (len < 0) {
 835                 dev_err(&priv->hdmi->dev,
 836                         "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 837                         frame->any.type, len);
 838                 return;
 839         }
 840
 841         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 842         reg_write_range(priv, addr, buf, len);
 843         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 844 }
 845
 846 static void tda998x_write_aif(struct tda998x_priv *priv,
 847                               const struct hdmi_audio_infoframe *cea)
 848 {
 849         union hdmi_infoframe frame;
 850
 851         frame.audio = *cea;
 852
 853         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 854 }
 855
 856 static void
 857 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
 858 {
 859         union hdmi_infoframe frame;
 860
 861         drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 862                                                  &priv->connector, mode);
 863         frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 864         drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode,
 865                                            priv->rgb_quant_range);
 866
 867         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 868 }
 869
 870 static void tda998x_write_vsi(struct tda998x_priv *priv,
 871                               const struct drm_display_mode *mode)
 872 {
 873         union hdmi_infoframe frame;
 874
 875         if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 876                                                         &priv->connector,
 877                                                         mode))
 878                 reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1);
 879         else
 880                 tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame);
 881 }
 882
 883 /* Audio support */
 884
 885 static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = {
 886         [AUDIO_ROUTE_I2S] = {
 887                 .ena_aclk = 1,
 888                 .mux_ap = MUX_AP_SELECT_I2S,
 889                 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK,
 890         },
 891         [AUDIO_ROUTE_SPDIF] = {
 892                 .ena_aclk = 0,
 893                 .mux_ap = MUX_AP_SELECT_SPDIF,
 894                 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF,
 895         },
 896 };
 897
 898 /* Configure the TDA998x audio data and clock routing. */
 899 static int tda998x_derive_routing(struct tda998x_priv *priv,
 900                                   struct tda998x_audio_settings *s,
 901                                   unsigned int route)
 902 {
 903         s->route = &tda998x_audio_route[route];
 904         s->ena_ap = priv->audio_port_enable[route];
 905         if (s->ena_ap == 0) {
 906                 dev_err(&priv->hdmi->dev, "no audio configuration found\n");
 907                 return -EINVAL;
 908         }
 909
 910         return 0;
 911 }
 912
 913 /*
 914  * The audio clock divisor register controls a divider producing Audio_Clk_Out
 915  * from SERclk by dividing it by 2^n where 0 <= n <= 5.  We don't know what
 916  * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock.
 917  *
 918  * It seems that Audio_Clk_Out must be the smallest value that is greater
 919  * than 128*fs, otherwise audio does not function. There is some suggestion
 920  * that 126*fs is a better value.
 921  */
 922 static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs)
 923 {
 924         unsigned long min_audio_clk = fs * 128;
 925         unsigned long ser_clk = priv->tmds_clock * 1000;
 926         u8 adiv;
 927
 928         for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--)
 929                 if (ser_clk > min_audio_clk << adiv)
 930                         break;
 931
 932         dev_dbg(&priv->hdmi->dev,
 933                 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n",
 934                 ser_clk, fs, min_audio_clk, adiv);
 935
 936         return adiv;
 937 }
 938
 939 /*
 940  * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
 941  * generate the CTS value.  It appears that the "measured time stamp" is
 942  * the number of TDMS clock cycles within a number of audio input clock
 943  * cycles defined by the k and N parameters defined below, in a similar
 944  * way to that which is set out in the CTS generation in the HDMI spec.
 945  *
 946  *  tmdsclk ----> mts -> /m ---> CTS
 947  *                 ^
 948  *  sclk -> /k -> /N
 949  *
 950  * CTS = mts / m, where m is 2^M.
 951  * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
 952  * /N is a divider based on the HDMI specified N value.
 953  *
 954  * This produces the following equation:
 955  *  CTS = tmds_clock * k * N / (sclk * m)
 956  *
 957  * When combined with the sink-side equation, and realising that sclk is
 958  * bclk_ratio * fs, we end up with:
 959  *  k = m * bclk_ratio / 128.
 960  *
 961  * Note: S/PDIF always uses a bclk_ratio of 64.
 962  */
 963 static int tda998x_derive_cts_n(struct tda998x_priv *priv,
 964                                 struct tda998x_audio_settings *settings,
 965                                 unsigned int ratio)
 966 {
 967         switch (ratio) {
 968         case 16:
 969                 settings->cts_n = CTS_N_M(3) | CTS_N_K(0);
 970                 break;
 971         case 32:
 972                 settings->cts_n = CTS_N_M(3) | CTS_N_K(1);
 973                 break;
 974         case 48:
 975                 settings->cts_n = CTS_N_M(3) | CTS_N_K(2);
 976                 break;
 977         case 64:
 978                 settings->cts_n = CTS_N_M(3) | CTS_N_K(3);
 979                 break;
 980         case 128:
 981                 settings->cts_n = CTS_N_M(0) | CTS_N_K(0);
 982                 break;
 983         default:
 984                 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n",
 985                         ratio);
 986                 return -EINVAL;
 987         }
 988         return 0;
 989 }
 990
 991 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 992 {
 993         if (on) {
 994                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 995                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 996                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 997         } else {
 998                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 999         }
1000 }
1001
1002 static void tda998x_configure_audio(struct tda998x_priv *priv)
1003 {
1004         const struct tda998x_audio_settings *settings = &priv->audio;
1005         u8 buf[6], adiv;
1006         u32 n;
1007
1008         /* If audio is not configured, there is nothing to do. */
1009         if (settings->ena_ap == 0)
1010                 return;
1011
1012         adiv = tda998x_get_adiv(priv, settings->sample_rate);
1013
1014         /* Enable audio ports */
1015         reg_write(priv, REG_ENA_AP, settings->ena_ap);
1016         reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1017         reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1018         reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1019         reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1020         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
1021                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
1022         reg_write(priv, REG_CTS_N, settings->cts_n);
1023         reg_write(priv, REG_AUDIO_DIV, adiv);
1024
1025         /*
1026          * This is the approximate value of N, which happens to be
1027          * the recommended values for non-coherent clocks.
1028          */
1029         n = 128 * settings->sample_rate / 1000;
1030
1031         /* Write the CTS and N values */
1032         buf[0] = 0x44;
1033         buf[1] = 0x42;
1034         buf[2] = 0x01;
1035         buf[3] = n;
1036         buf[4] = n >> 8;
1037         buf[5] = n >> 16;
1038         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
1039
1040         /* Reset CTS generator */
1041         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1042         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1043
1044         /* Write the channel status
1045          * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
1046          * there is a separate register for each I2S wire.
1047          */
1048         buf[0] = settings->status[0];
1049         buf[1] = settings->status[1];
1050         buf[2] = settings->status[3];
1051         buf[3] = settings->status[4];
1052         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
1053
1054         tda998x_audio_mute(priv, true);
1055         msleep(20);
1056         tda998x_audio_mute(priv, false);
1057
1058         tda998x_write_aif(priv, &settings->cea);
1059 }
1060
1061 static int tda998x_audio_hw_params(struct device *dev, void *data,
1062                                    struct hdmi_codec_daifmt *daifmt,
1063                                    struct hdmi_codec_params *params)
1064 {
1065         struct tda998x_priv *priv = dev_get_drvdata(dev);
1066         unsigned int bclk_ratio;
1067         bool spdif = daifmt->fmt == HDMI_SPDIF;
1068         int ret;
1069         struct tda998x_audio_settings audio = {
1070                 .sample_rate = params->sample_rate,
1071                 .cea = params->cea,
1072         };
1073
1074         memcpy(audio.status, params->iec.status,
1075                min(sizeof(audio.status), sizeof(params->iec.status)));
1076
1077         switch (daifmt->fmt) {
1078         case HDMI_I2S:
1079                 audio.i2s_format = I2S_FORMAT_PHILIPS;
1080                 break;
1081         case HDMI_LEFT_J:
1082                 audio.i2s_format = I2S_FORMAT_LEFT_J;
1083                 break;
1084         case HDMI_RIGHT_J:
1085                 audio.i2s_format = I2S_FORMAT_RIGHT_J;
1086                 break;
1087         case HDMI_SPDIF:
1088                 audio.i2s_format = 0;
1089                 break;
1090         default:
1091                 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1092                 return -EINVAL;
1093         }
1094
1095         if (!spdif &&
1096             (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1097              daifmt->bit_clk_master || daifmt->frame_clk_master)) {
1098                 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1099                         daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1100                         daifmt->bit_clk_master,
1101                         daifmt->frame_clk_master);
1102                 return -EINVAL;
1103         }
1104
1105         ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif);
1106         if (ret < 0)
1107                 return ret;
1108
1109         bclk_ratio = spdif ? 64 : params->sample_width * 2;
1110         ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio);
1111         if (ret < 0)
1112                 return ret;
1113
1114         mutex_lock(&priv->audio_mutex);
1115         priv->audio = audio;
1116         if (priv->supports_infoframes && priv->sink_has_audio)
1117                 tda998x_configure_audio(priv);
1118         mutex_unlock(&priv->audio_mutex);
1119
1120         return 0;
1121 }
1122
1123 static void tda998x_audio_shutdown(struct device *dev, void *data)
1124 {
1125         struct tda998x_priv *priv = dev_get_drvdata(dev);
1126
1127         mutex_lock(&priv->audio_mutex);
1128
1129         reg_write(priv, REG_ENA_AP, 0);
1130         priv->audio.ena_ap = 0;
1131
1132         mutex_unlock(&priv->audio_mutex);
1133 }
1134
1135 int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
1136 {
1137         struct tda998x_priv *priv = dev_get_drvdata(dev);
1138
1139         mutex_lock(&priv->audio_mutex);
1140
1141         tda998x_audio_mute(priv, enable);
1142
1143         mutex_unlock(&priv->audio_mutex);
1144         return 0;
1145 }
1146
1147 static int tda998x_audio_get_eld(struct device *dev, void *data,
1148                                  uint8_t *buf, size_t len)
1149 {
1150         struct tda998x_priv *priv = dev_get_drvdata(dev);
1151
1152         mutex_lock(&priv->audio_mutex);
1153         memcpy(buf, priv->connector.eld,
1154                min(sizeof(priv->connector.eld), len));
1155         mutex_unlock(&priv->audio_mutex);
1156
1157         return 0;
1158 }
1159
1160 static const struct hdmi_codec_ops audio_codec_ops = {
1161         .hw_params = tda998x_audio_hw_params,
1162         .audio_shutdown = tda998x_audio_shutdown,
1163         .digital_mute = tda998x_audio_digital_mute,
1164         .get_eld = tda998x_audio_get_eld,
1165 };
1166
1167 static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1168                                     struct device *dev)
1169 {
1170         struct hdmi_codec_pdata codec_data = {
1171                 .ops = &audio_codec_ops,
1172                 .max_i2s_channels = 2,
1173         };
1174
1175         if (priv->audio_port_enable[AUDIO_ROUTE_I2S])
1176                 codec_data.i2s = 1;
1177         if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1178                 codec_data.spdif = 1;
1179
1180         priv->audio_pdev = platform_device_register_data(
1181                 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1182                 &codec_data, sizeof(codec_data));
1183
1184         return PTR_ERR_OR_ZERO(priv->audio_pdev);
1185 }
1186
1187 /* DRM connector functions */
1188
1189 static enum drm_connector_status
1190 tda998x_connector_detect(struct drm_connector *connector, bool force)
1191 {
1192         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1193         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1194
1195         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1196                         connector_status_disconnected;
1197 }
1198
1199 static void tda998x_connector_destroy(struct drm_connector *connector)
1200 {
1201         drm_connector_cleanup(connector);
1202 }
1203
1204 static const struct drm_connector_funcs tda998x_connector_funcs = {
1205         .reset = drm_atomic_helper_connector_reset,
1206         .fill_modes = drm_helper_probe_single_connector_modes,
1207         .detect = tda998x_connector_detect,
1208         .destroy = tda998x_connector_destroy,
1209         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1210         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1211 };
1212
1213 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1214 {
1215         struct tda998x_priv *priv = data;
1216         u8 offset, segptr;
1217         int ret, i;
1218
1219         offset = (blk & 1) ? 128 : 0;
1220         segptr = blk / 2;
1221
1222         mutex_lock(&priv->edid_mutex);
1223
1224         reg_write(priv, REG_DDC_ADDR, 0xa0);
1225         reg_write(priv, REG_DDC_OFFS, offset);
1226         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1227         reg_write(priv, REG_DDC_SEGM, segptr);
1228
1229         /* enable reading EDID: */
1230         priv->wq_edid_wait = 1;
1231         reg_write(priv, REG_EDID_CTRL, 0x1);
1232
1233         /* flag must be cleared by sw: */
1234         reg_write(priv, REG_EDID_CTRL, 0x0);
1235
1236         /* wait for block read to complete: */
1237         if (priv->hdmi->irq) {
1238                 i = wait_event_timeout(priv->wq_edid,
1239                                         !priv->wq_edid_wait,
1240                                         msecs_to_jiffies(100));
1241                 if (i < 0) {
1242                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1243                         ret = i;
1244                         goto failed;
1245                 }
1246         } else {
1247                 for (i = 100; i > 0; i--) {
1248                         msleep(1);
1249                         ret = reg_read(priv, REG_INT_FLAGS_2);
1250                         if (ret < 0)
1251                                 goto failed;
1252                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1253                                 break;
1254                 }
1255         }
1256
1257         if (i == 0) {
1258                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1259                 ret = -ETIMEDOUT;
1260                 goto failed;
1261         }
1262
1263         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1264         if (ret != length) {
1265                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1266                         blk, ret);
1267                 goto failed;
1268         }
1269
1270         ret = 0;
1271
1272  failed:
1273         mutex_unlock(&priv->edid_mutex);
1274         return ret;
1275 }
1276
1277 static int tda998x_connector_get_modes(struct drm_connector *connector)
1278 {
1279         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1280         struct edid *edid;
1281         int n;
1282
1283         /*
1284          * If we get killed while waiting for the HPD timeout, return
1285          * no modes found: we are not in a restartable path, so we
1286          * can't handle signals gracefully.
1287          */
1288         if (tda998x_edid_delay_wait(priv))
1289                 return 0;
1290
1291         if (priv->rev == TDA19988)
1292                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1293
1294         edid = drm_do_get_edid(connector, read_edid_block, priv);
1295
1296         if (priv->rev == TDA19988)
1297                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1298
1299         if (!edid) {
1300                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1301                 return 0;
1302         }
1303
1304         drm_connector_update_edid_property(connector, edid);
1305         cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1306
1307         mutex_lock(&priv->audio_mutex);
1308         n = drm_add_edid_modes(connector, edid);
1309         priv->sink_has_audio = drm_detect_monitor_audio(edid);
1310         mutex_unlock(&priv->audio_mutex);
1311
1312         kfree(edid);
1313
1314         return n;
1315 }
1316
1317 static struct drm_encoder *
1318 tda998x_connector_best_encoder(struct drm_connector *connector)
1319 {
1320         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1321
1322         return priv->bridge.encoder;
1323 }
1324
1325 static
1326 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1327         .get_modes = tda998x_connector_get_modes,
1328         .best_encoder = tda998x_connector_best_encoder,
1329 };
1330
1331 static int tda998x_connector_init(struct tda998x_priv *priv,
1332                                   struct drm_device *drm)
1333 {
1334         struct drm_connector *connector = &priv->connector;
1335         int ret;
1336
1337         connector->interlace_allowed = 1;
1338
1339         if (priv->hdmi->irq)
1340                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1341         else
1342                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1343                         DRM_CONNECTOR_POLL_DISCONNECT;
1344
1345         drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1346         ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1347                                  DRM_MODE_CONNECTOR_HDMIA);
1348         if (ret)
1349                 return ret;
1350
1351         drm_connector_attach_encoder(&priv->connector,
1352                                      priv->bridge.encoder);
1353
1354         return 0;
1355 }
1356
1357 /* DRM bridge functions */
1358
1359 static int tda998x_bridge_attach(struct drm_bridge *bridge)
1360 {
1361         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1362
1363         return tda998x_connector_init(priv, bridge->dev);
1364 }
1365
1366 static void tda998x_bridge_detach(struct drm_bridge *bridge)
1367 {
1368         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1369
1370         drm_connector_cleanup(&priv->connector);
1371 }
1372
1373 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1374                                      const struct drm_display_mode *mode)
1375 {
1376         /* TDA19988 dotclock can go up to 165MHz */
1377         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1378
1379         if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1380                 return MODE_CLOCK_HIGH;
1381         if (mode->htotal >= BIT(13))
1382                 return MODE_BAD_HVALUE;
1383         if (mode->vtotal >= BIT(11))
1384                 return MODE_BAD_VVALUE;
1385         return MODE_OK;
1386 }
1387
1388 static void tda998x_bridge_enable(struct drm_bridge *bridge)
1389 {
1390         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1391
1392         if (!priv->is_on) {
1393                 /* enable video ports, audio will be enabled later */
1394                 reg_write(priv, REG_ENA_VP_0, 0xff);
1395                 reg_write(priv, REG_ENA_VP_1, 0xff);
1396                 reg_write(priv, REG_ENA_VP_2, 0xff);
1397                 /* set muxing after enabling ports: */
1398                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1399                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1400                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1401
1402                 priv->is_on = true;
1403         }
1404 }
1405
1406 static void tda998x_bridge_disable(struct drm_bridge *bridge)
1407 {
1408         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1409
1410         if (priv->is_on) {
1411                 /* disable video ports */
1412                 reg_write(priv, REG_ENA_VP_0, 0x00);
1413                 reg_write(priv, REG_ENA_VP_1, 0x00);
1414                 reg_write(priv, REG_ENA_VP_2, 0x00);
1415
1416                 priv->is_on = false;
1417         }
1418 }
1419
1420 static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1421                                     const struct drm_display_mode *mode,
1422                                     const struct drm_display_mode *adjusted_mode)
1423 {
1424         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1425         unsigned long tmds_clock;
1426         u16 ref_pix, ref_line, n_pix, n_line;
1427         u16 hs_pix_s, hs_pix_e;
1428         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1429         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1430         u16 vwin1_line_s, vwin1_line_e;
1431         u16 vwin2_line_s, vwin2_line_e;
1432         u16 de_pix_s, de_pix_e;
1433         u8 reg, div, rep, sel_clk;
1434
1435         /*
1436          * Since we are "computer" like, our source invariably produces
1437          * full-range RGB.  If the monitor supports full-range, then use
1438          * it, otherwise reduce to limited-range.
1439          */
1440         priv->rgb_quant_range =
1441                 priv->connector.display_info.rgb_quant_range_selectable ?
1442                 HDMI_QUANTIZATION_RANGE_FULL :
1443                 drm_default_rgb_quant_range(adjusted_mode);
1444
1445         /*
1446          * Internally TDA998x is using ITU-R BT.656 style sync but
1447          * we get VESA style sync. TDA998x is using a reference pixel
1448          * relative to ITU to sync to the input frame and for output
1449          * sync generation. Currently, we are using reference detection
1450          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1451          * which is position of rising VS with coincident rising HS.
1452          *
1453          * Now there is some issues to take care of:
1454          * - HDMI data islands require sync-before-active
1455          * - TDA998x register values must be > 0 to be enabled
1456          * - REFLINE needs an additional offset of +1
1457          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1458          *
1459          * So we add +1 to all horizontal and vertical register values,
1460          * plus an additional +3 for REFPIX as we are using RGB input only.
1461          */
1462         n_pix        = mode->htotal;
1463         n_line       = mode->vtotal;
1464
1465         hs_pix_e     = mode->hsync_end - mode->hdisplay;
1466         hs_pix_s     = mode->hsync_start - mode->hdisplay;
1467         de_pix_e     = mode->htotal;
1468         de_pix_s     = mode->htotal - mode->hdisplay;
1469         ref_pix      = 3 + hs_pix_s;
1470
1471         /*
1472          * Attached LCD controllers may generate broken sync. Allow
1473          * those to adjust the position of the rising VS edge by adding
1474          * HSKEW to ref_pix.
1475          */
1476         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1477                 ref_pix += adjusted_mode->hskew;
1478
1479         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1480                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
1481                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1482                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1483                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1484                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
1485                 vs1_line_e   = vs1_line_s +
1486                                mode->vsync_end - mode->vsync_start;
1487                 vwin2_line_s = vwin2_line_e = 0;
1488                 vs2_pix_s    = vs2_pix_e  = 0;
1489                 vs2_line_s   = vs2_line_e = 0;
1490         } else {
1491                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
1492                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1493                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1494                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1495                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
1496                 vs1_line_e   = vs1_line_s +
1497                                (mode->vsync_end - mode->vsync_start)/2;
1498                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1499                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1500                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
1501                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
1502                 vs2_line_e   = vs2_line_s +
1503                                (mode->vsync_end - mode->vsync_start)/2;
1504         }
1505
1506         /*
1507          * Select pixel repeat depending on the double-clock flag
1508          * (which means we have to repeat each pixel once.)
1509          */
1510         rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0;
1511         sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 |
1512                   SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0);
1513
1514         /* the TMDS clock is scaled up by the pixel repeat */
1515         tmds_clock = mode->clock * (1 + rep);
1516
1517         /*
1518          * The divisor is power-of-2. The TDA9983B datasheet gives
1519          * this as ranges of Msample/s, which is 10x the TMDS clock:
1520          *   0 - 800 to 1500 Msample/s
1521          *   1 - 400 to 800 Msample/s
1522          *   2 - 200 to 400 Msample/s
1523          *   3 - as 2 above
1524          */
1525         for (div = 0; div < 3; div++)
1526                 if (80000 >> div <= tmds_clock)
1527                         break;
1528
1529         mutex_lock(&priv->audio_mutex);
1530
1531         priv->tmds_clock = tmds_clock;
1532
1533         /* mute the audio FIFO: */
1534         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1535
1536         /* set HDMI HDCP mode off: */
1537         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1538         reg_clear(priv, REG_TX33, TX33_HDMI);
1539         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1540
1541         /* no pre-filter or interpolator: */
1542         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1543                         HVF_CNTRL_0_INTPOL(0));
1544         reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1545         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1546         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1547                         VIP_CNTRL_4_BLC(0));
1548
1549         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1550         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1551                                           PLL_SERIAL_3_SRL_DE);
1552         reg_write(priv, REG_SERIALIZER, 0);
1553         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1554
1555         reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));
1556         reg_write(priv, REG_SEL_CLK, sel_clk);
1557         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1558                         PLL_SERIAL_2_SRL_PR(rep));
1559
1560         /* set color matrix according to output rgb quant range */
1561         if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
1562                 static u8 tda998x_full_to_limited_range[] = {
1563                         MAT_CONTRL_MAT_SC(2),
1564                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1565                         0x03, 0x6f, 0x00, 0x00, 0x00, 0x00,
1566                         0x00, 0x00, 0x03, 0x6f, 0x00, 0x00,
1567                         0x00, 0x00, 0x00, 0x00, 0x03, 0x6f,
1568                         0x00, 0x40, 0x00, 0x40, 0x00, 0x40
1569                 };
1570                 reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1571                 reg_write_range(priv, REG_MAT_CONTRL,
1572                                 tda998x_full_to_limited_range,
1573                                 sizeof(tda998x_full_to_limited_range));
1574         } else {
1575                 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1576                                         MAT_CONTRL_MAT_SC(1));
1577                 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1578         }
1579
1580         /* set BIAS tmds value: */
1581         reg_write(priv, REG_ANA_GENERAL, 0x09);
1582
1583         /*
1584          * Sync on rising HSYNC/VSYNC
1585          */
1586         reg = VIP_CNTRL_3_SYNC_HS;
1587
1588         /*
1589          * TDA19988 requires high-active sync at input stage,
1590          * so invert low-active sync provided by master encoder here
1591          */
1592         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1593                 reg |= VIP_CNTRL_3_H_TGL;
1594         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1595                 reg |= VIP_CNTRL_3_V_TGL;
1596         reg_write(priv, REG_VIP_CNTRL_3, reg);
1597
1598         reg_write(priv, REG_VIDFORMAT, 0x00);
1599         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1600         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1601         reg_write16(priv, REG_NPIX_MSB, n_pix);
1602         reg_write16(priv, REG_NLINE_MSB, n_line);
1603         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1604         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1605         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1606         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1607         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1608         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1609         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1610         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1611         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1612         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1613         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1614         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1615         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1616         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1617         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1618         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1619
1620         if (priv->rev == TDA19988) {
1621                 /* let incoming pixels fill the active space (if any) */
1622                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1623         }
1624
1625         /*
1626          * Always generate sync polarity relative to input sync and
1627          * revert input stage toggled sync at output stage
1628          */
1629         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1630         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1631                 reg |= TBG_CNTRL_1_H_TGL;
1632         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1633                 reg |= TBG_CNTRL_1_V_TGL;
1634         reg_write(priv, REG_TBG_CNTRL_1, reg);
1635
1636         /* must be last register set: */
1637         reg_write(priv, REG_TBG_CNTRL_0, 0);
1638
1639         /* CEA-861B section 6 says that:
1640          * CEA version 1 (CEA-861) has no support for infoframes.
1641          * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1642          * and optional basic audio.
1643          * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1644          * and optional digital audio, with audio infoframes.
1645          *
1646          * Since we only support generation of version 2 AVI infoframes,
1647          * ignore CEA version 2 and below (iow, behave as if we're a
1648          * CEA-861 source.)
1649          */
1650         priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1651
1652         if (priv->supports_infoframes) {
1653                 /* We need to turn HDMI HDCP stuff on to get audio through */
1654                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1655                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1656                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1657                 reg_set(priv, REG_TX33, TX33_HDMI);
1658
1659                 tda998x_write_avi(priv, adjusted_mode);
1660                 tda998x_write_vsi(priv, adjusted_mode);
1661
1662                 if (priv->sink_has_audio)
1663                         tda998x_configure_audio(priv);
1664         }
1665
1666         mutex_unlock(&priv->audio_mutex);
1667 }
1668
1669 static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1670         .attach = tda998x_bridge_attach,
1671         .detach = tda998x_bridge_detach,
1672         .mode_valid = tda998x_bridge_mode_valid,
1673         .disable = tda998x_bridge_disable,
1674         .mode_set = tda998x_bridge_mode_set,
1675         .enable = tda998x_bridge_enable,
1676 };
1677
1678 /* I2C driver functions */
1679
1680 static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1681                                    struct device_node *np)
1682 {
1683         const u32 *port_data;
1684         u32 size;
1685         int i;
1686
1687         port_data = of_get_property(np, "audio-ports", &size);
1688         if (!port_data)
1689                 return 0;
1690
1691         size /= sizeof(u32);
1692         if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) {
1693                 dev_err(&priv->hdmi->dev,
1694                         "Bad number of elements in audio-ports dt-property\n");
1695                 return -EINVAL;
1696         }
1697
1698         size /= 2;
1699
1700         for (i = 0; i < size; i++) {
1701                 unsigned int route;
1702                 u8 afmt = be32_to_cpup(&port_data[2*i]);
1703                 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1704
1705                 switch (afmt) {
1706                 case AFMT_I2S:
1707                         route = AUDIO_ROUTE_I2S;
1708                         break;
1709                 case AFMT_SPDIF:
1710                         route = AUDIO_ROUTE_SPDIF;
1711                         break;
1712                 default:
1713                         dev_err(&priv->hdmi->dev,
1714                                 "Bad audio format %u\n", afmt);
1715                         return -EINVAL;
1716                 }
1717
1718                 if (!ena_ap) {
1719                         dev_err(&priv->hdmi->dev, "invalid zero port config\n");
1720                         continue;
1721                 }
1722
1723                 if (priv->audio_port_enable[route]) {
1724                         dev_err(&priv->hdmi->dev,
1725                                 "%s format already configured\n",
1726                                 route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S");
1727                         return -EINVAL;
1728                 }
1729
1730                 priv->audio_port_enable[route] = ena_ap;
1731         }
1732         return 0;
1733 }
1734
1735 static int tda998x_set_config(struct tda998x_priv *priv,
1736                               const struct tda998x_encoder_params *p)
1737 {
1738         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1739                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1740                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
1741                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1742         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1743                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1744                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
1745                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1746         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1747                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1748                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
1749                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1750
1751         if (p->audio_params.format != AFMT_UNUSED) {
1752                 unsigned int ratio, route;
1753                 bool spdif = p->audio_params.format == AFMT_SPDIF;
1754
1755                 route = AUDIO_ROUTE_I2S + spdif;
1756
1757                 priv->audio.route = &tda998x_audio_route[route];
1758                 priv->audio.cea = p->audio_params.cea;
1759                 priv->audio.sample_rate = p->audio_params.sample_rate;
1760                 memcpy(priv->audio.status, p->audio_params.status,
1761                        min(sizeof(priv->audio.status),
1762                            sizeof(p->audio_params.status)));
1763                 priv->audio.ena_ap = p->audio_params.config;
1764                 priv->audio.i2s_format = I2S_FORMAT_PHILIPS;
1765
1766                 ratio = spdif ? 64 : p->audio_params.sample_width * 2;
1767                 return tda998x_derive_cts_n(priv, &priv->audio, ratio);
1768         }
1769
1770         return 0;
1771 }
1772
1773 static void tda998x_destroy(struct device *dev)
1774 {
1775         struct tda998x_priv *priv = dev_get_drvdata(dev);
1776
1777         drm_bridge_remove(&priv->bridge);
1778
1779         /* disable all IRQs and free the IRQ handler */
1780         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1781         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1782
1783         if (priv->audio_pdev)
1784                 platform_device_unregister(priv->audio_pdev);
1785
1786         if (priv->hdmi->irq)
1787                 free_irq(priv->hdmi->irq, priv);
1788
1789         del_timer_sync(&priv->edid_delay_timer);
1790         cancel_work_sync(&priv->detect_work);
1791
1792         i2c_unregister_device(priv->cec);
1793
1794         if (priv->cec_notify)
1795                 cec_notifier_put(priv->cec_notify);
1796 }
1797
1798 static int tda998x_create(struct device *dev)
1799 {
1800         struct i2c_client *client = to_i2c_client(dev);
1801         struct device_node *np = client->dev.of_node;
1802         struct i2c_board_info cec_info;
1803         struct tda998x_priv *priv;
1804         u32 video;
1805         int rev_lo, rev_hi, ret;
1806
1807         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1808         if (!priv)
1809                 return -ENOMEM;
1810
1811         dev_set_drvdata(dev, priv);
1812
1813         mutex_init(&priv->mutex);       /* protect the page access */
1814         mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1815         mutex_init(&priv->edid_mutex);
1816         INIT_LIST_HEAD(&priv->bridge.list);
1817         init_waitqueue_head(&priv->edid_delay_waitq);
1818         timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1819         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1820
1821         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1822         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1823         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1824
1825         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1826         priv->cec_addr = 0x34 + (client->addr & 0x03);
1827         priv->current_page = 0xff;
1828         priv->hdmi = client;
1829
1830         /* wake up the device: */
1831         cec_write(priv, REG_CEC_ENAMODS,
1832                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1833
1834         tda998x_reset(priv);
1835
1836         /* read version: */
1837         rev_lo = reg_read(priv, REG_VERSION_LSB);
1838         if (rev_lo < 0) {
1839                 dev_err(dev, "failed to read version: %d\n", rev_lo);
1840                 return rev_lo;
1841         }
1842
1843         rev_hi = reg_read(priv, REG_VERSION_MSB);
1844         if (rev_hi < 0) {
1845                 dev_err(dev, "failed to read version: %d\n", rev_hi);
1846                 return rev_hi;
1847         }
1848
1849         priv->rev = rev_lo | rev_hi << 8;
1850
1851         /* mask off feature bits: */
1852         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1853
1854         switch (priv->rev) {
1855         case TDA9989N2:
1856                 dev_info(dev, "found TDA9989 n2");
1857                 break;
1858         case TDA19989:
1859                 dev_info(dev, "found TDA19989");
1860                 break;
1861         case TDA19989N2:
1862                 dev_info(dev, "found TDA19989 n2");
1863                 break;
1864         case TDA19988:
1865                 dev_info(dev, "found TDA19988");
1866                 break;
1867         default:
1868                 dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1869                 return -ENXIO;
1870         }
1871
1872         /* after reset, enable DDC: */
1873         reg_write(priv, REG_DDC_DISABLE, 0x00);
1874
1875         /* set clock on DDC channel: */
1876         reg_write(priv, REG_TX3, 39);
1877
1878         /* if necessary, disable multi-master: */
1879         if (priv->rev == TDA19989)
1880                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1881
1882         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1883                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1884
1885         /* ensure interrupts are disabled */
1886         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1887
1888         /* clear pending interrupts */
1889         cec_read(priv, REG_CEC_RXSHPDINT);
1890         reg_read(priv, REG_INT_FLAGS_0);
1891         reg_read(priv, REG_INT_FLAGS_1);
1892         reg_read(priv, REG_INT_FLAGS_2);
1893
1894         /* initialize the optional IRQ */
1895         if (client->irq) {
1896                 unsigned long irq_flags;
1897
1898                 /* init read EDID waitqueue and HDP work */
1899                 init_waitqueue_head(&priv->wq_edid);
1900
1901                 irq_flags =
1902                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1903
1904                 priv->cec_glue.irq_flags = irq_flags;
1905
1906                 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1907                 ret = request_threaded_irq(client->irq, NULL,
1908                                            tda998x_irq_thread, irq_flags,
1909                                            "tda998x", priv);
1910                 if (ret) {
1911                         dev_err(dev, "failed to request IRQ#%u: %d\n",
1912                                 client->irq, ret);
1913                         goto err_irq;
1914                 }
1915
1916                 /* enable HPD irq */
1917                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1918         }
1919
1920         priv->cec_notify = cec_notifier_get(dev);
1921         if (!priv->cec_notify) {
1922                 ret = -ENOMEM;
1923                 goto fail;
1924         }
1925
1926         priv->cec_glue.parent = dev;
1927         priv->cec_glue.data = priv;
1928         priv->cec_glue.init = tda998x_cec_hook_init;
1929         priv->cec_glue.exit = tda998x_cec_hook_exit;
1930         priv->cec_glue.open = tda998x_cec_hook_open;
1931         priv->cec_glue.release = tda998x_cec_hook_release;
1932
1933         /*
1934          * Some TDA998x are actually two I2C devices merged onto one piece
1935          * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1936          * with a slightly modified TDA9950 CEC device.  The CEC device
1937          * is at the TDA9950 address, with the address pins strapped across
1938          * to the TDA998x address pins.  Hence, it always has the same
1939          * offset.
1940          */
1941         memset(&cec_info, 0, sizeof(cec_info));
1942         strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1943         cec_info.addr = priv->cec_addr;
1944         cec_info.platform_data = &priv->cec_glue;
1945         cec_info.irq = client->irq;
1946
1947         priv->cec = i2c_new_device(client->adapter, &cec_info);
1948         if (!priv->cec) {
1949                 ret = -ENODEV;
1950                 goto fail;
1951         }
1952
1953         /* enable EDID read irq: */
1954         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1955
1956         if (np) {
1957                 /* get the device tree parameters */
1958                 ret = of_property_read_u32(np, "video-ports", &video);
1959                 if (ret == 0) {
1960                         priv->vip_cntrl_0 = video >> 16;
1961                         priv->vip_cntrl_1 = video >> 8;
1962                         priv->vip_cntrl_2 = video;
1963                 }
1964
1965                 ret = tda998x_get_audio_ports(priv, np);
1966                 if (ret)
1967                         goto fail;
1968
1969                 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] ||
1970                     priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1971                         tda998x_audio_codec_init(priv, &client->dev);
1972         } else if (dev->platform_data) {
1973                 ret = tda998x_set_config(priv, dev->platform_data);
1974                 if (ret)
1975                         goto fail;
1976         }
1977
1978         priv->bridge.funcs = &tda998x_bridge_funcs;
1979 #ifdef CONFIG_OF
1980         priv->bridge.of_node = dev->of_node;
1981 #endif
1982
1983         drm_bridge_add(&priv->bridge);
1984
1985         return 0;
1986
1987 fail:
1988         tda998x_destroy(dev);
1989 err_irq:
1990         return ret;
1991 }
1992
1993 /* DRM encoder functions */
1994
1995 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1996 {
1997         drm_encoder_cleanup(encoder);
1998 }
1999
2000 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
2001         .destroy = tda998x_encoder_destroy,
2002 };
2003
2004 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
2005 {
2006         struct tda998x_priv *priv = dev_get_drvdata(dev);
2007         u32 crtcs = 0;
2008         int ret;
2009
2010         if (dev->of_node)
2011                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
2012
2013         /* If no CRTCs were found, fall back to our old behaviour */
2014         if (crtcs == 0) {
2015                 dev_warn(dev, "Falling back to first CRTC\n");
2016                 crtcs = 1 << 0;
2017         }
2018
2019         priv->encoder.possible_crtcs = crtcs;
2020
2021         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
2022                                DRM_MODE_ENCODER_TMDS, NULL);
2023         if (ret)
2024                 goto err_encoder;
2025
2026         ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL);
2027         if (ret)
2028                 goto err_bridge;
2029
2030         return 0;
2031
2032 err_bridge:
2033         drm_encoder_cleanup(&priv->encoder);
2034 err_encoder:
2035         return ret;
2036 }
2037
2038 static int tda998x_bind(struct device *dev, struct device *master, void *data)
2039 {
2040         struct drm_device *drm = data;
2041
2042         return tda998x_encoder_init(dev, drm);
2043 }
2044
2045 static void tda998x_unbind(struct device *dev, struct device *master,
2046                            void *data)
2047 {
2048         struct tda998x_priv *priv = dev_get_drvdata(dev);
2049
2050         drm_encoder_cleanup(&priv->encoder);
2051 }
2052
2053 static const struct component_ops tda998x_ops = {
2054         .bind = tda998x_bind,
2055         .unbind = tda998x_unbind,
2056 };
2057
2058 static int
2059 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
2060 {
2061         int ret;
2062
2063         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2064                 dev_warn(&client->dev, "adapter does not support I2C\n");
2065                 return -EIO;
2066         }
2067
2068         ret = tda998x_create(&client->dev);
2069         if (ret)
2070                 return ret;
2071
2072         ret = component_add(&client->dev, &tda998x_ops);
2073         if (ret)
2074                 tda998x_destroy(&client->dev);
2075         return ret;
2076 }
2077
2078 static int tda998x_remove(struct i2c_client *client)
2079 {
2080         component_del(&client->dev, &tda998x_ops);
2081         tda998x_destroy(&client->dev);
2082         return 0;
2083 }
2084
2085 #ifdef CONFIG_OF
2086 static const struct of_device_id tda998x_dt_ids[] = {
2087         { .compatible = "nxp,tda998x", },
2088         { }
2089 };
2090 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
2091 #endif
2092
2093 static const struct i2c_device_id tda998x_ids[] = {
2094         { "tda998x", 0 },
2095         { }
2096 };
2097 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
2098
2099 static struct i2c_driver tda998x_driver = {
2100         .probe = tda998x_probe,
2101         .remove = tda998x_remove,
2102         .driver = {
2103                 .name = "tda998x",
2104                 .of_match_table = of_match_ptr(tda998x_dt_ids),
2105         },
2106         .id_table = tda998x_ids,
2107 };
2108
2109 module_i2c_driver(tda998x_driver);
2110
2111 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
2112 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
2113 MODULE_LICENSE("GPL");