drivers/gpu/drm/exynos/exynos_drm_scaler.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2017 Samsung Electronics Co.Ltd
   4  * Author:
   5  *      Andrzej Pietrasiewicz <andrzejtp2010@gmail.com>
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/err.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17
  18 #include <drm/exynos_drm.h>
  19
  20 #include "exynos_drm_drv.h"
  21 #include "exynos_drm_fb.h"
  22 #include "exynos_drm_ipp.h"
  23 #include "regs-scaler.h"
  24
  25 #define scaler_read(offset)             readl(scaler->regs + (offset))
  26 #define scaler_write(cfg, offset)       writel(cfg, scaler->regs + (offset))
  27 #define SCALER_MAX_CLK                  4
  28 #define SCALER_AUTOSUSPEND_DELAY        2000
  29 #define SCALER_RESET_WAIT_RETRIES       100
  30
  31 struct scaler_data {
  32         const char      *clk_name[SCALER_MAX_CLK];
  33         unsigned int    num_clk;
  34         const struct exynos_drm_ipp_formats *formats;
  35         unsigned int    num_formats;
  36 };
  37
  38 struct scaler_context {
  39         struct exynos_drm_ipp           ipp;
  40         struct drm_device               *drm_dev;
  41         struct device                   *dev;
  42         void __iomem                    *regs;
  43         struct clk                      *clock[SCALER_MAX_CLK];
  44         struct exynos_drm_ipp_task      *task;
  45         const struct scaler_data        *scaler_data;
  46 };
  47
  48 struct scaler_format {
  49         u32     drm_fmt;
  50         u32     internal_fmt;
  51         u32     chroma_tile_w;
  52         u32     chroma_tile_h;
  53 };
  54
  55 static const struct scaler_format scaler_formats[] = {
  56         { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
  57         { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
  58         { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
  59         { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
  60         { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
  61         { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
  62         { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
  63         { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
  64         { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
  65         { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
  66         { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
  67         { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
  68         { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
  69         { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
  70         { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
  71         { DRM_FORMAT_XRGB4444, SCALER_ARGB4444, 0, 0 },
  72         { DRM_FORMAT_ARGB4444, SCALER_ARGB4444, 0, 0 },
  73         { DRM_FORMAT_XRGB8888, SCALER_ARGB8888, 0, 0 },
  74         { DRM_FORMAT_ARGB8888, SCALER_ARGB8888, 0, 0 },
  75         { DRM_FORMAT_RGBX8888, SCALER_RGBA8888, 0, 0 },
  76         { DRM_FORMAT_RGBA8888, SCALER_RGBA8888, 0, 0 },
  77 };
  78
  79 static const struct scaler_format *scaler_get_format(u32 drm_fmt)
  80 {
  81         int i;
  82
  83         for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
  84                 if (scaler_formats[i].drm_fmt == drm_fmt)
  85                         return &scaler_formats[i];
  86
  87         return NULL;
  88 }
  89
  90 static inline int scaler_reset(struct scaler_context *scaler)
  91 {
  92         int retry = SCALER_RESET_WAIT_RETRIES;
  93
  94         scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG);
  95         do {
  96                 cpu_relax();
  97         } while (--retry > 1 &&
  98                  scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET);
  99         do {
 100                 cpu_relax();
 101                 scaler_write(1, SCALER_INT_EN);
 102         } while (--retry > 0 && scaler_read(SCALER_INT_EN) != 1);
 103
 104         return retry ? 0 : -EIO;
 105 }
 106
 107 static inline void scaler_enable_int(struct scaler_context *scaler)
 108 {
 109         u32 val;
 110
 111         val = SCALER_INT_EN_TIMEOUT |
 112                 SCALER_INT_EN_ILLEGAL_BLEND |
 113                 SCALER_INT_EN_ILLEGAL_RATIO |
 114                 SCALER_INT_EN_ILLEGAL_DST_HEIGHT |
 115                 SCALER_INT_EN_ILLEGAL_DST_WIDTH |
 116                 SCALER_INT_EN_ILLEGAL_DST_V_POS |
 117                 SCALER_INT_EN_ILLEGAL_DST_H_POS |
 118                 SCALER_INT_EN_ILLEGAL_DST_C_SPAN |
 119                 SCALER_INT_EN_ILLEGAL_DST_Y_SPAN |
 120                 SCALER_INT_EN_ILLEGAL_DST_CR_BASE |
 121                 SCALER_INT_EN_ILLEGAL_DST_CB_BASE |
 122                 SCALER_INT_EN_ILLEGAL_DST_Y_BASE |
 123                 SCALER_INT_EN_ILLEGAL_DST_COLOR |
 124                 SCALER_INT_EN_ILLEGAL_SRC_HEIGHT |
 125                 SCALER_INT_EN_ILLEGAL_SRC_WIDTH |
 126                 SCALER_INT_EN_ILLEGAL_SRC_CV_POS |
 127                 SCALER_INT_EN_ILLEGAL_SRC_CH_POS |
 128                 SCALER_INT_EN_ILLEGAL_SRC_YV_POS |
 129                 SCALER_INT_EN_ILLEGAL_SRC_YH_POS |
 130                 SCALER_INT_EN_ILLEGAL_DST_SPAN |
 131                 SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN |
 132                 SCALER_INT_EN_ILLEGAL_SRC_CR_BASE |
 133                 SCALER_INT_EN_ILLEGAL_SRC_CB_BASE |
 134                 SCALER_INT_EN_ILLEGAL_SRC_Y_BASE |
 135                 SCALER_INT_EN_ILLEGAL_SRC_COLOR |
 136                 SCALER_INT_EN_FRAME_END;
 137         scaler_write(val, SCALER_INT_EN);
 138 }
 139
 140 static inline void scaler_set_src_fmt(struct scaler_context *scaler,
 141         u32 src_fmt, u32 tile)
 142 {
 143         u32 val;
 144
 145         val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10);
 146         scaler_write(val, SCALER_SRC_CFG);
 147 }
 148
 149 static inline void scaler_set_src_base(struct scaler_context *scaler,
 150         struct exynos_drm_ipp_buffer *src_buf)
 151 {
 152         static unsigned int bases[] = {
 153                 SCALER_SRC_Y_BASE,
 154                 SCALER_SRC_CB_BASE,
 155                 SCALER_SRC_CR_BASE,
 156         };
 157         int i;
 158
 159         for (i = 0; i < src_buf->format->num_planes; ++i)
 160                 scaler_write(src_buf->dma_addr[i], bases[i]);
 161 }
 162
 163 static inline void scaler_set_src_span(struct scaler_context *scaler,
 164         struct exynos_drm_ipp_buffer *src_buf)
 165 {
 166         u32 val;
 167
 168         val = SCALER_SRC_SPAN_SET_Y_SPAN(src_buf->buf.pitch[0] /
 169                 src_buf->format->cpp[0]);
 170
 171         if (src_buf->format->num_planes > 1)
 172                 val |= SCALER_SRC_SPAN_SET_C_SPAN(src_buf->buf.pitch[1]);
 173
 174         scaler_write(val, SCALER_SRC_SPAN);
 175 }
 176
 177 static inline void scaler_set_src_luma_chroma_pos(struct scaler_context *scaler,
 178                         struct drm_exynos_ipp_task_rect *src_pos,
 179                         const struct scaler_format *fmt)
 180 {
 181         u32 val;
 182
 183         val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2);
 184         val |=  SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2);
 185         scaler_write(val, SCALER_SRC_Y_POS);
 186         val = SCALER_SRC_C_POS_SET_CH_POS(
 187                 (src_pos->x * fmt->chroma_tile_w / 16) << 2);
 188         val |=  SCALER_SRC_C_POS_SET_CV_POS(
 189                 (src_pos->y * fmt->chroma_tile_h / 16) << 2);
 190         scaler_write(val, SCALER_SRC_C_POS);
 191 }
 192
 193 static inline void scaler_set_src_wh(struct scaler_context *scaler,
 194         struct drm_exynos_ipp_task_rect *src_pos)
 195 {
 196         u32 val;
 197
 198         val = SCALER_SRC_WH_SET_WIDTH(src_pos->w);
 199         val |= SCALER_SRC_WH_SET_HEIGHT(src_pos->h);
 200         scaler_write(val, SCALER_SRC_WH);
 201 }
 202
 203 static inline void scaler_set_dst_fmt(struct scaler_context *scaler,
 204         u32 dst_fmt)
 205 {
 206         u32 val;
 207
 208         val = SCALER_DST_CFG_SET_COLOR_FORMAT(dst_fmt);
 209         scaler_write(val, SCALER_DST_CFG);
 210 }
 211
 212 static inline void scaler_set_dst_base(struct scaler_context *scaler,
 213         struct exynos_drm_ipp_buffer *dst_buf)
 214 {
 215         static unsigned int bases[] = {
 216                 SCALER_DST_Y_BASE,
 217                 SCALER_DST_CB_BASE,
 218                 SCALER_DST_CR_BASE,
 219         };
 220         int i;
 221
 222         for (i = 0; i < dst_buf->format->num_planes; ++i)
 223                 scaler_write(dst_buf->dma_addr[i], bases[i]);
 224 }
 225
 226 static inline void scaler_set_dst_span(struct scaler_context *scaler,
 227         struct exynos_drm_ipp_buffer *dst_buf)
 228 {
 229         u32 val;
 230
 231         val = SCALER_DST_SPAN_SET_Y_SPAN(dst_buf->buf.pitch[0] /
 232                 dst_buf->format->cpp[0]);
 233
 234         if (dst_buf->format->num_planes > 1)
 235                 val |= SCALER_DST_SPAN_SET_C_SPAN(dst_buf->buf.pitch[1]);
 236
 237         scaler_write(val, SCALER_DST_SPAN);
 238 }
 239
 240 static inline void scaler_set_dst_luma_pos(struct scaler_context *scaler,
 241         struct drm_exynos_ipp_task_rect *dst_pos)
 242 {
 243         u32 val;
 244
 245         val = SCALER_DST_WH_SET_WIDTH(dst_pos->w);
 246         val |= SCALER_DST_WH_SET_HEIGHT(dst_pos->h);
 247         scaler_write(val, SCALER_DST_WH);
 248 }
 249
 250 static inline void scaler_set_dst_wh(struct scaler_context *scaler,
 251         struct drm_exynos_ipp_task_rect *dst_pos)
 252 {
 253         u32 val;
 254
 255         val = SCALER_DST_POS_SET_H_POS(dst_pos->x);
 256         val |= SCALER_DST_POS_SET_V_POS(dst_pos->y);
 257         scaler_write(val, SCALER_DST_POS);
 258 }
 259
 260 static inline void scaler_set_hv_ratio(struct scaler_context *scaler,
 261         unsigned int rotation,
 262         struct drm_exynos_ipp_task_rect *src_pos,
 263         struct drm_exynos_ipp_task_rect *dst_pos)
 264 {
 265         u32 val, h_ratio, v_ratio;
 266
 267         if (drm_rotation_90_or_270(rotation)) {
 268                 h_ratio = (src_pos->h << 16) / dst_pos->w;
 269                 v_ratio = (src_pos->w << 16) / dst_pos->h;
 270         } else {
 271                 h_ratio = (src_pos->w << 16) / dst_pos->w;
 272                 v_ratio = (src_pos->h << 16) / dst_pos->h;
 273         }
 274
 275         val = SCALER_H_RATIO_SET(h_ratio);
 276         scaler_write(val, SCALER_H_RATIO);
 277
 278         val = SCALER_V_RATIO_SET(v_ratio);
 279         scaler_write(val, SCALER_V_RATIO);
 280 }
 281
 282 static inline void scaler_set_rotation(struct scaler_context *scaler,
 283         unsigned int rotation)
 284 {
 285         u32 val = 0;
 286
 287         if (rotation & DRM_MODE_ROTATE_90)
 288                 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_90);
 289         else if (rotation & DRM_MODE_ROTATE_180)
 290                 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_180);
 291         else if (rotation & DRM_MODE_ROTATE_270)
 292                 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_270);
 293         if (rotation & DRM_MODE_REFLECT_X)
 294                 val |= SCALER_ROT_CFG_FLIP_X_EN;
 295         if (rotation & DRM_MODE_REFLECT_Y)
 296                 val |= SCALER_ROT_CFG_FLIP_Y_EN;
 297         scaler_write(val, SCALER_ROT_CFG);
 298 }
 299
 300 static inline void scaler_set_csc(struct scaler_context *scaler,
 301         const struct drm_format_info *fmt)
 302 {
 303         static const u32 csc_mtx[2][3][3] = {
 304                 { /* YCbCr to RGB */
 305                         {0x254, 0x000, 0x331},
 306                         {0x254, 0xf38, 0xe60},
 307                         {0x254, 0x409, 0x000},
 308                 },
 309                 { /* RGB to YCbCr */
 310                         {0x084, 0x102, 0x032},
 311                         {0xfb4, 0xf6b, 0x0e1},
 312                         {0x0e1, 0xf44, 0xfdc},
 313                 },
 314         };
 315         int i, j, dir;
 316
 317         switch (fmt->format) {
 318         case DRM_FORMAT_RGB565:
 319         case DRM_FORMAT_XRGB1555:
 320         case DRM_FORMAT_ARGB1555:
 321         case DRM_FORMAT_XRGB4444:
 322         case DRM_FORMAT_ARGB4444:
 323         case DRM_FORMAT_XRGB8888:
 324         case DRM_FORMAT_ARGB8888:
 325         case DRM_FORMAT_RGBX8888:
 326         case DRM_FORMAT_RGBA8888:
 327                 dir = 1;
 328                 break;
 329         default:
 330                 dir = 0;
 331         }
 332
 333         for (i = 0; i < 3; i++)
 334                 for (j = 0; j < 3; j++)
 335                         scaler_write(csc_mtx[dir][i][j], SCALER_CSC_COEF(j, i));
 336 }
 337
 338 static inline void scaler_set_timer(struct scaler_context *scaler,
 339         unsigned int timer, unsigned int divider)
 340 {
 341         u32 val;
 342
 343         val = SCALER_TIMEOUT_CTRL_TIMER_ENABLE;
 344         val |= SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(timer);
 345         val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider);
 346         scaler_write(val, SCALER_TIMEOUT_CTRL);
 347 }
 348
 349 static inline void scaler_start_hw(struct scaler_context *scaler)
 350 {
 351         scaler_write(SCALER_CFG_START_CMD, SCALER_CFG);
 352 }
 353
 354 static int scaler_commit(struct exynos_drm_ipp *ipp,
 355                           struct exynos_drm_ipp_task *task)
 356 {
 357         struct scaler_context *scaler =
 358                         container_of(ipp, struct scaler_context, ipp);
 359
 360         struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect;
 361         struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect;
 362         const struct scaler_format *src_fmt, *dst_fmt;
 363
 364         src_fmt = scaler_get_format(task->src.buf.fourcc);
 365         dst_fmt = scaler_get_format(task->dst.buf.fourcc);
 366
 367         pm_runtime_get_sync(scaler->dev);
 368         if (scaler_reset(scaler)) {
 369                 pm_runtime_put(scaler->dev);
 370                 return -EIO;
 371         }
 372
 373         scaler->task = task;
 374
 375         scaler_set_src_fmt(
 376                 scaler, src_fmt->internal_fmt, task->src.buf.modifier != 0);
 377         scaler_set_src_base(scaler, &task->src);
 378         scaler_set_src_span(scaler, &task->src);
 379         scaler_set_src_luma_chroma_pos(scaler, src_pos, src_fmt);
 380         scaler_set_src_wh(scaler, src_pos);
 381
 382         scaler_set_dst_fmt(scaler, dst_fmt->internal_fmt);
 383         scaler_set_dst_base(scaler, &task->dst);
 384         scaler_set_dst_span(scaler, &task->dst);
 385         scaler_set_dst_luma_pos(scaler, dst_pos);
 386         scaler_set_dst_wh(scaler, dst_pos);
 387
 388         scaler_set_hv_ratio(scaler, task->transform.rotation, src_pos, dst_pos);
 389         scaler_set_rotation(scaler, task->transform.rotation);
 390
 391         scaler_set_csc(scaler, task->src.format);
 392
 393         scaler_set_timer(scaler, 0xffff, 0xf);
 394
 395         scaler_enable_int(scaler);
 396         scaler_start_hw(scaler);
 397
 398         return 0;
 399 }
 400
 401 static struct exynos_drm_ipp_funcs ipp_funcs = {
 402         .commit = scaler_commit,
 403 };
 404
 405 static inline void scaler_disable_int(struct scaler_context *scaler)
 406 {
 407         scaler_write(0, SCALER_INT_EN);
 408 }
 409
 410 static inline u32 scaler_get_int_status(struct scaler_context *scaler)
 411 {
 412         u32 val = scaler_read(SCALER_INT_STATUS);
 413
 414         scaler_write(val, SCALER_INT_STATUS);
 415
 416         return val;
 417 }
 418
 419 static inline int scaler_task_done(u32 val)
 420 {
 421         return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL;
 422 }
 423
 424 static irqreturn_t scaler_irq_handler(int irq, void *arg)
 425 {
 426         struct scaler_context *scaler = arg;
 427
 428         u32 val = scaler_get_int_status(scaler);
 429
 430         scaler_disable_int(scaler);
 431
 432         if (scaler->task) {
 433                 struct exynos_drm_ipp_task *task = scaler->task;
 434
 435                 scaler->task = NULL;
 436                 pm_runtime_mark_last_busy(scaler->dev);
 437                 pm_runtime_put_autosuspend(scaler->dev);
 438                 exynos_drm_ipp_task_done(task, scaler_task_done(val));
 439         }
 440
 441         return IRQ_HANDLED;
 442 }
 443
 444 static int scaler_bind(struct device *dev, struct device *master, void *data)
 445 {
 446         struct scaler_context *scaler = dev_get_drvdata(dev);
 447         struct drm_device *drm_dev = data;
 448         struct exynos_drm_ipp *ipp = &scaler->ipp;
 449
 450         scaler->drm_dev = drm_dev;
 451         ipp->drm_dev = drm_dev;
 452         exynos_drm_register_dma(drm_dev, dev);
 453
 454         exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
 455                         DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
 456                         DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
 457                         scaler->scaler_data->formats,
 458                         scaler->scaler_data->num_formats, "scaler");
 459
 460         dev_info(dev, "The exynos scaler has been probed successfully\n");
 461
 462         return 0;
 463 }
 464
 465 static void scaler_unbind(struct device *dev, struct device *master,
 466                         void *data)
 467 {
 468         struct scaler_context *scaler = dev_get_drvdata(dev);
 469         struct exynos_drm_ipp *ipp = &scaler->ipp;
 470
 471         exynos_drm_ipp_unregister(dev, ipp);
 472         exynos_drm_unregister_dma(scaler->drm_dev, scaler->dev);
 473 }
 474
 475 static const struct component_ops scaler_component_ops = {
 476         .bind   = scaler_bind,
 477         .unbind = scaler_unbind,
 478 };
 479
 480 static int scaler_probe(struct platform_device *pdev)
 481 {
 482         struct device *dev = &pdev->dev;
 483         struct resource *regs_res;
 484         struct scaler_context *scaler;
 485         int irq;
 486         int ret, i;
 487
 488         scaler = devm_kzalloc(dev, sizeof(*scaler), GFP_KERNEL);
 489         if (!scaler)
 490                 return -ENOMEM;
 491
 492         scaler->scaler_data =
 493                 (struct scaler_data *)of_device_get_match_data(dev);
 494
 495         scaler->dev = dev;
 496         regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 497         scaler->regs = devm_ioremap_resource(dev, regs_res);
 498         if (IS_ERR(scaler->regs))
 499                 return PTR_ERR(scaler->regs);
 500
 501         irq = platform_get_irq(pdev, 0);
 502         if (irq < 0) {
 503                 dev_err(dev, "failed to get irq\n");
 504                 return irq;
 505         }
 506
 507         ret = devm_request_threaded_irq(dev, irq, NULL, scaler_irq_handler,
 508                                         IRQF_ONESHOT, "drm_scaler", scaler);
 509         if (ret < 0) {
 510                 dev_err(dev, "failed to request irq\n");
 511                 return ret;
 512         }
 513
 514         for (i = 0; i < scaler->scaler_data->num_clk; ++i) {
 515                 scaler->clock[i] = devm_clk_get(dev,
 516                                               scaler->scaler_data->clk_name[i]);
 517                 if (IS_ERR(scaler->clock[i])) {
 518                         dev_err(dev, "failed to get clock\n");
 519                         return PTR_ERR(scaler->clock[i]);
 520                 }
 521         }
 522
 523         pm_runtime_use_autosuspend(dev);
 524         pm_runtime_set_autosuspend_delay(dev, SCALER_AUTOSUSPEND_DELAY);
 525         pm_runtime_enable(dev);
 526         platform_set_drvdata(pdev, scaler);
 527
 528         ret = component_add(dev, &scaler_component_ops);
 529         if (ret)
 530                 goto err_ippdrv_register;
 531
 532         return 0;
 533
 534 err_ippdrv_register:
 535         pm_runtime_dont_use_autosuspend(dev);
 536         pm_runtime_disable(dev);
 537         return ret;
 538 }
 539
 540 static int scaler_remove(struct platform_device *pdev)
 541 {
 542         struct device *dev = &pdev->dev;
 543
 544         component_del(dev, &scaler_component_ops);
 545         pm_runtime_dont_use_autosuspend(dev);
 546         pm_runtime_disable(dev);
 547
 548         return 0;
 549 }
 550
 551 #ifdef CONFIG_PM
 552
 553 static int clk_disable_unprepare_wrapper(struct clk *clk)
 554 {
 555         clk_disable_unprepare(clk);
 556
 557         return 0;
 558 }
 559
 560 static int scaler_clk_ctrl(struct scaler_context *scaler, bool enable)
 561 {
 562         int (*clk_fun)(struct clk *clk), i;
 563
 564         clk_fun = enable ? clk_prepare_enable : clk_disable_unprepare_wrapper;
 565
 566         for (i = 0; i < scaler->scaler_data->num_clk; ++i)
 567                 clk_fun(scaler->clock[i]);
 568
 569         return 0;
 570 }
 571
 572 static int scaler_runtime_suspend(struct device *dev)
 573 {
 574         struct scaler_context *scaler = dev_get_drvdata(dev);
 575
 576         return  scaler_clk_ctrl(scaler, false);
 577 }
 578
 579 static int scaler_runtime_resume(struct device *dev)
 580 {
 581         struct scaler_context *scaler = dev_get_drvdata(dev);
 582
 583         return  scaler_clk_ctrl(scaler, true);
 584 }
 585 #endif
 586
 587 static const struct dev_pm_ops scaler_pm_ops = {
 588         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 589                                 pm_runtime_force_resume)
 590         SET_RUNTIME_PM_OPS(scaler_runtime_suspend, scaler_runtime_resume, NULL)
 591 };
 592
 593 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_hv_limits[] = {
 594         { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
 595         { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
 596         { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
 597                           .v = { 65536 * 1 / 4, 65536 * 16 }) },
 598 };
 599
 600 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_h_limits[] = {
 601         { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
 602         { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) },
 603         { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
 604                           .v = { 65536 * 1 / 4, 65536 * 16 }) },
 605 };
 606
 607 static const struct drm_exynos_ipp_limit scaler_5420_one_pixel_limits[] = {
 608         { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
 609         { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
 610                           .v = { 65536 * 1 / 4, 65536 * 16 }) },
 611 };
 612
 613 static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
 614         { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
 615         { IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
 616         { IPP_SCALE_LIMIT(.h = {1, 1}, .v = {1, 1})},
 617         { }
 618 };
 619
 620 #define IPP_SRCDST_TILE_FORMAT(f, l)    \
 621         IPP_SRCDST_MFORMAT(f, DRM_FORMAT_MOD_SAMSUNG_16_16_TILE, (l))
 622
 623 static const struct exynos_drm_ipp_formats exynos5420_formats[] = {
 624         /* SCALER_YUV420_2P_UV */
 625         { IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) },
 626
 627         /* SCALER_YUV420_2P_VU */
 628         { IPP_SRCDST_FORMAT(NV12, scaler_5420_two_pixel_hv_limits) },
 629
 630         /* SCALER_YUV420_3P */
 631         { IPP_SRCDST_FORMAT(YUV420, scaler_5420_two_pixel_hv_limits) },
 632
 633         /* SCALER_YUV422_1P_YUYV */
 634         { IPP_SRCDST_FORMAT(YUYV, scaler_5420_two_pixel_h_limits) },
 635
 636         /* SCALER_YUV422_1P_UYVY */
 637         { IPP_SRCDST_FORMAT(UYVY, scaler_5420_two_pixel_h_limits) },
 638
 639         /* SCALER_YUV422_1P_YVYU */
 640         { IPP_SRCDST_FORMAT(YVYU, scaler_5420_two_pixel_h_limits) },
 641
 642         /* SCALER_YUV422_2P_UV */
 643         { IPP_SRCDST_FORMAT(NV61, scaler_5420_two_pixel_h_limits) },
 644
 645         /* SCALER_YUV422_2P_VU */
 646         { IPP_SRCDST_FORMAT(NV16, scaler_5420_two_pixel_h_limits) },
 647
 648         /* SCALER_YUV422_3P */
 649         { IPP_SRCDST_FORMAT(YUV422, scaler_5420_two_pixel_h_limits) },
 650
 651         /* SCALER_YUV444_2P_UV */
 652         { IPP_SRCDST_FORMAT(NV42, scaler_5420_one_pixel_limits) },
 653
 654         /* SCALER_YUV444_2P_VU */
 655         { IPP_SRCDST_FORMAT(NV24, scaler_5420_one_pixel_limits) },
 656
 657         /* SCALER_YUV444_3P */
 658         { IPP_SRCDST_FORMAT(YUV444, scaler_5420_one_pixel_limits) },
 659
 660         /* SCALER_RGB_565 */
 661         { IPP_SRCDST_FORMAT(RGB565, scaler_5420_one_pixel_limits) },
 662
 663         /* SCALER_ARGB1555 */
 664         { IPP_SRCDST_FORMAT(XRGB1555, scaler_5420_one_pixel_limits) },
 665
 666         /* SCALER_ARGB1555 */
 667         { IPP_SRCDST_FORMAT(ARGB1555, scaler_5420_one_pixel_limits) },
 668
 669         /* SCALER_ARGB4444 */
 670         { IPP_SRCDST_FORMAT(XRGB4444, scaler_5420_one_pixel_limits) },
 671
 672         /* SCALER_ARGB4444 */
 673         { IPP_SRCDST_FORMAT(ARGB4444, scaler_5420_one_pixel_limits) },
 674
 675         /* SCALER_ARGB8888 */
 676         { IPP_SRCDST_FORMAT(XRGB8888, scaler_5420_one_pixel_limits) },
 677
 678         /* SCALER_ARGB8888 */
 679         { IPP_SRCDST_FORMAT(ARGB8888, scaler_5420_one_pixel_limits) },
 680
 681         /* SCALER_RGBA8888 */
 682         { IPP_SRCDST_FORMAT(RGBX8888, scaler_5420_one_pixel_limits) },
 683
 684         /* SCALER_RGBA8888 */
 685         { IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) },
 686
 687         /* SCALER_YUV420_2P_UV TILE */
 688         { IPP_SRCDST_TILE_FORMAT(NV21, scaler_5420_tile_limits) },
 689
 690         /* SCALER_YUV420_2P_VU TILE */
 691         { IPP_SRCDST_TILE_FORMAT(NV12, scaler_5420_tile_limits) },
 692
 693         /* SCALER_YUV420_3P TILE */
 694         { IPP_SRCDST_TILE_FORMAT(YUV420, scaler_5420_tile_limits) },
 695
 696         /* SCALER_YUV422_1P_YUYV TILE */
 697         { IPP_SRCDST_TILE_FORMAT(YUYV, scaler_5420_tile_limits) },
 698 };
 699
 700 static const struct scaler_data exynos5420_data = {
 701         .clk_name       = {"mscl"},
 702         .num_clk        = 1,
 703         .formats        = exynos5420_formats,
 704         .num_formats    = ARRAY_SIZE(exynos5420_formats),
 705 };
 706
 707 static const struct scaler_data exynos5433_data = {
 708         .clk_name       = {"pclk", "aclk", "aclk_xiu"},
 709         .num_clk        = 3,
 710         .formats        = exynos5420_formats, /* intentional */
 711         .num_formats    = ARRAY_SIZE(exynos5420_formats),
 712 };
 713
 714 static const struct of_device_id exynos_scaler_match[] = {
 715         {
 716                 .compatible = "samsung,exynos5420-scaler",
 717                 .data = &exynos5420_data,
 718         }, {
 719                 .compatible = "samsung,exynos5433-scaler",
 720                 .data = &exynos5433_data,
 721         }, {
 722         },
 723 };
 724 MODULE_DEVICE_TABLE(of, exynos_scaler_match);
 725
 726 struct platform_driver scaler_driver = {
 727         .probe          = scaler_probe,
 728         .remove         = scaler_remove,
 729         .driver         = {
 730                 .name   = "exynos-scaler",
 731                 .owner  = THIS_MODULE,
 732                 .pm     = &scaler_pm_ops,
 733                 .of_match_table = exynos_scaler_match,
 734         },
 735 };