drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fb.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_plane.h"
  35 #include "exynos_drm_iommu.h"
  36
  37 /*
  38  * FIMD stands for Fully Interactive Mobile Display and
  39  * as a display controller, it transfers contents drawn on memory
  40  * to a LCD Panel through Display Interfaces such as RGB or
  41  * CPU Interface.
  42  */
  43
  44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  45
  46 /* position control register for hardware window 0, 2 ~ 4.*/
  47 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  48 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  49 /*
  50  * size control register for hardware windows 0 and alpha control register
  51  * for hardware windows 1 ~ 4
  52  */
  53 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  54 /* size control register for hardware windows 1 ~ 2. */
  55 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  56
  57 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  58 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  59
  60 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  61 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  62 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  63 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  64
  65 /* color key control register for hardware window 1 ~ 4. */
  66 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  67 /* color key value register for hardware window 1 ~ 4. */
  68 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  69
  70 /* I80 trigger control register */
  71 #define TRIGCON                         0x1A4
  72 #define TRGMODE_ENABLE                  (1 << 0)
  73 #define SWTRGCMD_ENABLE                 (1 << 1)
  74 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
  75 #define HWTRGEN_ENABLE                  (1 << 3)
  76 #define HWTRGMASK_ENABLE                (1 << 4)
  77 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
  78 #define HWTRIGEN_PER_ENABLE             (1 << 31)
  79
  80 /* display mode change control register except exynos4 */
  81 #define VIDOUT_CON                      0x000
  82 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  83
  84 /* I80 interface control for main LDI register */
  85 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  86 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  87 #define LCD_CS_SETUP(x)                 ((x) << 16)
  88 #define LCD_WR_SETUP(x)                 ((x) << 12)
  89 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  90 #define LCD_WR_HOLD(x)                  ((x) << 4)
  91 #define I80IFEN_ENABLE                  (1 << 0)
  92
  93 /* FIMD has totally five hardware windows. */
  94 #define WINDOWS_NR      5
  95
  96 /* HW trigger flag on i80 panel. */
  97 #define I80_HW_TRG     (1 << 1)
  98
  99 struct fimd_driver_data {
 100         unsigned int timing_base;
 101         unsigned int lcdblk_offset;
 102         unsigned int lcdblk_vt_shift;
 103         unsigned int lcdblk_bypass_shift;
 104         unsigned int lcdblk_mic_bypass_shift;
 105         unsigned int trg_type;
 106
 107         unsigned int has_shadowcon:1;
 108         unsigned int has_clksel:1;
 109         unsigned int has_limited_fmt:1;
 110         unsigned int has_vidoutcon:1;
 111         unsigned int has_vtsel:1;
 112         unsigned int has_mic_bypass:1;
 113         unsigned int has_dp_clk:1;
 114         unsigned int has_hw_trigger:1;
 115         unsigned int has_trigger_per_te:1;
 116 };
 117
 118 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 119         .timing_base = 0x0,
 120         .has_clksel = 1,
 121         .has_limited_fmt = 1,
 122 };
 123
 124 static struct fimd_driver_data s5pv210_fimd_driver_data = {
 125         .timing_base = 0x0,
 126         .has_shadowcon = 1,
 127         .has_clksel = 1,
 128 };
 129
 130 static struct fimd_driver_data exynos3_fimd_driver_data = {
 131         .timing_base = 0x20000,
 132         .lcdblk_offset = 0x210,
 133         .lcdblk_bypass_shift = 1,
 134         .has_shadowcon = 1,
 135         .has_vidoutcon = 1,
 136 };
 137
 138 static struct fimd_driver_data exynos4_fimd_driver_data = {
 139         .timing_base = 0x0,
 140         .lcdblk_offset = 0x210,
 141         .lcdblk_vt_shift = 10,
 142         .lcdblk_bypass_shift = 1,
 143         .has_shadowcon = 1,
 144         .has_vtsel = 1,
 145 };
 146
 147 static struct fimd_driver_data exynos5_fimd_driver_data = {
 148         .timing_base = 0x20000,
 149         .lcdblk_offset = 0x214,
 150         .lcdblk_vt_shift = 24,
 151         .lcdblk_bypass_shift = 15,
 152         .has_shadowcon = 1,
 153         .has_vidoutcon = 1,
 154         .has_vtsel = 1,
 155         .has_dp_clk = 1,
 156 };
 157
 158 static struct fimd_driver_data exynos5420_fimd_driver_data = {
 159         .timing_base = 0x20000,
 160         .lcdblk_offset = 0x214,
 161         .lcdblk_vt_shift = 24,
 162         .lcdblk_bypass_shift = 15,
 163         .lcdblk_mic_bypass_shift = 11,
 164         .has_shadowcon = 1,
 165         .has_vidoutcon = 1,
 166         .has_vtsel = 1,
 167         .has_mic_bypass = 1,
 168         .has_dp_clk = 1,
 169 };
 170
 171 struct fimd_context {
 172         struct device                   *dev;
 173         struct drm_device               *drm_dev;
 174         struct exynos_drm_crtc          *crtc;
 175         struct exynos_drm_plane         planes[WINDOWS_NR];
 176         struct exynos_drm_plane_config  configs[WINDOWS_NR];
 177         struct clk                      *bus_clk;
 178         struct clk                      *lcd_clk;
 179         void __iomem                    *regs;
 180         struct regmap                   *sysreg;
 181         unsigned long                   irq_flags;
 182         u32                             vidcon0;
 183         u32                             vidcon1;
 184         u32                             vidout_con;
 185         u32                             i80ifcon;
 186         bool                            i80_if;
 187         bool                            suspended;
 188         wait_queue_head_t               wait_vsync_queue;
 189         atomic_t                        wait_vsync_event;
 190         atomic_t                        win_updated;
 191         atomic_t                        triggering;
 192         u32                             clkdiv;
 193
 194         const struct fimd_driver_data *driver_data;
 195         struct drm_encoder *encoder;
 196         struct exynos_drm_clk           dp_clk;
 197 };
 198
 199 static const struct of_device_id fimd_driver_dt_match[] = {
 200         { .compatible = "samsung,s3c6400-fimd",
 201           .data = &s3c64xx_fimd_driver_data },
 202         { .compatible = "samsung,s5pv210-fimd",
 203           .data = &s5pv210_fimd_driver_data },
 204         { .compatible = "samsung,exynos3250-fimd",
 205           .data = &exynos3_fimd_driver_data },
 206         { .compatible = "samsung,exynos4210-fimd",
 207           .data = &exynos4_fimd_driver_data },
 208         { .compatible = "samsung,exynos5250-fimd",
 209           .data = &exynos5_fimd_driver_data },
 210         { .compatible = "samsung,exynos5420-fimd",
 211           .data = &exynos5420_fimd_driver_data },
 212         {},
 213 };
 214 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 215
 216 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
 217         DRM_PLANE_TYPE_PRIMARY,
 218         DRM_PLANE_TYPE_OVERLAY,
 219         DRM_PLANE_TYPE_OVERLAY,
 220         DRM_PLANE_TYPE_OVERLAY,
 221         DRM_PLANE_TYPE_CURSOR,
 222 };
 223
 224 static const uint32_t fimd_formats[] = {
 225         DRM_FORMAT_C8,
 226         DRM_FORMAT_XRGB1555,
 227         DRM_FORMAT_RGB565,
 228         DRM_FORMAT_XRGB8888,
 229         DRM_FORMAT_ARGB8888,
 230 };
 231
 232 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 233 {
 234         struct fimd_context *ctx = crtc->ctx;
 235         u32 val;
 236
 237         if (ctx->suspended)
 238                 return -EPERM;
 239
 240         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 241                 val = readl(ctx->regs + VIDINTCON0);
 242
 243                 val |= VIDINTCON0_INT_ENABLE;
 244
 245                 if (ctx->i80_if) {
 246                         val |= VIDINTCON0_INT_I80IFDONE;
 247                         val |= VIDINTCON0_INT_SYSMAINCON;
 248                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 249                 } else {
 250                         val |= VIDINTCON0_INT_FRAME;
 251
 252                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 253                         val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
 254                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 255                         val |= VIDINTCON0_FRAMESEL1_NONE;
 256                 }
 257
 258                 writel(val, ctx->regs + VIDINTCON0);
 259         }
 260
 261         return 0;
 262 }
 263
 264 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 265 {
 266         struct fimd_context *ctx = crtc->ctx;
 267         u32 val;
 268
 269         if (ctx->suspended)
 270                 return;
 271
 272         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 273                 val = readl(ctx->regs + VIDINTCON0);
 274
 275                 val &= ~VIDINTCON0_INT_ENABLE;
 276
 277                 if (ctx->i80_if) {
 278                         val &= ~VIDINTCON0_INT_I80IFDONE;
 279                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 280                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 281                 } else
 282                         val &= ~VIDINTCON0_INT_FRAME;
 283
 284                 writel(val, ctx->regs + VIDINTCON0);
 285         }
 286 }
 287
 288 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 289 {
 290         struct fimd_context *ctx = crtc->ctx;
 291
 292         if (ctx->suspended)
 293                 return;
 294
 295         atomic_set(&ctx->wait_vsync_event, 1);
 296
 297         /*
 298          * wait for FIMD to signal VSYNC interrupt or return after
 299          * timeout which is set to 50ms (refresh rate of 20).
 300          */
 301         if (!wait_event_timeout(ctx->wait_vsync_queue,
 302                                 !atomic_read(&ctx->wait_vsync_event),
 303                                 HZ/20))
 304                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 305 }
 306
 307 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 308                                         bool enable)
 309 {
 310         u32 val = readl(ctx->regs + WINCON(win));
 311
 312         if (enable)
 313                 val |= WINCONx_ENWIN;
 314         else
 315                 val &= ~WINCONx_ENWIN;
 316
 317         writel(val, ctx->regs + WINCON(win));
 318 }
 319
 320 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 321                                                 unsigned int win,
 322                                                 bool enable)
 323 {
 324         u32 val = readl(ctx->regs + SHADOWCON);
 325
 326         if (enable)
 327                 val |= SHADOWCON_CHx_ENABLE(win);
 328         else
 329                 val &= ~SHADOWCON_CHx_ENABLE(win);
 330
 331         writel(val, ctx->regs + SHADOWCON);
 332 }
 333
 334 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 335 {
 336         struct fimd_context *ctx = crtc->ctx;
 337         unsigned int win, ch_enabled = 0;
 338
 339         DRM_DEBUG_KMS("%s\n", __FILE__);
 340
 341         /* Hardware is in unknown state, so ensure it gets enabled properly */
 342         pm_runtime_get_sync(ctx->dev);
 343
 344         clk_prepare_enable(ctx->bus_clk);
 345         clk_prepare_enable(ctx->lcd_clk);
 346
 347         /* Check if any channel is enabled. */
 348         for (win = 0; win < WINDOWS_NR; win++) {
 349                 u32 val = readl(ctx->regs + WINCON(win));
 350
 351                 if (val & WINCONx_ENWIN) {
 352                         fimd_enable_video_output(ctx, win, false);
 353
 354                         if (ctx->driver_data->has_shadowcon)
 355                                 fimd_enable_shadow_channel_path(ctx, win,
 356                                                                 false);
 357
 358                         ch_enabled = 1;
 359                 }
 360         }
 361
 362         /* Wait for vsync, as disable channel takes effect at next vsync */
 363         if (ch_enabled) {
 364                 ctx->suspended = false;
 365
 366                 fimd_enable_vblank(ctx->crtc);
 367                 fimd_wait_for_vblank(ctx->crtc);
 368                 fimd_disable_vblank(ctx->crtc);
 369
 370                 ctx->suspended = true;
 371         }
 372
 373         clk_disable_unprepare(ctx->lcd_clk);
 374         clk_disable_unprepare(ctx->bus_clk);
 375
 376         pm_runtime_put(ctx->dev);
 377 }
 378
 379
 380 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
 381                 struct drm_crtc_state *state)
 382 {
 383         struct drm_display_mode *mode = &state->adjusted_mode;
 384         struct fimd_context *ctx = crtc->ctx;
 385         unsigned long ideal_clk, lcd_rate;
 386         u32 clkdiv;
 387
 388         if (mode->clock == 0) {
 389                 DRM_INFO("Mode has zero clock value.\n");
 390                 return -EINVAL;
 391         }
 392
 393         ideal_clk = mode->clock * 1000;
 394
 395         if (ctx->i80_if) {
 396                 /*
 397                  * The frame done interrupt should be occurred prior to the
 398                  * next TE signal.
 399                  */
 400                 ideal_clk *= 2;
 401         }
 402
 403         lcd_rate = clk_get_rate(ctx->lcd_clk);
 404         if (2 * lcd_rate < ideal_clk) {
 405                 DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
 406                          lcd_rate, ideal_clk);
 407                 return -EINVAL;
 408         }
 409
 410         /* Find the clock divider value that gets us closest to ideal_clk */
 411         clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
 412         if (clkdiv >= 0x200) {
 413                 DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk);
 414                 return -EINVAL;
 415         }
 416
 417         ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
 418
 419         return 0;
 420 }
 421
 422 static void fimd_setup_trigger(struct fimd_context *ctx)
 423 {
 424         void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
 425         u32 trg_type = ctx->driver_data->trg_type;
 426         u32 val = readl(timing_base + TRIGCON);
 427
 428         val &= ~(TRGMODE_ENABLE);
 429
 430         if (trg_type == I80_HW_TRG) {
 431                 if (ctx->driver_data->has_hw_trigger)
 432                         val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
 433                 if (ctx->driver_data->has_trigger_per_te)
 434                         val |= HWTRIGEN_PER_ENABLE;
 435         } else {
 436                 val |= TRGMODE_ENABLE;
 437         }
 438
 439         writel(val, timing_base + TRIGCON);
 440 }
 441
 442 static void fimd_commit(struct exynos_drm_crtc *crtc)
 443 {
 444         struct fimd_context *ctx = crtc->ctx;
 445         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 446         const struct fimd_driver_data *driver_data = ctx->driver_data;
 447         void *timing_base = ctx->regs + driver_data->timing_base;
 448         u32 val;
 449
 450         if (ctx->suspended)
 451                 return;
 452
 453         /* nothing to do if we haven't set the mode yet */
 454         if (mode->htotal == 0 || mode->vtotal == 0)
 455                 return;
 456
 457         if (ctx->i80_if) {
 458                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 459                 writel(val, timing_base + I80IFCONFAx(0));
 460
 461                 /* disable auto frame rate */
 462                 writel(0, timing_base + I80IFCONFBx(0));
 463
 464                 /* set video type selection to I80 interface */
 465                 if (driver_data->has_vtsel && ctx->sysreg &&
 466                                 regmap_update_bits(ctx->sysreg,
 467                                         driver_data->lcdblk_offset,
 468                                         0x3 << driver_data->lcdblk_vt_shift,
 469                                         0x1 << driver_data->lcdblk_vt_shift)) {
 470                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 471                         return;
 472                 }
 473         } else {
 474                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 475                 u32 vidcon1;
 476
 477                 /* setup polarity values */
 478                 vidcon1 = ctx->vidcon1;
 479                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 480                         vidcon1 |= VIDCON1_INV_VSYNC;
 481                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 482                         vidcon1 |= VIDCON1_INV_HSYNC;
 483                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 484
 485                 /* setup vertical timing values. */
 486                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 487                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 488                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 489
 490                 val = VIDTCON0_VBPD(vbpd - 1) |
 491                         VIDTCON0_VFPD(vfpd - 1) |
 492                         VIDTCON0_VSPW(vsync_len - 1);
 493                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 494
 495                 /* setup horizontal timing values.  */
 496                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 497                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 498                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 499
 500                 val = VIDTCON1_HBPD(hbpd - 1) |
 501                         VIDTCON1_HFPD(hfpd - 1) |
 502                         VIDTCON1_HSPW(hsync_len - 1);
 503                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 504         }
 505
 506         if (driver_data->has_vidoutcon)
 507                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 508
 509         /* set bypass selection */
 510         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 511                                 driver_data->lcdblk_offset,
 512                                 0x1 << driver_data->lcdblk_bypass_shift,
 513                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 514                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 515                 return;
 516         }
 517
 518         /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
 519          * bit should be cleared.
 520          */
 521         if (driver_data->has_mic_bypass && ctx->sysreg &&
 522             regmap_update_bits(ctx->sysreg,
 523                                 driver_data->lcdblk_offset,
 524                                 0x1 << driver_data->lcdblk_mic_bypass_shift,
 525                                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
 526                 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
 527                 return;
 528         }
 529
 530         /* setup horizontal and vertical display size. */
 531         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 532                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 533                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 534                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 535         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 536
 537         fimd_setup_trigger(ctx);
 538
 539         /*
 540          * fields of register with prefix '_F' would be updated
 541          * at vsync(same as dma start)
 542          */
 543         val = ctx->vidcon0;
 544         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 545
 546         if (ctx->driver_data->has_clksel)
 547                 val |= VIDCON0_CLKSEL_LCD;
 548
 549         if (ctx->clkdiv > 1)
 550                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 551
 552         writel(val, ctx->regs + VIDCON0);
 553 }
 554
 555
 556 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 557                                 uint32_t pixel_format, int width)
 558 {
 559         unsigned long val;
 560
 561         val = WINCONx_ENWIN;
 562
 563         /*
 564          * In case of s3c64xx, window 0 doesn't support alpha channel.
 565          * So the request format is ARGB8888 then change it to XRGB8888.
 566          */
 567         if (ctx->driver_data->has_limited_fmt && !win) {
 568                 if (pixel_format == DRM_FORMAT_ARGB8888)
 569                         pixel_format = DRM_FORMAT_XRGB8888;
 570         }
 571
 572         switch (pixel_format) {
 573         case DRM_FORMAT_C8:
 574                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 575                 val |= WINCONx_BURSTLEN_8WORD;
 576                 val |= WINCONx_BYTSWP;
 577                 break;
 578         case DRM_FORMAT_XRGB1555:
 579                 val |= WINCON0_BPPMODE_16BPP_1555;
 580                 val |= WINCONx_HAWSWP;
 581                 val |= WINCONx_BURSTLEN_16WORD;
 582                 break;
 583         case DRM_FORMAT_RGB565:
 584                 val |= WINCON0_BPPMODE_16BPP_565;
 585                 val |= WINCONx_HAWSWP;
 586                 val |= WINCONx_BURSTLEN_16WORD;
 587                 break;
 588         case DRM_FORMAT_XRGB8888:
 589                 val |= WINCON0_BPPMODE_24BPP_888;
 590                 val |= WINCONx_WSWP;
 591                 val |= WINCONx_BURSTLEN_16WORD;
 592                 break;
 593         case DRM_FORMAT_ARGB8888:
 594         default:
 595                 val |= WINCON1_BPPMODE_25BPP_A1888
 596                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 597                 val |= WINCONx_WSWP;
 598                 val |= WINCONx_BURSTLEN_16WORD;
 599                 break;
 600         }
 601
 602         /*
 603          * Setting dma-burst to 16Word causes permanent tearing for very small
 604          * buffers, e.g. cursor buffer. Burst Mode switching which based on
 605          * plane size is not recommended as plane size varies alot towards the
 606          * end of the screen and rapid movement causes unstable DMA, but it is
 607          * still better to change dma-burst than displaying garbage.
 608          */
 609
 610         if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 611                 val &= ~WINCONx_BURSTLEN_MASK;
 612                 val |= WINCONx_BURSTLEN_4WORD;
 613         }
 614
 615         writel(val, ctx->regs + WINCON(win));
 616
 617         /* hardware window 0 doesn't support alpha channel. */
 618         if (win != 0) {
 619                 /* OSD alpha */
 620                 val = VIDISD14C_ALPHA0_R(0xf) |
 621                         VIDISD14C_ALPHA0_G(0xf) |
 622                         VIDISD14C_ALPHA0_B(0xf) |
 623                         VIDISD14C_ALPHA1_R(0xf) |
 624                         VIDISD14C_ALPHA1_G(0xf) |
 625                         VIDISD14C_ALPHA1_B(0xf);
 626
 627                 writel(val, ctx->regs + VIDOSD_C(win));
 628
 629                 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
 630                         VIDW_ALPHA_G(0xf);
 631                 writel(val, ctx->regs + VIDWnALPHA0(win));
 632                 writel(val, ctx->regs + VIDWnALPHA1(win));
 633         }
 634 }
 635
 636 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 637 {
 638         unsigned int keycon0 = 0, keycon1 = 0;
 639
 640         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 641                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 642
 643         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 644
 645         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 646         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 647 }
 648
 649 /**
 650  * shadow_protect_win() - disable updating values from shadow registers at vsync
 651  *
 652  * @win: window to protect registers for
 653  * @protect: 1 to protect (disable updates)
 654  */
 655 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 656                                     unsigned int win, bool protect)
 657 {
 658         u32 reg, bits, val;
 659
 660         /*
 661          * SHADOWCON/PRTCON register is used for enabling timing.
 662          *
 663          * for example, once only width value of a register is set,
 664          * if the dma is started then fimd hardware could malfunction so
 665          * with protect window setting, the register fields with prefix '_F'
 666          * wouldn't be updated at vsync also but updated once unprotect window
 667          * is set.
 668          */
 669
 670         if (ctx->driver_data->has_shadowcon) {
 671                 reg = SHADOWCON;
 672                 bits = SHADOWCON_WINx_PROTECT(win);
 673         } else {
 674                 reg = PRTCON;
 675                 bits = PRTCON_PROTECT;
 676         }
 677
 678         val = readl(ctx->regs + reg);
 679         if (protect)
 680                 val |= bits;
 681         else
 682                 val &= ~bits;
 683         writel(val, ctx->regs + reg);
 684 }
 685
 686 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
 687 {
 688         struct fimd_context *ctx = crtc->ctx;
 689         int i;
 690
 691         if (ctx->suspended)
 692                 return;
 693
 694         for (i = 0; i < WINDOWS_NR; i++)
 695                 fimd_shadow_protect_win(ctx, i, true);
 696 }
 697
 698 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
 699 {
 700         struct fimd_context *ctx = crtc->ctx;
 701         int i;
 702
 703         if (ctx->suspended)
 704                 return;
 705
 706         for (i = 0; i < WINDOWS_NR; i++)
 707                 fimd_shadow_protect_win(ctx, i, false);
 708
 709         exynos_crtc_handle_event(crtc);
 710 }
 711
 712 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 713                               struct exynos_drm_plane *plane)
 714 {
 715         struct exynos_drm_plane_state *state =
 716                                 to_exynos_plane_state(plane->base.state);
 717         struct fimd_context *ctx = crtc->ctx;
 718         struct drm_framebuffer *fb = state->base.fb;
 719         dma_addr_t dma_addr;
 720         unsigned long val, size, offset;
 721         unsigned int last_x, last_y, buf_offsize, line_size;
 722         unsigned int win = plane->index;
 723         unsigned int cpp = fb->format->cpp[0];
 724         unsigned int pitch = fb->pitches[0];
 725
 726         if (ctx->suspended)
 727                 return;
 728
 729         offset = state->src.x * cpp;
 730         offset += state->src.y * pitch;
 731
 732         /* buffer start address */
 733         dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
 734         val = (unsigned long)dma_addr;
 735         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 736
 737         /* buffer end address */
 738         size = pitch * state->crtc.h;
 739         val = (unsigned long)(dma_addr + size);
 740         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 741
 742         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 743                         (unsigned long)dma_addr, val, size);
 744         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 745                         state->crtc.w, state->crtc.h);
 746
 747         /* buffer size */
 748         buf_offsize = pitch - (state->crtc.w * cpp);
 749         line_size = state->crtc.w * cpp;
 750         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 751                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 752                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 753                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 754         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 755
 756         /* OSD position */
 757         val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
 758                 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
 759                 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
 760                 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
 761         writel(val, ctx->regs + VIDOSD_A(win));
 762
 763         last_x = state->crtc.x + state->crtc.w;
 764         if (last_x)
 765                 last_x--;
 766         last_y = state->crtc.y + state->crtc.h;
 767         if (last_y)
 768                 last_y--;
 769
 770         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 771                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 772
 773         writel(val, ctx->regs + VIDOSD_B(win));
 774
 775         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 776                         state->crtc.x, state->crtc.y, last_x, last_y);
 777
 778         /* OSD size */
 779         if (win != 3 && win != 4) {
 780                 u32 offset = VIDOSD_D(win);
 781                 if (win == 0)
 782                         offset = VIDOSD_C(win);
 783                 val = state->crtc.w * state->crtc.h;
 784                 writel(val, ctx->regs + offset);
 785
 786                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 787         }
 788
 789         fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w);
 790
 791         /* hardware window 0 doesn't support color key. */
 792         if (win != 0)
 793                 fimd_win_set_colkey(ctx, win);
 794
 795         fimd_enable_video_output(ctx, win, true);
 796
 797         if (ctx->driver_data->has_shadowcon)
 798                 fimd_enable_shadow_channel_path(ctx, win, true);
 799
 800         if (ctx->i80_if)
 801                 atomic_set(&ctx->win_updated, 1);
 802 }
 803
 804 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 805                                struct exynos_drm_plane *plane)
 806 {
 807         struct fimd_context *ctx = crtc->ctx;
 808         unsigned int win = plane->index;
 809
 810         if (ctx->suspended)
 811                 return;
 812
 813         fimd_enable_video_output(ctx, win, false);
 814
 815         if (ctx->driver_data->has_shadowcon)
 816                 fimd_enable_shadow_channel_path(ctx, win, false);
 817 }
 818
 819 static void fimd_enable(struct exynos_drm_crtc *crtc)
 820 {
 821         struct fimd_context *ctx = crtc->ctx;
 822
 823         if (!ctx->suspended)
 824                 return;
 825
 826         ctx->suspended = false;
 827
 828         pm_runtime_get_sync(ctx->dev);
 829
 830         /* if vblank was enabled status, enable it again. */
 831         if (test_and_clear_bit(0, &ctx->irq_flags))
 832                 fimd_enable_vblank(ctx->crtc);
 833
 834         fimd_commit(ctx->crtc);
 835 }
 836
 837 static void fimd_disable(struct exynos_drm_crtc *crtc)
 838 {
 839         struct fimd_context *ctx = crtc->ctx;
 840         int i;
 841
 842         if (ctx->suspended)
 843                 return;
 844
 845         /*
 846          * We need to make sure that all windows are disabled before we
 847          * suspend that connector. Otherwise we might try to scan from
 848          * a destroyed buffer later.
 849          */
 850         for (i = 0; i < WINDOWS_NR; i++)
 851                 fimd_disable_plane(crtc, &ctx->planes[i]);
 852
 853         fimd_enable_vblank(crtc);
 854         fimd_wait_for_vblank(crtc);
 855         fimd_disable_vblank(crtc);
 856
 857         writel(0, ctx->regs + VIDCON0);
 858
 859         pm_runtime_put_sync(ctx->dev);
 860         ctx->suspended = true;
 861 }
 862
 863 static void fimd_trigger(struct device *dev)
 864 {
 865         struct fimd_context *ctx = dev_get_drvdata(dev);
 866         const struct fimd_driver_data *driver_data = ctx->driver_data;
 867         void *timing_base = ctx->regs + driver_data->timing_base;
 868         u32 reg;
 869
 870          /*
 871           * Skips triggering if in triggering state, because multiple triggering
 872           * requests can cause panel reset.
 873           */
 874         if (atomic_read(&ctx->triggering))
 875                 return;
 876
 877         /* Enters triggering mode */
 878         atomic_set(&ctx->triggering, 1);
 879
 880         reg = readl(timing_base + TRIGCON);
 881         reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
 882         writel(reg, timing_base + TRIGCON);
 883
 884         /*
 885          * Exits triggering mode if vblank is not enabled yet, because when the
 886          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 887          */
 888         if (!test_bit(0, &ctx->irq_flags))
 889                 atomic_set(&ctx->triggering, 0);
 890 }
 891
 892 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 893 {
 894         struct fimd_context *ctx = crtc->ctx;
 895         u32 trg_type = ctx->driver_data->trg_type;
 896
 897         /* Checks the crtc is detached already from encoder */
 898         if (!ctx->drm_dev)
 899                 return;
 900
 901         if (trg_type == I80_HW_TRG)
 902                 goto out;
 903
 904         /*
 905          * If there is a page flip request, triggers and handles the page flip
 906          * event so that current fb can be updated into panel GRAM.
 907          */
 908         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 909                 fimd_trigger(ctx->dev);
 910
 911 out:
 912         /* Wakes up vsync event queue */
 913         if (atomic_read(&ctx->wait_vsync_event)) {
 914                 atomic_set(&ctx->wait_vsync_event, 0);
 915                 wake_up(&ctx->wait_vsync_queue);
 916         }
 917
 918         if (test_bit(0, &ctx->irq_flags))
 919                 drm_crtc_handle_vblank(&ctx->crtc->base);
 920 }
 921
 922 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
 923 {
 924         struct fimd_context *ctx = container_of(clk, struct fimd_context,
 925                                                 dp_clk);
 926         u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
 927         writel(val, ctx->regs + DP_MIE_CLKCON);
 928 }
 929
 930 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
 931         .enable = fimd_enable,
 932         .disable = fimd_disable,
 933         .enable_vblank = fimd_enable_vblank,
 934         .disable_vblank = fimd_disable_vblank,
 935         .atomic_begin = fimd_atomic_begin,
 936         .update_plane = fimd_update_plane,
 937         .disable_plane = fimd_disable_plane,
 938         .atomic_flush = fimd_atomic_flush,
 939         .atomic_check = fimd_atomic_check,
 940         .te_handler = fimd_te_handler,
 941 };
 942
 943 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 944 {
 945         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 946         u32 val, clear_bit;
 947
 948         val = readl(ctx->regs + VIDINTCON1);
 949
 950         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
 951         if (val & clear_bit)
 952                 writel(clear_bit, ctx->regs + VIDINTCON1);
 953
 954         /* check the crtc is detached already from encoder */
 955         if (!ctx->drm_dev)
 956                 goto out;
 957
 958         if (!ctx->i80_if)
 959                 drm_crtc_handle_vblank(&ctx->crtc->base);
 960
 961         if (ctx->i80_if) {
 962                 /* Exits triggering mode */
 963                 atomic_set(&ctx->triggering, 0);
 964         } else {
 965                 /* set wait vsync event to zero and wake up queue. */
 966                 if (atomic_read(&ctx->wait_vsync_event)) {
 967                         atomic_set(&ctx->wait_vsync_event, 0);
 968                         wake_up(&ctx->wait_vsync_queue);
 969                 }
 970         }
 971
 972 out:
 973         return IRQ_HANDLED;
 974 }
 975
 976 static int fimd_bind(struct device *dev, struct device *master, void *data)
 977 {
 978         struct fimd_context *ctx = dev_get_drvdata(dev);
 979         struct drm_device *drm_dev = data;
 980         struct exynos_drm_plane *exynos_plane;
 981         unsigned int i;
 982         int ret;
 983
 984         ctx->drm_dev = drm_dev;
 985
 986         for (i = 0; i < WINDOWS_NR; i++) {
 987                 ctx->configs[i].pixel_formats = fimd_formats;
 988                 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
 989                 ctx->configs[i].zpos = i;
 990                 ctx->configs[i].type = fimd_win_types[i];
 991                 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
 992                                         &ctx->configs[i]);
 993                 if (ret)
 994                         return ret;
 995         }
 996
 997         exynos_plane = &ctx->planes[DEFAULT_WIN];
 998         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 999                         EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
1000         if (IS_ERR(ctx->crtc))
1001                 return PTR_ERR(ctx->crtc);
1002
1003         if (ctx->driver_data->has_dp_clk) {
1004                 ctx->dp_clk.enable = fimd_dp_clock_enable;
1005                 ctx->crtc->pipe_clk = &ctx->dp_clk;
1006         }
1007
1008         if (ctx->encoder)
1009                 exynos_dpi_bind(drm_dev, ctx->encoder);
1010
1011         if (is_drm_iommu_supported(drm_dev))
1012                 fimd_clear_channels(ctx->crtc);
1013
1014         return drm_iommu_attach_device(drm_dev, dev);
1015 }
1016
1017 static void fimd_unbind(struct device *dev, struct device *master,
1018                         void *data)
1019 {
1020         struct fimd_context *ctx = dev_get_drvdata(dev);
1021
1022         fimd_disable(ctx->crtc);
1023
1024         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
1025
1026         if (ctx->encoder)
1027                 exynos_dpi_remove(ctx->encoder);
1028 }
1029
1030 static const struct component_ops fimd_component_ops = {
1031         .bind   = fimd_bind,
1032         .unbind = fimd_unbind,
1033 };
1034
1035 static int fimd_probe(struct platform_device *pdev)
1036 {
1037         struct device *dev = &pdev->dev;
1038         struct fimd_context *ctx;
1039         struct device_node *i80_if_timings;
1040         struct resource *res;
1041         int ret;
1042
1043         if (!dev->of_node)
1044                 return -ENODEV;
1045
1046         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1047         if (!ctx)
1048                 return -ENOMEM;
1049
1050         ctx->dev = dev;
1051         ctx->suspended = true;
1052         ctx->driver_data = of_device_get_match_data(dev);
1053
1054         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1055                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1056         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1057                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1058
1059         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1060         if (i80_if_timings) {
1061                 u32 val;
1062
1063                 ctx->i80_if = true;
1064
1065                 if (ctx->driver_data->has_vidoutcon)
1066                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1067                 else
1068                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1069                 /*
1070                  * The user manual describes that this "DSI_EN" bit is required
1071                  * to enable I80 24-bit data interface.
1072                  */
1073                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1074
1075                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1076                         val = 0;
1077                 ctx->i80ifcon = LCD_CS_SETUP(val);
1078                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1079                         val = 0;
1080                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1081                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1082                         val = 1;
1083                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1084                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1085                         val = 0;
1086                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1087         }
1088         of_node_put(i80_if_timings);
1089
1090         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1091                                                         "samsung,sysreg");
1092         if (IS_ERR(ctx->sysreg)) {
1093                 dev_warn(dev, "failed to get system register.\n");
1094                 ctx->sysreg = NULL;
1095         }
1096
1097         ctx->bus_clk = devm_clk_get(dev, "fimd");
1098         if (IS_ERR(ctx->bus_clk)) {
1099                 dev_err(dev, "failed to get bus clock\n");
1100                 return PTR_ERR(ctx->bus_clk);
1101         }
1102
1103         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1104         if (IS_ERR(ctx->lcd_clk)) {
1105                 dev_err(dev, "failed to get lcd clock\n");
1106                 return PTR_ERR(ctx->lcd_clk);
1107         }
1108
1109         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1110
1111         ctx->regs = devm_ioremap_resource(dev, res);
1112         if (IS_ERR(ctx->regs))
1113                 return PTR_ERR(ctx->regs);
1114
1115         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1116                                            ctx->i80_if ? "lcd_sys" : "vsync");
1117         if (!res) {
1118                 dev_err(dev, "irq request failed.\n");
1119                 return -ENXIO;
1120         }
1121
1122         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1123                                                         0, "drm_fimd", ctx);
1124         if (ret) {
1125                 dev_err(dev, "irq request failed.\n");
1126                 return ret;
1127         }
1128
1129         init_waitqueue_head(&ctx->wait_vsync_queue);
1130         atomic_set(&ctx->wait_vsync_event, 0);
1131
1132         platform_set_drvdata(pdev, ctx);
1133
1134         ctx->encoder = exynos_dpi_probe(dev);
1135         if (IS_ERR(ctx->encoder))
1136                 return PTR_ERR(ctx->encoder);
1137
1138         pm_runtime_enable(dev);
1139
1140         ret = component_add(dev, &fimd_component_ops);
1141         if (ret)
1142                 goto err_disable_pm_runtime;
1143
1144         return ret;
1145
1146 err_disable_pm_runtime:
1147         pm_runtime_disable(dev);
1148
1149         return ret;
1150 }
1151
1152 static int fimd_remove(struct platform_device *pdev)
1153 {
1154         pm_runtime_disable(&pdev->dev);
1155
1156         component_del(&pdev->dev, &fimd_component_ops);
1157
1158         return 0;
1159 }
1160
1161 #ifdef CONFIG_PM
1162 static int exynos_fimd_suspend(struct device *dev)
1163 {
1164         struct fimd_context *ctx = dev_get_drvdata(dev);
1165
1166         clk_disable_unprepare(ctx->lcd_clk);
1167         clk_disable_unprepare(ctx->bus_clk);
1168
1169         return 0;
1170 }
1171
1172 static int exynos_fimd_resume(struct device *dev)
1173 {
1174         struct fimd_context *ctx = dev_get_drvdata(dev);
1175         int ret;
1176
1177         ret = clk_prepare_enable(ctx->bus_clk);
1178         if (ret < 0) {
1179                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1180                 return ret;
1181         }
1182
1183         ret = clk_prepare_enable(ctx->lcd_clk);
1184         if  (ret < 0) {
1185                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1186                 return ret;
1187         }
1188
1189         return 0;
1190 }
1191 #endif
1192
1193 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1194         SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1195         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1196                                 pm_runtime_force_resume)
1197 };
1198
1199 struct platform_driver fimd_driver = {
1200         .probe          = fimd_probe,
1201         .remove         = fimd_remove,
1202         .driver         = {
1203                 .name   = "exynos4-fb",
1204                 .owner  = THIS_MODULE,
1205                 .pm     = &exynos_fimd_pm_ops,
1206                 .of_match_table = fimd_driver_dt_match,
1207         },
1208 };