1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/hdmi.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/regmap.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spinlock.h>
22 #include <media/cec-notifier.h>
24 #include <uapi/linux/media-bus-format.h>
25 #include <uapi/linux/videodev2.h>
27 #include <drm/bridge/dw_hdmi.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_edid.h>
32 #include <drm/drm_of.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_probe_helper.h>
35 #include <drm/drm_scdc_helper.h>
37 #include "dw-hdmi-audio.h"
38 #include "dw-hdmi-cec.h"
41 #define DDC_CI_ADDR 0x37
42 #define DDC_SEGMENT_ADDR 0x30
44 #define HDMI_EDID_LEN 512
46 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
47 #define SCDC_MIN_SOURCE_VERSION 0x1
49 #define HDMI14_MAX_TMDSCLK 340000000
65 static const u16 csc_coeff_default[3][4] = {
66 { 0x2000, 0x0000, 0x0000, 0x0000 },
67 { 0x0000, 0x2000, 0x0000, 0x0000 },
68 { 0x0000, 0x0000, 0x2000, 0x0000 }
71 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
72 { 0x2000, 0x6926, 0x74fd, 0x010e },
73 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
74 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
77 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
78 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
79 { 0x2000, 0x3264, 0x0000, 0x7e6d },
80 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
83 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
84 { 0x2591, 0x1322, 0x074b, 0x0000 },
85 { 0x6535, 0x2000, 0x7acc, 0x0200 },
86 { 0x6acd, 0x7534, 0x2000, 0x0200 }
89 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
90 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
91 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
92 { 0x6756, 0x78ab, 0x2000, 0x0200 }
95 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
96 { 0x1b7c, 0x0000, 0x0000, 0x0020 },
97 { 0x0000, 0x1b7c, 0x0000, 0x0020 },
98 { 0x0000, 0x0000, 0x1b7c, 0x0020 }
102 bool mdataenablepolarity;
104 unsigned int mpixelclock;
105 unsigned int mpixelrepetitioninput;
106 unsigned int mpixelrepetitionoutput;
107 unsigned int mtmdsclock;
110 struct hdmi_data_info {
111 unsigned int enc_in_bus_format;
112 unsigned int enc_out_bus_format;
113 unsigned int enc_in_encoding;
114 unsigned int enc_out_encoding;
115 unsigned int pix_repet_factor;
116 unsigned int hdcp_enable;
117 struct hdmi_vmode video_mode;
118 bool rgb_limited_range;
122 struct i2c_adapter adap;
124 struct mutex lock; /* used to serialize data transfers */
125 struct completion cmp;
133 struct dw_hdmi_phy_data {
134 enum dw_hdmi_phy_type type;
138 int (*configure)(struct dw_hdmi *hdmi,
139 const struct dw_hdmi_plat_data *pdata,
140 unsigned long mpixelclock);
144 struct drm_connector connector;
145 struct drm_bridge bridge;
147 unsigned int version;
149 struct platform_device *audio;
150 struct platform_device *cec;
152 struct clk *isfr_clk;
153 struct clk *iahb_clk;
155 struct dw_hdmi_i2c *i2c;
157 struct hdmi_data_info hdmi_data;
158 const struct dw_hdmi_plat_data *plat_data;
162 u8 edid[HDMI_EDID_LEN];
165 const struct dw_hdmi_phy_ops *ops;
171 struct drm_display_mode previous_mode;
173 struct i2c_adapter *ddc;
178 struct pinctrl *pinctrl;
179 struct pinctrl_state *default_state;
180 struct pinctrl_state *unwedge_state;
182 struct mutex mutex; /* for state below and previous_mode */
183 enum drm_connector_force force; /* mutex-protected force state */
184 bool disabled; /* DRM has disabled our bridge */
185 bool bridge_is_on; /* indicates the bridge is on */
186 bool rxsense; /* rxsense state */
187 u8 phy_mask; /* desired phy int mask settings */
188 u8 mc_clkdis; /* clock disable register */
190 spinlock_t audio_lock;
191 struct mutex audio_mutex;
192 unsigned int sample_rate;
193 unsigned int audio_cts;
194 unsigned int audio_n;
197 unsigned int reg_shift;
199 void (*enable_audio)(struct dw_hdmi *hdmi);
200 void (*disable_audio)(struct dw_hdmi *hdmi);
202 struct mutex cec_notifier_mutex;
203 struct cec_notifier *cec_notifier;
205 hdmi_codec_plugged_cb plugged_cb;
206 struct device *codec_dev;
207 enum drm_connector_status last_connector_result;
210 #define HDMI_IH_PHY_STAT0_RX_SENSE \
211 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
212 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
214 #define HDMI_PHY_RX_SENSE \
215 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
216 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
218 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
220 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
223 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
225 unsigned int val = 0;
227 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
232 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
234 if (hdmi->plugged_cb && hdmi->codec_dev)
235 hdmi->plugged_cb(hdmi->codec_dev, plugged);
238 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
239 struct device *codec_dev)
243 mutex_lock(&hdmi->mutex);
244 hdmi->plugged_cb = fn;
245 hdmi->codec_dev = codec_dev;
246 plugged = hdmi->last_connector_result == connector_status_connected;
247 handle_plugged_change(hdmi, plugged);
248 mutex_unlock(&hdmi->mutex);
252 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
254 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
256 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
259 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
262 hdmi_modb(hdmi, data << shift, mask, reg);
265 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
267 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
268 HDMI_PHY_I2CM_INT_ADDR);
270 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
271 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
272 HDMI_PHY_I2CM_CTLINT_ADDR);
275 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
277 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
278 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
280 /* Set done, not acknowledged and arbitration interrupt polarities */
281 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
282 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
285 /* Clear DONE and ERROR interrupts */
286 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
289 /* Mute DONE and ERROR interrupts */
290 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
291 HDMI_IH_MUTE_I2CM_STAT0);
294 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
296 /* If no unwedge state then give up */
297 if (!hdmi->unwedge_state)
300 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
303 * This is a huge hack to workaround a problem where the dw_hdmi i2c
304 * bus could sometimes get wedged. Once wedged there doesn't appear
305 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
306 * other than pulsing the SDA line.
308 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
310 * 1. Remux the pin as a GPIO output, driven low.
311 * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
312 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
314 * At the moment of remuxing, the line will still be low due to its
315 * recent stint as an output, but then it will be pulled high by the
316 * (presumed) external pullup. dw_hdmi seems to see this as a rising
317 * edge and that seems to get it out of its jam.
319 * This wedging was only ever seen on one TV, and only on one of
320 * its HDMI ports. It happened when the TV was powered on while the
321 * device was plugged in. A scope trace shows the TV bringing both SDA
322 * and SCL low, then bringing them both back up at roughly the same
323 * time. Presumably this confuses dw_hdmi because it saw activity but
324 * no real STOP (maybe it thinks there's another master on the bus?).
325 * Giving it a clean rising edge of SDA while SCL is already high
326 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
329 * Note that after coming back alive, transfers seem to immediately
330 * resume, so if we unwedge due to a timeout we should wait a little
331 * longer for our transfer to finish, since it might have just started
334 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
336 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
341 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
343 struct dw_hdmi_i2c *i2c = hdmi->i2c;
346 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
348 /* If we can't unwedge, return timeout */
349 if (!dw_hdmi_i2c_unwedge(hdmi))
352 /* We tried to unwedge; give it another chance */
353 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
358 /* Check for error condition on the bus */
359 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
365 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
366 unsigned char *buf, unsigned int length)
368 struct dw_hdmi_i2c *i2c = hdmi->i2c;
371 if (!i2c->is_regaddr) {
372 dev_dbg(hdmi->dev, "set read register address to 0\n");
373 i2c->slave_reg = 0x00;
374 i2c->is_regaddr = true;
378 reinit_completion(&i2c->cmp);
380 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
382 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
383 HDMI_I2CM_OPERATION);
385 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
386 HDMI_I2CM_OPERATION);
388 ret = dw_hdmi_i2c_wait(hdmi);
392 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
394 i2c->is_segment = false;
399 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
400 unsigned char *buf, unsigned int length)
402 struct dw_hdmi_i2c *i2c = hdmi->i2c;
405 if (!i2c->is_regaddr) {
406 /* Use the first write byte as register address */
407 i2c->slave_reg = buf[0];
410 i2c->is_regaddr = true;
414 reinit_completion(&i2c->cmp);
416 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
417 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
418 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
419 HDMI_I2CM_OPERATION);
421 ret = dw_hdmi_i2c_wait(hdmi);
429 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
430 struct i2c_msg *msgs, int num)
432 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
433 struct dw_hdmi_i2c *i2c = hdmi->i2c;
434 u8 addr = msgs[0].addr;
437 if (addr == DDC_CI_ADDR)
439 * The internal I2C controller does not support the multi-byte
440 * read and write operations needed for DDC/CI.
441 * TOFIX: Blacklist the DDC/CI address until we filter out
442 * unsupported I2C operations.
446 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
448 for (i = 0; i < num; i++) {
449 if (msgs[i].len == 0) {
451 "unsupported transfer %d/%d, no data\n",
457 mutex_lock(&i2c->lock);
459 /* Unmute DONE and ERROR interrupts */
460 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
462 /* Set slave device address taken from the first I2C message */
463 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
465 /* Set slave device register address on transfer */
466 i2c->is_regaddr = false;
468 /* Set segment pointer for I2C extended read mode operation */
469 i2c->is_segment = false;
471 for (i = 0; i < num; i++) {
472 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
473 i + 1, num, msgs[i].len, msgs[i].flags);
474 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
475 i2c->is_segment = true;
476 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
477 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
479 if (msgs[i].flags & I2C_M_RD)
480 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
483 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
493 /* Mute DONE and ERROR interrupts */
494 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
495 HDMI_IH_MUTE_I2CM_STAT0);
497 mutex_unlock(&i2c->lock);
502 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
504 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
507 static const struct i2c_algorithm dw_hdmi_algorithm = {
508 .master_xfer = dw_hdmi_i2c_xfer,
509 .functionality = dw_hdmi_i2c_func,
512 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
514 struct i2c_adapter *adap;
515 struct dw_hdmi_i2c *i2c;
518 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
520 return ERR_PTR(-ENOMEM);
522 mutex_init(&i2c->lock);
523 init_completion(&i2c->cmp);
526 adap->class = I2C_CLASS_DDC;
527 adap->owner = THIS_MODULE;
528 adap->dev.parent = hdmi->dev;
529 adap->algo = &dw_hdmi_algorithm;
530 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
531 i2c_set_adapdata(adap, hdmi);
533 ret = i2c_add_adapter(adap);
535 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
536 devm_kfree(hdmi->dev, i2c);
542 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
547 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
550 /* Must be set/cleared first */
551 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
553 /* nshift factor = 0 */
554 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
556 /* Use automatic CTS generation mode when CTS is not set */
558 hdmi_writeb(hdmi, ((cts >> 16) &
559 HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
560 HDMI_AUD_CTS3_CTS_MANUAL,
563 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
564 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
565 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
567 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
568 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
569 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
572 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
574 unsigned int n = (128 * freq) / 1000;
575 unsigned int mult = 1;
577 while (freq > 48000) {
584 if (pixel_clk == 25175000)
586 else if (pixel_clk == 27027000)
588 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
596 if (pixel_clk == 25175000)
598 else if (pixel_clk == 74176000)
600 else if (pixel_clk == 148352000)
608 if (pixel_clk == 25175000)
610 else if (pixel_clk == 27027000)
612 else if (pixel_clk == 74176000)
614 else if (pixel_clk == 148352000)
629 * When transmitting IEC60958 linear PCM audio, these registers allow to
630 * configure the channel status information of all the channel status
631 * bits in the IEC60958 frame. For the moment this configuration is only
632 * used when the I2S audio interface, General Purpose Audio (GPA),
633 * or AHB audio DMA (AHBAUDDMA) interface is active
634 * (for S/PDIF interface this information comes from the stream).
636 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
640 * Set channel status register for frequency and word length.
641 * Use default values for other registers.
643 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
644 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
646 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
648 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
649 unsigned long pixel_clk, unsigned int sample_rate)
651 unsigned long ftdms = pixel_clk;
656 n = hdmi_compute_n(sample_rate, pixel_clk);
658 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
660 /* Only compute CTS when using internal AHB audio */
661 if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
663 * Compute the CTS value from the N value. Note that CTS and N
664 * can be up to 20 bits in total, so we need 64-bit math. Also
665 * note that our TDMS clock is not fully accurate; it is
666 * accurate to kHz. This can introduce an unnecessary remainder
667 * in the calculation below, so we don't try to warn about that.
669 tmp = (u64)ftdms * n;
670 do_div(tmp, 128 * sample_rate);
673 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
674 __func__, sample_rate,
675 ftdms / 1000000, (ftdms / 1000) % 1000,
681 spin_lock_irq(&hdmi->audio_lock);
683 hdmi->audio_cts = cts;
684 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
685 spin_unlock_irq(&hdmi->audio_lock);
688 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
690 mutex_lock(&hdmi->audio_mutex);
691 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
692 mutex_unlock(&hdmi->audio_mutex);
695 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
697 mutex_lock(&hdmi->audio_mutex);
698 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
700 mutex_unlock(&hdmi->audio_mutex);
703 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
705 mutex_lock(&hdmi->audio_mutex);
706 hdmi->sample_rate = rate;
707 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
709 mutex_unlock(&hdmi->audio_mutex);
711 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
713 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
717 mutex_lock(&hdmi->audio_mutex);
720 * For >2 channel PCM audio, we need to select layout 1
721 * and set an appropriate channel map.
724 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
726 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
728 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
731 /* Set the audio infoframes channel count */
732 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
733 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
735 mutex_unlock(&hdmi->audio_mutex);
737 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
739 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
741 mutex_lock(&hdmi->audio_mutex);
743 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
745 mutex_unlock(&hdmi->audio_mutex);
747 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
749 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
752 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
754 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
755 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
758 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
760 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
763 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
765 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
768 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
770 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
771 hdmi_enable_audio_clk(hdmi, true);
774 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
776 hdmi_enable_audio_clk(hdmi, false);
779 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
783 spin_lock_irqsave(&hdmi->audio_lock, flags);
784 hdmi->audio_enable = true;
785 if (hdmi->enable_audio)
786 hdmi->enable_audio(hdmi);
787 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
789 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
791 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
795 spin_lock_irqsave(&hdmi->audio_lock, flags);
796 hdmi->audio_enable = false;
797 if (hdmi->disable_audio)
798 hdmi->disable_audio(hdmi);
799 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
801 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
803 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
805 switch (bus_format) {
806 case MEDIA_BUS_FMT_RGB888_1X24:
807 case MEDIA_BUS_FMT_RGB101010_1X30:
808 case MEDIA_BUS_FMT_RGB121212_1X36:
809 case MEDIA_BUS_FMT_RGB161616_1X48:
817 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
819 switch (bus_format) {
820 case MEDIA_BUS_FMT_YUV8_1X24:
821 case MEDIA_BUS_FMT_YUV10_1X30:
822 case MEDIA_BUS_FMT_YUV12_1X36:
823 case MEDIA_BUS_FMT_YUV16_1X48:
831 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
833 switch (bus_format) {
834 case MEDIA_BUS_FMT_UYVY8_1X16:
835 case MEDIA_BUS_FMT_UYVY10_1X20:
836 case MEDIA_BUS_FMT_UYVY12_1X24:
844 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
846 switch (bus_format) {
847 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
848 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
849 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
850 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
858 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
860 switch (bus_format) {
861 case MEDIA_BUS_FMT_RGB888_1X24:
862 case MEDIA_BUS_FMT_YUV8_1X24:
863 case MEDIA_BUS_FMT_UYVY8_1X16:
864 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
867 case MEDIA_BUS_FMT_RGB101010_1X30:
868 case MEDIA_BUS_FMT_YUV10_1X30:
869 case MEDIA_BUS_FMT_UYVY10_1X20:
870 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
873 case MEDIA_BUS_FMT_RGB121212_1X36:
874 case MEDIA_BUS_FMT_YUV12_1X36:
875 case MEDIA_BUS_FMT_UYVY12_1X24:
876 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
879 case MEDIA_BUS_FMT_RGB161616_1X48:
880 case MEDIA_BUS_FMT_YUV16_1X48:
881 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
890 * this submodule is responsible for the video data synchronization.
891 * for example, for RGB 4:4:4 input, the data map is defined as
892 * pin{47~40} <==> R[7:0]
893 * pin{31~24} <==> G[7:0]
894 * pin{15~8} <==> B[7:0]
896 static void hdmi_video_sample(struct dw_hdmi *hdmi)
898 int color_format = 0;
901 switch (hdmi->hdmi_data.enc_in_bus_format) {
902 case MEDIA_BUS_FMT_RGB888_1X24:
905 case MEDIA_BUS_FMT_RGB101010_1X30:
908 case MEDIA_BUS_FMT_RGB121212_1X36:
911 case MEDIA_BUS_FMT_RGB161616_1X48:
915 case MEDIA_BUS_FMT_YUV8_1X24:
916 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
919 case MEDIA_BUS_FMT_YUV10_1X30:
920 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
923 case MEDIA_BUS_FMT_YUV12_1X36:
924 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
927 case MEDIA_BUS_FMT_YUV16_1X48:
928 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
932 case MEDIA_BUS_FMT_UYVY8_1X16:
935 case MEDIA_BUS_FMT_UYVY10_1X20:
938 case MEDIA_BUS_FMT_UYVY12_1X24:
946 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
947 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
948 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
949 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
951 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
952 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
953 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
954 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
955 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
956 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
957 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
958 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
959 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
960 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
961 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
964 static int is_color_space_conversion(struct dw_hdmi *hdmi)
966 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
967 bool is_input_rgb, is_output_rgb;
969 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
970 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
972 return (is_input_rgb != is_output_rgb) ||
973 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
976 static int is_color_space_decimation(struct dw_hdmi *hdmi)
978 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
981 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
982 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
988 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
990 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
993 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
994 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1000 static bool is_csc_needed(struct dw_hdmi *hdmi)
1002 return is_color_space_conversion(hdmi) ||
1003 is_color_space_decimation(hdmi) ||
1004 is_color_space_interpolation(hdmi);
1007 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1009 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1010 bool is_input_rgb, is_output_rgb;
1014 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1015 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1017 if (!is_input_rgb && is_output_rgb) {
1018 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1019 csc_coeff = &csc_coeff_rgb_out_eitu601;
1021 csc_coeff = &csc_coeff_rgb_out_eitu709;
1022 } else if (is_input_rgb && !is_output_rgb) {
1023 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1024 csc_coeff = &csc_coeff_rgb_in_eitu601;
1026 csc_coeff = &csc_coeff_rgb_in_eitu709;
1028 } else if (is_input_rgb && is_output_rgb &&
1029 hdmi->hdmi_data.rgb_limited_range) {
1030 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
1033 /* The CSC registers are sequential, alternating MSB then LSB */
1034 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1035 u16 coeff_a = (*csc_coeff)[0][i];
1036 u16 coeff_b = (*csc_coeff)[1][i];
1037 u16 coeff_c = (*csc_coeff)[2][i];
1039 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1040 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1041 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1042 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1043 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1044 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1047 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1051 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1053 int color_depth = 0;
1054 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1057 /* YCC422 interpolation to 444 mode */
1058 if (is_color_space_interpolation(hdmi))
1059 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1060 else if (is_color_space_decimation(hdmi))
1061 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1063 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1065 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1068 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1071 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1074 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1081 /* Configure the CSC registers */
1082 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1083 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1086 dw_hdmi_update_csc_coeffs(hdmi);
1090 * HDMI video packetizer is used to packetize the data.
1091 * for example, if input is YCC422 mode or repeater is used,
1092 * data should be repacked this module can be bypassed.
1094 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1096 unsigned int color_depth = 0;
1097 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1098 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1099 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1102 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1103 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1104 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1105 switch (hdmi_bus_fmt_color_depth(
1106 hdmi->hdmi_data.enc_out_bus_format)) {
1109 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1121 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1123 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1124 switch (hdmi_bus_fmt_color_depth(
1125 hdmi->hdmi_data.enc_out_bus_format)) {
1128 remap_size = HDMI_VP_REMAP_YCC422_16bit;
1131 remap_size = HDMI_VP_REMAP_YCC422_20bit;
1134 remap_size = HDMI_VP_REMAP_YCC422_24bit;
1140 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1145 /* set the packetizer registers */
1146 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1147 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1148 ((hdmi_data->pix_repet_factor <<
1149 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1150 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1151 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1153 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1154 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1156 /* Data from pixel repeater block */
1157 if (hdmi_data->pix_repet_factor > 1) {
1158 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1159 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1160 } else { /* data from packetizer block */
1161 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1162 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1165 hdmi_modb(hdmi, vp_conf,
1166 HDMI_VP_CONF_PR_EN_MASK |
1167 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1169 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1170 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1172 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1174 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1175 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1176 HDMI_VP_CONF_PP_EN_ENABLE |
1177 HDMI_VP_CONF_YCC422_EN_DISABLE;
1178 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1179 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1180 HDMI_VP_CONF_PP_EN_DISABLE |
1181 HDMI_VP_CONF_YCC422_EN_ENABLE;
1182 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1183 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1184 HDMI_VP_CONF_PP_EN_DISABLE |
1185 HDMI_VP_CONF_YCC422_EN_DISABLE;
1190 hdmi_modb(hdmi, vp_conf,
1191 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1192 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1194 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1195 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1196 HDMI_VP_STUFF_PP_STUFFING_MASK |
1197 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1199 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1203 /* -----------------------------------------------------------------------------
1204 * Synopsys PHY Handling
1207 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1210 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1211 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1214 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1218 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1223 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1228 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1231 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1232 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1233 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1234 HDMI_PHY_I2CM_DATAO_1_ADDR);
1235 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1236 HDMI_PHY_I2CM_DATAO_0_ADDR);
1237 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1238 HDMI_PHY_I2CM_OPERATION_ADDR);
1239 hdmi_phy_wait_i2c_done(hdmi, 1000);
1241 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1243 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
1244 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
1245 const struct drm_display_info *display)
1247 /* Completely disable SCDC support for older controllers */
1248 if (hdmi->version < 0x200a)
1251 /* Disable if no DDC bus */
1255 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1256 if (!display->hdmi.scdc.supported ||
1257 !display->hdmi.scdc.scrambling.supported)
1261 * Disable if display only support low TMDS rates and scrambling
1262 * for low rates is not supported either
1264 if (!display->hdmi.scdc.scrambling.low_rates &&
1265 display->max_tmds_clock <= 340000)
1272 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1273 * - The Source shall suspend transmission of the TMDS clock and data
1274 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1275 * from a 0 to a 1 or from a 1 to a 0
1276 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1277 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1278 * transmission of TMDS clock and data
1280 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1281 * helper should called right before enabling the TMDS Clock and Data in
1282 * the PHY configuration callback.
1284 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
1285 const struct drm_display_info *display)
1287 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1289 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1290 if (dw_hdmi_support_scdc(hdmi, display)) {
1291 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1292 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1294 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1297 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1299 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1301 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1302 HDMI_PHY_CONF0_PDZ_OFFSET,
1303 HDMI_PHY_CONF0_PDZ_MASK);
1306 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1308 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1309 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1310 HDMI_PHY_CONF0_ENTMDS_MASK);
1313 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1315 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1316 HDMI_PHY_CONF0_SVSRET_OFFSET,
1317 HDMI_PHY_CONF0_SVSRET_MASK);
1320 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1322 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1323 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1324 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1326 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1328 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1330 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1331 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1332 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1334 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1336 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1338 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1339 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1340 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1343 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1345 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1346 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1347 HDMI_PHY_CONF0_SELDIPIF_MASK);
1350 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1352 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1353 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1354 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1356 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1358 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1360 hdmi_phy_test_clear(hdmi, 1);
1361 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1362 hdmi_phy_test_clear(hdmi, 0);
1364 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1366 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1368 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1372 if (phy->gen == 1) {
1373 dw_hdmi_phy_enable_tmds(hdmi, 0);
1374 dw_hdmi_phy_enable_powerdown(hdmi, true);
1378 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1381 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1382 * to low power mode.
1384 for (i = 0; i < 5; ++i) {
1385 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1386 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1389 usleep_range(1000, 2000);
1392 if (val & HDMI_PHY_TX_PHY_LOCK)
1393 dev_warn(hdmi->dev, "PHY failed to power down\n");
1395 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1397 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1400 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1402 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1406 if (phy->gen == 1) {
1407 dw_hdmi_phy_enable_powerdown(hdmi, false);
1409 /* Toggle TMDS enable. */
1410 dw_hdmi_phy_enable_tmds(hdmi, 0);
1411 dw_hdmi_phy_enable_tmds(hdmi, 1);
1415 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1416 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1418 /* Wait for PHY PLL lock */
1419 for (i = 0; i < 5; ++i) {
1420 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1424 usleep_range(1000, 2000);
1428 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1432 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1437 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1438 * information the DWC MHL PHY has the same register layout and is thus also
1439 * supported by this function.
1441 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1442 const struct dw_hdmi_plat_data *pdata,
1443 unsigned long mpixelclock)
1445 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1446 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1447 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1449 /* TOFIX Will need 420 specific PHY configuration tables */
1451 /* PLL/MPLL Cfg - always match on final entry */
1452 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1453 if (mpixelclock <= mpll_config->mpixelclock)
1456 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1457 if (mpixelclock <= curr_ctrl->mpixelclock)
1460 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1461 if (mpixelclock <= phy_config->mpixelclock)
1464 if (mpll_config->mpixelclock == ~0UL ||
1465 curr_ctrl->mpixelclock == ~0UL ||
1466 phy_config->mpixelclock == ~0UL)
1469 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1470 HDMI_3D_TX_PHY_CPCE_CTRL);
1471 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1472 HDMI_3D_TX_PHY_GMPCTRL);
1473 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1474 HDMI_3D_TX_PHY_CURRCTRL);
1476 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1477 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1478 HDMI_3D_TX_PHY_MSM_CTRL);
1480 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1481 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1482 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1483 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1484 HDMI_3D_TX_PHY_VLEVCTRL);
1486 /* Override and disable clock termination. */
1487 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1488 HDMI_3D_TX_PHY_CKCALCTRL);
1493 static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1494 const struct drm_display_info *display)
1496 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1497 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1498 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1499 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1502 dw_hdmi_phy_power_off(hdmi);
1504 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1506 /* Leave low power consumption mode by asserting SVSRET. */
1507 if (phy->has_svsret)
1508 dw_hdmi_phy_enable_svsret(hdmi, 1);
1510 dw_hdmi_phy_reset(hdmi);
1512 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1514 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1516 /* Write to the PHY as configured by the platform */
1517 if (pdata->configure_phy)
1518 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1520 ret = phy->configure(hdmi, pdata, mpixelclock);
1522 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1527 /* Wait for resuming transmission of TMDS clock and data */
1528 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1531 return dw_hdmi_phy_power_on(hdmi);
1534 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1535 const struct drm_display_info *display,
1536 const struct drm_display_mode *mode)
1540 /* HDMI Phy spec says to do the phy initialization sequence twice */
1541 for (i = 0; i < 2; i++) {
1542 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1543 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1545 ret = hdmi_phy_configure(hdmi, display);
1553 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1555 dw_hdmi_phy_power_off(hdmi);
1558 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1561 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1562 connector_status_connected : connector_status_disconnected;
1564 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1566 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1567 bool force, bool disabled, bool rxsense)
1569 u8 old_mask = hdmi->phy_mask;
1571 if (force || disabled || !rxsense)
1572 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1574 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1576 if (old_mask != hdmi->phy_mask)
1577 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1579 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1581 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1584 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1585 * any pending interrupt.
1587 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1588 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1591 /* Enable cable hot plug irq. */
1592 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1594 /* Clear and unmute interrupts. */
1595 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1597 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1598 HDMI_IH_MUTE_PHY_STAT0);
1600 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1602 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1603 .init = dw_hdmi_phy_init,
1604 .disable = dw_hdmi_phy_disable,
1605 .read_hpd = dw_hdmi_phy_read_hpd,
1606 .update_hpd = dw_hdmi_phy_update_hpd,
1607 .setup_hpd = dw_hdmi_phy_setup_hpd,
1610 /* -----------------------------------------------------------------------------
1614 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1618 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1619 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1621 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1623 /* disable rx detect */
1624 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1625 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1627 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1629 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1630 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1633 static void hdmi_config_AVI(struct dw_hdmi *hdmi,
1634 const struct drm_display_mode *mode)
1636 struct hdmi_avi_infoframe frame;
1639 /* Initialise info frame from DRM mode */
1640 drm_hdmi_avi_infoframe_from_display_mode(&frame,
1641 &hdmi->connector, mode);
1643 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1644 drm_hdmi_avi_infoframe_quant_range(&frame, &hdmi->connector,
1646 hdmi->hdmi_data.rgb_limited_range ?
1647 HDMI_QUANTIZATION_RANGE_LIMITED :
1648 HDMI_QUANTIZATION_RANGE_FULL);
1650 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1651 frame.ycc_quantization_range =
1652 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1655 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1656 frame.colorspace = HDMI_COLORSPACE_YUV444;
1657 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1658 frame.colorspace = HDMI_COLORSPACE_YUV422;
1659 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1660 frame.colorspace = HDMI_COLORSPACE_YUV420;
1662 frame.colorspace = HDMI_COLORSPACE_RGB;
1664 /* Set up colorimetry */
1665 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1666 switch (hdmi->hdmi_data.enc_out_encoding) {
1667 case V4L2_YCBCR_ENC_601:
1668 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1669 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1671 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1672 frame.extended_colorimetry =
1673 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1675 case V4L2_YCBCR_ENC_709:
1676 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1677 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1679 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1680 frame.extended_colorimetry =
1681 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1683 default: /* Carries no data */
1684 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1685 frame.extended_colorimetry =
1686 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1690 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1691 frame.extended_colorimetry =
1692 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1696 * The Designware IP uses a different byte format from standard
1697 * AVI info frames, though generally the bits are in the correct
1702 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1703 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1704 * bit 6 rather than 4.
1706 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1707 if (frame.active_aspect & 15)
1708 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1709 if (frame.top_bar || frame.bottom_bar)
1710 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1711 if (frame.left_bar || frame.right_bar)
1712 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1713 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1715 /* AVI data byte 2 differences: none */
1716 val = ((frame.colorimetry & 0x3) << 6) |
1717 ((frame.picture_aspect & 0x3) << 4) |
1718 (frame.active_aspect & 0xf);
1719 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1721 /* AVI data byte 3 differences: none */
1722 val = ((frame.extended_colorimetry & 0x7) << 4) |
1723 ((frame.quantization_range & 0x3) << 2) |
1726 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1727 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1729 /* AVI data byte 4 differences: none */
1730 val = frame.video_code & 0x7f;
1731 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1733 /* AVI Data Byte 5- set up input and output pixel repetition */
1734 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1735 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1736 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1737 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1738 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1739 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1740 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1743 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1744 * ycc range in bits 2,3 rather than 6,7
1746 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1747 (frame.content_type & 0x3);
1748 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1750 /* AVI Data Bytes 6-13 */
1751 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1752 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1753 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1754 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1755 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1756 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1757 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1758 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1761 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1762 const struct drm_display_mode *mode)
1764 struct hdmi_vendor_infoframe frame;
1768 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1773 * Going into that statement does not means vendor infoframe
1774 * fails. It just informed us that vendor infoframe is not
1775 * needed for the selected mode. Only 4k or stereoscopic 3D
1776 * mode requires vendor infoframe. So just simply return.
1780 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1782 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1786 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1787 HDMI_FC_DATAUTO0_VSD_MASK);
1789 /* Set the length of HDMI vendor specific InfoFrame payload */
1790 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1792 /* Set 24bit IEEE Registration Identifier */
1793 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1794 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1795 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1797 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1798 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1799 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1801 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1802 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1804 /* Packet frame interpolation */
1805 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1807 /* Auto packets per frame and line spacing */
1808 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1810 /* Configures the Frame Composer On RDRB mode */
1811 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1812 HDMI_FC_DATAUTO0_VSD_MASK);
1815 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi)
1817 const struct drm_connector_state *conn_state = hdmi->connector.state;
1818 struct hdmi_drm_infoframe frame;
1823 if (!hdmi->plat_data->use_drm_infoframe)
1826 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
1827 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1829 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1833 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1835 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1839 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
1840 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
1842 for (i = 0; i < frame.length; i++)
1843 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
1845 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
1846 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
1847 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1850 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1851 const struct drm_display_info *display,
1852 const struct drm_display_mode *mode)
1855 const struct drm_hdmi_info *hdmi_info = &display->hdmi;
1856 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1857 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1858 unsigned int vdisplay, hdisplay;
1860 vmode->mpixelclock = mode->clock * 1000;
1862 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1864 vmode->mtmdsclock = vmode->mpixelclock;
1866 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1867 switch (hdmi_bus_fmt_color_depth(
1868 hdmi->hdmi_data.enc_out_bus_format)) {
1870 vmode->mtmdsclock = vmode->mpixelclock * 2;
1873 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
1876 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
1881 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1882 vmode->mtmdsclock /= 2;
1884 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
1886 /* Set up HDMI_FC_INVIDCONF */
1887 inv_val = (hdmi->hdmi_data.hdcp_enable ||
1888 (dw_hdmi_support_scdc(hdmi, display) &&
1889 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1890 hdmi_info->scdc.scrambling.low_rates)) ?
1891 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1892 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1894 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1895 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1896 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1898 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1899 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1900 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1902 inv_val |= (vmode->mdataenablepolarity ?
1903 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1904 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1906 if (hdmi->vic == 39)
1907 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1909 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1910 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1911 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1913 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1914 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1915 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1917 inv_val |= hdmi->sink_is_hdmi ?
1918 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1919 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1921 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1923 hdisplay = mode->hdisplay;
1924 hblank = mode->htotal - mode->hdisplay;
1925 h_de_hs = mode->hsync_start - mode->hdisplay;
1926 hsync_len = mode->hsync_end - mode->hsync_start;
1929 * When we're setting a YCbCr420 mode, we need
1930 * to adjust the horizontal timing to suit.
1932 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1939 vdisplay = mode->vdisplay;
1940 vblank = mode->vtotal - mode->vdisplay;
1941 v_de_vs = mode->vsync_start - mode->vdisplay;
1942 vsync_len = mode->vsync_end - mode->vsync_start;
1945 * When we're setting an interlaced mode, we need
1946 * to adjust the vertical timing to suit.
1948 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1955 /* Scrambling Control */
1956 if (dw_hdmi_support_scdc(hdmi, display)) {
1957 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1958 hdmi_info->scdc.scrambling.low_rates) {
1960 * HDMI2.0 Specifies the following procedure:
1961 * After the Source Device has determined that
1962 * SCDC_Present is set (=1), the Source Device should
1963 * write the accurate Version of the Source Device
1964 * to the Source Version field in the SCDCS.
1965 * Source Devices compliant shall set the
1966 * Source Version = 1.
1968 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
1970 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1971 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1973 /* Enabled Scrambling in the Sink */
1974 drm_scdc_set_scrambling(hdmi->ddc, 1);
1977 * To activate the scrambler feature, you must ensure
1978 * that the quasi-static configuration bit
1979 * fc_invidconf.HDCP_keepout is set at configuration
1980 * time, before the required mc_swrstzreq.tmdsswrst_req
1981 * reset request is issued.
1983 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1985 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1987 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1988 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1990 drm_scdc_set_scrambling(hdmi->ddc, 0);
1994 /* Set up horizontal active pixel width */
1995 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1996 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1998 /* Set up vertical active lines */
1999 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
2000 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
2002 /* Set up horizontal blanking pixel region width */
2003 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
2004 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
2006 /* Set up vertical blanking pixel region width */
2007 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
2009 /* Set up HSYNC active edge delay width (in pixel clks) */
2010 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
2011 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
2013 /* Set up VSYNC active edge delay (in lines) */
2014 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
2016 /* Set up HSYNC active pulse width (in pixel clks) */
2017 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
2018 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
2020 /* Set up VSYNC active edge delay (in lines) */
2021 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
2024 /* HDMI Initialization Step B.4 */
2025 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
2027 /* control period minimum duration */
2028 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
2029 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
2030 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
2032 /* Set to fill TMDS data channels */
2033 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
2034 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
2035 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2037 /* Enable pixel clock and tmds data path */
2038 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2039 HDMI_MC_CLKDIS_CSCCLK_DISABLE |
2040 HDMI_MC_CLKDIS_AUDCLK_DISABLE |
2041 HDMI_MC_CLKDIS_PREPCLK_DISABLE |
2042 HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2043 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2044 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2046 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2047 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2049 /* Enable csc path */
2050 if (is_csc_needed(hdmi)) {
2051 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2052 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2054 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2057 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2058 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2060 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2065 /* Workaround to clear the overflow condition */
2066 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2073 * Under some circumstances the Frame Composer arithmetic unit can miss
2074 * an FC register write due to being busy processing the previous one.
2075 * The issue can be worked around by issuing a TMDS software reset and
2076 * then write one of the FC registers several times.
2078 * The number of iterations matters and depends on the HDMI TX revision
2079 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
2080 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
2081 * as needing the workaround, with 4 iterations for v1.30a and 1
2082 * iteration for others.
2083 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
2084 * the workaround with a single iteration.
2085 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
2086 * been identified as needing the workaround with a single iteration.
2089 switch (hdmi->version) {
2105 /* TMDS software reset */
2106 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2108 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2109 for (i = 0; i < count; i++)
2110 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2113 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2115 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
2116 HDMI_IH_MUTE_FC_STAT2);
2119 static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2120 const struct drm_display_mode *mode)
2122 struct drm_connector *connector = &hdmi->connector;
2125 hdmi_disable_overflow_interrupts(hdmi);
2127 hdmi->vic = drm_match_cea_mode(mode);
2130 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2132 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2135 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2136 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2137 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2138 (hdmi->vic == 17) || (hdmi->vic == 18))
2139 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2141 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2143 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2144 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2146 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
2147 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2149 /* TOFIX: Get input encoding from plat data or fallback to none */
2150 if (hdmi->plat_data->input_bus_encoding)
2151 hdmi->hdmi_data.enc_in_encoding =
2152 hdmi->plat_data->input_bus_encoding;
2154 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2156 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
2157 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2159 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2160 drm_default_rgb_quant_range(mode) ==
2161 HDMI_QUANTIZATION_RANGE_LIMITED;
2163 hdmi->hdmi_data.pix_repet_factor = 0;
2164 hdmi->hdmi_data.hdcp_enable = 0;
2165 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2167 /* HDMI Initialization Step B.1 */
2168 hdmi_av_composer(hdmi, &connector->display_info, mode);
2170 /* HDMI Initializateion Step B.2 */
2171 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2172 &connector->display_info,
2173 &hdmi->previous_mode);
2176 hdmi->phy.enabled = true;
2178 /* HDMI Initialization Step B.3 */
2179 dw_hdmi_enable_video_path(hdmi);
2181 if (hdmi->sink_has_audio) {
2182 dev_dbg(hdmi->dev, "sink has audio support\n");
2184 /* HDMI Initialization Step E - Configure audio */
2185 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2186 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2189 /* not for DVI mode */
2190 if (hdmi->sink_is_hdmi) {
2191 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2193 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2194 hdmi_config_AVI(hdmi, mode);
2195 hdmi_config_vendor_specific_infoframe(hdmi, mode);
2196 hdmi_config_drm_infoframe(hdmi);
2198 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2201 hdmi_video_packetize(hdmi);
2202 hdmi_video_csc(hdmi);
2203 hdmi_video_sample(hdmi);
2204 hdmi_tx_hdcp_config(hdmi);
2206 dw_hdmi_clear_overflow(hdmi);
2211 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2216 * Boot up defaults are:
2217 * HDMI_IH_MUTE = 0x03 (disabled)
2218 * HDMI_IH_MUTE_* = 0x00 (enabled)
2220 * Disable top level interrupt bits in HDMI block
2222 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2223 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2224 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2226 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2228 /* by default mask all interrupts */
2229 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2230 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2231 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2232 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2233 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2234 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2235 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2236 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2237 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2238 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2239 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2240 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2241 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2242 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2244 /* Disable interrupts in the IH_MUTE_* registers */
2245 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2246 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2247 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2248 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2249 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2250 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2251 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2252 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2253 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2254 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2256 /* Enable top level interrupt bits in HDMI block */
2257 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2258 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2259 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2262 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2264 hdmi->bridge_is_on = true;
2265 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
2268 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2270 if (hdmi->phy.enabled) {
2271 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2272 hdmi->phy.enabled = false;
2275 hdmi->bridge_is_on = false;
2278 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2280 int force = hdmi->force;
2282 if (hdmi->disabled) {
2283 force = DRM_FORCE_OFF;
2284 } else if (force == DRM_FORCE_UNSPECIFIED) {
2286 force = DRM_FORCE_ON;
2288 force = DRM_FORCE_OFF;
2291 if (force == DRM_FORCE_OFF) {
2292 if (hdmi->bridge_is_on)
2293 dw_hdmi_poweroff(hdmi);
2295 if (!hdmi->bridge_is_on)
2296 dw_hdmi_poweron(hdmi);
2301 * Adjust the detection of RXSENSE according to whether we have a forced
2302 * connection mode enabled, or whether we have been disabled. There is
2303 * no point processing RXSENSE interrupts if we have a forced connection
2304 * state, or DRM has us disabled.
2306 * We also disable rxsense interrupts when we think we're disconnected
2307 * to avoid floating TDMS signals giving false rxsense interrupts.
2309 * Note: we still need to listen for HPD interrupts even when DRM has us
2310 * disabled so that we can detect a connect event.
2312 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2314 if (hdmi->phy.ops->update_hpd)
2315 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2316 hdmi->force, hdmi->disabled,
2320 static enum drm_connector_status
2321 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2323 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2325 enum drm_connector_status result;
2327 mutex_lock(&hdmi->mutex);
2328 hdmi->force = DRM_FORCE_UNSPECIFIED;
2329 dw_hdmi_update_power(hdmi);
2330 dw_hdmi_update_phy_mask(hdmi);
2331 mutex_unlock(&hdmi->mutex);
2333 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2335 mutex_lock(&hdmi->mutex);
2336 if (result != hdmi->last_connector_result) {
2337 dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2338 handle_plugged_change(hdmi,
2339 result == connector_status_connected);
2340 hdmi->last_connector_result = result;
2342 mutex_unlock(&hdmi->mutex);
2347 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2349 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2357 edid = drm_get_edid(connector, hdmi->ddc);
2359 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2360 edid->width_cm, edid->height_cm);
2362 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2363 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2364 drm_connector_update_edid_property(connector, edid);
2365 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2366 ret = drm_add_edid_modes(connector, edid);
2369 dev_dbg(hdmi->dev, "failed to get edid\n");
2375 static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
2376 const struct drm_connector_state *new_state)
2378 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
2379 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
2381 if (!old_blob || !new_blob)
2382 return old_blob == new_blob;
2384 if (old_blob->length != new_blob->length)
2387 return !memcmp(old_blob->data, new_blob->data, old_blob->length);
2390 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
2391 struct drm_atomic_state *state)
2393 struct drm_connector_state *old_state =
2394 drm_atomic_get_old_connector_state(state, connector);
2395 struct drm_connector_state *new_state =
2396 drm_atomic_get_new_connector_state(state, connector);
2397 struct drm_crtc *crtc = new_state->crtc;
2398 struct drm_crtc_state *crtc_state;
2403 if (!hdr_metadata_equal(old_state, new_state)) {
2404 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2405 if (IS_ERR(crtc_state))
2406 return PTR_ERR(crtc_state);
2408 crtc_state->mode_changed = true;
2414 static void dw_hdmi_connector_force(struct drm_connector *connector)
2416 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2419 mutex_lock(&hdmi->mutex);
2420 hdmi->force = connector->force;
2421 dw_hdmi_update_power(hdmi);
2422 dw_hdmi_update_phy_mask(hdmi);
2423 mutex_unlock(&hdmi->mutex);
2426 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2427 .fill_modes = drm_helper_probe_single_connector_modes,
2428 .detect = dw_hdmi_connector_detect,
2429 .destroy = drm_connector_cleanup,
2430 .force = dw_hdmi_connector_force,
2431 .reset = drm_atomic_helper_connector_reset,
2432 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2433 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2436 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2437 .get_modes = dw_hdmi_connector_get_modes,
2438 .atomic_check = dw_hdmi_connector_atomic_check,
2442 * Possible output formats :
2443 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2444 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2445 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2446 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2447 * - MEDIA_BUS_FMT_YUV16_1X48,
2448 * - MEDIA_BUS_FMT_RGB161616_1X48,
2449 * - MEDIA_BUS_FMT_UYVY12_1X24,
2450 * - MEDIA_BUS_FMT_YUV12_1X36,
2451 * - MEDIA_BUS_FMT_RGB121212_1X36,
2452 * - MEDIA_BUS_FMT_UYVY10_1X20,
2453 * - MEDIA_BUS_FMT_YUV10_1X30,
2454 * - MEDIA_BUS_FMT_RGB101010_1X30,
2455 * - MEDIA_BUS_FMT_UYVY8_1X16,
2456 * - MEDIA_BUS_FMT_YUV8_1X24,
2457 * - MEDIA_BUS_FMT_RGB888_1X24,
2460 /* Can return a maximum of 11 possible output formats for a mode/connector */
2461 #define MAX_OUTPUT_SEL_FORMATS 11
2463 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
2464 struct drm_bridge_state *bridge_state,
2465 struct drm_crtc_state *crtc_state,
2466 struct drm_connector_state *conn_state,
2467 unsigned int *num_output_fmts)
2469 struct drm_connector *conn = conn_state->connector;
2470 struct drm_display_info *info = &conn->display_info;
2471 struct drm_display_mode *mode = &crtc_state->mode;
2472 u8 max_bpc = conn_state->max_requested_bpc;
2473 bool is_hdmi2_sink = info->hdmi.scdc.supported ||
2474 (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
2478 *num_output_fmts = 0;
2480 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
2485 /* If dw-hdmi is the only bridge, avoid negociating with ourselves */
2486 if (list_is_singular(&bridge->encoder->bridge_chain)) {
2487 *num_output_fmts = 1;
2488 output_fmts[0] = MEDIA_BUS_FMT_FIXED;
2494 * If the current mode enforces 4:2:0, force the output but format
2495 * to 4:2:0 and do not add the YUV422/444/RGB formats
2497 if (conn->ycbcr_420_allowed &&
2498 (drm_mode_is_420_only(info, mode) ||
2499 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
2501 /* Order bus formats from 16bit to 8bit if supported */
2502 if (max_bpc >= 16 && info->bpc == 16 &&
2503 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
2504 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
2506 if (max_bpc >= 12 && info->bpc >= 12 &&
2507 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
2508 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
2510 if (max_bpc >= 10 && info->bpc >= 10 &&
2511 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
2512 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
2514 /* Default 8bit fallback */
2515 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
2517 *num_output_fmts = i;
2523 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
2524 * if supported. In any case the default RGB888 format is added
2527 if (max_bpc >= 16 && info->bpc == 16) {
2528 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2529 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2531 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2534 if (max_bpc >= 12 && info->bpc >= 12) {
2535 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2536 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2538 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2539 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2541 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2544 if (max_bpc >= 10 && info->bpc >= 10) {
2545 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2546 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2548 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2549 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2551 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2554 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
2555 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2557 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
2558 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2560 /* Default 8bit RGB fallback */
2561 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2563 *num_output_fmts = i;
2569 * Possible input formats :
2570 * - MEDIA_BUS_FMT_RGB888_1X24
2571 * - MEDIA_BUS_FMT_YUV8_1X24
2572 * - MEDIA_BUS_FMT_UYVY8_1X16
2573 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2574 * - MEDIA_BUS_FMT_RGB101010_1X30
2575 * - MEDIA_BUS_FMT_YUV10_1X30
2576 * - MEDIA_BUS_FMT_UYVY10_1X20
2577 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2578 * - MEDIA_BUS_FMT_RGB121212_1X36
2579 * - MEDIA_BUS_FMT_YUV12_1X36
2580 * - MEDIA_BUS_FMT_UYVY12_1X24
2581 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2582 * - MEDIA_BUS_FMT_RGB161616_1X48
2583 * - MEDIA_BUS_FMT_YUV16_1X48
2584 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2587 /* Can return a maximum of 3 possible input formats for an output format */
2588 #define MAX_INPUT_SEL_FORMATS 3
2590 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
2591 struct drm_bridge_state *bridge_state,
2592 struct drm_crtc_state *crtc_state,
2593 struct drm_connector_state *conn_state,
2595 unsigned int *num_input_fmts)
2600 *num_input_fmts = 0;
2602 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
2607 switch (output_fmt) {
2608 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
2609 case MEDIA_BUS_FMT_FIXED:
2610 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2613 case MEDIA_BUS_FMT_RGB888_1X24:
2614 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2615 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2616 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2618 case MEDIA_BUS_FMT_YUV8_1X24:
2619 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2620 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2621 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2623 case MEDIA_BUS_FMT_UYVY8_1X16:
2624 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2625 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2626 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2630 case MEDIA_BUS_FMT_RGB101010_1X30:
2631 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2632 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2633 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2635 case MEDIA_BUS_FMT_YUV10_1X30:
2636 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2637 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2638 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2640 case MEDIA_BUS_FMT_UYVY10_1X20:
2641 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2642 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2643 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2647 case MEDIA_BUS_FMT_RGB121212_1X36:
2648 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2649 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2650 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2652 case MEDIA_BUS_FMT_YUV12_1X36:
2653 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2654 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2655 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2657 case MEDIA_BUS_FMT_UYVY12_1X24:
2658 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2659 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2660 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2664 case MEDIA_BUS_FMT_RGB161616_1X48:
2665 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2666 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2668 case MEDIA_BUS_FMT_YUV16_1X48:
2669 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2670 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2674 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
2675 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2676 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
2677 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
2678 input_fmts[i++] = output_fmt;
2682 *num_input_fmts = i;
2684 if (*num_input_fmts == 0) {
2692 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
2693 struct drm_bridge_state *bridge_state,
2694 struct drm_crtc_state *crtc_state,
2695 struct drm_connector_state *conn_state)
2697 struct dw_hdmi *hdmi = bridge->driver_private;
2699 hdmi->hdmi_data.enc_out_bus_format =
2700 bridge_state->output_bus_cfg.format;
2702 hdmi->hdmi_data.enc_in_bus_format =
2703 bridge_state->input_bus_cfg.format;
2705 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
2706 bridge_state->input_bus_cfg.format,
2707 bridge_state->output_bus_cfg.format);
2712 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
2713 enum drm_bridge_attach_flags flags)
2715 struct dw_hdmi *hdmi = bridge->driver_private;
2716 struct drm_encoder *encoder = bridge->encoder;
2717 struct drm_connector *connector = &hdmi->connector;
2718 struct cec_connector_info conn_info;
2719 struct cec_notifier *notifier;
2721 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
2722 DRM_ERROR("Fix bridge driver to make connector optional!");
2726 connector->interlace_allowed = 1;
2727 connector->polled = DRM_CONNECTOR_POLL_HPD;
2729 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2731 drm_connector_init_with_ddc(bridge->dev, connector,
2732 &dw_hdmi_connector_funcs,
2733 DRM_MODE_CONNECTOR_HDMIA,
2737 * drm_connector_attach_max_bpc_property() requires the
2738 * connector to have a state.
2740 drm_atomic_helper_connector_reset(connector);
2742 drm_connector_attach_max_bpc_property(connector, 8, 16);
2744 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2745 drm_object_attach_property(&connector->base,
2746 connector->dev->mode_config.hdr_output_metadata_property, 0);
2748 drm_connector_attach_encoder(connector, encoder);
2750 cec_fill_conn_info_from_drm(&conn_info, connector);
2752 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2756 mutex_lock(&hdmi->cec_notifier_mutex);
2757 hdmi->cec_notifier = notifier;
2758 mutex_unlock(&hdmi->cec_notifier_mutex);
2763 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2765 struct dw_hdmi *hdmi = bridge->driver_private;
2767 mutex_lock(&hdmi->cec_notifier_mutex);
2768 cec_notifier_conn_unregister(hdmi->cec_notifier);
2769 hdmi->cec_notifier = NULL;
2770 mutex_unlock(&hdmi->cec_notifier_mutex);
2773 static enum drm_mode_status
2774 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2775 const struct drm_display_info *info,
2776 const struct drm_display_mode *mode)
2778 struct dw_hdmi *hdmi = bridge->driver_private;
2779 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2780 enum drm_mode_status mode_status = MODE_OK;
2782 /* We don't support double-clocked modes */
2783 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2786 if (pdata->mode_valid)
2787 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
2793 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2794 const struct drm_display_mode *orig_mode,
2795 const struct drm_display_mode *mode)
2797 struct dw_hdmi *hdmi = bridge->driver_private;
2799 mutex_lock(&hdmi->mutex);
2801 /* Store the display mode for plugin/DKMS poweron events */
2802 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2804 mutex_unlock(&hdmi->mutex);
2807 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2809 struct dw_hdmi *hdmi = bridge->driver_private;
2811 mutex_lock(&hdmi->mutex);
2812 hdmi->disabled = true;
2813 dw_hdmi_update_power(hdmi);
2814 dw_hdmi_update_phy_mask(hdmi);
2815 mutex_unlock(&hdmi->mutex);
2818 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2820 struct dw_hdmi *hdmi = bridge->driver_private;
2822 mutex_lock(&hdmi->mutex);
2823 hdmi->disabled = false;
2824 dw_hdmi_update_power(hdmi);
2825 dw_hdmi_update_phy_mask(hdmi);
2826 mutex_unlock(&hdmi->mutex);
2829 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2830 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2831 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2832 .atomic_reset = drm_atomic_helper_bridge_reset,
2833 .attach = dw_hdmi_bridge_attach,
2834 .detach = dw_hdmi_bridge_detach,
2835 .atomic_check = dw_hdmi_bridge_atomic_check,
2836 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
2837 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
2838 .enable = dw_hdmi_bridge_enable,
2839 .disable = dw_hdmi_bridge_disable,
2840 .mode_set = dw_hdmi_bridge_mode_set,
2841 .mode_valid = dw_hdmi_bridge_mode_valid,
2844 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2846 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2849 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2853 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2857 complete(&i2c->cmp);
2862 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2864 struct dw_hdmi *hdmi = dev_id;
2866 irqreturn_t ret = IRQ_NONE;
2869 ret = dw_hdmi_i2c_irq(hdmi);
2871 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2873 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2874 return IRQ_WAKE_THREAD;
2880 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2882 mutex_lock(&hdmi->mutex);
2886 * If the RX sense status indicates we're disconnected,
2887 * clear the software rxsense status.
2890 hdmi->rxsense = false;
2893 * Only set the software rxsense status when both
2894 * rxsense and hpd indicates we're connected.
2895 * This avoids what seems to be bad behaviour in
2896 * at least iMX6S versions of the phy.
2899 hdmi->rxsense = true;
2901 dw_hdmi_update_power(hdmi);
2902 dw_hdmi_update_phy_mask(hdmi);
2904 mutex_unlock(&hdmi->mutex);
2906 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2908 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2910 struct dw_hdmi *hdmi = dev_id;
2911 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2913 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2914 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2915 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2918 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2919 phy_pol_mask |= HDMI_PHY_HPD;
2920 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2921 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2922 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2923 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2924 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2925 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2926 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2927 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2930 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2933 * RX sense tells us whether the TDMS transmitters are detecting
2934 * load - in other words, there's something listening on the
2935 * other end of the link. Use this to decide whether we should
2936 * power on the phy as HPD may be toggled by the sink to merely
2937 * ask the source to re-read the EDID.
2940 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2941 dw_hdmi_setup_rx_sense(hdmi,
2942 phy_stat & HDMI_PHY_HPD,
2943 phy_stat & HDMI_PHY_RX_SENSE);
2945 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
2946 mutex_lock(&hdmi->cec_notifier_mutex);
2947 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
2948 mutex_unlock(&hdmi->cec_notifier_mutex);
2952 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2953 dev_dbg(hdmi->dev, "EVENT=%s\n",
2954 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2955 if (hdmi->bridge.dev)
2956 drm_helper_hpd_irq_event(hdmi->bridge.dev);
2959 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2960 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2961 HDMI_IH_MUTE_PHY_STAT0);
2966 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2968 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2969 .name = "DWC HDMI TX PHY",
2972 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2973 .name = "DWC MHL PHY + HEAC PHY",
2976 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2978 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2979 .name = "DWC MHL PHY",
2982 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2984 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2985 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2987 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2989 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2990 .name = "DWC HDMI 3D TX PHY",
2992 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2994 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2995 .name = "DWC HDMI 2.0 TX PHY",
2998 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3000 .type = DW_HDMI_PHY_VENDOR_PHY,
3001 .name = "Vendor PHY",
3005 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
3010 phy_type = hdmi->plat_data->phy_force_vendor ?
3011 DW_HDMI_PHY_VENDOR_PHY :
3012 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
3014 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
3015 /* Vendor PHYs require support from the glue layer. */
3016 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3018 "Vendor HDMI PHY not supported by glue layer\n");
3022 hdmi->phy.ops = hdmi->plat_data->phy_ops;
3023 hdmi->phy.data = hdmi->plat_data->phy_data;
3024 hdmi->phy.name = hdmi->plat_data->phy_name;
3028 /* Synopsys PHYs are handled internally. */
3029 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
3030 if (dw_hdmi_phys[i].type == phy_type) {
3031 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3032 hdmi->phy.name = dw_hdmi_phys[i].name;
3033 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3035 if (!dw_hdmi_phys[i].configure &&
3036 !hdmi->plat_data->configure_phy) {
3037 dev_err(hdmi->dev, "%s requires platform support\n",
3046 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3050 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
3052 mutex_lock(&hdmi->mutex);
3053 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
3054 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3055 mutex_unlock(&hdmi->mutex);
3058 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
3060 mutex_lock(&hdmi->mutex);
3061 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
3062 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3063 mutex_unlock(&hdmi->mutex);
3066 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
3067 .write = hdmi_writeb,
3069 .enable = dw_hdmi_cec_enable,
3070 .disable = dw_hdmi_cec_disable,
3073 static const struct regmap_config hdmi_regmap_8bit_config = {
3077 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
3080 static const struct regmap_config hdmi_regmap_32bit_config = {
3084 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
3087 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
3089 initialize_hdmi_ih_mutes(hdmi);
3092 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
3093 * Even if we are using a separate i2c adapter doing this doesn't
3096 dw_hdmi_i2c_init(hdmi);
3098 if (hdmi->phy.ops->setup_hpd)
3099 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
3102 static struct dw_hdmi *
3103 __dw_hdmi_probe(struct platform_device *pdev,
3104 const struct dw_hdmi_plat_data *plat_data)
3106 struct device *dev = &pdev->dev;
3107 struct device_node *np = dev->of_node;
3108 struct platform_device_info pdevinfo;
3109 struct device_node *ddc_node;
3110 struct dw_hdmi_cec_data cec;
3111 struct dw_hdmi *hdmi;
3112 struct resource *iores = NULL;
3121 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
3123 return ERR_PTR(-ENOMEM);
3125 hdmi->plat_data = plat_data;
3127 hdmi->sample_rate = 48000;
3128 hdmi->disabled = true;
3129 hdmi->rxsense = true;
3130 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
3131 hdmi->mc_clkdis = 0x7f;
3132 hdmi->last_connector_result = connector_status_disconnected;
3134 mutex_init(&hdmi->mutex);
3135 mutex_init(&hdmi->audio_mutex);
3136 mutex_init(&hdmi->cec_notifier_mutex);
3137 spin_lock_init(&hdmi->audio_lock);
3139 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
3141 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
3142 of_node_put(ddc_node);
3144 dev_dbg(hdmi->dev, "failed to read ddc node\n");
3145 return ERR_PTR(-EPROBE_DEFER);
3149 dev_dbg(hdmi->dev, "no ddc property found\n");
3152 if (!plat_data->regm) {
3153 const struct regmap_config *reg_config;
3155 of_property_read_u32(np, "reg-io-width", &val);
3158 reg_config = &hdmi_regmap_32bit_config;
3159 hdmi->reg_shift = 2;
3162 reg_config = &hdmi_regmap_8bit_config;
3165 dev_err(dev, "reg-io-width must be 1 or 4\n");
3166 return ERR_PTR(-EINVAL);
3169 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3170 hdmi->regs = devm_ioremap_resource(dev, iores);
3171 if (IS_ERR(hdmi->regs)) {
3172 ret = PTR_ERR(hdmi->regs);
3176 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
3177 if (IS_ERR(hdmi->regm)) {
3178 dev_err(dev, "Failed to configure regmap\n");
3179 ret = PTR_ERR(hdmi->regm);
3183 hdmi->regm = plat_data->regm;
3186 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
3187 if (IS_ERR(hdmi->isfr_clk)) {
3188 ret = PTR_ERR(hdmi->isfr_clk);
3189 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3193 ret = clk_prepare_enable(hdmi->isfr_clk);
3195 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
3199 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
3200 if (IS_ERR(hdmi->iahb_clk)) {
3201 ret = PTR_ERR(hdmi->iahb_clk);
3202 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3206 ret = clk_prepare_enable(hdmi->iahb_clk);
3208 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
3212 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
3213 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
3214 hdmi->cec_clk = NULL;
3215 } else if (IS_ERR(hdmi->cec_clk)) {
3216 ret = PTR_ERR(hdmi->cec_clk);
3217 if (ret != -EPROBE_DEFER)
3218 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3221 hdmi->cec_clk = NULL;
3224 ret = clk_prepare_enable(hdmi->cec_clk);
3226 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
3232 /* Product and revision IDs */
3233 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
3234 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
3235 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
3236 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
3238 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
3239 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
3240 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3241 hdmi->version, prod_id0, prod_id1);
3246 ret = dw_hdmi_detect_phy(hdmi);
3250 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3251 hdmi->version >> 12, hdmi->version & 0xfff,
3252 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
3255 dw_hdmi_init_hw(hdmi);
3257 irq = platform_get_irq(pdev, 0);
3263 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
3264 dw_hdmi_irq, IRQF_SHARED,
3265 dev_name(dev), hdmi);
3270 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
3271 * N and cts values before enabling phy
3273 hdmi_init_clk_regenerator(hdmi);
3275 /* If DDC bus is not specified, try to register HDMI I2C bus */
3277 /* Look for (optional) stuff related to unwedging */
3278 hdmi->pinctrl = devm_pinctrl_get(dev);
3279 if (!IS_ERR(hdmi->pinctrl)) {
3280 hdmi->unwedge_state =
3281 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
3282 hdmi->default_state =
3283 pinctrl_lookup_state(hdmi->pinctrl, "default");
3285 if (IS_ERR(hdmi->default_state) ||
3286 IS_ERR(hdmi->unwedge_state)) {
3287 if (!IS_ERR(hdmi->unwedge_state))
3289 "Unwedge requires default pinctrl\n");
3290 hdmi->default_state = NULL;
3291 hdmi->unwedge_state = NULL;
3295 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
3296 if (IS_ERR(hdmi->ddc))
3300 hdmi->bridge.driver_private = hdmi;
3301 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
3303 hdmi->bridge.of_node = pdev->dev.of_node;
3306 if (hdmi->version >= 0x200a)
3307 hdmi->connector.ycbcr_420_allowed =
3308 hdmi->plat_data->ycbcr_420_allowed;
3310 hdmi->connector.ycbcr_420_allowed = false;
3312 memset(&pdevinfo, 0, sizeof(pdevinfo));
3313 pdevinfo.parent = dev;
3314 pdevinfo.id = PLATFORM_DEVID_AUTO;
3316 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
3317 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
3319 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
3320 struct dw_hdmi_audio_data audio;
3322 audio.phys = iores->start;
3323 audio.base = hdmi->regs;
3326 audio.eld = hdmi->connector.eld;
3327 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
3328 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
3330 pdevinfo.name = "dw-hdmi-ahb-audio";
3331 pdevinfo.data = &audio;
3332 pdevinfo.size_data = sizeof(audio);
3333 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3334 hdmi->audio = platform_device_register_full(&pdevinfo);
3335 } else if (config0 & HDMI_CONFIG0_I2S) {
3336 struct dw_hdmi_i2s_audio_data audio;
3339 audio.eld = hdmi->connector.eld;
3340 audio.write = hdmi_writeb;
3341 audio.read = hdmi_readb;
3342 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
3343 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
3345 pdevinfo.name = "dw-hdmi-i2s-audio";
3346 pdevinfo.data = &audio;
3347 pdevinfo.size_data = sizeof(audio);
3348 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3349 hdmi->audio = platform_device_register_full(&pdevinfo);
3352 if (config0 & HDMI_CONFIG0_CEC) {
3354 cec.ops = &dw_hdmi_cec_ops;
3357 pdevinfo.name = "dw-hdmi-cec";
3358 pdevinfo.data = &cec;
3359 pdevinfo.size_data = sizeof(cec);
3360 pdevinfo.dma_mask = 0;
3362 hdmi->cec = platform_device_register_full(&pdevinfo);
3369 i2c_del_adapter(&hdmi->i2c->adap);
3373 clk_disable_unprepare(hdmi->iahb_clk);
3375 clk_disable_unprepare(hdmi->cec_clk);
3377 clk_disable_unprepare(hdmi->isfr_clk);
3379 i2c_put_adapter(hdmi->ddc);
3381 return ERR_PTR(ret);
3384 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
3386 if (hdmi->audio && !IS_ERR(hdmi->audio))
3387 platform_device_unregister(hdmi->audio);
3388 if (!IS_ERR(hdmi->cec))
3389 platform_device_unregister(hdmi->cec);
3391 /* Disable all interrupts */
3392 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3394 clk_disable_unprepare(hdmi->iahb_clk);
3395 clk_disable_unprepare(hdmi->isfr_clk);
3397 clk_disable_unprepare(hdmi->cec_clk);
3400 i2c_del_adapter(&hdmi->i2c->adap);
3402 i2c_put_adapter(hdmi->ddc);
3405 /* -----------------------------------------------------------------------------
3406 * Probe/remove API, used from platforms based on the DRM bridge API.
3408 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
3409 const struct dw_hdmi_plat_data *plat_data)
3411 struct dw_hdmi *hdmi;
3413 hdmi = __dw_hdmi_probe(pdev, plat_data);
3417 drm_bridge_add(&hdmi->bridge);
3421 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
3423 void dw_hdmi_remove(struct dw_hdmi *hdmi)
3425 drm_bridge_remove(&hdmi->bridge);
3427 __dw_hdmi_remove(hdmi);
3429 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
3431 /* -----------------------------------------------------------------------------
3432 * Bind/unbind API, used from platforms based on the component framework.
3434 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
3435 struct drm_encoder *encoder,
3436 const struct dw_hdmi_plat_data *plat_data)
3438 struct dw_hdmi *hdmi;
3441 hdmi = __dw_hdmi_probe(pdev, plat_data);
3445 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
3447 dw_hdmi_remove(hdmi);
3448 DRM_ERROR("Failed to initialize bridge with drm\n");
3449 return ERR_PTR(ret);
3454 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
3456 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
3458 __dw_hdmi_remove(hdmi);
3460 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
3462 void dw_hdmi_resume(struct dw_hdmi *hdmi)
3464 dw_hdmi_init_hw(hdmi);
3466 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
3468 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3469 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3470 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3471 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
3472 MODULE_DESCRIPTION("DW HDMI transmitter driver");
3473 MODULE_LICENSE("GPL");
3474 MODULE_ALIAS("platform:dw-hdmi");