drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3 * Analogix DP (Display Port) core interface driver.
   4 *
   5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   6 * Author: Jingoo Han <jg1.han@samsung.com>
   7 */
   8
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/err.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <drm/bridge/analogix_dp.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_crtc.h>
  24 #include <drm/drm_device.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drm_print.h>
  27 #include <drm/drm_probe_helper.h>
  28
  29 #include "analogix_dp_core.h"
  30 #include "analogix_dp_reg.h"
  31
  32 #define to_dp(nm)       container_of(nm, struct analogix_dp_device, nm)
  33
  34 static const bool verify_fast_training;
  35
  36 struct bridge_init {
  37         struct i2c_client *client;
  38         struct device_node *node;
  39 };
  40
  41 static int analogix_dp_init_dp(struct analogix_dp_device *dp)
  42 {
  43         int ret;
  44
  45         analogix_dp_reset(dp);
  46
  47         analogix_dp_swreset(dp);
  48
  49         analogix_dp_init_analog_param(dp);
  50         analogix_dp_init_interrupt(dp);
  51
  52         /* SW defined function Normal operation */
  53         analogix_dp_enable_sw_function(dp);
  54
  55         analogix_dp_config_interrupt(dp);
  56         ret = analogix_dp_init_analog_func(dp);
  57         if (ret)
  58                 return ret;
  59
  60         analogix_dp_init_hpd(dp);
  61         analogix_dp_init_aux(dp);
  62         return 0;
  63 }
  64
  65 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  66 {
  67         int timeout_loop = 0;
  68
  69         while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  70                 if (analogix_dp_get_plug_in_status(dp) == 0)
  71                         return 0;
  72
  73                 timeout_loop++;
  74                 usleep_range(1000, 1100);
  75         }
  76
  77         /*
  78          * Some edp screen do not have hpd signal, so we can't just
  79          * return failed when hpd plug in detect failed, DT property
  80          * "force-hpd" would indicate whether driver need this.
  81          */
  82         if (!dp->force_hpd)
  83                 return -ETIMEDOUT;
  84
  85         /*
  86          * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  87          * will not work, so we need to give a force hpd action to
  88          * set HPD_STATUS manually.
  89          */
  90         dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  91
  92         analogix_dp_force_hpd(dp);
  93
  94         if (analogix_dp_get_plug_in_status(dp) != 0) {
  95                 dev_err(dp->dev, "failed to get hpd plug in status\n");
  96                 return -EINVAL;
  97         }
  98
  99         dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
 100
 101         return 0;
 102 }
 103
 104 int analogix_dp_psr_enabled(struct analogix_dp_device *dp)
 105 {
 106
 107         return dp->psr_enable;
 108 }
 109 EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled);
 110
 111 int analogix_dp_enable_psr(struct analogix_dp_device *dp)
 112 {
 113         struct dp_sdp psr_vsc;
 114
 115         if (!dp->psr_enable)
 116                 return 0;
 117
 118         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 119         memset(&psr_vsc, 0, sizeof(psr_vsc));
 120         psr_vsc.sdp_header.HB0 = 0;
 121         psr_vsc.sdp_header.HB1 = 0x7;
 122         psr_vsc.sdp_header.HB2 = 0x2;
 123         psr_vsc.sdp_header.HB3 = 0x8;
 124
 125         psr_vsc.db[0] = 0;
 126         psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
 127
 128         return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
 129 }
 130 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
 131
 132 int analogix_dp_disable_psr(struct analogix_dp_device *dp)
 133 {
 134         struct dp_sdp psr_vsc;
 135         int ret;
 136
 137         if (!dp->psr_enable)
 138                 return 0;
 139
 140         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 141         memset(&psr_vsc, 0, sizeof(psr_vsc));
 142         psr_vsc.sdp_header.HB0 = 0;
 143         psr_vsc.sdp_header.HB1 = 0x7;
 144         psr_vsc.sdp_header.HB2 = 0x2;
 145         psr_vsc.sdp_header.HB3 = 0x8;
 146
 147         psr_vsc.db[0] = 0;
 148         psr_vsc.db[1] = 0;
 149
 150         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 151         if (ret != 1) {
 152                 dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret);
 153                 return ret;
 154         }
 155
 156         return analogix_dp_send_psr_spd(dp, &psr_vsc, false);
 157 }
 158 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
 159
 160 static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
 161 {
 162         unsigned char psr_version;
 163         int ret;
 164
 165         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
 166         if (ret != 1) {
 167                 dev_err(dp->dev, "failed to get PSR version, disable it\n");
 168                 return ret;
 169         }
 170
 171         dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
 172
 173         dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
 174
 175         return 0;
 176 }
 177
 178 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
 179 {
 180         unsigned char psr_en;
 181         int ret;
 182
 183         /* Disable psr function */
 184         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
 185         if (ret != 1) {
 186                 dev_err(dp->dev, "failed to get psr config\n");
 187                 goto end;
 188         }
 189
 190         psr_en &= ~DP_PSR_ENABLE;
 191         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 192         if (ret != 1) {
 193                 dev_err(dp->dev, "failed to disable panel psr\n");
 194                 goto end;
 195         }
 196
 197         /* Main-Link transmitter remains active during PSR active states */
 198         psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
 199         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 200         if (ret != 1) {
 201                 dev_err(dp->dev, "failed to set panel psr\n");
 202                 goto end;
 203         }
 204
 205         /* Enable psr function */
 206         psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
 207                  DP_PSR_CRC_VERIFICATION;
 208         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 209         if (ret != 1) {
 210                 dev_err(dp->dev, "failed to set panel psr\n");
 211                 goto end;
 212         }
 213
 214         analogix_dp_enable_psr_crc(dp);
 215
 216         return 0;
 217 end:
 218         dev_err(dp->dev, "enable psr fail, force to disable psr\n");
 219         dp->psr_enable = false;
 220
 221         return ret;
 222 }
 223
 224 static int
 225 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 226                                        bool enable)
 227 {
 228         u8 data;
 229         int ret;
 230
 231         ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
 232         if (ret != 1)
 233                 return ret;
 234
 235         if (enable)
 236                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 237                                          DP_LANE_COUNT_ENHANCED_FRAME_EN |
 238                                          DPCD_LANE_COUNT_SET(data));
 239         else
 240                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 241                                          DPCD_LANE_COUNT_SET(data));
 242
 243         return ret < 0 ? ret : 0;
 244 }
 245
 246 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
 247                                                   u8 *enhanced_mode_support)
 248 {
 249         u8 data;
 250         int ret;
 251
 252         ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 253         if (ret != 1) {
 254                 *enhanced_mode_support = 0;
 255                 return ret;
 256         }
 257
 258         *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
 259
 260         return 0;
 261 }
 262
 263 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 264 {
 265         u8 data;
 266         int ret;
 267
 268         ret = analogix_dp_is_enhanced_mode_available(dp, &data);
 269         if (ret < 0)
 270                 return ret;
 271
 272         ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
 273         if (ret < 0)
 274                 return ret;
 275
 276         analogix_dp_enable_enhanced_mode(dp, data);
 277
 278         return 0;
 279 }
 280
 281 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 282 {
 283         int ret;
 284
 285         analogix_dp_set_training_pattern(dp, DP_NONE);
 286
 287         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 288                                  DP_TRAINING_PATTERN_DISABLE);
 289
 290         return ret < 0 ? ret : 0;
 291 }
 292
 293 static void
 294 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 295                                        int pre_emphasis, int lane)
 296 {
 297         switch (lane) {
 298         case 0:
 299                 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 300                 break;
 301         case 1:
 302                 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 303                 break;
 304
 305         case 2:
 306                 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 307                 break;
 308
 309         case 3:
 310                 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 311                 break;
 312         }
 313 }
 314
 315 static int analogix_dp_link_start(struct analogix_dp_device *dp)
 316 {
 317         u8 buf[4];
 318         int lane, lane_count, pll_tries, retval;
 319
 320         lane_count = dp->link_train.lane_count;
 321
 322         dp->link_train.lt_state = CLOCK_RECOVERY;
 323         dp->link_train.eq_loop = 0;
 324
 325         for (lane = 0; lane < lane_count; lane++)
 326                 dp->link_train.cr_loop[lane] = 0;
 327
 328         /* Set link rate and count as you want to establish*/
 329         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 330         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 331
 332         /* Setup RX configuration */
 333         buf[0] = dp->link_train.link_rate;
 334         buf[1] = dp->link_train.lane_count;
 335         retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
 336         if (retval < 0)
 337                 return retval;
 338         /* set enhanced mode if available */
 339         retval = analogix_dp_set_enhanced_mode(dp);
 340         if (retval < 0) {
 341                 dev_err(dp->dev, "failed to set enhance mode\n");
 342                 return retval;
 343         }
 344
 345         /* Set TX pre-emphasis to minimum */
 346         for (lane = 0; lane < lane_count; lane++)
 347                 analogix_dp_set_lane_lane_pre_emphasis(dp,
 348                         PRE_EMPHASIS_LEVEL_0, lane);
 349
 350         /* Wait for PLL lock */
 351         pll_tries = 0;
 352         while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 353                 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 354                         dev_err(dp->dev, "Wait for PLL lock timed out\n");
 355                         return -ETIMEDOUT;
 356                 }
 357
 358                 pll_tries++;
 359                 usleep_range(90, 120);
 360         }
 361
 362         /* Set training pattern 1 */
 363         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 364
 365         /* Set RX training pattern */
 366         retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 367                                     DP_LINK_SCRAMBLING_DISABLE |
 368                                         DP_TRAINING_PATTERN_1);
 369         if (retval < 0)
 370                 return retval;
 371
 372         for (lane = 0; lane < lane_count; lane++)
 373                 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 374                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 375
 376         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
 377                                    lane_count);
 378         if (retval < 0)
 379                 return retval;
 380
 381         return 0;
 382 }
 383
 384 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 385 {
 386         int shift = (lane & 1) * 4;
 387         u8 link_value = link_status[lane >> 1];
 388
 389         return (link_value >> shift) & 0xf;
 390 }
 391
 392 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 393 {
 394         int lane;
 395         u8 lane_status;
 396
 397         for (lane = 0; lane < lane_count; lane++) {
 398                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 399                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 400                         return -EINVAL;
 401         }
 402         return 0;
 403 }
 404
 405 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 406                                      int lane_count)
 407 {
 408         int lane;
 409         u8 lane_status;
 410
 411         if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 412                 return -EINVAL;
 413
 414         for (lane = 0; lane < lane_count; lane++) {
 415                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 416                 lane_status &= DP_CHANNEL_EQ_BITS;
 417                 if (lane_status != DP_CHANNEL_EQ_BITS)
 418                         return -EINVAL;
 419         }
 420
 421         return 0;
 422 }
 423
 424 static unsigned char
 425 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 426 {
 427         int shift = (lane & 1) * 4;
 428         u8 link_value = adjust_request[lane >> 1];
 429
 430         return (link_value >> shift) & 0x3;
 431 }
 432
 433 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 434                                         u8 adjust_request[2],
 435                                         int lane)
 436 {
 437         int shift = (lane & 1) * 4;
 438         u8 link_value = adjust_request[lane >> 1];
 439
 440         return ((link_value >> shift) & 0xc) >> 2;
 441 }
 442
 443 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 444                                                u8 training_lane_set, int lane)
 445 {
 446         switch (lane) {
 447         case 0:
 448                 analogix_dp_set_lane0_link_training(dp, training_lane_set);
 449                 break;
 450         case 1:
 451                 analogix_dp_set_lane1_link_training(dp, training_lane_set);
 452                 break;
 453
 454         case 2:
 455                 analogix_dp_set_lane2_link_training(dp, training_lane_set);
 456                 break;
 457
 458         case 3:
 459                 analogix_dp_set_lane3_link_training(dp, training_lane_set);
 460                 break;
 461         }
 462 }
 463
 464 static unsigned int
 465 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
 466                                    int lane)
 467 {
 468         u32 reg;
 469
 470         switch (lane) {
 471         case 0:
 472                 reg = analogix_dp_get_lane0_link_training(dp);
 473                 break;
 474         case 1:
 475                 reg = analogix_dp_get_lane1_link_training(dp);
 476                 break;
 477         case 2:
 478                 reg = analogix_dp_get_lane2_link_training(dp);
 479                 break;
 480         case 3:
 481                 reg = analogix_dp_get_lane3_link_training(dp);
 482                 break;
 483         default:
 484                 WARN_ON(1);
 485                 return 0;
 486         }
 487
 488         return reg;
 489 }
 490
 491 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 492 {
 493         analogix_dp_training_pattern_dis(dp);
 494         analogix_dp_set_enhanced_mode(dp);
 495
 496         dp->link_train.lt_state = FAILED;
 497 }
 498
 499 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 500                                                  u8 adjust_request[2])
 501 {
 502         int lane, lane_count;
 503         u8 voltage_swing, pre_emphasis, training_lane;
 504
 505         lane_count = dp->link_train.lane_count;
 506         for (lane = 0; lane < lane_count; lane++) {
 507                 voltage_swing = analogix_dp_get_adjust_request_voltage(
 508                                                 adjust_request, lane);
 509                 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 510                                                 adjust_request, lane);
 511                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 512                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 513
 514                 if (voltage_swing == VOLTAGE_LEVEL_3)
 515                         training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 516                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 517                         training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 518
 519                 dp->link_train.training_lane[lane] = training_lane;
 520         }
 521 }
 522
 523 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 524 {
 525         int lane, lane_count, retval;
 526         u8 voltage_swing, pre_emphasis, training_lane;
 527         u8 link_status[2], adjust_request[2];
 528
 529         usleep_range(100, 101);
 530
 531         lane_count = dp->link_train.lane_count;
 532
 533         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 534         if (retval < 0)
 535                 return retval;
 536
 537         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 538                                   adjust_request, 2);
 539         if (retval < 0)
 540                 return retval;
 541
 542         if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 543                 /* set training pattern 2 for EQ */
 544                 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 545
 546                 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 547                                             DP_LINK_SCRAMBLING_DISABLE |
 548                                                 DP_TRAINING_PATTERN_2);
 549                 if (retval < 0)
 550                         return retval;
 551
 552                 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
 553                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 554         } else {
 555                 for (lane = 0; lane < lane_count; lane++) {
 556                         training_lane = analogix_dp_get_lane_link_training(
 557                                                         dp, lane);
 558                         voltage_swing = analogix_dp_get_adjust_request_voltage(
 559                                                         adjust_request, lane);
 560                         pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 561                                                         adjust_request, lane);
 562
 563                         if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
 564                                         voltage_swing &&
 565                             DPCD_PRE_EMPHASIS_GET(training_lane) ==
 566                                         pre_emphasis)
 567                                 dp->link_train.cr_loop[lane]++;
 568
 569                         if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 570                             voltage_swing == VOLTAGE_LEVEL_3 ||
 571                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 572                                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 573                                         dp->link_train.cr_loop[lane],
 574                                         voltage_swing, pre_emphasis);
 575                                 analogix_dp_reduce_link_rate(dp);
 576                                 return -EIO;
 577                         }
 578                 }
 579         }
 580
 581         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 582
 583         for (lane = 0; lane < lane_count; lane++)
 584                 analogix_dp_set_lane_link_training(dp,
 585                         dp->link_train.training_lane[lane], lane);
 586
 587         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 588                                    dp->link_train.training_lane, lane_count);
 589         if (retval < 0)
 590                 return retval;
 591
 592         return 0;
 593 }
 594
 595 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 596 {
 597         int lane, lane_count, retval;
 598         u32 reg;
 599         u8 link_align, link_status[2], adjust_request[2];
 600
 601         usleep_range(400, 401);
 602
 603         lane_count = dp->link_train.lane_count;
 604
 605         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 606         if (retval < 0)
 607                 return retval;
 608
 609         if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
 610                 analogix_dp_reduce_link_rate(dp);
 611                 return -EIO;
 612         }
 613
 614         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 615                                   adjust_request, 2);
 616         if (retval < 0)
 617                 return retval;
 618
 619         retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 620                                    &link_align);
 621         if (retval < 0)
 622                 return retval;
 623
 624         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 625
 626         if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 627                 /* traing pattern Set to Normal */
 628                 retval = analogix_dp_training_pattern_dis(dp);
 629                 if (retval < 0)
 630                         return retval;
 631
 632                 dev_dbg(dp->dev, "Link Training success!\n");
 633                 analogix_dp_get_link_bandwidth(dp, &reg);
 634                 dp->link_train.link_rate = reg;
 635                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 636                         dp->link_train.link_rate);
 637
 638                 analogix_dp_get_lane_count(dp, &reg);
 639                 dp->link_train.lane_count = reg;
 640                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 641                         dp->link_train.lane_count);
 642
 643                 dp->link_train.lt_state = FINISHED;
 644
 645                 return 0;
 646         }
 647
 648         /* not all locked */
 649         dp->link_train.eq_loop++;
 650
 651         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 652                 dev_err(dp->dev, "EQ Max loop\n");
 653                 analogix_dp_reduce_link_rate(dp);
 654                 return -EIO;
 655         }
 656
 657         for (lane = 0; lane < lane_count; lane++)
 658                 analogix_dp_set_lane_link_training(dp,
 659                         dp->link_train.training_lane[lane], lane);
 660
 661         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 662                                    dp->link_train.training_lane, lane_count);
 663         if (retval < 0)
 664                 return retval;
 665
 666         return 0;
 667 }
 668
 669 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 670                                              u8 *bandwidth)
 671 {
 672         u8 data;
 673
 674         /*
 675          * For DP rev.1.1, Maximum link rate of Main Link lanes
 676          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 677          * For DP rev.1.2, Maximum link rate of Main Link lanes
 678          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 679          */
 680         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
 681         *bandwidth = data;
 682 }
 683
 684 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 685                                               u8 *lane_count)
 686 {
 687         u8 data;
 688
 689         /*
 690          * For DP rev.1.1, Maximum number of Main Link lanes
 691          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 692          */
 693         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 694         *lane_count = DPCD_MAX_LANE_COUNT(data);
 695 }
 696
 697 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
 698                                        u32 max_lanes, u32 max_rate)
 699 {
 700         int retval = 0;
 701         bool training_finished = false;
 702
 703         /*
 704          * MACRO_RST must be applied after the PLL_LOCK to avoid
 705          * the DP inter pair skew issue for at least 10 us
 706          */
 707         analogix_dp_reset_macro(dp);
 708
 709         /* Initialize by reading RX's DPCD */
 710         analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 711         analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 712
 713         if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
 714             (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
 715             (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 716                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 717                         dp->link_train.link_rate);
 718                 dp->link_train.link_rate = DP_LINK_BW_1_62;
 719         }
 720
 721         if (dp->link_train.lane_count == 0) {
 722                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 723                         dp->link_train.lane_count);
 724                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 725         }
 726
 727         /* Setup TX lane count & rate */
 728         if (dp->link_train.lane_count > max_lanes)
 729                 dp->link_train.lane_count = max_lanes;
 730         if (dp->link_train.link_rate > max_rate)
 731                 dp->link_train.link_rate = max_rate;
 732
 733         /* All DP analog module power up */
 734         analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 735
 736         dp->link_train.lt_state = START;
 737
 738         /* Process here */
 739         while (!retval && !training_finished) {
 740                 switch (dp->link_train.lt_state) {
 741                 case START:
 742                         retval = analogix_dp_link_start(dp);
 743                         if (retval)
 744                                 dev_err(dp->dev, "LT link start failed!\n");
 745                         break;
 746                 case CLOCK_RECOVERY:
 747                         retval = analogix_dp_process_clock_recovery(dp);
 748                         if (retval)
 749                                 dev_err(dp->dev, "LT CR failed!\n");
 750                         break;
 751                 case EQUALIZER_TRAINING:
 752                         retval = analogix_dp_process_equalizer_training(dp);
 753                         if (retval)
 754                                 dev_err(dp->dev, "LT EQ failed!\n");
 755                         break;
 756                 case FINISHED:
 757                         training_finished = 1;
 758                         break;
 759                 case FAILED:
 760                         return -EREMOTEIO;
 761                 }
 762         }
 763         if (retval)
 764                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 765
 766         return retval;
 767 }
 768
 769 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
 770 {
 771         int i, ret;
 772         u8 link_align, link_status[2];
 773         enum pll_status status;
 774
 775         analogix_dp_reset_macro(dp);
 776
 777         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 778         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 779
 780         for (i = 0; i < dp->link_train.lane_count; i++) {
 781                 analogix_dp_set_lane_link_training(dp,
 782                         dp->link_train.training_lane[i], i);
 783         }
 784
 785         ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
 786                                  status != PLL_UNLOCKED, 120,
 787                                  120 * DP_TIMEOUT_LOOP_COUNT);
 788         if (ret) {
 789                 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
 790                 return ret;
 791         }
 792
 793         /* source Set training pattern 1 */
 794         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 795         /* From DP spec, pattern must be on-screen for a minimum 500us */
 796         usleep_range(500, 600);
 797
 798         analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 799         /* From DP spec, pattern must be on-screen for a minimum 500us */
 800         usleep_range(500, 600);
 801
 802         /* TODO: enhanced_mode?*/
 803         analogix_dp_set_training_pattern(dp, DP_NONE);
 804
 805         /*
 806          * Useful for debugging issues with fast link training, disable for more
 807          * speed
 808          */
 809         if (verify_fast_training) {
 810                 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 811                                         &link_align);
 812                 if (ret < 0) {
 813                         DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
 814                                       ret);
 815                         return ret;
 816                 }
 817
 818                 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
 819                                        2);
 820                 if (ret < 0) {
 821                         DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
 822                                       ret);
 823                         return ret;
 824                 }
 825
 826                 if (analogix_dp_clock_recovery_ok(link_status,
 827                                                   dp->link_train.lane_count)) {
 828                         DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
 829                         analogix_dp_reduce_link_rate(dp);
 830                         return -EIO;
 831                 }
 832
 833                 if (analogix_dp_channel_eq_ok(link_status, link_align,
 834                                               dp->link_train.lane_count)) {
 835                         DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
 836                         analogix_dp_reduce_link_rate(dp);
 837                         return -EIO;
 838                 }
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int analogix_dp_train_link(struct analogix_dp_device *dp)
 845 {
 846         if (dp->fast_train_enable)
 847                 return analogix_dp_fast_link_train(dp);
 848
 849         return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
 850                                            dp->video_info.max_link_rate);
 851 }
 852
 853 static int analogix_dp_config_video(struct analogix_dp_device *dp)
 854 {
 855         int timeout_loop = 0;
 856         int done_count = 0;
 857
 858         analogix_dp_config_video_slave_mode(dp);
 859
 860         analogix_dp_set_video_color_format(dp);
 861
 862         if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 863                 dev_err(dp->dev, "PLL is not locked yet.\n");
 864                 return -EINVAL;
 865         }
 866
 867         for (;;) {
 868                 timeout_loop++;
 869                 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 870                         break;
 871                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 872                         dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
 873                         return -ETIMEDOUT;
 874                 }
 875                 usleep_range(1000, 1001);
 876         }
 877
 878         /* Set to use the register calculated M/N video */
 879         analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 880
 881         /* For video bist, Video timing must be generated by register */
 882         analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 883
 884         /* Disable video mute */
 885         analogix_dp_enable_video_mute(dp, 0);
 886
 887         /* Configure video slave mode */
 888         analogix_dp_enable_video_master(dp, 0);
 889
 890         /* Enable video */
 891         analogix_dp_start_video(dp);
 892
 893         timeout_loop = 0;
 894
 895         for (;;) {
 896                 timeout_loop++;
 897                 if (analogix_dp_is_video_stream_on(dp) == 0) {
 898                         done_count++;
 899                         if (done_count > 10)
 900                                 break;
 901                 } else if (done_count) {
 902                         done_count = 0;
 903                 }
 904                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 905                         dev_warn(dp->dev,
 906                                  "Ignoring timeout of video streamclk ok\n");
 907                         break;
 908                 }
 909
 910                 usleep_range(1000, 1001);
 911         }
 912
 913         return 0;
 914 }
 915
 916 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 917                                        bool enable)
 918 {
 919         u8 data;
 920         int ret;
 921
 922         if (enable) {
 923                 analogix_dp_enable_scrambling(dp);
 924
 925                 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 926                                         &data);
 927                 if (ret != 1)
 928                         return ret;
 929                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 930                                    (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 931         } else {
 932                 analogix_dp_disable_scrambling(dp);
 933
 934                 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 935                                         &data);
 936                 if (ret != 1)
 937                         return ret;
 938                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 939                                    (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 940         }
 941         return ret < 0 ? ret : 0;
 942 }
 943
 944 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 945 {
 946         struct analogix_dp_device *dp = arg;
 947         irqreturn_t ret = IRQ_NONE;
 948         enum dp_irq_type irq_type;
 949
 950         irq_type = analogix_dp_get_irq_type(dp);
 951         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 952                 analogix_dp_mute_hpd_interrupt(dp);
 953                 ret = IRQ_WAKE_THREAD;
 954         }
 955
 956         return ret;
 957 }
 958
 959 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 960 {
 961         struct analogix_dp_device *dp = arg;
 962         enum dp_irq_type irq_type;
 963
 964         irq_type = analogix_dp_get_irq_type(dp);
 965         if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
 966             irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
 967                 dev_dbg(dp->dev, "Detected cable status changed!\n");
 968                 if (dp->drm_dev)
 969                         drm_helper_hpd_irq_event(dp->drm_dev);
 970         }
 971
 972         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 973                 analogix_dp_clear_hotplug_interrupts(dp);
 974                 analogix_dp_unmute_hpd_interrupt(dp);
 975         }
 976
 977         return IRQ_HANDLED;
 978 }
 979
 980 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
 981 {
 982         int ret;
 983         u8 spread;
 984
 985         ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
 986         if (ret != 1) {
 987                 dev_err(dp->dev, "failed to read downspread %d\n", ret);
 988                 return ret;
 989         }
 990         dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
 991         dev_dbg(dp->dev, "fast link training %s\n",
 992                 dp->fast_train_enable ? "supported" : "unsupported");
 993         return 0;
 994 }
 995
 996 static int analogix_dp_commit(struct analogix_dp_device *dp)
 997 {
 998         int ret;
 999
1000         /* Keep the panel disabled while we configure video */
1001         if (dp->plat_data->panel) {
1002                 if (drm_panel_disable(dp->plat_data->panel))
1003                         DRM_ERROR("failed to disable the panel\n");
1004         }
1005
1006         ret = analogix_dp_train_link(dp);
1007         if (ret) {
1008                 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
1009                 return ret;
1010         }
1011
1012         ret = analogix_dp_enable_scramble(dp, 1);
1013         if (ret < 0) {
1014                 dev_err(dp->dev, "can not enable scramble\n");
1015                 return ret;
1016         }
1017
1018         analogix_dp_init_video(dp);
1019         ret = analogix_dp_config_video(dp);
1020         if (ret) {
1021                 dev_err(dp->dev, "unable to config video\n");
1022                 return ret;
1023         }
1024
1025         /* Safe to enable the panel now */
1026         if (dp->plat_data->panel) {
1027                 ret = drm_panel_enable(dp->plat_data->panel);
1028                 if (ret) {
1029                         DRM_ERROR("failed to enable the panel\n");
1030                         return ret;
1031                 }
1032         }
1033
1034         ret = analogix_dp_detect_sink_psr(dp);
1035         if (ret)
1036                 return ret;
1037
1038         if (dp->psr_enable) {
1039                 ret = analogix_dp_enable_sink_psr(dp);
1040                 if (ret)
1041                         return ret;
1042         }
1043
1044         /* Check whether panel supports fast training */
1045         ret =  analogix_dp_fast_link_train_detection(dp);
1046         if (ret)
1047                 dp->psr_enable = false;
1048
1049         return ret;
1050 }
1051
1052 /*
1053  * This function is a bit of a catch-all for panel preparation, hopefully
1054  * simplifying the logic of functions that need to prepare/unprepare the panel
1055  * below.
1056  *
1057  * If @prepare is true, this function will prepare the panel. Conversely, if it
1058  * is false, the panel will be unprepared.
1059  *
1060  * If @is_modeset_prepare is true, the function will disregard the current state
1061  * of the panel and either prepare/unprepare the panel based on @prepare. Once
1062  * it finishes, it will update dp->panel_is_modeset to reflect the current state
1063  * of the panel.
1064  */
1065 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
1066                                      bool prepare, bool is_modeset_prepare)
1067 {
1068         int ret = 0;
1069
1070         if (!dp->plat_data->panel)
1071                 return 0;
1072
1073         mutex_lock(&dp->panel_lock);
1074
1075         /*
1076          * Exit early if this is a temporary prepare/unprepare and we're already
1077          * modeset (since we neither want to prepare twice or unprepare early).
1078          */
1079         if (dp->panel_is_modeset && !is_modeset_prepare)
1080                 goto out;
1081
1082         if (prepare)
1083                 ret = drm_panel_prepare(dp->plat_data->panel);
1084         else
1085                 ret = drm_panel_unprepare(dp->plat_data->panel);
1086
1087         if (ret)
1088                 goto out;
1089
1090         if (is_modeset_prepare)
1091                 dp->panel_is_modeset = prepare;
1092
1093 out:
1094         mutex_unlock(&dp->panel_lock);
1095         return ret;
1096 }
1097
1098 static int analogix_dp_get_modes(struct drm_connector *connector)
1099 {
1100         struct analogix_dp_device *dp = to_dp(connector);
1101         struct edid *edid;
1102         int ret, num_modes = 0;
1103
1104         if (dp->plat_data->panel) {
1105                 num_modes += drm_panel_get_modes(dp->plat_data->panel);
1106         } else {
1107                 ret = analogix_dp_prepare_panel(dp, true, false);
1108                 if (ret) {
1109                         DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1110                         return 0;
1111                 }
1112
1113                 pm_runtime_get_sync(dp->dev);
1114                 edid = drm_get_edid(connector, &dp->aux.ddc);
1115                 pm_runtime_put(dp->dev);
1116                 if (edid) {
1117                         drm_connector_update_edid_property(&dp->connector,
1118                                                            edid);
1119                         num_modes += drm_add_edid_modes(&dp->connector, edid);
1120                         kfree(edid);
1121                 }
1122
1123                 ret = analogix_dp_prepare_panel(dp, false, false);
1124                 if (ret)
1125                         DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1126         }
1127
1128         if (dp->plat_data->get_modes)
1129                 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1130
1131         return num_modes;
1132 }
1133
1134 static struct drm_encoder *
1135 analogix_dp_best_encoder(struct drm_connector *connector)
1136 {
1137         struct analogix_dp_device *dp = to_dp(connector);
1138
1139         return dp->encoder;
1140 }
1141
1142 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1143         .get_modes = analogix_dp_get_modes,
1144         .best_encoder = analogix_dp_best_encoder,
1145 };
1146
1147 static enum drm_connector_status
1148 analogix_dp_detect(struct drm_connector *connector, bool force)
1149 {
1150         struct analogix_dp_device *dp = to_dp(connector);
1151         enum drm_connector_status status = connector_status_disconnected;
1152         int ret;
1153
1154         if (dp->plat_data->panel)
1155                 return connector_status_connected;
1156
1157         ret = analogix_dp_prepare_panel(dp, true, false);
1158         if (ret) {
1159                 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1160                 return connector_status_disconnected;
1161         }
1162
1163         if (!analogix_dp_detect_hpd(dp))
1164                 status = connector_status_connected;
1165
1166         ret = analogix_dp_prepare_panel(dp, false, false);
1167         if (ret)
1168                 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1169
1170         return status;
1171 }
1172
1173 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1174         .fill_modes = drm_helper_probe_single_connector_modes,
1175         .detect = analogix_dp_detect,
1176         .destroy = drm_connector_cleanup,
1177         .reset = drm_atomic_helper_connector_reset,
1178         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1179         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1180 };
1181
1182 static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
1183 {
1184         struct analogix_dp_device *dp = bridge->driver_private;
1185         struct drm_encoder *encoder = dp->encoder;
1186         struct drm_connector *connector = NULL;
1187         int ret = 0;
1188
1189         if (!bridge->encoder) {
1190                 DRM_ERROR("Parent encoder object not found");
1191                 return -ENODEV;
1192         }
1193
1194         if (!dp->plat_data->skip_connector) {
1195                 connector = &dp->connector;
1196                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1197
1198                 ret = drm_connector_init(dp->drm_dev, connector,
1199                                          &analogix_dp_connector_funcs,
1200                                          DRM_MODE_CONNECTOR_eDP);
1201                 if (ret) {
1202                         DRM_ERROR("Failed to initialize connector with drm\n");
1203                         return ret;
1204                 }
1205
1206                 drm_connector_helper_add(connector,
1207                                          &analogix_dp_connector_helper_funcs);
1208                 drm_connector_attach_encoder(connector, encoder);
1209         }
1210
1211         /*
1212          * NOTE: the connector registration is implemented in analogix
1213          * platform driver, that to say connector would be exist after
1214          * plat_data->attch return, that's why we record the connector
1215          * point after plat attached.
1216          */
1217         if (dp->plat_data->attach) {
1218                 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1219                 if (ret) {
1220                         DRM_ERROR("Failed at platform attach func\n");
1221                         return ret;
1222                 }
1223         }
1224
1225         if (dp->plat_data->panel) {
1226                 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1227                 if (ret) {
1228                         DRM_ERROR("Failed to attach panel\n");
1229                         return ret;
1230                 }
1231         }
1232
1233         return 0;
1234 }
1235
1236 static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge)
1237 {
1238         struct analogix_dp_device *dp = bridge->driver_private;
1239         int ret;
1240
1241         ret = analogix_dp_prepare_panel(dp, true, true);
1242         if (ret)
1243                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1244 }
1245
1246 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1247 {
1248         int ret;
1249
1250         pm_runtime_get_sync(dp->dev);
1251
1252         ret = clk_prepare_enable(dp->clock);
1253         if (ret < 0) {
1254                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1255                 goto out_dp_clk_pre;
1256         }
1257
1258         if (dp->plat_data->power_on_start)
1259                 dp->plat_data->power_on_start(dp->plat_data);
1260
1261         phy_power_on(dp->phy);
1262
1263         ret = analogix_dp_init_dp(dp);
1264         if (ret)
1265                 goto out_dp_init;
1266
1267         /*
1268          * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1269          * We should first make sure the HPD signal is asserted high by device
1270          * when we want to establish a link with it.
1271          */
1272         ret = analogix_dp_detect_hpd(dp);
1273         if (ret) {
1274                 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1275                 goto out_dp_init;
1276         }
1277
1278         ret = analogix_dp_commit(dp);
1279         if (ret) {
1280                 DRM_ERROR("dp commit error, ret = %d\n", ret);
1281                 goto out_dp_init;
1282         }
1283
1284         if (dp->plat_data->power_on_end)
1285                 dp->plat_data->power_on_end(dp->plat_data);
1286
1287         enable_irq(dp->irq);
1288         return 0;
1289
1290 out_dp_init:
1291         phy_power_off(dp->phy);
1292         if (dp->plat_data->power_off)
1293                 dp->plat_data->power_off(dp->plat_data);
1294         clk_disable_unprepare(dp->clock);
1295 out_dp_clk_pre:
1296         pm_runtime_put_sync(dp->dev);
1297
1298         return ret;
1299 }
1300
1301 static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
1302 {
1303         struct analogix_dp_device *dp = bridge->driver_private;
1304         int timeout_loop = 0;
1305
1306         if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1307                 return;
1308
1309         while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1310                 if (analogix_dp_set_bridge(dp) == 0) {
1311                         dp->dpms_mode = DRM_MODE_DPMS_ON;
1312                         return;
1313                 }
1314                 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1315                         timeout_loop);
1316                 timeout_loop++;
1317                 usleep_range(10, 11);
1318         }
1319         dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1320 }
1321
1322 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1323 {
1324         struct analogix_dp_device *dp = bridge->driver_private;
1325         int ret;
1326
1327         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1328                 return;
1329
1330         if (dp->plat_data->panel) {
1331                 if (drm_panel_disable(dp->plat_data->panel)) {
1332                         DRM_ERROR("failed to disable the panel\n");
1333                         return;
1334                 }
1335         }
1336
1337         disable_irq(dp->irq);
1338
1339         if (dp->plat_data->power_off)
1340                 dp->plat_data->power_off(dp->plat_data);
1341
1342         analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1343         phy_power_off(dp->phy);
1344
1345         clk_disable_unprepare(dp->clock);
1346
1347         pm_runtime_put_sync(dp->dev);
1348
1349         ret = analogix_dp_prepare_panel(dp, false, true);
1350         if (ret)
1351                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1352
1353         dp->psr_enable = false;
1354         dp->fast_train_enable = false;
1355         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1356 }
1357
1358 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1359                                 const struct drm_display_mode *orig_mode,
1360                                 const struct drm_display_mode *mode)
1361 {
1362         struct analogix_dp_device *dp = bridge->driver_private;
1363         struct drm_display_info *display_info = &dp->connector.display_info;
1364         struct video_info *video = &dp->video_info;
1365         struct device_node *dp_node = dp->dev->of_node;
1366         int vic;
1367
1368         /* Input video interlaces & hsync pol & vsync pol */
1369         video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1370         video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1371         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1372
1373         /* Input video dynamic_range & colorimetry */
1374         vic = drm_match_cea_mode(mode);
1375         if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1376             (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1377                 video->dynamic_range = CEA;
1378                 video->ycbcr_coeff = COLOR_YCBCR601;
1379         } else if (vic) {
1380                 video->dynamic_range = CEA;
1381                 video->ycbcr_coeff = COLOR_YCBCR709;
1382         } else {
1383                 video->dynamic_range = VESA;
1384                 video->ycbcr_coeff = COLOR_YCBCR709;
1385         }
1386
1387         /* Input vide bpc and color_formats */
1388         switch (display_info->bpc) {
1389         case 12:
1390                 video->color_depth = COLOR_12;
1391                 break;
1392         case 10:
1393                 video->color_depth = COLOR_10;
1394                 break;
1395         case 8:
1396                 video->color_depth = COLOR_8;
1397                 break;
1398         case 6:
1399                 video->color_depth = COLOR_6;
1400                 break;
1401         default:
1402                 video->color_depth = COLOR_8;
1403                 break;
1404         }
1405         if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1406                 video->color_space = COLOR_YCBCR444;
1407         else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1408                 video->color_space = COLOR_YCBCR422;
1409         else
1410                 video->color_space = COLOR_RGB;
1411
1412         /*
1413          * NOTE: those property parsing code is used for providing backward
1414          * compatibility for samsung platform.
1415          * Due to we used the "of_property_read_u32" interfaces, when this
1416          * property isn't present, the "video_info" can keep the original
1417          * values and wouldn't be modified.
1418          */
1419         of_property_read_u32(dp_node, "samsung,color-space",
1420                              &video->color_space);
1421         of_property_read_u32(dp_node, "samsung,dynamic-range",
1422                              &video->dynamic_range);
1423         of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1424                              &video->ycbcr_coeff);
1425         of_property_read_u32(dp_node, "samsung,color-depth",
1426                              &video->color_depth);
1427         if (of_property_read_bool(dp_node, "hsync-active-high"))
1428                 video->h_sync_polarity = true;
1429         if (of_property_read_bool(dp_node, "vsync-active-high"))
1430                 video->v_sync_polarity = true;
1431         if (of_property_read_bool(dp_node, "interlaced"))
1432                 video->interlaced = true;
1433 }
1434
1435 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
1436 {
1437         /* do nothing */
1438 }
1439
1440 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1441         .pre_enable = analogix_dp_bridge_pre_enable,
1442         .enable = analogix_dp_bridge_enable,
1443         .disable = analogix_dp_bridge_disable,
1444         .post_disable = analogix_dp_bridge_nop,
1445         .mode_set = analogix_dp_bridge_mode_set,
1446         .attach = analogix_dp_bridge_attach,
1447 };
1448
1449 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1450                                      struct analogix_dp_device *dp)
1451 {
1452         struct drm_bridge *bridge;
1453         int ret;
1454
1455         bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1456         if (!bridge) {
1457                 DRM_ERROR("failed to allocate for drm bridge\n");
1458                 return -ENOMEM;
1459         }
1460
1461         dp->bridge = bridge;
1462
1463         bridge->driver_private = dp;
1464         bridge->funcs = &analogix_dp_bridge_funcs;
1465
1466         ret = drm_bridge_attach(dp->encoder, bridge, NULL);
1467         if (ret) {
1468                 DRM_ERROR("failed to attach drm bridge\n");
1469                 return -EINVAL;
1470         }
1471
1472         return 0;
1473 }
1474
1475 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1476 {
1477         struct device_node *dp_node = dp->dev->of_node;
1478         struct video_info *video_info = &dp->video_info;
1479
1480         switch (dp->plat_data->dev_type) {
1481         case RK3288_DP:
1482         case RK3399_EDP:
1483                 /*
1484                  * Like Rk3288 DisplayPort TRM indicate that "Main link
1485                  * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1486                  */
1487                 video_info->max_link_rate = 0x0A;
1488                 video_info->max_lane_count = 0x04;
1489                 break;
1490         case EXYNOS_DP:
1491                 /*
1492                  * NOTE: those property parseing code is used for
1493                  * providing backward compatibility for samsung platform.
1494                  */
1495                 of_property_read_u32(dp_node, "samsung,link-rate",
1496                                      &video_info->max_link_rate);
1497                 of_property_read_u32(dp_node, "samsung,lane-count",
1498                                      &video_info->max_lane_count);
1499                 break;
1500         }
1501
1502         return 0;
1503 }
1504
1505 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1506                                        struct drm_dp_aux_msg *msg)
1507 {
1508         struct analogix_dp_device *dp = to_dp(aux);
1509
1510         return analogix_dp_transfer(dp, msg);
1511 }
1512
1513 struct analogix_dp_device *
1514 analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1515                  struct analogix_dp_plat_data *plat_data)
1516 {
1517         struct platform_device *pdev = to_platform_device(dev);
1518         struct analogix_dp_device *dp;
1519         struct resource *res;
1520         unsigned int irq_flags;
1521         int ret;
1522
1523         if (!plat_data) {
1524                 dev_err(dev, "Invalided input plat_data\n");
1525                 return ERR_PTR(-EINVAL);
1526         }
1527
1528         dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1529         if (!dp)
1530                 return ERR_PTR(-ENOMEM);
1531
1532         dp->dev = &pdev->dev;
1533         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1534
1535         mutex_init(&dp->panel_lock);
1536         dp->panel_is_modeset = false;
1537
1538         /*
1539          * platform dp driver need containor_of the plat_data to get
1540          * the driver private data, so we need to store the point of
1541          * plat_data, not the context of plat_data.
1542          */
1543         dp->plat_data = plat_data;
1544
1545         ret = analogix_dp_dt_parse_pdata(dp);
1546         if (ret)
1547                 return ERR_PTR(ret);
1548
1549         dp->phy = devm_phy_get(dp->dev, "dp");
1550         if (IS_ERR(dp->phy)) {
1551                 dev_err(dp->dev, "no DP phy configured\n");
1552                 ret = PTR_ERR(dp->phy);
1553                 if (ret) {
1554                         /*
1555                          * phy itself is not enabled, so we can move forward
1556                          * assigning NULL to phy pointer.
1557                          */
1558                         if (ret == -ENOSYS || ret == -ENODEV)
1559                                 dp->phy = NULL;
1560                         else
1561                                 return ERR_PTR(ret);
1562                 }
1563         }
1564
1565         dp->clock = devm_clk_get(&pdev->dev, "dp");
1566         if (IS_ERR(dp->clock)) {
1567                 dev_err(&pdev->dev, "failed to get clock\n");
1568                 return ERR_CAST(dp->clock);
1569         }
1570
1571         clk_prepare_enable(dp->clock);
1572
1573         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1574
1575         dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1576         if (IS_ERR(dp->reg_base))
1577                 return ERR_CAST(dp->reg_base);
1578
1579         dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1580
1581         /* Try two different names */
1582         dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1583         if (!dp->hpd_gpiod)
1584                 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
1585                                                         GPIOD_IN);
1586         if (IS_ERR(dp->hpd_gpiod)) {
1587                 dev_err(dev, "error getting HDP GPIO: %ld\n",
1588                         PTR_ERR(dp->hpd_gpiod));
1589                 return ERR_CAST(dp->hpd_gpiod);
1590         }
1591
1592         if (dp->hpd_gpiod) {
1593                 /*
1594                  * Set up the hotplug GPIO from the device tree as an interrupt.
1595                  * Simply specifying a different interrupt in the device tree
1596                  * doesn't work since we handle hotplug rather differently when
1597                  * using a GPIO.  We also need the actual GPIO specifier so
1598                  * that we can get the current state of the GPIO.
1599                  */
1600                 dp->irq = gpiod_to_irq(dp->hpd_gpiod);
1601                 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1602         } else {
1603                 dp->irq = platform_get_irq(pdev, 0);
1604                 irq_flags = 0;
1605         }
1606
1607         if (dp->irq == -ENXIO) {
1608                 dev_err(&pdev->dev, "failed to get irq\n");
1609                 return ERR_PTR(-ENODEV);
1610         }
1611
1612         ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1613                                         analogix_dp_hardirq,
1614                                         analogix_dp_irq_thread,
1615                                         irq_flags, "analogix-dp", dp);
1616         if (ret) {
1617                 dev_err(&pdev->dev, "failed to request irq\n");
1618                 goto err_disable_pm_runtime;
1619         }
1620         disable_irq(dp->irq);
1621
1622         dp->drm_dev = drm_dev;
1623         dp->encoder = dp->plat_data->encoder;
1624
1625         dp->aux.name = "DP-AUX";
1626         dp->aux.transfer = analogix_dpaux_transfer;
1627         dp->aux.dev = &pdev->dev;
1628
1629         ret = drm_dp_aux_register(&dp->aux);
1630         if (ret)
1631                 return ERR_PTR(ret);
1632
1633         pm_runtime_enable(dev);
1634
1635         ret = analogix_dp_create_bridge(drm_dev, dp);
1636         if (ret) {
1637                 DRM_ERROR("failed to create bridge (%d)\n", ret);
1638                 goto err_disable_pm_runtime;
1639         }
1640
1641         return dp;
1642
1643 err_disable_pm_runtime:
1644
1645         pm_runtime_disable(dev);
1646
1647         return ERR_PTR(ret);
1648 }
1649 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1650
1651 void analogix_dp_unbind(struct analogix_dp_device *dp)
1652 {
1653         analogix_dp_bridge_disable(dp->bridge);
1654         dp->connector.funcs->destroy(&dp->connector);
1655
1656         if (dp->plat_data->panel) {
1657                 if (drm_panel_unprepare(dp->plat_data->panel))
1658                         DRM_ERROR("failed to turnoff the panel\n");
1659                 if (drm_panel_detach(dp->plat_data->panel))
1660                         DRM_ERROR("failed to detach the panel\n");
1661         }
1662
1663         drm_dp_aux_unregister(&dp->aux);
1664         pm_runtime_disable(dp->dev);
1665         clk_disable_unprepare(dp->clock);
1666 }
1667 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1668
1669 #ifdef CONFIG_PM
1670 int analogix_dp_suspend(struct analogix_dp_device *dp)
1671 {
1672         clk_disable_unprepare(dp->clock);
1673
1674         if (dp->plat_data->panel) {
1675                 if (drm_panel_unprepare(dp->plat_data->panel))
1676                         DRM_ERROR("failed to turnoff the panel\n");
1677         }
1678
1679         return 0;
1680 }
1681 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1682
1683 int analogix_dp_resume(struct analogix_dp_device *dp)
1684 {
1685         int ret;
1686
1687         ret = clk_prepare_enable(dp->clock);
1688         if (ret < 0) {
1689                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1690                 return ret;
1691         }
1692
1693         if (dp->plat_data->panel) {
1694                 if (drm_panel_prepare(dp->plat_data->panel)) {
1695                         DRM_ERROR("failed to setup the panel\n");
1696                         return -EBUSY;
1697                 }
1698         }
1699
1700         return 0;
1701 }
1702 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1703 #endif
1704
1705 int analogix_dp_start_crc(struct drm_connector *connector)
1706 {
1707         struct analogix_dp_device *dp = to_dp(connector);
1708
1709         if (!connector->state->crtc) {
1710                 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1711                           connector->name);
1712                 return -EINVAL;
1713         }
1714
1715         return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1716 }
1717 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1718
1719 int analogix_dp_stop_crc(struct drm_connector *connector)
1720 {
1721         struct analogix_dp_device *dp = to_dp(connector);
1722
1723         return drm_dp_stop_crc(&dp->aux);
1724 }
1725 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1726
1727 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1728 MODULE_DESCRIPTION("Analogix DP Core Driver");
1729 MODULE_LICENSE("GPL v2");