drivers/gpu/drm/arm/malidp_planes.c

   1 /*
   2  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   3  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * ARM Mali DP plane manipulation routines.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_fb_cma_helper.h>
  17 #include <drm/drm_gem_cma_helper.h>
  18 #include <drm/drm_plane_helper.h>
  19 #include <drm/drm_print.h>
  20
  21 #include "malidp_hw.h"
  22 #include "malidp_drv.h"
  23
  24 /* Layer specific register offsets */
  25 #define MALIDP_LAYER_FORMAT             0x000
  26 #define   LAYER_FORMAT_MASK             0x3f
  27 #define MALIDP_LAYER_CONTROL            0x004
  28 #define   LAYER_ENABLE                  (1 << 0)
  29 #define   LAYER_FLOWCFG_MASK            7
  30 #define   LAYER_FLOWCFG(x)              (((x) & LAYER_FLOWCFG_MASK) << 1)
  31 #define     LAYER_FLOWCFG_SCALE_SE      3
  32 #define   LAYER_ROT_OFFSET              8
  33 #define   LAYER_H_FLIP                  (1 << 10)
  34 #define   LAYER_V_FLIP                  (1 << 11)
  35 #define   LAYER_ROT_MASK                (0xf << 8)
  36 #define   LAYER_COMP_MASK               (0x3 << 12)
  37 #define   LAYER_COMP_PIXEL              (0x3 << 12)
  38 #define   LAYER_COMP_PLANE              (0x2 << 12)
  39 #define   LAYER_ALPHA_OFFSET            (16)
  40 #define   LAYER_ALPHA_MASK              (0xff)
  41 #define   LAYER_ALPHA(x)                (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET)
  42 #define MALIDP_LAYER_COMPOSE            0x008
  43 #define MALIDP_LAYER_SIZE               0x00c
  44 #define   LAYER_H_VAL(x)                (((x) & 0x1fff) << 0)
  45 #define   LAYER_V_VAL(x)                (((x) & 0x1fff) << 16)
  46 #define MALIDP_LAYER_COMP_SIZE          0x010
  47 #define MALIDP_LAYER_OFFSET             0x014
  48 #define MALIDP550_LS_ENABLE             0x01c
  49 #define MALIDP550_LS_R1_IN_SIZE         0x020
  50
  51 /*
  52  * This 4-entry look-up-table is used to determine the full 8-bit alpha value
  53  * for formats with 1- or 2-bit alpha channels.
  54  * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
  55  * opacity for 2-bit formats.
  56  */
  57 #define MALIDP_ALPHA_LUT 0xffaa5500
  58
  59 static void malidp_de_plane_destroy(struct drm_plane *plane)
  60 {
  61         struct malidp_plane *mp = to_malidp_plane(plane);
  62
  63         drm_plane_cleanup(plane);
  64         kfree(mp);
  65 }
  66
  67 /*
  68  * Replicate what the default ->reset hook does: free the state pointer and
  69  * allocate a new empty object. We just need enough space to store
  70  * a malidp_plane_state instead of a drm_plane_state.
  71  */
  72 static void malidp_plane_reset(struct drm_plane *plane)
  73 {
  74         struct malidp_plane_state *state = to_malidp_plane_state(plane->state);
  75
  76         if (state)
  77                 __drm_atomic_helper_plane_destroy_state(&state->base);
  78         kfree(state);
  79         plane->state = NULL;
  80         state = kzalloc(sizeof(*state), GFP_KERNEL);
  81         if (state) {
  82                 state->base.plane = plane;
  83                 state->base.rotation = DRM_MODE_ROTATE_0;
  84                 plane->state = &state->base;
  85         }
  86 }
  87
  88 static struct
  89 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
  90 {
  91         struct malidp_plane_state *state, *m_state;
  92
  93         if (!plane->state)
  94                 return NULL;
  95
  96         state = kmalloc(sizeof(*state), GFP_KERNEL);
  97         if (!state)
  98                 return NULL;
  99
 100         m_state = to_malidp_plane_state(plane->state);
 101         __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
 102         state->rotmem_size = m_state->rotmem_size;
 103         state->format = m_state->format;
 104         state->n_planes = m_state->n_planes;
 105
 106         return &state->base;
 107 }
 108
 109 static void malidp_destroy_plane_state(struct drm_plane *plane,
 110                                        struct drm_plane_state *state)
 111 {
 112         struct malidp_plane_state *m_state = to_malidp_plane_state(state);
 113
 114         __drm_atomic_helper_plane_destroy_state(state);
 115         kfree(m_state);
 116 }
 117
 118 static void malidp_plane_atomic_print_state(struct drm_printer *p,
 119                                             const struct drm_plane_state *state)
 120 {
 121         struct malidp_plane_state *ms = to_malidp_plane_state(state);
 122
 123         drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
 124         drm_printf(p, "\tformat_id=%u\n", ms->format);
 125         drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
 126 }
 127
 128 static const struct drm_plane_funcs malidp_de_plane_funcs = {
 129         .update_plane = drm_atomic_helper_update_plane,
 130         .disable_plane = drm_atomic_helper_disable_plane,
 131         .destroy = malidp_de_plane_destroy,
 132         .reset = malidp_plane_reset,
 133         .atomic_duplicate_state = malidp_duplicate_plane_state,
 134         .atomic_destroy_state = malidp_destroy_plane_state,
 135         .atomic_print_state = malidp_plane_atomic_print_state,
 136 };
 137
 138 static int malidp_se_check_scaling(struct malidp_plane *mp,
 139                                    struct drm_plane_state *state)
 140 {
 141         struct drm_crtc_state *crtc_state =
 142                 drm_atomic_get_existing_crtc_state(state->state, state->crtc);
 143         struct malidp_crtc_state *mc;
 144         u32 src_w, src_h;
 145         int ret;
 146
 147         if (!crtc_state)
 148                 return -EINVAL;
 149
 150         mc = to_malidp_crtc_state(crtc_state);
 151
 152         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 153                                                   0, INT_MAX, true, true);
 154         if (ret)
 155                 return ret;
 156
 157         if (state->rotation & MALIDP_ROTATED_MASK) {
 158                 src_w = state->src_h >> 16;
 159                 src_h = state->src_w >> 16;
 160         } else {
 161                 src_w = state->src_w >> 16;
 162                 src_h = state->src_h >> 16;
 163         }
 164
 165         if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
 166                 /* Scaling not necessary for this plane. */
 167                 mc->scaled_planes_mask &= ~(mp->layer->id);
 168                 return 0;
 169         }
 170
 171         if (mp->layer->id & (DE_SMART | DE_GRAPHICS2))
 172                 return -EINVAL;
 173
 174         mc->scaled_planes_mask |= mp->layer->id;
 175         /* Defer scaling requirements calculation to the crtc check. */
 176         return 0;
 177 }
 178
 179 static int malidp_de_plane_check(struct drm_plane *plane,
 180                                  struct drm_plane_state *state)
 181 {
 182         struct malidp_plane *mp = to_malidp_plane(plane);
 183         struct malidp_plane_state *ms = to_malidp_plane_state(state);
 184         bool rotated = state->rotation & MALIDP_ROTATED_MASK;
 185         struct drm_framebuffer *fb;
 186         int i, ret;
 187
 188         if (!state->crtc || !state->fb)
 189                 return 0;
 190
 191         fb = state->fb;
 192
 193         ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
 194                                              mp->layer->id,
 195                                              fb->format->format);
 196         if (ms->format == MALIDP_INVALID_FORMAT_ID)
 197                 return -EINVAL;
 198
 199         ms->n_planes = fb->format->num_planes;
 200         for (i = 0; i < ms->n_planes; i++) {
 201                 u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated);
 202                 if (fb->pitches[i] & (alignment - 1)) {
 203                         DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
 204                                       fb->pitches[i], i);
 205                         return -EINVAL;
 206                 }
 207         }
 208
 209         if ((state->crtc_w > mp->hwdev->max_line_size) ||
 210             (state->crtc_h > mp->hwdev->max_line_size) ||
 211             (state->crtc_w < mp->hwdev->min_line_size) ||
 212             (state->crtc_h < mp->hwdev->min_line_size))
 213                 return -EINVAL;
 214
 215         /*
 216          * DP550/650 video layers can accept 3 plane formats only if
 217          * fb->pitches[1] == fb->pitches[2] since they don't have a
 218          * third plane stride register.
 219          */
 220         if (ms->n_planes == 3 &&
 221             !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
 222             (state->fb->pitches[1] != state->fb->pitches[2]))
 223                 return -EINVAL;
 224
 225         ret = malidp_se_check_scaling(mp, state);
 226         if (ret)
 227                 return ret;
 228
 229         /* packed RGB888 / BGR888 can't be rotated or flipped */
 230         if (state->rotation != DRM_MODE_ROTATE_0 &&
 231             (fb->format->format == DRM_FORMAT_RGB888 ||
 232              fb->format->format == DRM_FORMAT_BGR888))
 233                 return -EINVAL;
 234
 235         ms->rotmem_size = 0;
 236         if (state->rotation & MALIDP_ROTATED_MASK) {
 237                 int val;
 238
 239                 val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w,
 240                                                      state->crtc_h,
 241                                                      fb->format->format);
 242                 if (val < 0)
 243                         return val;
 244
 245                 ms->rotmem_size = val;
 246         }
 247
 248         return 0;
 249 }
 250
 251 static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
 252                                         int num_planes, unsigned int pitches[3])
 253 {
 254         int i;
 255         int num_strides = num_planes;
 256
 257         if (!mp->layer->stride_offset)
 258                 return;
 259
 260         if (num_planes == 3)
 261                 num_strides = (mp->hwdev->hw->features &
 262                                MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;
 263
 264         for (i = 0; i < num_strides; ++i)
 265                 malidp_hw_write(mp->hwdev, pitches[i],
 266                                 mp->layer->base +
 267                                 mp->layer->stride_offset + i * 4);
 268 }
 269
 270 static const s16
 271 malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = {
 272         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 273                 1192,    0, 1634,
 274                 1192, -401, -832,
 275                 1192, 2066,    0,
 276                   64,  512,  512
 277         },
 278         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
 279                 1024,    0, 1436,
 280                 1024, -352, -731,
 281                 1024, 1815,    0,
 282                    0,  512,  512
 283         },
 284         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 285                 1192,    0, 1836,
 286                 1192, -218, -546,
 287                 1192, 2163,    0,
 288                   64,  512,  512
 289         },
 290         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
 291                 1024,    0, 1613,
 292                 1024, -192, -479,
 293                 1024, 1900,    0,
 294                    0,  512,  512
 295         },
 296         [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 297                 1024,    0, 1476,
 298                 1024, -165, -572,
 299                 1024, 1884,    0,
 300                    0,  512,  512
 301         },
 302         [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = {
 303                 1024,    0, 1510,
 304                 1024, -168, -585,
 305                 1024, 1927,    0,
 306                    0,  512,  512
 307         }
 308 };
 309
 310 static void malidp_de_set_color_encoding(struct malidp_plane *plane,
 311                                          enum drm_color_encoding enc,
 312                                          enum drm_color_range range)
 313 {
 314         unsigned int i;
 315
 316         for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) {
 317                 /* coefficients are signed, two's complement values */
 318                 malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i],
 319                                 plane->layer->base + plane->layer->yuv2rgb_offset +
 320                                 i * 4);
 321         }
 322 }
 323
 324 static void malidp_de_plane_update(struct drm_plane *plane,
 325                                    struct drm_plane_state *old_state)
 326 {
 327         struct malidp_plane *mp;
 328         struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
 329         u32 src_w, src_h, dest_w, dest_h, val;
 330         int i;
 331         bool format_has_alpha = plane->state->fb->format->has_alpha;
 332
 333         mp = to_malidp_plane(plane);
 334
 335         /* convert src values from Q16 fixed point to integer */
 336         src_w = plane->state->src_w >> 16;
 337         src_h = plane->state->src_h >> 16;
 338         dest_w = plane->state->crtc_w;
 339         dest_h = plane->state->crtc_h;
 340
 341         val = malidp_hw_read(mp->hwdev, mp->layer->base);
 342         val = (val & ~LAYER_FORMAT_MASK) | ms->format;
 343         malidp_hw_write(mp->hwdev, val, mp->layer->base);
 344
 345         for (i = 0; i < ms->n_planes; i++) {
 346                 /* calculate the offset for the layer's plane registers */
 347                 u16 ptr = mp->layer->ptr + (i << 4);
 348                 dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb,
 349                                                              plane->state, i);
 350
 351                 malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);
 352                 malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);
 353         }
 354         malidp_de_set_plane_pitches(mp, ms->n_planes,
 355                                     plane->state->fb->pitches);
 356
 357         if ((plane->state->color_encoding != old_state->color_encoding) ||
 358             (plane->state->color_range != old_state->color_range))
 359                 malidp_de_set_color_encoding(mp, plane->state->color_encoding,
 360                                              plane->state->color_range);
 361
 362         malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
 363                         mp->layer->base + MALIDP_LAYER_SIZE);
 364
 365         malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
 366                         mp->layer->base + MALIDP_LAYER_COMP_SIZE);
 367
 368         malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
 369                         LAYER_V_VAL(plane->state->crtc_y),
 370                         mp->layer->base + MALIDP_LAYER_OFFSET);
 371
 372         if (mp->layer->id == DE_SMART)
 373                 malidp_hw_write(mp->hwdev,
 374                                 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
 375                                 mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
 376
 377         /* first clear the rotation bits */
 378         val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
 379         val &= ~LAYER_ROT_MASK;
 380
 381         /* setup the rotation and axis flip bits */
 382         if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
 383                 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
 384                        LAYER_ROT_OFFSET;
 385         if (plane->state->rotation & DRM_MODE_REFLECT_X)
 386                 val |= LAYER_H_FLIP;
 387         if (plane->state->rotation & DRM_MODE_REFLECT_Y)
 388                 val |= LAYER_V_FLIP;
 389
 390         val &= ~LAYER_COMP_MASK;
 391         if (format_has_alpha) {
 392
 393                 /*
 394                  * always enable pixel alpha blending until we have a way
 395                  * to change blend modes
 396                  */
 397                 val |= LAYER_COMP_PIXEL;
 398         } else {
 399
 400                 /*
 401                  * do not enable pixel alpha blending as the color channel
 402                  * does not have any alpha information
 403                  */
 404                 val |= LAYER_COMP_PLANE;
 405
 406                 /* Set layer alpha coefficient to 0xff ie fully opaque */
 407                 val |= LAYER_ALPHA(0xff);
 408         }
 409
 410         val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
 411         if (plane->state->crtc) {
 412                 struct malidp_crtc_state *m =
 413                         to_malidp_crtc_state(plane->state->crtc->state);
 414
 415                 if (m->scaler_config.scale_enable &&
 416                     m->scaler_config.plane_src_id == mp->layer->id)
 417                         val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
 418         }
 419
 420         /* set the 'enable layer' bit */
 421         val |= LAYER_ENABLE;
 422
 423         malidp_hw_write(mp->hwdev, val,
 424                         mp->layer->base + MALIDP_LAYER_CONTROL);
 425 }
 426
 427 static void malidp_de_plane_disable(struct drm_plane *plane,
 428                                     struct drm_plane_state *state)
 429 {
 430         struct malidp_plane *mp = to_malidp_plane(plane);
 431
 432         malidp_hw_clearbits(mp->hwdev,
 433                             LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK),
 434                             mp->layer->base + MALIDP_LAYER_CONTROL);
 435 }
 436
 437 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
 438         .atomic_check = malidp_de_plane_check,
 439         .atomic_update = malidp_de_plane_update,
 440         .atomic_disable = malidp_de_plane_disable,
 441 };
 442
 443 int malidp_de_planes_init(struct drm_device *drm)
 444 {
 445         struct malidp_drm *malidp = drm->dev_private;
 446         const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
 447         struct malidp_plane *plane = NULL;
 448         enum drm_plane_type plane_type;
 449         unsigned long crtcs = 1 << drm->mode_config.num_crtc;
 450         unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
 451                               DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
 452         u32 *formats;
 453         int ret, i, j, n;
 454
 455         formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
 456         if (!formats) {
 457                 ret = -ENOMEM;
 458                 goto cleanup;
 459         }
 460
 461         for (i = 0; i < map->n_layers; i++) {
 462                 u8 id = map->layers[i].id;
 463
 464                 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 465                 if (!plane) {
 466                         ret = -ENOMEM;
 467                         goto cleanup;
 468                 }
 469
 470                 /* build the list of DRM supported formats based on the map */
 471                 for (n = 0, j = 0;  j < map->n_pixel_formats; j++) {
 472                         if ((map->pixel_formats[j].layer & id) == id)
 473                                 formats[n++] = map->pixel_formats[j].format;
 474                 }
 475
 476                 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
 477                                         DRM_PLANE_TYPE_OVERLAY;
 478                 ret = drm_universal_plane_init(drm, &plane->base, crtcs,
 479                                                &malidp_de_plane_funcs, formats,
 480                                                n, NULL, plane_type, NULL);
 481                 if (ret < 0)
 482                         goto cleanup;
 483
 484                 drm_plane_helper_add(&plane->base,
 485                                      &malidp_de_plane_helper_funcs);
 486                 plane->hwdev = malidp->dev;
 487                 plane->layer = &map->layers[i];
 488
 489                 if (id == DE_SMART) {
 490                         /*
 491                          * Enable the first rectangle in the SMART layer to be
 492                          * able to use it as a drm plane.
 493                          */
 494                         malidp_hw_write(malidp->dev, 1,
 495                                         plane->layer->base + MALIDP550_LS_ENABLE);
 496                         /* Skip the features which the SMART layer doesn't have. */
 497                         continue;
 498                 }
 499
 500                 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
 501                 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
 502                                 plane->layer->base + MALIDP_LAYER_COMPOSE);
 503
 504                 /* Attach the YUV->RGB property only to video layers */
 505                 if (id & (DE_VIDEO1 | DE_VIDEO2)) {
 506                         /* default encoding for YUV->RGB is BT601 NARROW */
 507                         enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601;
 508                         enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE;
 509
 510                         ret = drm_plane_create_color_properties(&plane->base,
 511                                         BIT(DRM_COLOR_YCBCR_BT601) | \
 512                                         BIT(DRM_COLOR_YCBCR_BT709) | \
 513                                         BIT(DRM_COLOR_YCBCR_BT2020),
 514                                         BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \
 515                                         BIT(DRM_COLOR_YCBCR_FULL_RANGE),
 516                                         enc, range);
 517                         if (!ret)
 518                                 /* program the HW registers */
 519                                 malidp_de_set_color_encoding(plane, enc, range);
 520                         else
 521                                 DRM_WARN("Failed to create video layer %d color properties\n", id);
 522                 }
 523         }
 524
 525         kfree(formats);
 526
 527         return 0;
 528
 529 cleanup:
 530         kfree(formats);
 531
 532         return ret;
 533 }