drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SWSMU_CODE_LAYER_L3
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_smu.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_atombios.h"
  35 #include "smu_v14_0.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "amdgpu_ras.h"
  39 #include "smu_cmn.h"
  40
  41 #include "asic_reg/mp/mp_14_0_0_offset.h"
  42 #include "asic_reg/mp/mp_14_0_0_sh_mask.h"
  43
  44 /*
  45  * DO NOT use these for err/warn/info/debug messages.
  46  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  47  * They are more MGPU friendly.
  48  */
  49 #undef pr_err
  50 #undef pr_warn
  51 #undef pr_info
  52 #undef pr_debug
  53
  54 MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin");
  55
  56 int smu_v14_0_init_microcode(struct smu_context *smu)
  57 {
  58         struct amdgpu_device *adev = smu->adev;
  59         char fw_name[30];
  60         char ucode_prefix[15];
  61         int err = 0;
  62         const struct smc_firmware_header_v1_0 *hdr;
  63         const struct common_firmware_header *header;
  64         struct amdgpu_firmware_info *ucode = NULL;
  65
  66         /* doesn't need to load smu firmware in IOV mode */
  67         if (amdgpu_sriov_vf(adev))
  68                 return 0;
  69
  70         amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
  71
  72         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
  73
  74         err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name);
  75         if (err)
  76                 goto out;
  77
  78         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
  79         amdgpu_ucode_print_smc_hdr(&hdr->header);
  80         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
  81
  82         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
  83                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
  84                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
  85                 ucode->fw = adev->pm.fw;
  86                 header = (const struct common_firmware_header *)ucode->fw->data;
  87                 adev->firmware.fw_size +=
  88                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  89         }
  90
  91 out:
  92         if (err)
  93                 amdgpu_ucode_release(&adev->pm.fw);
  94         return err;
  95 }
  96
  97 void smu_v14_0_fini_microcode(struct smu_context *smu)
  98 {
  99         struct amdgpu_device *adev = smu->adev;
 100
 101         amdgpu_ucode_release(&adev->pm.fw);
 102         adev->pm.fw_version = 0;
 103 }
 104
 105 int smu_v14_0_load_microcode(struct smu_context *smu)
 106 {
 107 #if 0
 108         struct amdgpu_device *adev = smu->adev;
 109         const uint32_t *src;
 110         const struct smc_firmware_header_v1_0 *hdr;
 111         uint32_t addr_start = MP1_SRAM;
 112         uint32_t i;
 113         uint32_t smc_fw_size;
 114         uint32_t mp1_fw_flags;
 115
 116         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 117         src = (const uint32_t *)(adev->pm.fw->data +
 118                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 119         smc_fw_size = hdr->header.ucode_size_bytes;
 120
 121         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 122                 WREG32_PCIE(addr_start, src[i]);
 123                 addr_start += 4;
 124         }
 125
 126         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 127                     1 & MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
 128         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 129                     1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
 130
 131         for (i = 0; i < adev->usec_timeout; i++) {
 132                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 133                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 134                 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 135                     MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 136                         break;
 137                 udelay(1);
 138         }
 139
 140         if (i == adev->usec_timeout)
 141                 return -ETIME;
 142
 143 #endif
 144         return 0;
 145
 146 }
 147
 148 int smu_v14_0_init_pptable_microcode(struct smu_context *smu)
 149 {
 150         struct amdgpu_device *adev = smu->adev;
 151         struct amdgpu_firmware_info *ucode = NULL;
 152         uint32_t size = 0, pptable_id = 0;
 153         int ret = 0;
 154         void *table;
 155
 156         /* doesn't need to load smu firmware in IOV mode */
 157         if (amdgpu_sriov_vf(adev))
 158                 return 0;
 159
 160         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 161                 return 0;
 162
 163         if (!adev->scpm_enabled)
 164                 return 0;
 165
 166         /* override pptable_id from driver parameter */
 167         if (amdgpu_smu_pptable_id >= 0) {
 168                 pptable_id = amdgpu_smu_pptable_id;
 169                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 170         } else {
 171                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 172         }
 173
 174         /* "pptable_id == 0" means vbios carries the pptable. */
 175         if (!pptable_id)
 176                 return 0;
 177
 178         ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 179         if (ret)
 180                 return ret;
 181
 182         smu->pptable_firmware.data = table;
 183         smu->pptable_firmware.size = size;
 184
 185         ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
 186         ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
 187         ucode->fw = &smu->pptable_firmware;
 188         adev->firmware.fw_size +=
 189                 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
 190
 191         return 0;
 192 }
 193
 194 int smu_v14_0_check_fw_status(struct smu_context *smu)
 195 {
 196         struct amdgpu_device *adev = smu->adev;
 197         uint32_t mp1_fw_flags;
 198
 199         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 200                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 201
 202         if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 203             MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 204                 return 0;
 205
 206         return -EIO;
 207 }
 208
 209 int smu_v14_0_check_fw_version(struct smu_context *smu)
 210 {
 211         struct amdgpu_device *adev = smu->adev;
 212         uint32_t if_version = 0xff, smu_version = 0xff;
 213         uint8_t smu_program, smu_major, smu_minor, smu_debug;
 214         int ret = 0;
 215
 216         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 217         if (ret)
 218                 return ret;
 219
 220         smu_program = (smu_version >> 24) & 0xff;
 221         smu_major = (smu_version >> 16) & 0xff;
 222         smu_minor = (smu_version >> 8) & 0xff;
 223         smu_debug = (smu_version >> 0) & 0xff;
 224         if (smu->is_apu)
 225                 adev->pm.fw_version = smu_version;
 226
 227         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
 228         case IP_VERSION(14, 0, 2):
 229                 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
 230                 break;
 231         case IP_VERSION(14, 0, 0):
 232                 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
 233                 break;
 234         default:
 235                 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
 236                         amdgpu_ip_version(adev, MP1_HWIP, 0));
 237                 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_INV;
 238                 break;
 239         }
 240
 241         if (adev->pm.fw)
 242                 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
 243                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 244
 245         /*
 246          * 1. if_version mismatch is not critical as our fw is designed
 247          * to be backward compatible.
 248          * 2. New fw usually brings some optimizations. But that's visible
 249          * only on the paired driver.
 250          * Considering above, we just leave user a verbal message instead
 251          * of halt driver loading.
 252          */
 253         if (if_version != smu->smc_driver_if_version) {
 254                 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 255                          "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
 256                          smu->smc_driver_if_version, if_version,
 257                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 258                 dev_info(adev->dev, "SMU driver if version not matched\n");
 259         }
 260
 261         return ret;
 262 }
 263
 264 static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 265 {
 266         struct amdgpu_device *adev = smu->adev;
 267         uint32_t ppt_offset_bytes;
 268         const struct smc_firmware_header_v2_0 *v2;
 269
 270         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 271
 272         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 273         *size = le32_to_cpu(v2->ppt_size_bytes);
 274         *table = (uint8_t *)v2 + ppt_offset_bytes;
 275
 276         return 0;
 277 }
 278
 279 static int smu_v14_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 280                                       uint32_t *size, uint32_t pptable_id)
 281 {
 282         struct amdgpu_device *adev = smu->adev;
 283         const struct smc_firmware_header_v2_1 *v2_1;
 284         struct smc_soft_pptable_entry *entries;
 285         uint32_t pptable_count = 0;
 286         int i = 0;
 287
 288         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 289         entries = (struct smc_soft_pptable_entry *)
 290                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 291         pptable_count = le32_to_cpu(v2_1->pptable_count);
 292         for (i = 0; i < pptable_count; i++) {
 293                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 294                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 295                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 296                         break;
 297                 }
 298         }
 299
 300         if (i == pptable_count)
 301                 return -EINVAL;
 302
 303         return 0;
 304 }
 305
 306 static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
 307 {
 308         struct amdgpu_device *adev = smu->adev;
 309         uint16_t atom_table_size;
 310         uint8_t frev, crev;
 311         int ret, index;
 312
 313         dev_info(adev->dev, "use vbios provided pptable\n");
 314         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 315                                             powerplayinfo);
 316
 317         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 318                                              (uint8_t **)table);
 319         if (ret)
 320                 return ret;
 321
 322         if (size)
 323                 *size = atom_table_size;
 324
 325         return 0;
 326 }
 327
 328 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
 329                                         void **table,
 330                                         uint32_t *size,
 331                                         uint32_t pptable_id)
 332 {
 333         const struct smc_firmware_header_v1_0 *hdr;
 334         struct amdgpu_device *adev = smu->adev;
 335         uint16_t version_major, version_minor;
 336         int ret;
 337
 338         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 339         if (!hdr)
 340                 return -EINVAL;
 341
 342         dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
 343
 344         version_major = le16_to_cpu(hdr->header.header_version_major);
 345         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 346         if (version_major != 2) {
 347                 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
 348                         version_major, version_minor);
 349                 return -EINVAL;
 350         }
 351
 352         switch (version_minor) {
 353         case 0:
 354                 ret = smu_v14_0_set_pptable_v2_0(smu, table, size);
 355                 break;
 356         case 1:
 357                 ret = smu_v14_0_set_pptable_v2_1(smu, table, size, pptable_id);
 358                 break;
 359         default:
 360                 ret = -EINVAL;
 361                 break;
 362         }
 363
 364         return ret;
 365 }
 366
 367 int smu_v14_0_setup_pptable(struct smu_context *smu)
 368 {
 369         struct amdgpu_device *adev = smu->adev;
 370         uint32_t size = 0, pptable_id = 0;
 371         void *table;
 372         int ret = 0;
 373
 374         /* override pptable_id from driver parameter */
 375         if (amdgpu_smu_pptable_id >= 0) {
 376                 pptable_id = amdgpu_smu_pptable_id;
 377                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 378         } else {
 379                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 380         }
 381
 382         /* force using vbios pptable in sriov mode */
 383         if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
 384                 ret = smu_v14_0_get_pptable_from_vbios(smu, &table, &size);
 385         else
 386                 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 387
 388         if (ret)
 389                 return ret;
 390
 391         if (!smu->smu_table.power_play_table)
 392                 smu->smu_table.power_play_table = table;
 393         if (!smu->smu_table.power_play_table_size)
 394                 smu->smu_table.power_play_table_size = size;
 395
 396         return 0;
 397 }
 398
 399 int smu_v14_0_init_smc_tables(struct smu_context *smu)
 400 {
 401         struct smu_table_context *smu_table = &smu->smu_table;
 402         struct smu_table *tables = smu_table->tables;
 403         int ret = 0;
 404
 405         smu_table->driver_pptable =
 406                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 407         if (!smu_table->driver_pptable) {
 408                 ret = -ENOMEM;
 409                 goto err0_out;
 410         }
 411
 412         smu_table->max_sustainable_clocks =
 413                 kzalloc(sizeof(struct smu_14_0_max_sustainable_clocks), GFP_KERNEL);
 414         if (!smu_table->max_sustainable_clocks) {
 415                 ret = -ENOMEM;
 416                 goto err1_out;
 417         }
 418
 419         if (tables[SMU_TABLE_OVERDRIVE].size) {
 420                 smu_table->overdrive_table =
 421                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 422                 if (!smu_table->overdrive_table) {
 423                         ret = -ENOMEM;
 424                         goto err2_out;
 425                 }
 426
 427                 smu_table->boot_overdrive_table =
 428                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 429                 if (!smu_table->boot_overdrive_table) {
 430                         ret = -ENOMEM;
 431                         goto err3_out;
 432                 }
 433         }
 434
 435         smu_table->combo_pptable =
 436                 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
 437         if (!smu_table->combo_pptable) {
 438                 ret = -ENOMEM;
 439                 goto err4_out;
 440         }
 441
 442         return 0;
 443
 444 err4_out:
 445         kfree(smu_table->boot_overdrive_table);
 446 err3_out:
 447         kfree(smu_table->overdrive_table);
 448 err2_out:
 449         kfree(smu_table->max_sustainable_clocks);
 450 err1_out:
 451         kfree(smu_table->driver_pptable);
 452 err0_out:
 453         return ret;
 454 }
 455
 456 int smu_v14_0_fini_smc_tables(struct smu_context *smu)
 457 {
 458         struct smu_table_context *smu_table = &smu->smu_table;
 459         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 460
 461         kfree(smu_table->gpu_metrics_table);
 462         kfree(smu_table->combo_pptable);
 463         kfree(smu_table->boot_overdrive_table);
 464         kfree(smu_table->overdrive_table);
 465         kfree(smu_table->max_sustainable_clocks);
 466         kfree(smu_table->driver_pptable);
 467         smu_table->gpu_metrics_table = NULL;
 468         smu_table->combo_pptable = NULL;
 469         smu_table->boot_overdrive_table = NULL;
 470         smu_table->overdrive_table = NULL;
 471         smu_table->max_sustainable_clocks = NULL;
 472         smu_table->driver_pptable = NULL;
 473         kfree(smu_table->hardcode_pptable);
 474         smu_table->hardcode_pptable = NULL;
 475
 476         kfree(smu_table->ecc_table);
 477         kfree(smu_table->metrics_table);
 478         kfree(smu_table->watermarks_table);
 479         smu_table->ecc_table = NULL;
 480         smu_table->metrics_table = NULL;
 481         smu_table->watermarks_table = NULL;
 482         smu_table->metrics_time = 0;
 483
 484         kfree(smu_dpm->dpm_context);
 485         kfree(smu_dpm->golden_dpm_context);
 486         kfree(smu_dpm->dpm_current_power_state);
 487         kfree(smu_dpm->dpm_request_power_state);
 488         smu_dpm->dpm_context = NULL;
 489         smu_dpm->golden_dpm_context = NULL;
 490         smu_dpm->dpm_context_size = 0;
 491         smu_dpm->dpm_current_power_state = NULL;
 492         smu_dpm->dpm_request_power_state = NULL;
 493
 494         return 0;
 495 }
 496
 497 int smu_v14_0_init_power(struct smu_context *smu)
 498 {
 499         struct smu_power_context *smu_power = &smu->smu_power;
 500
 501         if (smu_power->power_context || smu_power->power_context_size != 0)
 502                 return -EINVAL;
 503
 504         smu_power->power_context = kzalloc(sizeof(struct smu_14_0_dpm_context),
 505                                            GFP_KERNEL);
 506         if (!smu_power->power_context)
 507                 return -ENOMEM;
 508         smu_power->power_context_size = sizeof(struct smu_14_0_dpm_context);
 509
 510         return 0;
 511 }
 512
 513 int smu_v14_0_fini_power(struct smu_context *smu)
 514 {
 515         struct smu_power_context *smu_power = &smu->smu_power;
 516
 517         if (!smu_power->power_context || smu_power->power_context_size == 0)
 518                 return -EINVAL;
 519
 520         kfree(smu_power->power_context);
 521         smu_power->power_context = NULL;
 522         smu_power->power_context_size = 0;
 523
 524         return 0;
 525 }
 526
 527 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu)
 528 {
 529         int ret, index;
 530         uint16_t size;
 531         uint8_t frev, crev;
 532         struct atom_common_table_header *header;
 533         struct atom_firmware_info_v3_4 *v_3_4;
 534         struct atom_firmware_info_v3_3 *v_3_3;
 535         struct atom_firmware_info_v3_1 *v_3_1;
 536         struct atom_smu_info_v3_6 *smu_info_v3_6;
 537         struct atom_smu_info_v4_0 *smu_info_v4_0;
 538
 539         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 540                                             firmwareinfo);
 541
 542         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 543                                              (uint8_t **)&header);
 544         if (ret)
 545                 return ret;
 546
 547         if (header->format_revision != 3) {
 548                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu14\n");
 549                 return -EINVAL;
 550         }
 551
 552         switch (header->content_revision) {
 553         case 0:
 554         case 1:
 555         case 2:
 556                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 557                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 558                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 559                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 560                 smu->smu_table.boot_values.socclk = 0;
 561                 smu->smu_table.boot_values.dcefclk = 0;
 562                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 563                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 564                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 565                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 566                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 567                 smu->smu_table.boot_values.pp_table_id = 0;
 568                 break;
 569         case 3:
 570                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 571                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 572                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 573                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 574                 smu->smu_table.boot_values.socclk = 0;
 575                 smu->smu_table.boot_values.dcefclk = 0;
 576                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 577                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 578                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 579                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 580                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 581                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 582                 break;
 583         case 4:
 584         default:
 585                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 586                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 587                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 588                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 589                 smu->smu_table.boot_values.socclk = 0;
 590                 smu->smu_table.boot_values.dcefclk = 0;
 591                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 592                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 593                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 594                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 595                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 596                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 597                 break;
 598         }
 599
 600         smu->smu_table.boot_values.format_revision = header->format_revision;
 601         smu->smu_table.boot_values.content_revision = header->content_revision;
 602
 603         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 604                                             smu_info);
 605         if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 606                                             (uint8_t **)&header)) {
 607
 608                 if ((frev == 3) && (crev == 6)) {
 609                         smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
 610
 611                         smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
 612                         smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
 613                         smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
 614                         smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
 615                 } else if ((frev == 3) && (crev == 1)) {
 616                         return 0;
 617                 } else if ((frev == 4) && (crev == 0)) {
 618                         smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
 619
 620                         smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
 621                         smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
 622                         smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
 623                         smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
 624                         smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
 625                 } else {
 626                         dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
 627                                                 (uint32_t)frev, (uint32_t)crev);
 628                 }
 629         }
 630
 631         return 0;
 632 }
 633
 634
 635 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu)
 636 {
 637         struct smu_table_context *smu_table = &smu->smu_table;
 638         struct smu_table *memory_pool = &smu_table->memory_pool;
 639         int ret = 0;
 640         uint64_t address;
 641         uint32_t address_low, address_high;
 642
 643         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 644                 return ret;
 645
 646         address = memory_pool->mc_address;
 647         address_high = (uint32_t)upper_32_bits(address);
 648         address_low  = (uint32_t)lower_32_bits(address);
 649
 650         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 651                                               address_high, NULL);
 652         if (ret)
 653                 return ret;
 654         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 655                                               address_low, NULL);
 656         if (ret)
 657                 return ret;
 658         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 659                                               (uint32_t)memory_pool->size, NULL);
 660         if (ret)
 661                 return ret;
 662
 663         return ret;
 664 }
 665
 666 int smu_v14_0_set_driver_table_location(struct smu_context *smu)
 667 {
 668         struct smu_table *driver_table = &smu->smu_table.driver_table;
 669         int ret = 0;
 670
 671         if (driver_table->mc_address) {
 672                 ret = smu_cmn_send_smc_msg_with_param(smu,
 673                                                       SMU_MSG_SetDriverDramAddrHigh,
 674                                                       upper_32_bits(driver_table->mc_address),
 675                                                       NULL);
 676                 if (!ret)
 677                         ret = smu_cmn_send_smc_msg_with_param(smu,
 678                                                               SMU_MSG_SetDriverDramAddrLow,
 679                                                               lower_32_bits(driver_table->mc_address),
 680                                                               NULL);
 681         }
 682
 683         return ret;
 684 }
 685
 686 int smu_v14_0_set_tool_table_location(struct smu_context *smu)
 687 {
 688         int ret = 0;
 689         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 690
 691         if (tool_table->mc_address) {
 692                 ret = smu_cmn_send_smc_msg_with_param(smu,
 693                                                       SMU_MSG_SetToolsDramAddrHigh,
 694                                                       upper_32_bits(tool_table->mc_address),
 695                                                       NULL);
 696                 if (!ret)
 697                         ret = smu_cmn_send_smc_msg_with_param(smu,
 698                                                               SMU_MSG_SetToolsDramAddrLow,
 699                                                               lower_32_bits(tool_table->mc_address),
 700                                                               NULL);
 701         }
 702
 703         return ret;
 704 }
 705
 706 int smu_v14_0_set_allowed_mask(struct smu_context *smu)
 707 {
 708         struct smu_feature *feature = &smu->smu_feature;
 709         int ret = 0;
 710         uint32_t feature_mask[2];
 711
 712         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
 713             feature->feature_num < 64)
 714                 return -EINVAL;
 715
 716         bitmap_to_arr32(feature_mask, feature->allowed, 64);
 717
 718         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 719                                               feature_mask[1], NULL);
 720         if (ret)
 721                 return ret;
 722
 723         return smu_cmn_send_smc_msg_with_param(smu,
 724                                                SMU_MSG_SetAllowedFeaturesMaskLow,
 725                                                feature_mask[0],
 726                                                NULL);
 727 }
 728
 729 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
 730 {
 731         int ret = 0;
 732         struct amdgpu_device *adev = smu->adev;
 733
 734         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
 735         case IP_VERSION(14, 0, 2):
 736         case IP_VERSION(14, 0, 0):
 737                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 738                         return 0;
 739                 if (enable)
 740                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 741                 else
 742                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 743                 break;
 744         default:
 745                 break;
 746         }
 747
 748         return ret;
 749 }
 750
 751 int smu_v14_0_system_features_control(struct smu_context *smu,
 752                                       bool en)
 753 {
 754         return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 755                                           SMU_MSG_DisableAllSmuFeatures), NULL);
 756 }
 757
 758 int smu_v14_0_notify_display_change(struct smu_context *smu)
 759 {
 760         int ret = 0;
 761
 762         if (!smu->pm_enabled)
 763                 return ret;
 764
 765         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 766             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 767                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 768
 769         return ret;
 770 }
 771
 772 int smu_v14_0_get_current_power_limit(struct smu_context *smu,
 773                                       uint32_t *power_limit)
 774 {
 775         int power_src;
 776         int ret = 0;
 777
 778         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 779                 return -EINVAL;
 780
 781         power_src = smu_cmn_to_asic_specific_index(smu,
 782                                                    CMN2ASIC_MAPPING_PWR,
 783                                                    smu->adev->pm.ac_power ?
 784                                                    SMU_POWER_SOURCE_AC :
 785                                                    SMU_POWER_SOURCE_DC);
 786         if (power_src < 0)
 787                 return -EINVAL;
 788
 789         ret = smu_cmn_send_smc_msg_with_param(smu,
 790                                               SMU_MSG_GetPptLimit,
 791                                               power_src << 16,
 792                                               power_limit);
 793         if (ret)
 794                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 795
 796         return ret;
 797 }
 798
 799 int smu_v14_0_set_power_limit(struct smu_context *smu,
 800                               enum smu_ppt_limit_type limit_type,
 801                               uint32_t limit)
 802 {
 803         int ret = 0;
 804
 805         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
 806                 return -EINVAL;
 807
 808         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 809                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 810                 return -EOPNOTSUPP;
 811         }
 812
 813         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
 814         if (ret) {
 815                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 816                 return ret;
 817         }
 818
 819         smu->current_power_limit = limit;
 820
 821         return 0;
 822 }
 823
 824 static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
 825                                    struct amdgpu_irq_src *source,
 826                                    unsigned tyep,
 827                                    enum amdgpu_interrupt_state state)
 828 {
 829         uint32_t val = 0;
 830
 831         switch (state) {
 832         case AMDGPU_IRQ_STATE_DISABLE:
 833                 /* For THM irqs */
 834                 // TODO
 835
 836                 /* For MP1 SW irqs */
 837                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
 838                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
 839                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
 840
 841                 break;
 842         case AMDGPU_IRQ_STATE_ENABLE:
 843                 /* For THM irqs */
 844                 // TODO
 845
 846                 /* For MP1 SW irqs */
 847                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
 848                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
 849                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
 850                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
 851
 852                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
 853                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
 854                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
 855
 856                 break;
 857         default:
 858                 break;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static int smu_v14_0_irq_process(struct amdgpu_device *adev,
 865                                  struct amdgpu_irq_src *source,
 866                                  struct amdgpu_iv_entry *entry)
 867 {
 868         // TODO
 869
 870         return 0;
 871 }
 872
 873 static const struct amdgpu_irq_src_funcs smu_v14_0_irq_funcs = {
 874         .set = smu_v14_0_set_irq_state,
 875         .process = smu_v14_0_irq_process,
 876 };
 877
 878 int smu_v14_0_register_irq_handler(struct smu_context *smu)
 879 {
 880         struct amdgpu_device *adev = smu->adev;
 881         struct amdgpu_irq_src *irq_src = &smu->irq_source;
 882         int ret = 0;
 883
 884         if (amdgpu_sriov_vf(adev))
 885                 return 0;
 886
 887         irq_src->num_types = 1;
 888         irq_src->funcs = &smu_v14_0_irq_funcs;
 889
 890         // TODO: THM related
 891
 892         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
 893                                 0xfe,
 894                                 irq_src);
 895         if (ret)
 896                 return ret;
 897
 898         return ret;
 899 }
 900
 901 static int smu_v14_0_wait_for_reset_complete(struct smu_context *smu,
 902                                              uint64_t event_arg)
 903 {
 904         int ret = 0;
 905
 906         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
 907         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
 908
 909         return ret;
 910 }
 911
 912 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
 913                              uint64_t event_arg)
 914 {
 915         int ret = -EINVAL;
 916
 917         switch (event) {
 918         case SMU_EVENT_RESET_COMPLETE:
 919                 ret = smu_v14_0_wait_for_reset_complete(smu, event_arg);
 920                 break;
 921         default:
 922                 break;
 923         }
 924
 925         return ret;
 926 }
 927
 928 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
 929                                     uint32_t *min, uint32_t *max)
 930 {
 931         int ret = 0, clk_id = 0;
 932         uint32_t param = 0;
 933         uint32_t clock_limit;
 934
 935         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
 936                 switch (clk_type) {
 937                 case SMU_MCLK:
 938                 case SMU_UCLK:
 939                         clock_limit = smu->smu_table.boot_values.uclk;
 940                         break;
 941                 case SMU_GFXCLK:
 942                 case SMU_SCLK:
 943                         clock_limit = smu->smu_table.boot_values.gfxclk;
 944                         break;
 945                 case SMU_SOCCLK:
 946                         clock_limit = smu->smu_table.boot_values.socclk;
 947                         break;
 948                 default:
 949                         clock_limit = 0;
 950                         break;
 951                 }
 952
 953                 /* clock in Mhz unit */
 954                 if (min)
 955                         *min = clock_limit / 100;
 956                 if (max)
 957                         *max = clock_limit / 100;
 958
 959                 return 0;
 960         }
 961
 962         clk_id = smu_cmn_to_asic_specific_index(smu,
 963                                                 CMN2ASIC_MAPPING_CLK,
 964                                                 clk_type);
 965         if (clk_id < 0) {
 966                 ret = -EINVAL;
 967                 goto failed;
 968         }
 969         param = (clk_id & 0xffff) << 16;
 970
 971         if (max) {
 972                 if (smu->adev->pm.ac_power)
 973                         ret = smu_cmn_send_smc_msg_with_param(smu,
 974                                                               SMU_MSG_GetMaxDpmFreq,
 975                                                               param,
 976                                                               max);
 977                 else
 978                         ret = smu_cmn_send_smc_msg_with_param(smu,
 979                                                               SMU_MSG_GetDcModeMaxDpmFreq,
 980                                                               param,
 981                                                               max);
 982                 if (ret)
 983                         goto failed;
 984         }
 985
 986         if (min) {
 987                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
 988                 if (ret)
 989                         goto failed;
 990         }
 991
 992 failed:
 993         return ret;
 994 }
 995
 996 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu,
 997                                           enum smu_clk_type clk_type,
 998                                           uint32_t min,
 999                                           uint32_t max)
1000 {
1001         int ret = 0, clk_id = 0;
1002         uint32_t param;
1003
1004         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1005                 return 0;
1006
1007         clk_id = smu_cmn_to_asic_specific_index(smu,
1008                                                 CMN2ASIC_MAPPING_CLK,
1009                                                 clk_type);
1010         if (clk_id < 0)
1011                 return clk_id;
1012
1013         if (max > 0) {
1014                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1015                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1016                                                       param, NULL);
1017                 if (ret)
1018                         goto out;
1019         }
1020
1021         if (min > 0) {
1022                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1023                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1024                                                       param, NULL);
1025                 if (ret)
1026                         goto out;
1027         }
1028
1029 out:
1030         return ret;
1031 }
1032
1033 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
1034                                           enum smu_clk_type clk_type,
1035                                           uint32_t min,
1036                                           uint32_t max)
1037 {
1038         int ret = 0, clk_id = 0;
1039         uint32_t param;
1040
1041         if (min <= 0 && max <= 0)
1042                 return -EINVAL;
1043
1044         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1045                 return 0;
1046
1047         clk_id = smu_cmn_to_asic_specific_index(smu,
1048                                                 CMN2ASIC_MAPPING_CLK,
1049                                                 clk_type);
1050         if (clk_id < 0)
1051                 return clk_id;
1052
1053         if (max > 0) {
1054                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1055                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1056                                                       param, NULL);
1057                 if (ret)
1058                         return ret;
1059         }
1060
1061         if (min > 0) {
1062                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1063                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1064                                                       param, NULL);
1065                 if (ret)
1066                         return ret;
1067         }
1068
1069         return ret;
1070 }
1071
1072 int smu_v14_0_set_performance_level(struct smu_context *smu,
1073                                     enum amd_dpm_forced_level level)
1074 {
1075         struct smu_14_0_dpm_context *dpm_context =
1076                 smu->smu_dpm.dpm_context;
1077         struct smu_14_0_dpm_table *gfx_table =
1078                 &dpm_context->dpm_tables.gfx_table;
1079         struct smu_14_0_dpm_table *mem_table =
1080                 &dpm_context->dpm_tables.uclk_table;
1081         struct smu_14_0_dpm_table *soc_table =
1082                 &dpm_context->dpm_tables.soc_table;
1083         struct smu_14_0_dpm_table *vclk_table =
1084                 &dpm_context->dpm_tables.vclk_table;
1085         struct smu_14_0_dpm_table *dclk_table =
1086                 &dpm_context->dpm_tables.dclk_table;
1087         struct smu_14_0_dpm_table *fclk_table =
1088                 &dpm_context->dpm_tables.fclk_table;
1089         struct smu_umd_pstate_table *pstate_table =
1090                 &smu->pstate_table;
1091         struct amdgpu_device *adev = smu->adev;
1092         uint32_t sclk_min = 0, sclk_max = 0;
1093         uint32_t mclk_min = 0, mclk_max = 0;
1094         uint32_t socclk_min = 0, socclk_max = 0;
1095         uint32_t vclk_min = 0, vclk_max = 0;
1096         uint32_t dclk_min = 0, dclk_max = 0;
1097         uint32_t fclk_min = 0, fclk_max = 0;
1098         int ret = 0, i;
1099
1100         switch (level) {
1101         case AMD_DPM_FORCED_LEVEL_HIGH:
1102                 sclk_min = sclk_max = gfx_table->max;
1103                 mclk_min = mclk_max = mem_table->max;
1104                 socclk_min = socclk_max = soc_table->max;
1105                 vclk_min = vclk_max = vclk_table->max;
1106                 dclk_min = dclk_max = dclk_table->max;
1107                 fclk_min = fclk_max = fclk_table->max;
1108                 break;
1109         case AMD_DPM_FORCED_LEVEL_LOW:
1110                 sclk_min = sclk_max = gfx_table->min;
1111                 mclk_min = mclk_max = mem_table->min;
1112                 socclk_min = socclk_max = soc_table->min;
1113                 vclk_min = vclk_max = vclk_table->min;
1114                 dclk_min = dclk_max = dclk_table->min;
1115                 fclk_min = fclk_max = fclk_table->min;
1116                 break;
1117         case AMD_DPM_FORCED_LEVEL_AUTO:
1118                 sclk_min = gfx_table->min;
1119                 sclk_max = gfx_table->max;
1120                 mclk_min = mem_table->min;
1121                 mclk_max = mem_table->max;
1122                 socclk_min = soc_table->min;
1123                 socclk_max = soc_table->max;
1124                 vclk_min = vclk_table->min;
1125                 vclk_max = vclk_table->max;
1126                 dclk_min = dclk_table->min;
1127                 dclk_max = dclk_table->max;
1128                 fclk_min = fclk_table->min;
1129                 fclk_max = fclk_table->max;
1130                 break;
1131         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1132                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1133                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1134                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1135                 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1136                 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1137                 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1138                 break;
1139         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1140                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1141                 break;
1142         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1143                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1144                 break;
1145         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1146                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1147                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1148                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1149                 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1150                 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1151                 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1152                 break;
1153         case AMD_DPM_FORCED_LEVEL_MANUAL:
1154         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1155                 return 0;
1156         default:
1157                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1158                 return -EINVAL;
1159         }
1160
1161         if (sclk_min && sclk_max) {
1162                 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1163                                                             SMU_GFXCLK,
1164                                                             sclk_min,
1165                                                             sclk_max);
1166                 if (ret)
1167                         return ret;
1168
1169                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1170                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1171         }
1172
1173         if (mclk_min && mclk_max) {
1174                 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1175                                                             SMU_MCLK,
1176                                                             mclk_min,
1177                                                             mclk_max);
1178                 if (ret)
1179                         return ret;
1180
1181                 pstate_table->uclk_pstate.curr.min = mclk_min;
1182                 pstate_table->uclk_pstate.curr.max = mclk_max;
1183         }
1184
1185         if (socclk_min && socclk_max) {
1186                 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1187                                                             SMU_SOCCLK,
1188                                                             socclk_min,
1189                                                             socclk_max);
1190                 if (ret)
1191                         return ret;
1192
1193                 pstate_table->socclk_pstate.curr.min = socclk_min;
1194                 pstate_table->socclk_pstate.curr.max = socclk_max;
1195         }
1196
1197         if (vclk_min && vclk_max) {
1198                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1199                         if (adev->vcn.harvest_config & (1 << i))
1200                                 continue;
1201                         ret = smu_v14_0_set_soft_freq_limited_range(smu,
1202                                                                     i ? SMU_VCLK1 : SMU_VCLK,
1203                                                                     vclk_min,
1204                                                                     vclk_max);
1205                         if (ret)
1206                                 return ret;
1207                 }
1208                 pstate_table->vclk_pstate.curr.min = vclk_min;
1209                 pstate_table->vclk_pstate.curr.max = vclk_max;
1210         }
1211
1212         if (dclk_min && dclk_max) {
1213                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1214                         if (adev->vcn.harvest_config & (1 << i))
1215                                 continue;
1216                         ret = smu_v14_0_set_soft_freq_limited_range(smu,
1217                                                                     i ? SMU_DCLK1 : SMU_DCLK,
1218                                                                     dclk_min,
1219                                                                     dclk_max);
1220                         if (ret)
1221                                 return ret;
1222                 }
1223                 pstate_table->dclk_pstate.curr.min = dclk_min;
1224                 pstate_table->dclk_pstate.curr.max = dclk_max;
1225         }
1226
1227         if (fclk_min && fclk_max) {
1228                 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1229                                                             SMU_FCLK,
1230                                                             fclk_min,
1231                                                             fclk_max);
1232                 if (ret)
1233                         return ret;
1234
1235                 pstate_table->fclk_pstate.curr.min = fclk_min;
1236                 pstate_table->fclk_pstate.curr.max = fclk_max;
1237         }
1238
1239         return ret;
1240 }
1241
1242 int smu_v14_0_set_power_source(struct smu_context *smu,
1243                                enum smu_power_src_type power_src)
1244 {
1245         int pwr_source;
1246
1247         pwr_source = smu_cmn_to_asic_specific_index(smu,
1248                                                     CMN2ASIC_MAPPING_PWR,
1249                                                     (uint32_t)power_src);
1250         if (pwr_source < 0)
1251                 return -EINVAL;
1252
1253         return smu_cmn_send_smc_msg_with_param(smu,
1254                                                SMU_MSG_NotifyPowerSource,
1255                                                pwr_source,
1256                                                NULL);
1257 }
1258
1259 static int smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu,
1260                                            enum smu_clk_type clk_type,
1261                                            uint16_t level,
1262                                            uint32_t *value)
1263 {
1264         int ret = 0, clk_id = 0;
1265         uint32_t param;
1266
1267         if (!value)
1268                 return -EINVAL;
1269
1270         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1271                 return 0;
1272
1273         clk_id = smu_cmn_to_asic_specific_index(smu,
1274                                                 CMN2ASIC_MAPPING_CLK,
1275                                                 clk_type);
1276         if (clk_id < 0)
1277                 return clk_id;
1278
1279         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1280
1281         ret = smu_cmn_send_smc_msg_with_param(smu,
1282                                               SMU_MSG_GetDpmFreqByIndex,
1283                                               param,
1284                                               value);
1285         if (ret)
1286                 return ret;
1287
1288         *value = *value & 0x7fffffff;
1289
1290         return ret;
1291 }
1292
1293 static int smu_v14_0_get_dpm_level_count(struct smu_context *smu,
1294                                          enum smu_clk_type clk_type,
1295                                          uint32_t *value)
1296 {
1297         int ret;
1298
1299         ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1300
1301         return ret;
1302 }
1303
1304 static int smu_v14_0_get_fine_grained_status(struct smu_context *smu,
1305                                              enum smu_clk_type clk_type,
1306                                              bool *is_fine_grained_dpm)
1307 {
1308         int ret = 0, clk_id = 0;
1309         uint32_t param;
1310         uint32_t value;
1311
1312         if (!is_fine_grained_dpm)
1313                 return -EINVAL;
1314
1315         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1316                 return 0;
1317
1318         clk_id = smu_cmn_to_asic_specific_index(smu,
1319                                                 CMN2ASIC_MAPPING_CLK,
1320                                                 clk_type);
1321         if (clk_id < 0)
1322                 return clk_id;
1323
1324         param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1325
1326         ret = smu_cmn_send_smc_msg_with_param(smu,
1327                                               SMU_MSG_GetDpmFreqByIndex,
1328                                               param,
1329                                               &value);
1330         if (ret)
1331                 return ret;
1332
1333         /*
1334          * BIT31:  1 - Fine grained DPM, 0 - Dicrete DPM
1335          * now, we un-support it
1336          */
1337         *is_fine_grained_dpm = value & 0x80000000;
1338
1339         return 0;
1340 }
1341
1342 int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
1343                                    enum smu_clk_type clk_type,
1344                                    struct smu_14_0_dpm_table *single_dpm_table)
1345 {
1346         int ret = 0;
1347         uint32_t clk;
1348         int i;
1349
1350         ret = smu_v14_0_get_dpm_level_count(smu,
1351                                             clk_type,
1352                                             &single_dpm_table->count);
1353         if (ret) {
1354                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1355                 return ret;
1356         }
1357
1358         ret = smu_v14_0_get_fine_grained_status(smu,
1359                                                 clk_type,
1360                                                 &single_dpm_table->is_fine_grained);
1361         if (ret) {
1362                 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1363                 return ret;
1364         }
1365
1366         for (i = 0; i < single_dpm_table->count; i++) {
1367                 ret = smu_v14_0_get_dpm_freq_by_index(smu,
1368                                                       clk_type,
1369                                                       i,
1370                                                       &clk);
1371                 if (ret) {
1372                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1373                         return ret;
1374                 }
1375
1376                 single_dpm_table->dpm_levels[i].value = clk;
1377                 single_dpm_table->dpm_levels[i].enabled = true;
1378
1379                 if (i == 0)
1380                         single_dpm_table->min = clk;
1381                 else if (i == single_dpm_table->count - 1)
1382                         single_dpm_table->max = clk;
1383         }
1384
1385         return 0;
1386 }
1387
1388 int smu_v14_0_set_vcn_enable(struct smu_context *smu,
1389                              bool enable)
1390 {
1391         struct amdgpu_device *adev = smu->adev;
1392         int i, ret = 0;
1393
1394         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1395                 if (adev->vcn.harvest_config & (1 << i))
1396                         continue;
1397
1398                 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1399                                                       SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1400                                                       i << 16U, NULL);
1401                 if (ret)
1402                         return ret;
1403         }
1404
1405         return ret;
1406 }
1407
1408 int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
1409                               bool enable)
1410 {
1411         return smu_cmn_send_smc_msg_with_param(smu, enable ?
1412                                                SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
1413                                                0, NULL);
1414 }
1415
1416 int smu_v14_0_run_btc(struct smu_context *smu)
1417 {
1418         int res;
1419
1420         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1421         if (res)
1422                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
1423
1424         return res;
1425 }
1426
1427 int smu_v14_0_gpo_control(struct smu_context *smu,
1428                           bool enablement)
1429 {
1430         int res;
1431
1432         res = smu_cmn_send_smc_msg_with_param(smu,
1433                                               SMU_MSG_AllowGpo,
1434                                               enablement ? 1 : 0,
1435                                               NULL);
1436         if (res)
1437                 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
1438
1439         return res;
1440 }
1441
1442 int smu_v14_0_deep_sleep_control(struct smu_context *smu,
1443                                  bool enablement)
1444 {
1445         struct amdgpu_device *adev = smu->adev;
1446         int ret = 0;
1447
1448         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
1449                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
1450                 if (ret) {
1451                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
1452                         return ret;
1453                 }
1454         }
1455
1456         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
1457                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
1458                 if (ret) {
1459                         dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
1460                         return ret;
1461                 }
1462         }
1463
1464         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
1465                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
1466                 if (ret) {
1467                         dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
1468                         return ret;
1469                 }
1470         }
1471
1472         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
1473                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
1474                 if (ret) {
1475                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
1476                         return ret;
1477                 }
1478         }
1479
1480         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
1481                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
1482                 if (ret) {
1483                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
1484                         return ret;
1485                 }
1486         }
1487
1488         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
1489                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
1490                 if (ret) {
1491                         dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
1492                         return ret;
1493                 }
1494         }
1495
1496         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
1497                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
1498                 if (ret) {
1499                         dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
1500                         return ret;
1501                 }
1502         }
1503
1504         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
1505                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
1506                 if (ret) {
1507                         dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
1508                         return ret;
1509                 }
1510         }
1511
1512         return ret;
1513 }
1514
1515 int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
1516                               bool enablement)
1517 {
1518         int ret = 0;
1519
1520         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
1521                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
1522
1523         return ret;
1524 }
1525
1526 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
1527                                       enum smu_baco_seq baco_seq)
1528 {
1529         struct smu_baco_context *smu_baco = &smu->smu_baco;
1530         int ret;
1531
1532         ret = smu_cmn_send_smc_msg_with_param(smu,
1533                                               SMU_MSG_ArmD3,
1534                                               baco_seq,
1535                                               NULL);
1536         if (ret)
1537                 return ret;
1538
1539         if (baco_seq == BACO_SEQ_BAMACO ||
1540             baco_seq == BACO_SEQ_BACO)
1541                 smu_baco->state = SMU_BACO_STATE_ENTER;
1542         else
1543                 smu_baco->state = SMU_BACO_STATE_EXIT;
1544
1545         return 0;
1546 }
1547
1548 bool smu_v14_0_baco_is_support(struct smu_context *smu)
1549 {
1550         struct smu_baco_context *smu_baco = &smu->smu_baco;
1551
1552         if (amdgpu_sriov_vf(smu->adev) ||
1553             !smu_baco->platform_support)
1554                 return false;
1555
1556         /* return true if ASIC is in BACO state already */
1557         if (smu_v14_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1558                 return true;
1559
1560         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1561             !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1562                 return false;
1563
1564         return true;
1565 }
1566
1567 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu)
1568 {
1569         struct smu_baco_context *smu_baco = &smu->smu_baco;
1570
1571         return smu_baco->state;
1572 }
1573
1574 int smu_v14_0_baco_set_state(struct smu_context *smu,
1575                              enum smu_baco_state state)
1576 {
1577         struct smu_baco_context *smu_baco = &smu->smu_baco;
1578         struct amdgpu_device *adev = smu->adev;
1579         int ret = 0;
1580
1581         if (smu_v14_0_baco_get_state(smu) == state)
1582                 return 0;
1583
1584         if (state == SMU_BACO_STATE_ENTER) {
1585                 ret = smu_cmn_send_smc_msg_with_param(smu,
1586                                                       SMU_MSG_EnterBaco,
1587                                                       smu_baco->maco_support ?
1588                                                       BACO_SEQ_BAMACO : BACO_SEQ_BACO,
1589                                                       NULL);
1590         } else {
1591                 ret = smu_cmn_send_smc_msg(smu,
1592                                            SMU_MSG_ExitBaco,
1593                                            NULL);
1594                 if (ret)
1595                         return ret;
1596
1597                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1598                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1599                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1600         }
1601
1602         if (!ret)
1603                 smu_baco->state = state;
1604
1605         return ret;
1606 }
1607
1608 int smu_v14_0_baco_enter(struct smu_context *smu)
1609 {
1610         int ret = 0;
1611
1612         ret = smu_v14_0_baco_set_state(smu,
1613                                        SMU_BACO_STATE_ENTER);
1614         if (ret)
1615                 return ret;
1616
1617         msleep(10);
1618
1619         return ret;
1620 }
1621
1622 int smu_v14_0_baco_exit(struct smu_context *smu)
1623 {
1624         return smu_v14_0_baco_set_state(smu,
1625                                         SMU_BACO_STATE_EXIT);
1626 }
1627
1628 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu)
1629 {
1630         uint16_t index;
1631
1632         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1633                                                SMU_MSG_EnableGfxImu);
1634         /* Param 1 to tell PMFW to enable GFXOFF feature */
1635         return smu_cmn_send_msg_without_waiting(smu, index, 1);
1636 }
1637
1638 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu)
1639 {
1640         struct smu_table_context *smu_table = &smu->smu_table;
1641
1642         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
1643                                     smu_table->clocks_table, false);
1644 }
1645
1646 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
1647                                 enum PP_OD_DPM_TABLE_COMMAND type,
1648                                 long input[], uint32_t size)
1649 {
1650         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1651         int ret = 0;
1652
1653         /* Only allowed in manual mode */
1654         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1655                 return -EINVAL;
1656
1657         switch (type) {
1658         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1659                 if (size != 2) {
1660                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1661                         return -EINVAL;
1662                 }
1663
1664                 if (input[0] == 0) {
1665                         if (input[1] < smu->gfx_default_hard_min_freq) {
1666                                 dev_warn(smu->adev->dev,
1667                                          "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1668                                          input[1], smu->gfx_default_hard_min_freq);
1669                                 return -EINVAL;
1670                         }
1671                         smu->gfx_actual_hard_min_freq = input[1];
1672                 } else if (input[0] == 1) {
1673                         if (input[1] > smu->gfx_default_soft_max_freq) {
1674                                 dev_warn(smu->adev->dev,
1675                                          "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1676                                          input[1], smu->gfx_default_soft_max_freq);
1677                                 return -EINVAL;
1678                         }
1679                         smu->gfx_actual_soft_max_freq = input[1];
1680                 } else {
1681                         return -EINVAL;
1682                 }
1683                 break;
1684         case PP_OD_RESTORE_DEFAULT_TABLE:
1685                 if (size != 0) {
1686                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1687                         return -EINVAL;
1688                 }
1689                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1690                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1691                 break;
1692         case PP_OD_COMMIT_DPM_TABLE:
1693                 if (size != 0) {
1694                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1695                         return -EINVAL;
1696                 }
1697                 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1698                         dev_err(smu->adev->dev,
1699                                 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1700                                 smu->gfx_actual_hard_min_freq,
1701                                 smu->gfx_actual_soft_max_freq);
1702                         return -EINVAL;
1703                 }
1704
1705                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1706                                                       smu->gfx_actual_hard_min_freq,
1707                                                       NULL);
1708                 if (ret) {
1709                         dev_err(smu->adev->dev, "Set hard min sclk failed!");
1710                         return ret;
1711                 }
1712
1713                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1714                                                       smu->gfx_actual_soft_max_freq,
1715                                                       NULL);
1716                 if (ret) {
1717                         dev_err(smu->adev->dev, "Set soft max sclk failed!");
1718                         return ret;
1719                 }
1720                 break;
1721         default:
1722                 return -ENOSYS;
1723         }
1724
1725         return ret;
1726 }
1727