drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37
  38 static const struct hwmon_temp_label {
  39         enum PP_HWMON_TEMP channel;
  40         const char *label;
  41 } temp_label[] = {
  42         {PP_TEMP_EDGE, "edge"},
  43         {PP_TEMP_JUNCTION, "junction"},
  44         {PP_TEMP_MEM, "mem"},
  45 };
  46
  47 const char * const amdgpu_pp_profile_name[] = {
  48         "BOOTUP_DEFAULT",
  49         "3D_FULL_SCREEN",
  50         "POWER_SAVING",
  51         "VIDEO",
  52         "VR",
  53         "COMPUTE",
  54         "CUSTOM",
  55         "WINDOW_3D",
  56         "CAPPED",
  57         "UNCAPPED",
  58 };
  59
  60 /**
  61  * DOC: power_dpm_state
  62  *
  63  * The power_dpm_state file is a legacy interface and is only provided for
  64  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  65  * certain power related parameters.  The file power_dpm_state is used for this.
  66  * It accepts the following arguments:
  67  *
  68  * - battery
  69  *
  70  * - balanced
  71  *
  72  * - performance
  73  *
  74  * battery
  75  *
  76  * On older GPUs, the vbios provided a special power state for battery
  77  * operation.  Selecting battery switched to this state.  This is no
  78  * longer provided on newer GPUs so the option does nothing in that case.
  79  *
  80  * balanced
  81  *
  82  * On older GPUs, the vbios provided a special power state for balanced
  83  * operation.  Selecting balanced switched to this state.  This is no
  84  * longer provided on newer GPUs so the option does nothing in that case.
  85  *
  86  * performance
  87  *
  88  * On older GPUs, the vbios provided a special power state for performance
  89  * operation.  Selecting performance switched to this state.  This is no
  90  * longer provided on newer GPUs so the option does nothing in that case.
  91  *
  92  */
  93
  94 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
  95                                           struct device_attribute *attr,
  96                                           char *buf)
  97 {
  98         struct drm_device *ddev = dev_get_drvdata(dev);
  99         struct amdgpu_device *adev = drm_to_adev(ddev);
 100         enum amd_pm_state_type pm;
 101         int ret;
 102
 103         if (amdgpu_in_reset(adev))
 104                 return -EPERM;
 105         if (adev->in_suspend && !adev->in_runpm)
 106                 return -EPERM;
 107
 108         ret = pm_runtime_get_sync(ddev->dev);
 109         if (ret < 0) {
 110                 pm_runtime_put_autosuspend(ddev->dev);
 111                 return ret;
 112         }
 113
 114         amdgpu_dpm_get_current_power_state(adev, &pm);
 115
 116         pm_runtime_mark_last_busy(ddev->dev);
 117         pm_runtime_put_autosuspend(ddev->dev);
 118
 119         return sysfs_emit(buf, "%s\n",
 120                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 121                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 122 }
 123
 124 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 125                                           struct device_attribute *attr,
 126                                           const char *buf,
 127                                           size_t count)
 128 {
 129         struct drm_device *ddev = dev_get_drvdata(dev);
 130         struct amdgpu_device *adev = drm_to_adev(ddev);
 131         enum amd_pm_state_type  state;
 132         int ret;
 133
 134         if (amdgpu_in_reset(adev))
 135                 return -EPERM;
 136         if (adev->in_suspend && !adev->in_runpm)
 137                 return -EPERM;
 138
 139         if (strncmp("battery", buf, strlen("battery")) == 0)
 140                 state = POWER_STATE_TYPE_BATTERY;
 141         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 142                 state = POWER_STATE_TYPE_BALANCED;
 143         else if (strncmp("performance", buf, strlen("performance")) == 0)
 144                 state = POWER_STATE_TYPE_PERFORMANCE;
 145         else
 146                 return -EINVAL;
 147
 148         ret = pm_runtime_get_sync(ddev->dev);
 149         if (ret < 0) {
 150                 pm_runtime_put_autosuspend(ddev->dev);
 151                 return ret;
 152         }
 153
 154         amdgpu_dpm_set_power_state(adev, state);
 155
 156         pm_runtime_mark_last_busy(ddev->dev);
 157         pm_runtime_put_autosuspend(ddev->dev);
 158
 159         return count;
 160 }
 161
 162
 163 /**
 164  * DOC: power_dpm_force_performance_level
 165  *
 166  * The amdgpu driver provides a sysfs API for adjusting certain power
 167  * related parameters.  The file power_dpm_force_performance_level is
 168  * used for this.  It accepts the following arguments:
 169  *
 170  * - auto
 171  *
 172  * - low
 173  *
 174  * - high
 175  *
 176  * - manual
 177  *
 178  * - profile_standard
 179  *
 180  * - profile_min_sclk
 181  *
 182  * - profile_min_mclk
 183  *
 184  * - profile_peak
 185  *
 186  * auto
 187  *
 188  * When auto is selected, the driver will attempt to dynamically select
 189  * the optimal power profile for current conditions in the driver.
 190  *
 191  * low
 192  *
 193  * When low is selected, the clocks are forced to the lowest power state.
 194  *
 195  * high
 196  *
 197  * When high is selected, the clocks are forced to the highest power state.
 198  *
 199  * manual
 200  *
 201  * When manual is selected, the user can manually adjust which power states
 202  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 203  * and pp_dpm_pcie files and adjust the power state transition heuristics
 204  * via the pp_power_profile_mode sysfs file.
 205  *
 206  * profile_standard
 207  * profile_min_sclk
 208  * profile_min_mclk
 209  * profile_peak
 210  *
 211  * When the profiling modes are selected, clock and power gating are
 212  * disabled and the clocks are set for different profiling cases. This
 213  * mode is recommended for profiling specific work loads where you do
 214  * not want clock or power gating for clock fluctuation to interfere
 215  * with your results. profile_standard sets the clocks to a fixed clock
 216  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 217  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 218  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 219  *
 220  */
 221
 222 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 223                                                             struct device_attribute *attr,
 224                                                             char *buf)
 225 {
 226         struct drm_device *ddev = dev_get_drvdata(dev);
 227         struct amdgpu_device *adev = drm_to_adev(ddev);
 228         enum amd_dpm_forced_level level = 0xff;
 229         int ret;
 230
 231         if (amdgpu_in_reset(adev))
 232                 return -EPERM;
 233         if (adev->in_suspend && !adev->in_runpm)
 234                 return -EPERM;
 235
 236         ret = pm_runtime_get_sync(ddev->dev);
 237         if (ret < 0) {
 238                 pm_runtime_put_autosuspend(ddev->dev);
 239                 return ret;
 240         }
 241
 242         level = amdgpu_dpm_get_performance_level(adev);
 243
 244         pm_runtime_mark_last_busy(ddev->dev);
 245         pm_runtime_put_autosuspend(ddev->dev);
 246
 247         return sysfs_emit(buf, "%s\n",
 248                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 249                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 250                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 251                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 252                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 253                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 254                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 255                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 256                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 257                           "unknown");
 258 }
 259
 260 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 261                                                             struct device_attribute *attr,
 262                                                             const char *buf,
 263                                                             size_t count)
 264 {
 265         struct drm_device *ddev = dev_get_drvdata(dev);
 266         struct amdgpu_device *adev = drm_to_adev(ddev);
 267         enum amd_dpm_forced_level level;
 268         int ret = 0;
 269
 270         if (amdgpu_in_reset(adev))
 271                 return -EPERM;
 272         if (adev->in_suspend && !adev->in_runpm)
 273                 return -EPERM;
 274
 275         if (strncmp("low", buf, strlen("low")) == 0) {
 276                 level = AMD_DPM_FORCED_LEVEL_LOW;
 277         } else if (strncmp("high", buf, strlen("high")) == 0) {
 278                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 279         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 280                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 281         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 282                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 283         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 284                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 285         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 286                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 287         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 288                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 289         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 290                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 291         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 292                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 293         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 294                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 295         }  else {
 296                 return -EINVAL;
 297         }
 298
 299         ret = pm_runtime_get_sync(ddev->dev);
 300         if (ret < 0) {
 301                 pm_runtime_put_autosuspend(ddev->dev);
 302                 return ret;
 303         }
 304
 305         mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 306         if (amdgpu_dpm_force_performance_level(adev, level)) {
 307                 pm_runtime_mark_last_busy(ddev->dev);
 308                 pm_runtime_put_autosuspend(ddev->dev);
 309                 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 310                 return -EINVAL;
 311         }
 312         /* override whatever a user ctx may have set */
 313         adev->pm.stable_pstate_ctx = NULL;
 314         mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 315
 316         pm_runtime_mark_last_busy(ddev->dev);
 317         pm_runtime_put_autosuspend(ddev->dev);
 318
 319         return count;
 320 }
 321
 322 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 323                 struct device_attribute *attr,
 324                 char *buf)
 325 {
 326         struct drm_device *ddev = dev_get_drvdata(dev);
 327         struct amdgpu_device *adev = drm_to_adev(ddev);
 328         struct pp_states_info data;
 329         uint32_t i;
 330         int buf_len, ret;
 331
 332         if (amdgpu_in_reset(adev))
 333                 return -EPERM;
 334         if (adev->in_suspend && !adev->in_runpm)
 335                 return -EPERM;
 336
 337         ret = pm_runtime_get_sync(ddev->dev);
 338         if (ret < 0) {
 339                 pm_runtime_put_autosuspend(ddev->dev);
 340                 return ret;
 341         }
 342
 343         if (amdgpu_dpm_get_pp_num_states(adev, &data))
 344                 memset(&data, 0, sizeof(data));
 345
 346         pm_runtime_mark_last_busy(ddev->dev);
 347         pm_runtime_put_autosuspend(ddev->dev);
 348
 349         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 350         for (i = 0; i < data.nums; i++)
 351                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 352                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 353                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 354                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 355                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 356
 357         return buf_len;
 358 }
 359
 360 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 361                 struct device_attribute *attr,
 362                 char *buf)
 363 {
 364         struct drm_device *ddev = dev_get_drvdata(dev);
 365         struct amdgpu_device *adev = drm_to_adev(ddev);
 366         struct pp_states_info data = {0};
 367         enum amd_pm_state_type pm = 0;
 368         int i = 0, ret = 0;
 369
 370         if (amdgpu_in_reset(adev))
 371                 return -EPERM;
 372         if (adev->in_suspend && !adev->in_runpm)
 373                 return -EPERM;
 374
 375         ret = pm_runtime_get_sync(ddev->dev);
 376         if (ret < 0) {
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return ret;
 379         }
 380
 381         amdgpu_dpm_get_current_power_state(adev, &pm);
 382
 383         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 384
 385         pm_runtime_mark_last_busy(ddev->dev);
 386         pm_runtime_put_autosuspend(ddev->dev);
 387
 388         if (ret)
 389                 return ret;
 390
 391         for (i = 0; i < data.nums; i++) {
 392                 if (pm == data.states[i])
 393                         break;
 394         }
 395
 396         if (i == data.nums)
 397                 i = -EINVAL;
 398
 399         return sysfs_emit(buf, "%d\n", i);
 400 }
 401
 402 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 403                 struct device_attribute *attr,
 404                 char *buf)
 405 {
 406         struct drm_device *ddev = dev_get_drvdata(dev);
 407         struct amdgpu_device *adev = drm_to_adev(ddev);
 408
 409         if (amdgpu_in_reset(adev))
 410                 return -EPERM;
 411         if (adev->in_suspend && !adev->in_runpm)
 412                 return -EPERM;
 413
 414         if (adev->pm.pp_force_state_enabled)
 415                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 416         else
 417                 return sysfs_emit(buf, "\n");
 418 }
 419
 420 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 421                 struct device_attribute *attr,
 422                 const char *buf,
 423                 size_t count)
 424 {
 425         struct drm_device *ddev = dev_get_drvdata(dev);
 426         struct amdgpu_device *adev = drm_to_adev(ddev);
 427         enum amd_pm_state_type state = 0;
 428         struct pp_states_info data;
 429         unsigned long idx;
 430         int ret;
 431
 432         if (amdgpu_in_reset(adev))
 433                 return -EPERM;
 434         if (adev->in_suspend && !adev->in_runpm)
 435                 return -EPERM;
 436
 437         adev->pm.pp_force_state_enabled = false;
 438
 439         if (strlen(buf) == 1)
 440                 return count;
 441
 442         ret = kstrtoul(buf, 0, &idx);
 443         if (ret || idx >= ARRAY_SIZE(data.states))
 444                 return -EINVAL;
 445
 446         idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 447
 448         ret = pm_runtime_get_sync(ddev->dev);
 449         if (ret < 0) {
 450                 pm_runtime_put_autosuspend(ddev->dev);
 451                 return ret;
 452         }
 453
 454         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 455         if (ret)
 456                 goto err_out;
 457
 458         state = data.states[idx];
 459
 460         /* only set user selected power states */
 461         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 462             state != POWER_STATE_TYPE_DEFAULT) {
 463                 ret = amdgpu_dpm_dispatch_task(adev,
 464                                 AMD_PP_TASK_ENABLE_USER_STATE, &state);
 465                 if (ret)
 466                         goto err_out;
 467
 468                 adev->pm.pp_force_state_enabled = true;
 469         }
 470
 471         pm_runtime_mark_last_busy(ddev->dev);
 472         pm_runtime_put_autosuspend(ddev->dev);
 473
 474         return count;
 475
 476 err_out:
 477         pm_runtime_mark_last_busy(ddev->dev);
 478         pm_runtime_put_autosuspend(ddev->dev);
 479         return ret;
 480 }
 481
 482 /**
 483  * DOC: pp_table
 484  *
 485  * The amdgpu driver provides a sysfs API for uploading new powerplay
 486  * tables.  The file pp_table is used for this.  Reading the file
 487  * will dump the current power play table.  Writing to the file
 488  * will attempt to upload a new powerplay table and re-initialize
 489  * powerplay using that new table.
 490  *
 491  */
 492
 493 static ssize_t amdgpu_get_pp_table(struct device *dev,
 494                 struct device_attribute *attr,
 495                 char *buf)
 496 {
 497         struct drm_device *ddev = dev_get_drvdata(dev);
 498         struct amdgpu_device *adev = drm_to_adev(ddev);
 499         char *table = NULL;
 500         int size, ret;
 501
 502         if (amdgpu_in_reset(adev))
 503                 return -EPERM;
 504         if (adev->in_suspend && !adev->in_runpm)
 505                 return -EPERM;
 506
 507         ret = pm_runtime_get_sync(ddev->dev);
 508         if (ret < 0) {
 509                 pm_runtime_put_autosuspend(ddev->dev);
 510                 return ret;
 511         }
 512
 513         size = amdgpu_dpm_get_pp_table(adev, &table);
 514
 515         pm_runtime_mark_last_busy(ddev->dev);
 516         pm_runtime_put_autosuspend(ddev->dev);
 517
 518         if (size <= 0)
 519                 return size;
 520
 521         if (size >= PAGE_SIZE)
 522                 size = PAGE_SIZE - 1;
 523
 524         memcpy(buf, table, size);
 525
 526         return size;
 527 }
 528
 529 static ssize_t amdgpu_set_pp_table(struct device *dev,
 530                 struct device_attribute *attr,
 531                 const char *buf,
 532                 size_t count)
 533 {
 534         struct drm_device *ddev = dev_get_drvdata(dev);
 535         struct amdgpu_device *adev = drm_to_adev(ddev);
 536         int ret = 0;
 537
 538         if (amdgpu_in_reset(adev))
 539                 return -EPERM;
 540         if (adev->in_suspend && !adev->in_runpm)
 541                 return -EPERM;
 542
 543         ret = pm_runtime_get_sync(ddev->dev);
 544         if (ret < 0) {
 545                 pm_runtime_put_autosuspend(ddev->dev);
 546                 return ret;
 547         }
 548
 549         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 550
 551         pm_runtime_mark_last_busy(ddev->dev);
 552         pm_runtime_put_autosuspend(ddev->dev);
 553
 554         if (ret)
 555                 return ret;
 556
 557         return count;
 558 }
 559
 560 /**
 561  * DOC: pp_od_clk_voltage
 562  *
 563  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 564  * in each power level within a power state.  The pp_od_clk_voltage is used for
 565  * this.
 566  *
 567  * Note that the actual memory controller clock rate are exposed, not
 568  * the effective memory clock of the DRAMs. To translate it, use the
 569  * following formula:
 570  *
 571  * Clock conversion (Mhz):
 572  *
 573  * HBM: effective_memory_clock = memory_controller_clock * 1
 574  *
 575  * G5: effective_memory_clock = memory_controller_clock * 1
 576  *
 577  * G6: effective_memory_clock = memory_controller_clock * 2
 578  *
 579  * DRAM data rate (MT/s):
 580  *
 581  * HBM: effective_memory_clock * 2 = data_rate
 582  *
 583  * G5: effective_memory_clock * 4 = data_rate
 584  *
 585  * G6: effective_memory_clock * 8 = data_rate
 586  *
 587  * Bandwidth (MB/s):
 588  *
 589  * data_rate * vram_bit_width / 8 = memory_bandwidth
 590  *
 591  * Some examples:
 592  *
 593  * G5 on RX460:
 594  *
 595  * memory_controller_clock = 1750 Mhz
 596  *
 597  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 598  *
 599  * data rate = 1750 * 4 = 7000 MT/s
 600  *
 601  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 602  *
 603  * G6 on RX5700:
 604  *
 605  * memory_controller_clock = 875 Mhz
 606  *
 607  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 608  *
 609  * data rate = 1750 * 8 = 14000 MT/s
 610  *
 611  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 612  *
 613  * < For Vega10 and previous ASICs >
 614  *
 615  * Reading the file will display:
 616  *
 617  * - a list of engine clock levels and voltages labeled OD_SCLK
 618  *
 619  * - a list of memory clock levels and voltages labeled OD_MCLK
 620  *
 621  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 622  *
 623  * To manually adjust these settings, first select manual using
 624  * power_dpm_force_performance_level. Enter a new value for each
 625  * level by writing a string that contains "s/m level clock voltage" to
 626  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 627  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 628  * 810 mV.  When you have edited all of the states as needed, write
 629  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 630  * default power levels, write "r" (reset) to the file to reset them.
 631  *
 632  *
 633  * < For Vega20 and newer ASICs >
 634  *
 635  * Reading the file will display:
 636  *
 637  * - minimum and maximum engine clock labeled OD_SCLK
 638  *
 639  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 640  *   clock labeled OD_MCLK
 641  *
 642  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 643  *   They can be used to calibrate the sclk voltage curve. This is
 644  *   available for Vega20 and NV1X.
 645  *
 646  * - voltage offset for the six anchor points of the v/f curve labeled
 647  *   OD_VDDC_CURVE. They can be used to calibrate the v/f curve. This
 648  *   is only availabe for some SMU13 ASICs.
 649  *
 650  * - voltage offset(in mV) applied on target voltage calculation.
 651  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
 652  *   Cavefish. For these ASICs, the target voltage calculation can be
 653  *   illustrated by "voltage = voltage calculated from v/f curve +
 654  *   overdrive vddgfx offset"
 655  *
 656  * - a list of valid ranges for sclk, mclk, and voltage curve points
 657  *   labeled OD_RANGE
 658  *
 659  * < For APUs >
 660  *
 661  * Reading the file will display:
 662  *
 663  * - minimum and maximum engine clock labeled OD_SCLK
 664  *
 665  * - a list of valid ranges for sclk labeled OD_RANGE
 666  *
 667  * < For VanGogh >
 668  *
 669  * Reading the file will display:
 670  *
 671  * - minimum and maximum engine clock labeled OD_SCLK
 672  * - minimum and maximum core clocks labeled OD_CCLK
 673  *
 674  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 675  *
 676  * To manually adjust these settings:
 677  *
 678  * - First select manual using power_dpm_force_performance_level
 679  *
 680  * - For clock frequency setting, enter a new value by writing a
 681  *   string that contains "s/m index clock" to the file. The index
 682  *   should be 0 if to set minimum clock. And 1 if to set maximum
 683  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 684  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 685  *   clocks on VanGogh, the string contains "p core index clock".
 686  *   E.g., "p 2 0 800" would set the minimum core clock on core
 687  *   2 to 800Mhz.
 688  *
 689  *   For sclk voltage curve,
 690  *     - For NV1X, enter the new values by writing a string that
 691  *       contains "vc point clock voltage" to the file. The points
 692  *       are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will update
 693  *       point1 with clock set as 300Mhz and voltage as 600mV. "vc 2
 694  *       1000 1000" will update point3 with clock set as 1000Mhz and
 695  *       voltage 1000mV.
 696  *     - For SMU13 ASICs, enter the new values by writing a string that
 697  *       contains "vc anchor_point_index voltage_offset" to the file.
 698  *       There are total six anchor points defined on the v/f curve with
 699  *       index as 0 - 5.
 700  *       - "vc 0 10" will update the voltage offset for point1 as 10mv.
 701  *       - "vc 5 -10" will update the voltage offset for point6 as -10mv.
 702  *
 703  *   To update the voltage offset applied for gfxclk/voltage calculation,
 704  *   enter the new value by writing a string that contains "vo offset".
 705  *   This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
 706  *   And the offset can be a positive or negative value.
 707  *
 708  * - When you have edited all of the states as needed, write "c" (commit)
 709  *   to the file to commit your changes
 710  *
 711  * - If you want to reset to the default power levels, write "r" (reset)
 712  *   to the file to reset them
 713  *
 714  */
 715
 716 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 717                 struct device_attribute *attr,
 718                 const char *buf,
 719                 size_t count)
 720 {
 721         struct drm_device *ddev = dev_get_drvdata(dev);
 722         struct amdgpu_device *adev = drm_to_adev(ddev);
 723         int ret;
 724         uint32_t parameter_size = 0;
 725         long parameter[64];
 726         char buf_cpy[128];
 727         char *tmp_str;
 728         char *sub_str;
 729         const char delimiter[3] = {' ', '\n', '\0'};
 730         uint32_t type;
 731
 732         if (amdgpu_in_reset(adev))
 733                 return -EPERM;
 734         if (adev->in_suspend && !adev->in_runpm)
 735                 return -EPERM;
 736
 737         if (count > 127)
 738                 return -EINVAL;
 739
 740         if (*buf == 's')
 741                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 742         else if (*buf == 'p')
 743                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 744         else if (*buf == 'm')
 745                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 746         else if (*buf == 'r')
 747                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 748         else if (*buf == 'c')
 749                 type = PP_OD_COMMIT_DPM_TABLE;
 750         else if (!strncmp(buf, "vc", 2))
 751                 type = PP_OD_EDIT_VDDC_CURVE;
 752         else if (!strncmp(buf, "vo", 2))
 753                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 754         else
 755                 return -EINVAL;
 756
 757         memcpy(buf_cpy, buf, count+1);
 758
 759         tmp_str = buf_cpy;
 760
 761         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 762              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 763                 tmp_str++;
 764         while (isspace(*++tmp_str));
 765
 766         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 767                 if (strlen(sub_str) == 0)
 768                         continue;
 769                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 770                 if (ret)
 771                         return -EINVAL;
 772                 parameter_size++;
 773
 774                 while (isspace(*tmp_str))
 775                         tmp_str++;
 776         }
 777
 778         ret = pm_runtime_get_sync(ddev->dev);
 779         if (ret < 0) {
 780                 pm_runtime_put_autosuspend(ddev->dev);
 781                 return ret;
 782         }
 783
 784         if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
 785                                               type,
 786                                               parameter,
 787                                               parameter_size))
 788                 goto err_out;
 789
 790         if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
 791                                           parameter, parameter_size))
 792                 goto err_out;
 793
 794         if (type == PP_OD_COMMIT_DPM_TABLE) {
 795                 if (amdgpu_dpm_dispatch_task(adev,
 796                                              AMD_PP_TASK_READJUST_POWER_STATE,
 797                                              NULL))
 798                         goto err_out;
 799         }
 800
 801         pm_runtime_mark_last_busy(ddev->dev);
 802         pm_runtime_put_autosuspend(ddev->dev);
 803
 804         return count;
 805
 806 err_out:
 807         pm_runtime_mark_last_busy(ddev->dev);
 808         pm_runtime_put_autosuspend(ddev->dev);
 809         return -EINVAL;
 810 }
 811
 812 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 813                 struct device_attribute *attr,
 814                 char *buf)
 815 {
 816         struct drm_device *ddev = dev_get_drvdata(dev);
 817         struct amdgpu_device *adev = drm_to_adev(ddev);
 818         int size = 0;
 819         int ret;
 820         enum pp_clock_type od_clocks[6] = {
 821                 OD_SCLK,
 822                 OD_MCLK,
 823                 OD_VDDC_CURVE,
 824                 OD_RANGE,
 825                 OD_VDDGFX_OFFSET,
 826                 OD_CCLK,
 827         };
 828         uint clk_index;
 829
 830         if (amdgpu_in_reset(adev))
 831                 return -EPERM;
 832         if (adev->in_suspend && !adev->in_runpm)
 833                 return -EPERM;
 834
 835         ret = pm_runtime_get_sync(ddev->dev);
 836         if (ret < 0) {
 837                 pm_runtime_put_autosuspend(ddev->dev);
 838                 return ret;
 839         }
 840
 841         for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
 842                 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
 843                 if (ret)
 844                         break;
 845         }
 846         if (ret == -ENOENT) {
 847                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 848                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
 849                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
 850                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
 851                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
 852                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
 853         }
 854
 855         if (size == 0)
 856                 size = sysfs_emit(buf, "\n");
 857
 858         pm_runtime_mark_last_busy(ddev->dev);
 859         pm_runtime_put_autosuspend(ddev->dev);
 860
 861         return size;
 862 }
 863
 864 /**
 865  * DOC: pp_features
 866  *
 867  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 868  * features to be enabled. The file pp_features is used for this. And
 869  * this is only available for Vega10 and later dGPUs.
 870  *
 871  * Reading back the file will show you the followings:
 872  * - Current ppfeature masks
 873  * - List of the all supported powerplay features with their naming,
 874  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 875  *
 876  * To manually enable or disable a specific feature, just set or clear
 877  * the corresponding bit from original ppfeature masks and input the
 878  * new ppfeature masks.
 879  */
 880 static ssize_t amdgpu_set_pp_features(struct device *dev,
 881                                       struct device_attribute *attr,
 882                                       const char *buf,
 883                                       size_t count)
 884 {
 885         struct drm_device *ddev = dev_get_drvdata(dev);
 886         struct amdgpu_device *adev = drm_to_adev(ddev);
 887         uint64_t featuremask;
 888         int ret;
 889
 890         if (amdgpu_in_reset(adev))
 891                 return -EPERM;
 892         if (adev->in_suspend && !adev->in_runpm)
 893                 return -EPERM;
 894
 895         ret = kstrtou64(buf, 0, &featuremask);
 896         if (ret)
 897                 return -EINVAL;
 898
 899         ret = pm_runtime_get_sync(ddev->dev);
 900         if (ret < 0) {
 901                 pm_runtime_put_autosuspend(ddev->dev);
 902                 return ret;
 903         }
 904
 905         ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 906
 907         pm_runtime_mark_last_busy(ddev->dev);
 908         pm_runtime_put_autosuspend(ddev->dev);
 909
 910         if (ret)
 911                 return -EINVAL;
 912
 913         return count;
 914 }
 915
 916 static ssize_t amdgpu_get_pp_features(struct device *dev,
 917                                       struct device_attribute *attr,
 918                                       char *buf)
 919 {
 920         struct drm_device *ddev = dev_get_drvdata(dev);
 921         struct amdgpu_device *adev = drm_to_adev(ddev);
 922         ssize_t size;
 923         int ret;
 924
 925         if (amdgpu_in_reset(adev))
 926                 return -EPERM;
 927         if (adev->in_suspend && !adev->in_runpm)
 928                 return -EPERM;
 929
 930         ret = pm_runtime_get_sync(ddev->dev);
 931         if (ret < 0) {
 932                 pm_runtime_put_autosuspend(ddev->dev);
 933                 return ret;
 934         }
 935
 936         size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 937         if (size <= 0)
 938                 size = sysfs_emit(buf, "\n");
 939
 940         pm_runtime_mark_last_busy(ddev->dev);
 941         pm_runtime_put_autosuspend(ddev->dev);
 942
 943         return size;
 944 }
 945
 946 /**
 947  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 948  *
 949  * The amdgpu driver provides a sysfs API for adjusting what power levels
 950  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 951  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 952  * this.
 953  *
 954  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 955  * Vega10 and later ASICs.
 956  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 957  *
 958  * Reading back the files will show you the available power levels within
 959  * the power state and the clock information for those levels.
 960  *
 961  * To manually adjust these states, first select manual using
 962  * power_dpm_force_performance_level.
 963  * Secondly, enter a new value for each level by inputing a string that
 964  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 965  * E.g.,
 966  *
 967  * .. code-block:: bash
 968  *
 969  *      echo "4 5 6" > pp_dpm_sclk
 970  *
 971  * will enable sclk levels 4, 5, and 6.
 972  *
 973  * NOTE: change to the dcefclk max dpm level is not supported now
 974  */
 975
 976 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
 977                 enum pp_clock_type type,
 978                 char *buf)
 979 {
 980         struct drm_device *ddev = dev_get_drvdata(dev);
 981         struct amdgpu_device *adev = drm_to_adev(ddev);
 982         int size = 0;
 983         int ret = 0;
 984
 985         if (amdgpu_in_reset(adev))
 986                 return -EPERM;
 987         if (adev->in_suspend && !adev->in_runpm)
 988                 return -EPERM;
 989
 990         ret = pm_runtime_get_sync(ddev->dev);
 991         if (ret < 0) {
 992                 pm_runtime_put_autosuspend(ddev->dev);
 993                 return ret;
 994         }
 995
 996         ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
 997         if (ret == -ENOENT)
 998                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
 999
1000         if (size == 0)
1001                 size = sysfs_emit(buf, "\n");
1002
1003         pm_runtime_mark_last_busy(ddev->dev);
1004         pm_runtime_put_autosuspend(ddev->dev);
1005
1006         return size;
1007 }
1008
1009 /*
1010  * Worst case: 32 bits individually specified, in octal at 12 characters
1011  * per line (+1 for \n).
1012  */
1013 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1014
1015 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1016 {
1017         int ret;
1018         unsigned long level;
1019         char *sub_str = NULL;
1020         char *tmp;
1021         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1022         const char delimiter[3] = {' ', '\n', '\0'};
1023         size_t bytes;
1024
1025         *mask = 0;
1026
1027         bytes = min(count, sizeof(buf_cpy) - 1);
1028         memcpy(buf_cpy, buf, bytes);
1029         buf_cpy[bytes] = '\0';
1030         tmp = buf_cpy;
1031         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1032                 if (strlen(sub_str)) {
1033                         ret = kstrtoul(sub_str, 0, &level);
1034                         if (ret || level > 31)
1035                                 return -EINVAL;
1036                         *mask |= 1 << level;
1037                 } else
1038                         break;
1039         }
1040
1041         return 0;
1042 }
1043
1044 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1045                 enum pp_clock_type type,
1046                 const char *buf,
1047                 size_t count)
1048 {
1049         struct drm_device *ddev = dev_get_drvdata(dev);
1050         struct amdgpu_device *adev = drm_to_adev(ddev);
1051         int ret;
1052         uint32_t mask = 0;
1053
1054         if (amdgpu_in_reset(adev))
1055                 return -EPERM;
1056         if (adev->in_suspend && !adev->in_runpm)
1057                 return -EPERM;
1058
1059         ret = amdgpu_read_mask(buf, count, &mask);
1060         if (ret)
1061                 return ret;
1062
1063         ret = pm_runtime_get_sync(ddev->dev);
1064         if (ret < 0) {
1065                 pm_runtime_put_autosuspend(ddev->dev);
1066                 return ret;
1067         }
1068
1069         ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1070
1071         pm_runtime_mark_last_busy(ddev->dev);
1072         pm_runtime_put_autosuspend(ddev->dev);
1073
1074         if (ret)
1075                 return -EINVAL;
1076
1077         return count;
1078 }
1079
1080 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1081                 struct device_attribute *attr,
1082                 char *buf)
1083 {
1084         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1085 }
1086
1087 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1088                 struct device_attribute *attr,
1089                 const char *buf,
1090                 size_t count)
1091 {
1092         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1093 }
1094
1095 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1096                 struct device_attribute *attr,
1097                 char *buf)
1098 {
1099         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1100 }
1101
1102 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1103                 struct device_attribute *attr,
1104                 const char *buf,
1105                 size_t count)
1106 {
1107         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1108 }
1109
1110 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1111                 struct device_attribute *attr,
1112                 char *buf)
1113 {
1114         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1115 }
1116
1117 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1118                 struct device_attribute *attr,
1119                 const char *buf,
1120                 size_t count)
1121 {
1122         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1123 }
1124
1125 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1126                 struct device_attribute *attr,
1127                 char *buf)
1128 {
1129         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1130 }
1131
1132 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1133                 struct device_attribute *attr,
1134                 const char *buf,
1135                 size_t count)
1136 {
1137         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1138 }
1139
1140 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1141                 struct device_attribute *attr,
1142                 char *buf)
1143 {
1144         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1145 }
1146
1147 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1148                 struct device_attribute *attr,
1149                 const char *buf,
1150                 size_t count)
1151 {
1152         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1153 }
1154
1155 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1156                 struct device_attribute *attr,
1157                 char *buf)
1158 {
1159         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1160 }
1161
1162 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1163                 struct device_attribute *attr,
1164                 const char *buf,
1165                 size_t count)
1166 {
1167         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1168 }
1169
1170 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1171                 struct device_attribute *attr,
1172                 char *buf)
1173 {
1174         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1175 }
1176
1177 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1178                 struct device_attribute *attr,
1179                 const char *buf,
1180                 size_t count)
1181 {
1182         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1183 }
1184
1185 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1186                 struct device_attribute *attr,
1187                 char *buf)
1188 {
1189         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1190 }
1191
1192 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1193                 struct device_attribute *attr,
1194                 const char *buf,
1195                 size_t count)
1196 {
1197         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1198 }
1199
1200 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1201                 struct device_attribute *attr,
1202                 char *buf)
1203 {
1204         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1205 }
1206
1207 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1208                 struct device_attribute *attr,
1209                 const char *buf,
1210                 size_t count)
1211 {
1212         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1213 }
1214
1215 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1216                 struct device_attribute *attr,
1217                 char *buf)
1218 {
1219         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1220 }
1221
1222 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1223                 struct device_attribute *attr,
1224                 const char *buf,
1225                 size_t count)
1226 {
1227         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1228 }
1229
1230 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1231                 struct device_attribute *attr,
1232                 char *buf)
1233 {
1234         struct drm_device *ddev = dev_get_drvdata(dev);
1235         struct amdgpu_device *adev = drm_to_adev(ddev);
1236         uint32_t value = 0;
1237         int ret;
1238
1239         if (amdgpu_in_reset(adev))
1240                 return -EPERM;
1241         if (adev->in_suspend && !adev->in_runpm)
1242                 return -EPERM;
1243
1244         ret = pm_runtime_get_sync(ddev->dev);
1245         if (ret < 0) {
1246                 pm_runtime_put_autosuspend(ddev->dev);
1247                 return ret;
1248         }
1249
1250         value = amdgpu_dpm_get_sclk_od(adev);
1251
1252         pm_runtime_mark_last_busy(ddev->dev);
1253         pm_runtime_put_autosuspend(ddev->dev);
1254
1255         return sysfs_emit(buf, "%d\n", value);
1256 }
1257
1258 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1259                 struct device_attribute *attr,
1260                 const char *buf,
1261                 size_t count)
1262 {
1263         struct drm_device *ddev = dev_get_drvdata(dev);
1264         struct amdgpu_device *adev = drm_to_adev(ddev);
1265         int ret;
1266         long int value;
1267
1268         if (amdgpu_in_reset(adev))
1269                 return -EPERM;
1270         if (adev->in_suspend && !adev->in_runpm)
1271                 return -EPERM;
1272
1273         ret = kstrtol(buf, 0, &value);
1274
1275         if (ret)
1276                 return -EINVAL;
1277
1278         ret = pm_runtime_get_sync(ddev->dev);
1279         if (ret < 0) {
1280                 pm_runtime_put_autosuspend(ddev->dev);
1281                 return ret;
1282         }
1283
1284         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1285
1286         pm_runtime_mark_last_busy(ddev->dev);
1287         pm_runtime_put_autosuspend(ddev->dev);
1288
1289         return count;
1290 }
1291
1292 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1293                 struct device_attribute *attr,
1294                 char *buf)
1295 {
1296         struct drm_device *ddev = dev_get_drvdata(dev);
1297         struct amdgpu_device *adev = drm_to_adev(ddev);
1298         uint32_t value = 0;
1299         int ret;
1300
1301         if (amdgpu_in_reset(adev))
1302                 return -EPERM;
1303         if (adev->in_suspend && !adev->in_runpm)
1304                 return -EPERM;
1305
1306         ret = pm_runtime_get_sync(ddev->dev);
1307         if (ret < 0) {
1308                 pm_runtime_put_autosuspend(ddev->dev);
1309                 return ret;
1310         }
1311
1312         value = amdgpu_dpm_get_mclk_od(adev);
1313
1314         pm_runtime_mark_last_busy(ddev->dev);
1315         pm_runtime_put_autosuspend(ddev->dev);
1316
1317         return sysfs_emit(buf, "%d\n", value);
1318 }
1319
1320 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1321                 struct device_attribute *attr,
1322                 const char *buf,
1323                 size_t count)
1324 {
1325         struct drm_device *ddev = dev_get_drvdata(dev);
1326         struct amdgpu_device *adev = drm_to_adev(ddev);
1327         int ret;
1328         long int value;
1329
1330         if (amdgpu_in_reset(adev))
1331                 return -EPERM;
1332         if (adev->in_suspend && !adev->in_runpm)
1333                 return -EPERM;
1334
1335         ret = kstrtol(buf, 0, &value);
1336
1337         if (ret)
1338                 return -EINVAL;
1339
1340         ret = pm_runtime_get_sync(ddev->dev);
1341         if (ret < 0) {
1342                 pm_runtime_put_autosuspend(ddev->dev);
1343                 return ret;
1344         }
1345
1346         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1347
1348         pm_runtime_mark_last_busy(ddev->dev);
1349         pm_runtime_put_autosuspend(ddev->dev);
1350
1351         return count;
1352 }
1353
1354 /**
1355  * DOC: pp_power_profile_mode
1356  *
1357  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1358  * related to switching between power levels in a power state.  The file
1359  * pp_power_profile_mode is used for this.
1360  *
1361  * Reading this file outputs a list of all of the predefined power profiles
1362  * and the relevant heuristics settings for that profile.
1363  *
1364  * To select a profile or create a custom profile, first select manual using
1365  * power_dpm_force_performance_level.  Writing the number of a predefined
1366  * profile to pp_power_profile_mode will enable those heuristics.  To
1367  * create a custom set of heuristics, write a string of numbers to the file
1368  * starting with the number of the custom profile along with a setting
1369  * for each heuristic parameter.  Due to differences across asic families
1370  * the heuristic parameters vary from family to family.
1371  *
1372  */
1373
1374 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1375                 struct device_attribute *attr,
1376                 char *buf)
1377 {
1378         struct drm_device *ddev = dev_get_drvdata(dev);
1379         struct amdgpu_device *adev = drm_to_adev(ddev);
1380         ssize_t size;
1381         int ret;
1382
1383         if (amdgpu_in_reset(adev))
1384                 return -EPERM;
1385         if (adev->in_suspend && !adev->in_runpm)
1386                 return -EPERM;
1387
1388         ret = pm_runtime_get_sync(ddev->dev);
1389         if (ret < 0) {
1390                 pm_runtime_put_autosuspend(ddev->dev);
1391                 return ret;
1392         }
1393
1394         size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1395         if (size <= 0)
1396                 size = sysfs_emit(buf, "\n");
1397
1398         pm_runtime_mark_last_busy(ddev->dev);
1399         pm_runtime_put_autosuspend(ddev->dev);
1400
1401         return size;
1402 }
1403
1404
1405 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1406                 struct device_attribute *attr,
1407                 const char *buf,
1408                 size_t count)
1409 {
1410         int ret;
1411         struct drm_device *ddev = dev_get_drvdata(dev);
1412         struct amdgpu_device *adev = drm_to_adev(ddev);
1413         uint32_t parameter_size = 0;
1414         long parameter[64];
1415         char *sub_str, buf_cpy[128];
1416         char *tmp_str;
1417         uint32_t i = 0;
1418         char tmp[2];
1419         long int profile_mode = 0;
1420         const char delimiter[3] = {' ', '\n', '\0'};
1421
1422         if (amdgpu_in_reset(adev))
1423                 return -EPERM;
1424         if (adev->in_suspend && !adev->in_runpm)
1425                 return -EPERM;
1426
1427         tmp[0] = *(buf);
1428         tmp[1] = '\0';
1429         ret = kstrtol(tmp, 0, &profile_mode);
1430         if (ret)
1431                 return -EINVAL;
1432
1433         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1434                 if (count < 2 || count > 127)
1435                         return -EINVAL;
1436                 while (isspace(*++buf))
1437                         i++;
1438                 memcpy(buf_cpy, buf, count-i);
1439                 tmp_str = buf_cpy;
1440                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1441                         if (strlen(sub_str) == 0)
1442                                 continue;
1443                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1444                         if (ret)
1445                                 return -EINVAL;
1446                         parameter_size++;
1447                         while (isspace(*tmp_str))
1448                                 tmp_str++;
1449                 }
1450         }
1451         parameter[parameter_size] = profile_mode;
1452
1453         ret = pm_runtime_get_sync(ddev->dev);
1454         if (ret < 0) {
1455                 pm_runtime_put_autosuspend(ddev->dev);
1456                 return ret;
1457         }
1458
1459         ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1460
1461         pm_runtime_mark_last_busy(ddev->dev);
1462         pm_runtime_put_autosuspend(ddev->dev);
1463
1464         if (!ret)
1465                 return count;
1466
1467         return -EINVAL;
1468 }
1469
1470 static unsigned int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev,
1471                                                     enum amd_pp_sensors sensor,
1472                                                     void *query)
1473 {
1474         int r, size = sizeof(uint32_t);
1475
1476         if (amdgpu_in_reset(adev))
1477                 return -EPERM;
1478         if (adev->in_suspend && !adev->in_runpm)
1479                 return -EPERM;
1480
1481         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1482         if (r < 0) {
1483                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1484                 return r;
1485         }
1486
1487         /* get the sensor value */
1488         r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
1489
1490         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1491         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1492
1493         return r;
1494 }
1495
1496 /**
1497  * DOC: gpu_busy_percent
1498  *
1499  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1500  * is as a percentage.  The file gpu_busy_percent is used for this.
1501  * The SMU firmware computes a percentage of load based on the
1502  * aggregate activity level in the IP cores.
1503  */
1504 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1505                                            struct device_attribute *attr,
1506                                            char *buf)
1507 {
1508         struct drm_device *ddev = dev_get_drvdata(dev);
1509         struct amdgpu_device *adev = drm_to_adev(ddev);
1510         unsigned int value;
1511         int r;
1512
1513         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
1514         if (r)
1515                 return r;
1516
1517         return sysfs_emit(buf, "%d\n", value);
1518 }
1519
1520 /**
1521  * DOC: mem_busy_percent
1522  *
1523  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1524  * is as a percentage.  The file mem_busy_percent is used for this.
1525  * The SMU firmware computes a percentage of load based on the
1526  * aggregate activity level in the IP cores.
1527  */
1528 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1529                                            struct device_attribute *attr,
1530                                            char *buf)
1531 {
1532         struct drm_device *ddev = dev_get_drvdata(dev);
1533         struct amdgpu_device *adev = drm_to_adev(ddev);
1534         unsigned int value;
1535         int r;
1536
1537         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
1538         if (r)
1539                 return r;
1540
1541         return sysfs_emit(buf, "%d\n", value);
1542 }
1543
1544 /**
1545  * DOC: pcie_bw
1546  *
1547  * The amdgpu driver provides a sysfs API for estimating how much data
1548  * has been received and sent by the GPU in the last second through PCIe.
1549  * The file pcie_bw is used for this.
1550  * The Perf counters count the number of received and sent messages and return
1551  * those values, as well as the maximum payload size of a PCIe packet (mps).
1552  * Note that it is not possible to easily and quickly obtain the size of each
1553  * packet transmitted, so we output the max payload size (mps) to allow for
1554  * quick estimation of the PCIe bandwidth usage
1555  */
1556 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1557                 struct device_attribute *attr,
1558                 char *buf)
1559 {
1560         struct drm_device *ddev = dev_get_drvdata(dev);
1561         struct amdgpu_device *adev = drm_to_adev(ddev);
1562         uint64_t count0 = 0, count1 = 0;
1563         int ret;
1564
1565         if (amdgpu_in_reset(adev))
1566                 return -EPERM;
1567         if (adev->in_suspend && !adev->in_runpm)
1568                 return -EPERM;
1569
1570         if (adev->flags & AMD_IS_APU)
1571                 return -ENODATA;
1572
1573         if (!adev->asic_funcs->get_pcie_usage)
1574                 return -ENODATA;
1575
1576         ret = pm_runtime_get_sync(ddev->dev);
1577         if (ret < 0) {
1578                 pm_runtime_put_autosuspend(ddev->dev);
1579                 return ret;
1580         }
1581
1582         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1583
1584         pm_runtime_mark_last_busy(ddev->dev);
1585         pm_runtime_put_autosuspend(ddev->dev);
1586
1587         return sysfs_emit(buf, "%llu %llu %i\n",
1588                           count0, count1, pcie_get_mps(adev->pdev));
1589 }
1590
1591 /**
1592  * DOC: unique_id
1593  *
1594  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1595  * The file unique_id is used for this.
1596  * This will provide a Unique ID that will persist from machine to machine
1597  *
1598  * NOTE: This will only work for GFX9 and newer. This file will be absent
1599  * on unsupported ASICs (GFX8 and older)
1600  */
1601 static ssize_t amdgpu_get_unique_id(struct device *dev,
1602                 struct device_attribute *attr,
1603                 char *buf)
1604 {
1605         struct drm_device *ddev = dev_get_drvdata(dev);
1606         struct amdgpu_device *adev = drm_to_adev(ddev);
1607
1608         if (amdgpu_in_reset(adev))
1609                 return -EPERM;
1610         if (adev->in_suspend && !adev->in_runpm)
1611                 return -EPERM;
1612
1613         if (adev->unique_id)
1614                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1615
1616         return 0;
1617 }
1618
1619 /**
1620  * DOC: thermal_throttling_logging
1621  *
1622  * Thermal throttling pulls down the clock frequency and thus the performance.
1623  * It's an useful mechanism to protect the chip from overheating. Since it
1624  * impacts performance, the user controls whether it is enabled and if so,
1625  * the log frequency.
1626  *
1627  * Reading back the file shows you the status(enabled or disabled) and
1628  * the interval(in seconds) between each thermal logging.
1629  *
1630  * Writing an integer to the file, sets a new logging interval, in seconds.
1631  * The value should be between 1 and 3600. If the value is less than 1,
1632  * thermal logging is disabled. Values greater than 3600 are ignored.
1633  */
1634 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1635                                                      struct device_attribute *attr,
1636                                                      char *buf)
1637 {
1638         struct drm_device *ddev = dev_get_drvdata(dev);
1639         struct amdgpu_device *adev = drm_to_adev(ddev);
1640
1641         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1642                           adev_to_drm(adev)->unique,
1643                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1644                           adev->throttling_logging_rs.interval / HZ + 1);
1645 }
1646
1647 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1648                                                      struct device_attribute *attr,
1649                                                      const char *buf,
1650                                                      size_t count)
1651 {
1652         struct drm_device *ddev = dev_get_drvdata(dev);
1653         struct amdgpu_device *adev = drm_to_adev(ddev);
1654         long throttling_logging_interval;
1655         unsigned long flags;
1656         int ret = 0;
1657
1658         ret = kstrtol(buf, 0, &throttling_logging_interval);
1659         if (ret)
1660                 return ret;
1661
1662         if (throttling_logging_interval > 3600)
1663                 return -EINVAL;
1664
1665         if (throttling_logging_interval > 0) {
1666                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1667                 /*
1668                  * Reset the ratelimit timer internals.
1669                  * This can effectively restart the timer.
1670                  */
1671                 adev->throttling_logging_rs.interval =
1672                         (throttling_logging_interval - 1) * HZ;
1673                 adev->throttling_logging_rs.begin = 0;
1674                 adev->throttling_logging_rs.printed = 0;
1675                 adev->throttling_logging_rs.missed = 0;
1676                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1677
1678                 atomic_set(&adev->throttling_logging_enabled, 1);
1679         } else {
1680                 atomic_set(&adev->throttling_logging_enabled, 0);
1681         }
1682
1683         return count;
1684 }
1685
1686 /**
1687  * DOC: apu_thermal_cap
1688  *
1689  * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1690  * limit temperature in millidegrees Celsius
1691  *
1692  * Reading back the file shows you core limit value
1693  *
1694  * Writing an integer to the file, sets a new thermal limit. The value
1695  * should be between 0 and 100. If the value is less than 0 or greater
1696  * than 100, then the write request will be ignored.
1697  */
1698 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1699                                          struct device_attribute *attr,
1700                                          char *buf)
1701 {
1702         int ret, size;
1703         u32 limit;
1704         struct drm_device *ddev = dev_get_drvdata(dev);
1705         struct amdgpu_device *adev = drm_to_adev(ddev);
1706
1707         ret = pm_runtime_get_sync(ddev->dev);
1708         if (ret < 0) {
1709                 pm_runtime_put_autosuspend(ddev->dev);
1710                 return ret;
1711         }
1712
1713         ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1714         if (!ret)
1715                 size = sysfs_emit(buf, "%u\n", limit);
1716         else
1717                 size = sysfs_emit(buf, "failed to get thermal limit\n");
1718
1719         pm_runtime_mark_last_busy(ddev->dev);
1720         pm_runtime_put_autosuspend(ddev->dev);
1721
1722         return size;
1723 }
1724
1725 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1726                                          struct device_attribute *attr,
1727                                          const char *buf,
1728                                          size_t count)
1729 {
1730         int ret;
1731         u32 value;
1732         struct drm_device *ddev = dev_get_drvdata(dev);
1733         struct amdgpu_device *adev = drm_to_adev(ddev);
1734
1735         ret = kstrtou32(buf, 10, &value);
1736         if (ret)
1737                 return ret;
1738
1739         if (value > 100) {
1740                 dev_err(dev, "Invalid argument !\n");
1741                 return -EINVAL;
1742         }
1743
1744         ret = pm_runtime_get_sync(ddev->dev);
1745         if (ret < 0) {
1746                 pm_runtime_put_autosuspend(ddev->dev);
1747                 return ret;
1748         }
1749
1750         ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1751         if (ret) {
1752                 dev_err(dev, "failed to update thermal limit\n");
1753                 return ret;
1754         }
1755
1756         pm_runtime_mark_last_busy(ddev->dev);
1757         pm_runtime_put_autosuspend(ddev->dev);
1758
1759         return count;
1760 }
1761
1762 /**
1763  * DOC: gpu_metrics
1764  *
1765  * The amdgpu driver provides a sysfs API for retrieving current gpu
1766  * metrics data. The file gpu_metrics is used for this. Reading the
1767  * file will dump all the current gpu metrics data.
1768  *
1769  * These data include temperature, frequency, engines utilization,
1770  * power consume, throttler status, fan speed and cpu core statistics(
1771  * available for APU only). That's it will give a snapshot of all sensors
1772  * at the same time.
1773  */
1774 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1775                                       struct device_attribute *attr,
1776                                       char *buf)
1777 {
1778         struct drm_device *ddev = dev_get_drvdata(dev);
1779         struct amdgpu_device *adev = drm_to_adev(ddev);
1780         void *gpu_metrics;
1781         ssize_t size = 0;
1782         int ret;
1783
1784         if (amdgpu_in_reset(adev))
1785                 return -EPERM;
1786         if (adev->in_suspend && !adev->in_runpm)
1787                 return -EPERM;
1788
1789         ret = pm_runtime_get_sync(ddev->dev);
1790         if (ret < 0) {
1791                 pm_runtime_put_autosuspend(ddev->dev);
1792                 return ret;
1793         }
1794
1795         size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1796         if (size <= 0)
1797                 goto out;
1798
1799         if (size >= PAGE_SIZE)
1800                 size = PAGE_SIZE - 1;
1801
1802         memcpy(buf, gpu_metrics, size);
1803
1804 out:
1805         pm_runtime_mark_last_busy(ddev->dev);
1806         pm_runtime_put_autosuspend(ddev->dev);
1807
1808         return size;
1809 }
1810
1811 static int amdgpu_show_powershift_percent(struct device *dev,
1812                                         char *buf, enum amd_pp_sensors sensor)
1813 {
1814         struct drm_device *ddev = dev_get_drvdata(dev);
1815         struct amdgpu_device *adev = drm_to_adev(ddev);
1816         uint32_t ss_power;
1817         int r = 0, i;
1818
1819         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1820         if (r == -EOPNOTSUPP) {
1821                 /* sensor not available on dGPU, try to read from APU */
1822                 adev = NULL;
1823                 mutex_lock(&mgpu_info.mutex);
1824                 for (i = 0; i < mgpu_info.num_gpu; i++) {
1825                         if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1826                                 adev = mgpu_info.gpu_ins[i].adev;
1827                                 break;
1828                         }
1829                 }
1830                 mutex_unlock(&mgpu_info.mutex);
1831                 if (adev)
1832                         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1833         }
1834
1835         if (r)
1836                 return r;
1837
1838         return sysfs_emit(buf, "%u%%\n", ss_power);
1839 }
1840
1841 /**
1842  * DOC: smartshift_apu_power
1843  *
1844  * The amdgpu driver provides a sysfs API for reporting APU power
1845  * shift in percentage if platform supports smartshift. Value 0 means that
1846  * there is no powershift and values between [1-100] means that the power
1847  * is shifted to APU, the percentage of boost is with respect to APU power
1848  * limit on the platform.
1849  */
1850
1851 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1852                                                char *buf)
1853 {
1854         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
1855 }
1856
1857 /**
1858  * DOC: smartshift_dgpu_power
1859  *
1860  * The amdgpu driver provides a sysfs API for reporting dGPU power
1861  * shift in percentage if platform supports smartshift. Value 0 means that
1862  * there is no powershift and values between [1-100] means that the power is
1863  * shifted to dGPU, the percentage of boost is with respect to dGPU power
1864  * limit on the platform.
1865  */
1866
1867 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1868                                                 char *buf)
1869 {
1870         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
1871 }
1872
1873 /**
1874  * DOC: smartshift_bias
1875  *
1876  * The amdgpu driver provides a sysfs API for reporting the
1877  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1878  * and the default is 0. -100 sets maximum preference to APU
1879  * and 100 sets max perference to dGPU.
1880  */
1881
1882 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1883                                           struct device_attribute *attr,
1884                                           char *buf)
1885 {
1886         int r = 0;
1887
1888         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1889
1890         return r;
1891 }
1892
1893 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1894                                           struct device_attribute *attr,
1895                                           const char *buf, size_t count)
1896 {
1897         struct drm_device *ddev = dev_get_drvdata(dev);
1898         struct amdgpu_device *adev = drm_to_adev(ddev);
1899         int r = 0;
1900         int bias = 0;
1901
1902         if (amdgpu_in_reset(adev))
1903                 return -EPERM;
1904         if (adev->in_suspend && !adev->in_runpm)
1905                 return -EPERM;
1906
1907         r = pm_runtime_get_sync(ddev->dev);
1908         if (r < 0) {
1909                 pm_runtime_put_autosuspend(ddev->dev);
1910                 return r;
1911         }
1912
1913         r = kstrtoint(buf, 10, &bias);
1914         if (r)
1915                 goto out;
1916
1917         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1918                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1919         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1920                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1921
1922         amdgpu_smartshift_bias = bias;
1923         r = count;
1924
1925         /* TODO: update bias level with SMU message */
1926
1927 out:
1928         pm_runtime_mark_last_busy(ddev->dev);
1929         pm_runtime_put_autosuspend(ddev->dev);
1930         return r;
1931 }
1932
1933 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1934                                 uint32_t mask, enum amdgpu_device_attr_states *states)
1935 {
1936         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1937                 *states = ATTR_STATE_UNSUPPORTED;
1938
1939         return 0;
1940 }
1941
1942 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1943                                uint32_t mask, enum amdgpu_device_attr_states *states)
1944 {
1945         uint32_t ss_power;
1946
1947         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1948                 *states = ATTR_STATE_UNSUPPORTED;
1949         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1950                  (void *)&ss_power))
1951                 *states = ATTR_STATE_UNSUPPORTED;
1952         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1953                  (void *)&ss_power))
1954                 *states = ATTR_STATE_UNSUPPORTED;
1955
1956         return 0;
1957 }
1958
1959 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1960         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1961         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1962         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1963         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1964         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1965         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1966         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1967         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1968         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1969         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1970         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1971         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1972         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1973         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1974         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1975         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1976         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
1977         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
1978         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1979         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
1980         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1981         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1982         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
1983         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1984         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1985         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1986         AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1987         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1988         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
1989                               .attr_update = ss_power_attr_update),
1990         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
1991                               .attr_update = ss_power_attr_update),
1992         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
1993                               .attr_update = ss_bias_attr_update),
1994 };
1995
1996 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1997                                uint32_t mask, enum amdgpu_device_attr_states *states)
1998 {
1999         struct device_attribute *dev_attr = &attr->dev_attr;
2000         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
2001         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2002         const char *attr_name = dev_attr->attr.name;
2003
2004         if (!(attr->flags & mask)) {
2005                 *states = ATTR_STATE_UNSUPPORTED;
2006                 return 0;
2007         }
2008
2009 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2010
2011         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2012                 if (gc_ver < IP_VERSION(9, 0, 0))
2013                         *states = ATTR_STATE_UNSUPPORTED;
2014         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2015                 if (gc_ver < IP_VERSION(9, 0, 0) ||
2016                     !amdgpu_device_has_display_hardware(adev))
2017                         *states = ATTR_STATE_UNSUPPORTED;
2018         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2019                 if (mp1_ver < IP_VERSION(10, 0, 0))
2020                         *states = ATTR_STATE_UNSUPPORTED;
2021         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2022                 *states = ATTR_STATE_UNSUPPORTED;
2023                 if (amdgpu_dpm_is_overdrive_supported(adev))
2024                         *states = ATTR_STATE_SUPPORTED;
2025         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2026                 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2027                         *states = ATTR_STATE_UNSUPPORTED;
2028         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2029                 /* PCIe Perf counters won't work on APU nodes */
2030                 if (adev->flags & AMD_IS_APU)
2031                         *states = ATTR_STATE_UNSUPPORTED;
2032         } else if (DEVICE_ATTR_IS(unique_id)) {
2033                 switch (gc_ver) {
2034                 case IP_VERSION(9, 0, 1):
2035                 case IP_VERSION(9, 4, 0):
2036                 case IP_VERSION(9, 4, 1):
2037                 case IP_VERSION(9, 4, 2):
2038                 case IP_VERSION(9, 4, 3):
2039                 case IP_VERSION(10, 3, 0):
2040                 case IP_VERSION(11, 0, 0):
2041                 case IP_VERSION(11, 0, 1):
2042                 case IP_VERSION(11, 0, 2):
2043                         *states = ATTR_STATE_SUPPORTED;
2044                         break;
2045                 default:
2046                         *states = ATTR_STATE_UNSUPPORTED;
2047                 }
2048         } else if (DEVICE_ATTR_IS(pp_features)) {
2049                 if ((adev->flags & AMD_IS_APU &&
2050                      gc_ver != IP_VERSION(9, 4, 3)) ||
2051                     gc_ver < IP_VERSION(9, 0, 0))
2052                         *states = ATTR_STATE_UNSUPPORTED;
2053         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2054                 if (gc_ver < IP_VERSION(9, 1, 0))
2055                         *states = ATTR_STATE_UNSUPPORTED;
2056         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2057                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2058                       gc_ver == IP_VERSION(10, 3, 0) ||
2059                       gc_ver == IP_VERSION(10, 1, 2) ||
2060                       gc_ver == IP_VERSION(11, 0, 0) ||
2061                       gc_ver == IP_VERSION(11, 0, 2) ||
2062                       gc_ver == IP_VERSION(11, 0, 3) ||
2063                       gc_ver == IP_VERSION(9, 4, 3)))
2064                         *states = ATTR_STATE_UNSUPPORTED;
2065         } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2066                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2067                            gc_ver == IP_VERSION(10, 3, 0) ||
2068                            gc_ver == IP_VERSION(11, 0, 2) ||
2069                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2070                         *states = ATTR_STATE_UNSUPPORTED;
2071         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2072                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2073                       gc_ver == IP_VERSION(10, 3, 0) ||
2074                       gc_ver == IP_VERSION(10, 1, 2) ||
2075                       gc_ver == IP_VERSION(11, 0, 0) ||
2076                       gc_ver == IP_VERSION(11, 0, 2) ||
2077                       gc_ver == IP_VERSION(11, 0, 3) ||
2078                       gc_ver == IP_VERSION(9, 4, 3)))
2079                         *states = ATTR_STATE_UNSUPPORTED;
2080         } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2081                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2082                            gc_ver == IP_VERSION(10, 3, 0) ||
2083                            gc_ver == IP_VERSION(11, 0, 2) ||
2084                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2085                         *states = ATTR_STATE_UNSUPPORTED;
2086         } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2087                 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2088                         *states = ATTR_STATE_UNSUPPORTED;
2089                 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
2090                         *states = ATTR_STATE_UNSUPPORTED;
2091         }
2092
2093         switch (gc_ver) {
2094         case IP_VERSION(9, 4, 1):
2095         case IP_VERSION(9, 4, 2):
2096                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2097                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2098                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2099                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2100                         dev_attr->attr.mode &= ~S_IWUGO;
2101                         dev_attr->store = NULL;
2102                 }
2103                 break;
2104         case IP_VERSION(10, 3, 0):
2105                 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2106                     amdgpu_sriov_vf(adev)) {
2107                         dev_attr->attr.mode &= ~0222;
2108                         dev_attr->store = NULL;
2109                 }
2110                 break;
2111         default:
2112                 break;
2113         }
2114
2115         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2116                 /* SMU MP1 does not support dcefclk level setting */
2117                 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2118                         dev_attr->attr.mode &= ~S_IWUGO;
2119                         dev_attr->store = NULL;
2120                 }
2121         }
2122
2123         /* setting should not be allowed from VF if not in one VF mode */
2124         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2125                 dev_attr->attr.mode &= ~S_IWUGO;
2126                 dev_attr->store = NULL;
2127         }
2128
2129 #undef DEVICE_ATTR_IS
2130
2131         return 0;
2132 }
2133
2134
2135 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2136                                      struct amdgpu_device_attr *attr,
2137                                      uint32_t mask, struct list_head *attr_list)
2138 {
2139         int ret = 0;
2140         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2141         struct amdgpu_device_attr_entry *attr_entry;
2142         struct device_attribute *dev_attr;
2143         const char *name;
2144
2145         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2146                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2147
2148         if (!attr)
2149                 return -EINVAL;
2150
2151         dev_attr = &attr->dev_attr;
2152         name = dev_attr->attr.name;
2153
2154         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2155
2156         ret = attr_update(adev, attr, mask, &attr_states);
2157         if (ret) {
2158                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2159                         name, ret);
2160                 return ret;
2161         }
2162
2163         if (attr_states == ATTR_STATE_UNSUPPORTED)
2164                 return 0;
2165
2166         ret = device_create_file(adev->dev, dev_attr);
2167         if (ret) {
2168                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2169                         name, ret);
2170         }
2171
2172         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2173         if (!attr_entry)
2174                 return -ENOMEM;
2175
2176         attr_entry->attr = attr;
2177         INIT_LIST_HEAD(&attr_entry->entry);
2178
2179         list_add_tail(&attr_entry->entry, attr_list);
2180
2181         return ret;
2182 }
2183
2184 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2185 {
2186         struct device_attribute *dev_attr = &attr->dev_attr;
2187
2188         device_remove_file(adev->dev, dev_attr);
2189 }
2190
2191 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2192                                              struct list_head *attr_list);
2193
2194 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2195                                             struct amdgpu_device_attr *attrs,
2196                                             uint32_t counts,
2197                                             uint32_t mask,
2198                                             struct list_head *attr_list)
2199 {
2200         int ret = 0;
2201         uint32_t i = 0;
2202
2203         for (i = 0; i < counts; i++) {
2204                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2205                 if (ret)
2206                         goto failed;
2207         }
2208
2209         return 0;
2210
2211 failed:
2212         amdgpu_device_attr_remove_groups(adev, attr_list);
2213
2214         return ret;
2215 }
2216
2217 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2218                                              struct list_head *attr_list)
2219 {
2220         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2221
2222         if (list_empty(attr_list))
2223                 return ;
2224
2225         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2226                 amdgpu_device_attr_remove(adev, entry->attr);
2227                 list_del(&entry->entry);
2228                 kfree(entry);
2229         }
2230 }
2231
2232 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2233                                       struct device_attribute *attr,
2234                                       char *buf)
2235 {
2236         struct amdgpu_device *adev = dev_get_drvdata(dev);
2237         int channel = to_sensor_dev_attr(attr)->index;
2238         int r, temp = 0;
2239
2240         if (channel >= PP_TEMP_MAX)
2241                 return -EINVAL;
2242
2243         switch (channel) {
2244         case PP_TEMP_JUNCTION:
2245                 /* get current junction temperature */
2246                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2247                                            (void *)&temp);
2248                 break;
2249         case PP_TEMP_EDGE:
2250                 /* get current edge temperature */
2251                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2252                                            (void *)&temp);
2253                 break;
2254         case PP_TEMP_MEM:
2255                 /* get current memory temperature */
2256                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2257                                            (void *)&temp);
2258                 break;
2259         default:
2260                 r = -EINVAL;
2261                 break;
2262         }
2263
2264         if (r)
2265                 return r;
2266
2267         return sysfs_emit(buf, "%d\n", temp);
2268 }
2269
2270 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2271                                              struct device_attribute *attr,
2272                                              char *buf)
2273 {
2274         struct amdgpu_device *adev = dev_get_drvdata(dev);
2275         int hyst = to_sensor_dev_attr(attr)->index;
2276         int temp;
2277
2278         if (hyst)
2279                 temp = adev->pm.dpm.thermal.min_temp;
2280         else
2281                 temp = adev->pm.dpm.thermal.max_temp;
2282
2283         return sysfs_emit(buf, "%d\n", temp);
2284 }
2285
2286 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2287                                              struct device_attribute *attr,
2288                                              char *buf)
2289 {
2290         struct amdgpu_device *adev = dev_get_drvdata(dev);
2291         int hyst = to_sensor_dev_attr(attr)->index;
2292         int temp;
2293
2294         if (hyst)
2295                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2296         else
2297                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2298
2299         return sysfs_emit(buf, "%d\n", temp);
2300 }
2301
2302 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2303                                              struct device_attribute *attr,
2304                                              char *buf)
2305 {
2306         struct amdgpu_device *adev = dev_get_drvdata(dev);
2307         int hyst = to_sensor_dev_attr(attr)->index;
2308         int temp;
2309
2310         if (hyst)
2311                 temp = adev->pm.dpm.thermal.min_mem_temp;
2312         else
2313                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2314
2315         return sysfs_emit(buf, "%d\n", temp);
2316 }
2317
2318 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2319                                              struct device_attribute *attr,
2320                                              char *buf)
2321 {
2322         int channel = to_sensor_dev_attr(attr)->index;
2323
2324         if (channel >= PP_TEMP_MAX)
2325                 return -EINVAL;
2326
2327         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2328 }
2329
2330 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2331                                              struct device_attribute *attr,
2332                                              char *buf)
2333 {
2334         struct amdgpu_device *adev = dev_get_drvdata(dev);
2335         int channel = to_sensor_dev_attr(attr)->index;
2336         int temp = 0;
2337
2338         if (channel >= PP_TEMP_MAX)
2339                 return -EINVAL;
2340
2341         switch (channel) {
2342         case PP_TEMP_JUNCTION:
2343                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2344                 break;
2345         case PP_TEMP_EDGE:
2346                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2347                 break;
2348         case PP_TEMP_MEM:
2349                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2350                 break;
2351         }
2352
2353         return sysfs_emit(buf, "%d\n", temp);
2354 }
2355
2356 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2357                                             struct device_attribute *attr,
2358                                             char *buf)
2359 {
2360         struct amdgpu_device *adev = dev_get_drvdata(dev);
2361         u32 pwm_mode = 0;
2362         int ret;
2363
2364         if (amdgpu_in_reset(adev))
2365                 return -EPERM;
2366         if (adev->in_suspend && !adev->in_runpm)
2367                 return -EPERM;
2368
2369         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2370         if (ret < 0) {
2371                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2372                 return ret;
2373         }
2374
2375         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2376
2377         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2378         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2379
2380         if (ret)
2381                 return -EINVAL;
2382
2383         return sysfs_emit(buf, "%u\n", pwm_mode);
2384 }
2385
2386 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2387                                             struct device_attribute *attr,
2388                                             const char *buf,
2389                                             size_t count)
2390 {
2391         struct amdgpu_device *adev = dev_get_drvdata(dev);
2392         int err, ret;
2393         int value;
2394
2395         if (amdgpu_in_reset(adev))
2396                 return -EPERM;
2397         if (adev->in_suspend && !adev->in_runpm)
2398                 return -EPERM;
2399
2400         err = kstrtoint(buf, 10, &value);
2401         if (err)
2402                 return err;
2403
2404         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2405         if (ret < 0) {
2406                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2407                 return ret;
2408         }
2409
2410         ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2411
2412         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2413         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2414
2415         if (ret)
2416                 return -EINVAL;
2417
2418         return count;
2419 }
2420
2421 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2422                                          struct device_attribute *attr,
2423                                          char *buf)
2424 {
2425         return sysfs_emit(buf, "%i\n", 0);
2426 }
2427
2428 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2429                                          struct device_attribute *attr,
2430                                          char *buf)
2431 {
2432         return sysfs_emit(buf, "%i\n", 255);
2433 }
2434
2435 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2436                                      struct device_attribute *attr,
2437                                      const char *buf, size_t count)
2438 {
2439         struct amdgpu_device *adev = dev_get_drvdata(dev);
2440         int err;
2441         u32 value;
2442         u32 pwm_mode;
2443
2444         if (amdgpu_in_reset(adev))
2445                 return -EPERM;
2446         if (adev->in_suspend && !adev->in_runpm)
2447                 return -EPERM;
2448
2449         err = kstrtou32(buf, 10, &value);
2450         if (err)
2451                 return err;
2452
2453         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2454         if (err < 0) {
2455                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2456                 return err;
2457         }
2458
2459         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2460         if (err)
2461                 goto out;
2462
2463         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2464                 pr_info("manual fan speed control should be enabled first\n");
2465                 err = -EINVAL;
2466                 goto out;
2467         }
2468
2469         err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2470
2471 out:
2472         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2473         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2474
2475         if (err)
2476                 return err;
2477
2478         return count;
2479 }
2480
2481 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2482                                      struct device_attribute *attr,
2483                                      char *buf)
2484 {
2485         struct amdgpu_device *adev = dev_get_drvdata(dev);
2486         int err;
2487         u32 speed = 0;
2488
2489         if (amdgpu_in_reset(adev))
2490                 return -EPERM;
2491         if (adev->in_suspend && !adev->in_runpm)
2492                 return -EPERM;
2493
2494         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2495         if (err < 0) {
2496                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2497                 return err;
2498         }
2499
2500         err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2501
2502         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2503         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2504
2505         if (err)
2506                 return err;
2507
2508         return sysfs_emit(buf, "%i\n", speed);
2509 }
2510
2511 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2512                                            struct device_attribute *attr,
2513                                            char *buf)
2514 {
2515         struct amdgpu_device *adev = dev_get_drvdata(dev);
2516         int err;
2517         u32 speed = 0;
2518
2519         if (amdgpu_in_reset(adev))
2520                 return -EPERM;
2521         if (adev->in_suspend && !adev->in_runpm)
2522                 return -EPERM;
2523
2524         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2525         if (err < 0) {
2526                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2527                 return err;
2528         }
2529
2530         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2531
2532         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2533         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2534
2535         if (err)
2536                 return err;
2537
2538         return sysfs_emit(buf, "%i\n", speed);
2539 }
2540
2541 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2542                                          struct device_attribute *attr,
2543                                          char *buf)
2544 {
2545         struct amdgpu_device *adev = dev_get_drvdata(dev);
2546         u32 min_rpm = 0;
2547         int r;
2548
2549         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2550                                    (void *)&min_rpm);
2551
2552         if (r)
2553                 return r;
2554
2555         return sysfs_emit(buf, "%d\n", min_rpm);
2556 }
2557
2558 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2559                                          struct device_attribute *attr,
2560                                          char *buf)
2561 {
2562         struct amdgpu_device *adev = dev_get_drvdata(dev);
2563         u32 max_rpm = 0;
2564         int r;
2565
2566         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2567                                    (void *)&max_rpm);
2568
2569         if (r)
2570                 return r;
2571
2572         return sysfs_emit(buf, "%d\n", max_rpm);
2573 }
2574
2575 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2576                                            struct device_attribute *attr,
2577                                            char *buf)
2578 {
2579         struct amdgpu_device *adev = dev_get_drvdata(dev);
2580         int err;
2581         u32 rpm = 0;
2582
2583         if (amdgpu_in_reset(adev))
2584                 return -EPERM;
2585         if (adev->in_suspend && !adev->in_runpm)
2586                 return -EPERM;
2587
2588         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2589         if (err < 0) {
2590                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2591                 return err;
2592         }
2593
2594         err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2595
2596         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2597         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2598
2599         if (err)
2600                 return err;
2601
2602         return sysfs_emit(buf, "%i\n", rpm);
2603 }
2604
2605 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2606                                      struct device_attribute *attr,
2607                                      const char *buf, size_t count)
2608 {
2609         struct amdgpu_device *adev = dev_get_drvdata(dev);
2610         int err;
2611         u32 value;
2612         u32 pwm_mode;
2613
2614         if (amdgpu_in_reset(adev))
2615                 return -EPERM;
2616         if (adev->in_suspend && !adev->in_runpm)
2617                 return -EPERM;
2618
2619         err = kstrtou32(buf, 10, &value);
2620         if (err)
2621                 return err;
2622
2623         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2624         if (err < 0) {
2625                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2626                 return err;
2627         }
2628
2629         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2630         if (err)
2631                 goto out;
2632
2633         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2634                 err = -ENODATA;
2635                 goto out;
2636         }
2637
2638         err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2639
2640 out:
2641         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2642         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2643
2644         if (err)
2645                 return err;
2646
2647         return count;
2648 }
2649
2650 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2651                                             struct device_attribute *attr,
2652                                             char *buf)
2653 {
2654         struct amdgpu_device *adev = dev_get_drvdata(dev);
2655         u32 pwm_mode = 0;
2656         int ret;
2657
2658         if (amdgpu_in_reset(adev))
2659                 return -EPERM;
2660         if (adev->in_suspend && !adev->in_runpm)
2661                 return -EPERM;
2662
2663         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2664         if (ret < 0) {
2665                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2666                 return ret;
2667         }
2668
2669         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2670
2671         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2672         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2673
2674         if (ret)
2675                 return -EINVAL;
2676
2677         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2678 }
2679
2680 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2681                                             struct device_attribute *attr,
2682                                             const char *buf,
2683                                             size_t count)
2684 {
2685         struct amdgpu_device *adev = dev_get_drvdata(dev);
2686         int err;
2687         int value;
2688         u32 pwm_mode;
2689
2690         if (amdgpu_in_reset(adev))
2691                 return -EPERM;
2692         if (adev->in_suspend && !adev->in_runpm)
2693                 return -EPERM;
2694
2695         err = kstrtoint(buf, 10, &value);
2696         if (err)
2697                 return err;
2698
2699         if (value == 0)
2700                 pwm_mode = AMD_FAN_CTRL_AUTO;
2701         else if (value == 1)
2702                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2703         else
2704                 return -EINVAL;
2705
2706         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2707         if (err < 0) {
2708                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2709                 return err;
2710         }
2711
2712         err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2713
2714         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2715         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2716
2717         if (err)
2718                 return -EINVAL;
2719
2720         return count;
2721 }
2722
2723 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2724                                         struct device_attribute *attr,
2725                                         char *buf)
2726 {
2727         struct amdgpu_device *adev = dev_get_drvdata(dev);
2728         u32 vddgfx;
2729         int r;
2730
2731         /* get the voltage */
2732         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
2733                                    (void *)&vddgfx);
2734         if (r)
2735                 return r;
2736
2737         return sysfs_emit(buf, "%d\n", vddgfx);
2738 }
2739
2740 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2741                                               struct device_attribute *attr,
2742                                               char *buf)
2743 {
2744         return sysfs_emit(buf, "vddgfx\n");
2745 }
2746
2747 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2748                                        struct device_attribute *attr,
2749                                        char *buf)
2750 {
2751         struct amdgpu_device *adev = dev_get_drvdata(dev);
2752         u32 vddnb;
2753         int r;
2754
2755         /* only APUs have vddnb */
2756         if  (!(adev->flags & AMD_IS_APU))
2757                 return -EINVAL;
2758
2759         /* get the voltage */
2760         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
2761                                    (void *)&vddnb);
2762         if (r)
2763                 return r;
2764
2765         return sysfs_emit(buf, "%d\n", vddnb);
2766 }
2767
2768 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2769                                               struct device_attribute *attr,
2770                                               char *buf)
2771 {
2772         return sysfs_emit(buf, "vddnb\n");
2773 }
2774
2775 static unsigned int amdgpu_hwmon_get_power(struct device *dev,
2776                                            enum amd_pp_sensors sensor)
2777 {
2778         struct amdgpu_device *adev = dev_get_drvdata(dev);
2779         unsigned int uw;
2780         u32 query = 0;
2781         int r;
2782
2783         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query);
2784         if (r)
2785                 return r;
2786
2787         /* convert to microwatts */
2788         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2789
2790         return uw;
2791 }
2792
2793 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2794                                            struct device_attribute *attr,
2795                                            char *buf)
2796 {
2797         unsigned int val;
2798
2799         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
2800         if (val < 0)
2801                 return val;
2802
2803         return sysfs_emit(buf, "%u\n", val);
2804 }
2805
2806 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
2807                                              struct device_attribute *attr,
2808                                              char *buf)
2809 {
2810         unsigned int val;
2811
2812         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
2813         if (val < 0)
2814                 return val;
2815
2816         return sysfs_emit(buf, "%u\n", val);
2817 }
2818
2819 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2820                                          struct device_attribute *attr,
2821                                          char *buf)
2822 {
2823         return sysfs_emit(buf, "%i\n", 0);
2824 }
2825
2826
2827 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2828                                         struct device_attribute *attr,
2829                                         char *buf,
2830                                         enum pp_power_limit_level pp_limit_level)
2831 {
2832         struct amdgpu_device *adev = dev_get_drvdata(dev);
2833         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2834         uint32_t limit;
2835         ssize_t size;
2836         int r;
2837
2838         if (amdgpu_in_reset(adev))
2839                 return -EPERM;
2840         if (adev->in_suspend && !adev->in_runpm)
2841                 return -EPERM;
2842
2843         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2844         if (r < 0) {
2845                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2846                 return r;
2847         }
2848
2849         r = amdgpu_dpm_get_power_limit(adev, &limit,
2850                                       pp_limit_level, power_type);
2851
2852         if (!r)
2853                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2854         else
2855                 size = sysfs_emit(buf, "\n");
2856
2857         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2858         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2859
2860         return size;
2861 }
2862
2863
2864 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2865                                          struct device_attribute *attr,
2866                                          char *buf)
2867 {
2868         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2869
2870 }
2871
2872 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2873                                          struct device_attribute *attr,
2874                                          char *buf)
2875 {
2876         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2877
2878 }
2879
2880 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2881                                          struct device_attribute *attr,
2882                                          char *buf)
2883 {
2884         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
2885
2886 }
2887
2888 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2889                                          struct device_attribute *attr,
2890                                          char *buf)
2891 {
2892         struct amdgpu_device *adev = dev_get_drvdata(dev);
2893         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2894
2895         if (gc_ver == IP_VERSION(10, 3, 1))
2896                 return sysfs_emit(buf, "%s\n",
2897                                   to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
2898                                   "fastPPT" : "slowPPT");
2899         else
2900                 return sysfs_emit(buf, "PPT\n");
2901 }
2902
2903 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2904                 struct device_attribute *attr,
2905                 const char *buf,
2906                 size_t count)
2907 {
2908         struct amdgpu_device *adev = dev_get_drvdata(dev);
2909         int limit_type = to_sensor_dev_attr(attr)->index;
2910         int err;
2911         u32 value;
2912
2913         if (amdgpu_in_reset(adev))
2914                 return -EPERM;
2915         if (adev->in_suspend && !adev->in_runpm)
2916                 return -EPERM;
2917
2918         if (amdgpu_sriov_vf(adev))
2919                 return -EINVAL;
2920
2921         err = kstrtou32(buf, 10, &value);
2922         if (err)
2923                 return err;
2924
2925         value = value / 1000000; /* convert to Watt */
2926         value |= limit_type << 24;
2927
2928         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2929         if (err < 0) {
2930                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2931                 return err;
2932         }
2933
2934         err = amdgpu_dpm_set_power_limit(adev, value);
2935
2936         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2937         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2938
2939         if (err)
2940                 return err;
2941
2942         return count;
2943 }
2944
2945 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2946                                       struct device_attribute *attr,
2947                                       char *buf)
2948 {
2949         struct amdgpu_device *adev = dev_get_drvdata(dev);
2950         uint32_t sclk;
2951         int r;
2952
2953         /* get the sclk */
2954         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2955                                    (void *)&sclk);
2956         if (r)
2957                 return r;
2958
2959         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
2960 }
2961
2962 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2963                                             struct device_attribute *attr,
2964                                             char *buf)
2965 {
2966         return sysfs_emit(buf, "sclk\n");
2967 }
2968
2969 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2970                                       struct device_attribute *attr,
2971                                       char *buf)
2972 {
2973         struct amdgpu_device *adev = dev_get_drvdata(dev);
2974         uint32_t mclk;
2975         int r;
2976
2977         /* get the sclk */
2978         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2979                                    (void *)&mclk);
2980         if (r)
2981                 return r;
2982
2983         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
2984 }
2985
2986 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2987                                             struct device_attribute *attr,
2988                                             char *buf)
2989 {
2990         return sysfs_emit(buf, "mclk\n");
2991 }
2992
2993 /**
2994  * DOC: hwmon
2995  *
2996  * The amdgpu driver exposes the following sensor interfaces:
2997  *
2998  * - GPU temperature (via the on-die sensor)
2999  *
3000  * - GPU voltage
3001  *
3002  * - Northbridge voltage (APUs only)
3003  *
3004  * - GPU power
3005  *
3006  * - GPU fan
3007  *
3008  * - GPU gfx/compute engine clock
3009  *
3010  * - GPU memory clock (dGPU only)
3011  *
3012  * hwmon interfaces for GPU temperature:
3013  *
3014  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3015  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3016  *
3017  * - temp[1-3]_label: temperature channel label
3018  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3019  *
3020  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3021  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3022  *
3023  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3024  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3025  *
3026  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3027  *   - these are supported on SOC15 dGPUs only
3028  *
3029  * hwmon interfaces for GPU voltage:
3030  *
3031  * - in0_input: the voltage on the GPU in millivolts
3032  *
3033  * - in1_input: the voltage on the Northbridge in millivolts
3034  *
3035  * hwmon interfaces for GPU power:
3036  *
3037  * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3038  *
3039  * - power1_input: instantaneous power used by the SoC in microWatts.  On APUs this includes the CPU.
3040  *
3041  * - power1_cap_min: minimum cap supported in microWatts
3042  *
3043  * - power1_cap_max: maximum cap supported in microWatts
3044  *
3045  * - power1_cap: selected power cap in microWatts
3046  *
3047  * hwmon interfaces for GPU fan:
3048  *
3049  * - pwm1: pulse width modulation fan level (0-255)
3050  *
3051  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3052  *
3053  * - pwm1_min: pulse width modulation fan control minimum level (0)
3054  *
3055  * - pwm1_max: pulse width modulation fan control maximum level (255)
3056  *
3057  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3058  *
3059  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3060  *
3061  * - fan1_input: fan speed in RPM
3062  *
3063  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3064  *
3065  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3066  *
3067  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3068  *       That will get the former one overridden.
3069  *
3070  * hwmon interfaces for GPU clocks:
3071  *
3072  * - freq1_input: the gfx/compute clock in hertz
3073  *
3074  * - freq2_input: the memory clock in hertz
3075  *
3076  * You can use hwmon tools like sensors to view this information on your system.
3077  *
3078  */
3079
3080 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3081 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3082 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3083 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3084 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3085 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3086 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3087 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3088 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3089 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3090 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3091 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3092 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3093 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3094 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3095 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3096 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3097 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3098 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3099 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3100 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3101 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3102 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3103 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3104 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3105 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3106 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3107 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3108 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3109 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
3110 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3111 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3112 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3113 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3114 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3115 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3116 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3117 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3118 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3119 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3120 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3121 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3122 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3123 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3124 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3125
3126 static struct attribute *hwmon_attributes[] = {
3127         &sensor_dev_attr_temp1_input.dev_attr.attr,
3128         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3129         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3130         &sensor_dev_attr_temp2_input.dev_attr.attr,
3131         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3132         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3133         &sensor_dev_attr_temp3_input.dev_attr.attr,
3134         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3135         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3136         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3137         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3138         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3139         &sensor_dev_attr_temp1_label.dev_attr.attr,
3140         &sensor_dev_attr_temp2_label.dev_attr.attr,
3141         &sensor_dev_attr_temp3_label.dev_attr.attr,
3142         &sensor_dev_attr_pwm1.dev_attr.attr,
3143         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3144         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3145         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3146         &sensor_dev_attr_fan1_input.dev_attr.attr,
3147         &sensor_dev_attr_fan1_min.dev_attr.attr,
3148         &sensor_dev_attr_fan1_max.dev_attr.attr,
3149         &sensor_dev_attr_fan1_target.dev_attr.attr,
3150         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3151         &sensor_dev_attr_in0_input.dev_attr.attr,
3152         &sensor_dev_attr_in0_label.dev_attr.attr,
3153         &sensor_dev_attr_in1_input.dev_attr.attr,
3154         &sensor_dev_attr_in1_label.dev_attr.attr,
3155         &sensor_dev_attr_power1_average.dev_attr.attr,
3156         &sensor_dev_attr_power1_input.dev_attr.attr,
3157         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3158         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3159         &sensor_dev_attr_power1_cap.dev_attr.attr,
3160         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3161         &sensor_dev_attr_power1_label.dev_attr.attr,
3162         &sensor_dev_attr_power2_average.dev_attr.attr,
3163         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3164         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3165         &sensor_dev_attr_power2_cap.dev_attr.attr,
3166         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3167         &sensor_dev_attr_power2_label.dev_attr.attr,
3168         &sensor_dev_attr_freq1_input.dev_attr.attr,
3169         &sensor_dev_attr_freq1_label.dev_attr.attr,
3170         &sensor_dev_attr_freq2_input.dev_attr.attr,
3171         &sensor_dev_attr_freq2_label.dev_attr.attr,
3172         NULL
3173 };
3174
3175 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3176                                         struct attribute *attr, int index)
3177 {
3178         struct device *dev = kobj_to_dev(kobj);
3179         struct amdgpu_device *adev = dev_get_drvdata(dev);
3180         umode_t effective_mode = attr->mode;
3181         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3182         uint32_t tmp;
3183
3184         /* under multi-vf mode, the hwmon attributes are all not supported */
3185         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3186                 return 0;
3187
3188         /* under pp one vf mode manage of hwmon attributes is not supported */
3189         if (amdgpu_sriov_is_pp_one_vf(adev))
3190                 effective_mode &= ~S_IWUSR;
3191
3192         /* Skip fan attributes if fan is not present */
3193         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3194             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3195             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3196             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3197             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3198             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3199             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3200             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3201             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3202                 return 0;
3203
3204         /* Skip fan attributes on APU */
3205         if ((adev->flags & AMD_IS_APU) &&
3206             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3207              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3208              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3209              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3210              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3211              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3212              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3213              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3214              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3215                 return 0;
3216
3217         /* Skip crit temp on APU */
3218         if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3219             (gc_ver == IP_VERSION(9, 4, 3))) &&
3220             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3221              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3222                 return 0;
3223
3224         /* Skip limit attributes if DPM is not enabled */
3225         if (!adev->pm.dpm_enabled &&
3226             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3227              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3228              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3229              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3230              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3231              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3232              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3233              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3234              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3235              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3236              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3237                 return 0;
3238
3239         /* mask fan attributes if we have no bindings for this asic to expose */
3240         if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3241               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3242             ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3243              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3244                 effective_mode &= ~S_IRUGO;
3245
3246         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3247               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3248               ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3249               attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3250                 effective_mode &= ~S_IWUSR;
3251
3252         /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3253         if (((adev->family == AMDGPU_FAMILY_SI) ||
3254              ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3255               (gc_ver != IP_VERSION(9, 4, 3)))) &&
3256             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3257              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3258              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3259              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3260                 return 0;
3261
3262         /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3263         if (((adev->family == AMDGPU_FAMILY_SI) ||
3264              ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3265             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3266                 return 0;
3267
3268         /* not all products support both average and instantaneous */
3269         if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
3270             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP)
3271                 return 0;
3272         if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
3273             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP)
3274                 return 0;
3275
3276         /* hide max/min values if we can't both query and manage the fan */
3277         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3278               (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3279               (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3280               (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3281             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3282              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3283                 return 0;
3284
3285         if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3286              (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3287              (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3288              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3289                 return 0;
3290
3291         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3292              adev->family == AMDGPU_FAMILY_KV ||        /* not implemented yet */
3293              (gc_ver == IP_VERSION(9, 4, 3))) &&
3294             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3295              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3296                 return 0;
3297
3298         /* only APUs other than gc 9,4,3 have vddnb */
3299         if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3300             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3301              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3302                 return 0;
3303
3304         /* no mclk on APUs other than gc 9,4,3*/
3305         if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3306             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3307              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3308                 return 0;
3309
3310         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3311             (gc_ver != IP_VERSION(9, 4, 3)) &&
3312             (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3313              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3314              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3315              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3316                 return 0;
3317
3318         /* hotspot temperature for gc 9,4,3*/
3319         if ((gc_ver == IP_VERSION(9, 4, 3)) &&
3320             (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3321              attr == &sensor_dev_attr_temp1_label.dev_attr.attr))
3322                 return 0;
3323
3324         /* only SOC15 dGPUs support hotspot and mem temperatures */
3325         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0) ||
3326             (gc_ver == IP_VERSION(9, 4, 3))) &&
3327             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3328              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3329              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3330              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3331              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3332              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3333              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3334                 return 0;
3335
3336         /* only Vangogh has fast PPT limit and power labels */
3337         if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3338             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3339              attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3340              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3341              attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3342              attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3343              attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3344                 return 0;
3345
3346         return effective_mode;
3347 }
3348
3349 static const struct attribute_group hwmon_attrgroup = {
3350         .attrs = hwmon_attributes,
3351         .is_visible = hwmon_attributes_visible,
3352 };
3353
3354 static const struct attribute_group *hwmon_groups[] = {
3355         &hwmon_attrgroup,
3356         NULL
3357 };
3358
3359 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3360 {
3361         int ret;
3362         uint32_t mask = 0;
3363
3364         if (adev->pm.sysfs_initialized)
3365                 return 0;
3366
3367         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3368
3369         if (adev->pm.dpm_enabled == 0)
3370                 return 0;
3371
3372         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3373                                                                    DRIVER_NAME, adev,
3374                                                                    hwmon_groups);
3375         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3376                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3377                 dev_err(adev->dev,
3378                         "Unable to register hwmon device: %d\n", ret);
3379                 return ret;
3380         }
3381
3382         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3383         case SRIOV_VF_MODE_ONE_VF:
3384                 mask = ATTR_FLAG_ONEVF;
3385                 break;
3386         case SRIOV_VF_MODE_MULTI_VF:
3387                 mask = 0;
3388                 break;
3389         case SRIOV_VF_MODE_BARE_METAL:
3390         default:
3391                 mask = ATTR_FLAG_MASK_ALL;
3392                 break;
3393         }
3394
3395         ret = amdgpu_device_attr_create_groups(adev,
3396                                                amdgpu_device_attrs,
3397                                                ARRAY_SIZE(amdgpu_device_attrs),
3398                                                mask,
3399                                                &adev->pm.pm_attr_list);
3400         if (ret)
3401                 return ret;
3402
3403         adev->pm.sysfs_initialized = true;
3404
3405         return 0;
3406 }
3407
3408 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3409 {
3410         if (adev->pm.int_hwmon_dev)
3411                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3412
3413         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3414 }
3415
3416 /*
3417  * Debugfs info
3418  */
3419 #if defined(CONFIG_DEBUG_FS)
3420
3421 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3422                                            struct amdgpu_device *adev)
3423 {
3424         uint16_t *p_val;
3425         uint32_t size;
3426         int i;
3427         uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
3428
3429         if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
3430                 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
3431                                 GFP_KERNEL);
3432
3433                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3434                                             (void *)p_val, &size)) {
3435                         for (i = 0; i < num_cpu_cores; i++)
3436                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3437                                            *(p_val + i), i);
3438                 }
3439
3440                 kfree(p_val);
3441         }
3442 }
3443
3444 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3445 {
3446         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
3447         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3448         uint32_t value;
3449         uint64_t value64 = 0;
3450         uint32_t query = 0;
3451         int size;
3452
3453         /* GPU Clocks */
3454         size = sizeof(value);
3455         seq_printf(m, "GFX Clocks and Power:\n");
3456
3457         amdgpu_debugfs_prints_cpu_info(m, adev);
3458
3459         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3460                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3461         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3462                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3463         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3464                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3465         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3466                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3467         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3468                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3469         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3470                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3471         size = sizeof(uint32_t);
3472         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size))
3473                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3474         size = sizeof(value);
3475         seq_printf(m, "\n");
3476
3477         /* GPU Temp */
3478         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3479                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3480
3481         /* GPU Load */
3482         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3483                 seq_printf(m, "GPU Load: %u %%\n", value);
3484         /* MEM Load */
3485         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3486                 seq_printf(m, "MEM Load: %u %%\n", value);
3487
3488         seq_printf(m, "\n");
3489
3490         /* SMC feature mask */
3491         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3492                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3493
3494         /* ASICs greater than CHIP_VEGA20 supports these sensors */
3495         if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
3496                 /* VCN clocks */
3497                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3498                         if (!value) {
3499                                 seq_printf(m, "VCN: Disabled\n");
3500                         } else {
3501                                 seq_printf(m, "VCN: Enabled\n");
3502                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3503                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3504                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3505                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3506                         }
3507                 }
3508                 seq_printf(m, "\n");
3509         } else {
3510                 /* UVD clocks */
3511                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3512                         if (!value) {
3513                                 seq_printf(m, "UVD: Disabled\n");
3514                         } else {
3515                                 seq_printf(m, "UVD: Enabled\n");
3516                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3517                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3518                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3519                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3520                         }
3521                 }
3522                 seq_printf(m, "\n");
3523
3524                 /* VCE clocks */
3525                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3526                         if (!value) {
3527                                 seq_printf(m, "VCE: Disabled\n");
3528                         } else {
3529                                 seq_printf(m, "VCE: Enabled\n");
3530                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3531                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3532                         }
3533                 }
3534         }
3535
3536         return 0;
3537 }
3538
3539 static const struct cg_flag_name clocks[] = {
3540         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
3541         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
3542         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
3543         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
3544         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
3545         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
3546         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
3547         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
3548         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
3549         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
3550         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
3551         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
3552         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
3553         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
3554         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
3555         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
3556         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
3557         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
3558         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
3559         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
3560         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
3561         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
3562         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
3563         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
3564         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
3565         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
3566         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
3567         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
3568         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
3569         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
3570         {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
3571         {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
3572         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
3573         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
3574         {0, NULL},
3575 };
3576
3577 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
3578 {
3579         int i;
3580
3581         for (i = 0; clocks[i].flag; i++)
3582                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3583                            (flags & clocks[i].flag) ? "On" : "Off");
3584 }
3585
3586 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3587 {
3588         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3589         struct drm_device *dev = adev_to_drm(adev);
3590         u64 flags = 0;
3591         int r;
3592
3593         if (amdgpu_in_reset(adev))
3594                 return -EPERM;
3595         if (adev->in_suspend && !adev->in_runpm)
3596                 return -EPERM;
3597
3598         r = pm_runtime_get_sync(dev->dev);
3599         if (r < 0) {
3600                 pm_runtime_put_autosuspend(dev->dev);
3601                 return r;
3602         }
3603
3604         if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
3605                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3606                 if (r)
3607                         goto out;
3608         }
3609
3610         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3611
3612         seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
3613         amdgpu_parse_cg_state(m, flags);
3614         seq_printf(m, "\n");
3615
3616 out:
3617         pm_runtime_mark_last_busy(dev->dev);
3618         pm_runtime_put_autosuspend(dev->dev);
3619
3620         return r;
3621 }
3622
3623 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3624
3625 /*
3626  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3627  *
3628  * Reads debug memory region allocated to PMFW
3629  */
3630 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3631                                          size_t size, loff_t *pos)
3632 {
3633         struct amdgpu_device *adev = file_inode(f)->i_private;
3634         size_t smu_prv_buf_size;
3635         void *smu_prv_buf;
3636         int ret = 0;
3637
3638         if (amdgpu_in_reset(adev))
3639                 return -EPERM;
3640         if (adev->in_suspend && !adev->in_runpm)
3641                 return -EPERM;
3642
3643         ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
3644         if (ret)
3645                 return ret;
3646
3647         if (!smu_prv_buf || !smu_prv_buf_size)
3648                 return -EINVAL;
3649
3650         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3651                                        smu_prv_buf_size);
3652 }
3653
3654 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3655         .owner = THIS_MODULE,
3656         .open = simple_open,
3657         .read = amdgpu_pm_prv_buffer_read,
3658         .llseek = default_llseek,
3659 };
3660
3661 #endif
3662
3663 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3664 {
3665 #if defined(CONFIG_DEBUG_FS)
3666         struct drm_minor *minor = adev_to_drm(adev)->primary;
3667         struct dentry *root = minor->debugfs_root;
3668
3669         if (!adev->pm.dpm_enabled)
3670                 return;
3671
3672         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3673                             &amdgpu_debugfs_pm_info_fops);
3674
3675         if (adev->pm.smu_prv_buffer_size > 0)
3676                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3677                                          adev,
3678                                          &amdgpu_debugfs_pm_prv_buffer_fops,
3679                                          adev->pm.smu_prv_buffer_size);
3680
3681         amdgpu_dpm_stb_debug_fs_init(adev);
3682 #endif
3683 }