drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h

   1 /*
   2  * Volcanic Islands IV SRC Register documentation
   3  *
   4  * Copyright (C) 2015  Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef _IVSRCID_VISLANDS30_H_
  25 #define _IVSRCID_VISLANDS30_H_
  26
  27
  28 // IV Source IDs
  29
  30 #define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT                         7       // 0x07
  31 #define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT                  0
  32
  33 #define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP                           8       // 0x08
  34 #define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP                    0
  35
  36 #define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT                         9       // 0x09
  37 #define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT                  0
  38
  39 #define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP                           10      // 0x0a
  40 #define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP                    0
  41
  42 #define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT                         11      // 0x0b
  43 #define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT                  0
  44
  45 #define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP                           12      // 0x0c
  46 #define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP                    0
  47
  48 #define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT                         13      // 0x0d
  49 #define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT                  0
  50
  51 #define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP                           14      // 0x0e
  52 #define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP                    0
  53
  54 #define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT                         15      // 0x0f
  55 #define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT                  0
  56
  57 #define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP                           16      // 0x10
  58 #define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP                    0
  59
  60 #define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT                         17      // 0x11
  61 #define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT                  0
  62
  63 #define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP                           18      // 0x12
  64 #define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP                    0
  65
  66 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0           19      // 0x13
  67 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0           7
  68
  69 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1           19      // 0x13
  70 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1           8
  71
  72 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2           19      // 0x13
  73 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2           9
  74
  75 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS          19      // 0x13
  76 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS          10
  77
  78 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC               19      // 0x13
  79 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC               11
  80
  81 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL             19      // 0x13
  82 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL             12
  83
  84 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0           20      // 0x14
  85 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0           7
  86
  87 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1           20      // 0x14
  88 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1           8
  89
  90 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2           20      // 0x14
  91 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2           9
  92
  93 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS          20      // 0x14
  94 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS          10
  95
  96 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC               20      // 0x14
  97 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC               11
  98
  99 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL             20      // 0x14
 100 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL             12
 101
 102 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0           21      // 0x15
 103 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0           7
 104
 105 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1           21      // 0x15
 106 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1           8
 107
 108 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2           21      // 0x15
 109 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2           9
 110
 111 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS          21      // 0x15
 112 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS          10
 113
 114 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC               21      // 0x15
 115 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC               11
 116
 117 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SIGNAL             21      // 0x15
 118 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SIGNAL             12
 119
 120 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0           22      // 0x16
 121 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT0           7
 122
 123 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT1           22      // 0x16
 124 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT1           8
 125
 126 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT2           22      // 0x16
 127 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT2           9
 128
 129 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC_LOSS          22      // 0x16
 130 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC_LOSS          10
 131
 132 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC               22      // 0x16
 133 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC               11
 134
 135 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SIGNAL             22      // 0x16
 136 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SIGNAL             12
 137
 138 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0           23      // 0x17
 139 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT0           7
 140
 141 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT1           23      // 0x17
 142 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT1           8
 143
 144 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT2           23      // 0x17
 145 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT2           9
 146
 147 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC_LOSS          23      // 0x17
 148 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC_LOSS          10
 149
 150 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC               23      // 0x17
 151 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC               11
 152
 153 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SIGNAL             23      // 0x17
 154 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SIGNAL             12
 155
 156 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0           24      // 0x18
 157 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT0           7
 158
 159 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT1           24      // 0x18
 160 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT1           8
 161
 162 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2           24      // 0x18
 163 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2           9
 164
 165 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A                        42      // 0x2a
 166 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A                 0
 167
 168 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B                    42          // 0x2a
 169 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B                 1
 170
 171 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C                    42          // 0x2a
 172 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C                 2
 173
 174 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D                    42          // 0x2a
 175 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D                 3
 176
 177 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E                        42      // 0x2a
 178 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E                 4
 179
 180 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F                        42      // 0x2a
 181 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F                 5
 182
 183 #define VISLANDS30_IV_SRCID_HPD_RX_A                                42      // 0x2a
 184 #define VISLANDS30_IV_EXTID_HPD_RX_A                         6
 185
 186 #define VISLANDS30_IV_SRCID_HPD_RX_B                                42      // 0x2a
 187 #define VISLANDS30_IV_EXTID_HPD_RX_B                         7
 188
 189 #define VISLANDS30_IV_SRCID_HPD_RX_C                                42      // 0x2a
 190 #define VISLANDS30_IV_EXTID_HPD_RX_C                         8
 191
 192 #define VISLANDS30_IV_SRCID_HPD_RX_D                                42      // 0x2a
 193 #define VISLANDS30_IV_EXTID_HPD_RX_D                         9
 194
 195 #define VISLANDS30_IV_SRCID_HPD_RX_E                                42      // 0x2a
 196 #define VISLANDS30_IV_EXTID_HPD_RX_E                         10
 197
 198 #define VISLANDS30_IV_SRCID_HPD_RX_F                                42      // 0x2a
 199 #define VISLANDS30_IV_EXTID_HPD_RX_F                         11
 200
 201 #endif // _IVSRCID_VISLANDS30_H_