2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
33 #if defined(_TEST_HARNESS)
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
44 #include "atomfirmware.h"
46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
48 /* Firmware versioning. */
49 #ifdef DMUB_EXPOSE_VERSION
50 #define DMUB_FW_VERSION_GIT_HASH 0x23db9b126
51 #define DMUB_FW_VERSION_MAJOR 0
52 #define DMUB_FW_VERSION_MINOR 0
53 #define DMUB_FW_VERSION_REVISION 62
54 #define DMUB_FW_VERSION_TEST 0
55 #define DMUB_FW_VERSION_VBIOS 0
56 #define DMUB_FW_VERSION_HOTFIX 0
57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \
58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \
59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \
60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \
61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \
62 (DMUB_FW_VERSION_HOTFIX & 0x3F))
66 //<DMUB_TYPES>==================================================================
67 /* Basic type definitions. */
69 #define __forceinline inline
72 * Flag from driver to indicate that ABM should be disabled gradually
73 * by slowly reversing all backlight programming and pixel compensation.
75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
78 * Flag from driver to indicate that ABM should be disabled immediately
79 * and undo all backlight programming and pixel compensation.
81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
84 * Flag from driver to indicate that ABM should be disabled immediately
85 * and keep the current backlight programming and pixel compensation.
87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
90 * Flag from driver to set the current ABM pipe index or ABM operating level.
92 #define SET_ABM_PIPE_NORMAL 1
95 * Number of ambient light levels in ABM algorithm.
97 #define NUM_AMBI_LEVEL 5
100 * Number of operating/aggression levels in ABM algorithm.
102 #define NUM_AGGR_LEVEL 4
105 * Number of segments in the gamma curve.
107 #define NUM_POWER_FN_SEGS 8
110 * Number of segments in the backlight curve.
112 #define NUM_BL_CURVE_SEGS 16
114 /* Maximum number of streams on any ASIC. */
115 #define DMUB_MAX_STREAMS 6
117 /* Maximum number of planes on any ASIC. */
118 #define DMUB_MAX_PLANES 6
120 /* Trace buffer offset for entry */
121 #define TRACE_BUFFER_ENTRY_OFFSET 16
124 * ABM backlight control version legacy
126 #define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_UNKNOWN 0x0
129 * ABM backlight control version with multi edp support
131 #define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1 0x1
134 * Physical framebuffer address location, 64-bit.
136 #ifndef PHYSICAL_ADDRESS_LOC
137 #define PHYSICAL_ADDRESS_LOC union large_integer
141 * OS/FW agnostic memcpy
144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
148 * OS/FW agnostic memset
151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
154 #if defined(__cplusplus)
159 * OS/FW agnostic udelay
162 #define dmub_udelay(microseconds) udelay(microseconds)
166 * union dmub_addr - DMUB physical/virtual 64-bit address.
170 uint32_t low_part; /**< Lower 32 bits */
171 uint32_t high_part; /**< Upper 32 bits */
172 } u; /*<< Low/high bit access */
173 uint64_t quad_part; /*<< 64 bit address */
177 * Flags that can be set by driver to change some PSR behaviour.
179 union dmub_psr_debug_flags {
185 * Enable visual confirm in FW.
187 uint32_t visual_confirm : 1;
189 * Use HW Lock Mgr object to do HW locking in FW.
191 uint32_t use_hw_lock_mgr : 1;
197 uint32_t log_line_nums : 1;
201 * Union for debug flags.
207 * DMUB feature capabilities.
208 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
210 struct dmub_feature_caps {
212 * Max PSR version supported by FW.
218 #if defined(__cplusplus)
222 //==============================================================================
223 //</DMUB_TYPES>=================================================================
224 //==============================================================================
225 //< DMUB_META>==================================================================
226 //==============================================================================
227 #pragma pack(push, 1)
229 /* Magic value for identifying dmub_fw_meta_info */
230 #define DMUB_FW_META_MAGIC 0x444D5542
232 /* Offset from the end of the file to the dmub_fw_meta_info */
233 #define DMUB_FW_META_OFFSET 0x24
236 * struct dmub_fw_meta_info - metadata associated with fw binary
238 * NOTE: This should be considered a stable API. Fields should
239 * not be repurposed or reordered. New fields should be
240 * added instead to extend the structure.
242 * @magic_value: magic value identifying DMUB firmware meta info
243 * @fw_region_size: size of the firmware state region
244 * @trace_buffer_size: size of the tracebuffer region
245 * @fw_version: the firmware version information
246 * @dal_fw: 1 if the firmware is DAL
248 struct dmub_fw_meta_info {
249 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
250 uint32_t fw_region_size; /**< size of the firmware state region */
251 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
252 uint32_t fw_version; /**< the firmware version information */
253 uint8_t dal_fw; /**< 1 if the firmware is DAL */
254 uint8_t reserved[3]; /**< padding bits */
258 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
261 struct dmub_fw_meta_info info; /**< metadata info */
262 uint8_t reserved[64]; /**< padding bits */
267 //==============================================================================
268 //< DMUB Trace Buffer>================================================================
269 //==============================================================================
271 * dmub_trace_code_t - firmware trace code, 32-bits
273 typedef uint32_t dmub_trace_code_t;
276 * struct dmcub_trace_buf_entry - Firmware trace entry
278 struct dmcub_trace_buf_entry {
279 dmub_trace_code_t trace_code; /**< trace code for the event */
280 uint32_t tick_count; /**< the tick count at time of trace */
281 uint32_t param0; /**< trace defined parameter 0 */
282 uint32_t param1; /**< trace defined parameter 1 */
285 //==============================================================================
286 //< DMUB_STATUS>================================================================
287 //==============================================================================
290 * DMCUB scratch registers can be used to determine firmware status.
291 * Current scratch register usage is as follows:
293 * SCRATCH0: FW Boot Status register
294 * SCRATCH15: FW Boot Options register
298 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
300 union dmub_fw_boot_status {
302 uint32_t dal_fw : 1; /**< 1 if DAL FW */
303 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
304 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
305 uint32_t restore_required : 1; /**< 1 if driver should call restore */
306 } bits; /**< status bits */
307 uint32_t all; /**< 32-bit access to status bits */
311 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
313 enum dmub_fw_boot_status_bit {
314 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
315 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
316 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
317 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
321 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15
323 union dmub_fw_boot_options {
325 uint32_t pemu_env : 1; /**< 1 if PEMU */
326 uint32_t fpga_env : 1; /**< 1 if FPGA */
327 uint32_t optimized_init : 1; /**< 1 if optimized init */
328 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
329 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
330 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
331 uint32_t reserved : 26; /**< reserved */
332 } bits; /**< boot bits */
333 uint32_t all; /**< 32-bit access to bits */
336 enum dmub_fw_boot_options_bit {
337 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
338 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
339 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
342 //==============================================================================
343 //</DMUB_STATUS>================================================================
344 //==============================================================================
345 //< DMUB_VBIOS>=================================================================
346 //==============================================================================
349 * enum dmub_cmd_vbios_type - VBIOS commands.
351 * Command IDs should be treated as stable ABI.
352 * Do not reuse or modify IDs.
354 enum dmub_cmd_vbios_type {
356 * Configures the DIG encoder.
358 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
362 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
364 * Sets the pixel clock/symbol clock.
366 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
368 * Enables or disables power gating.
370 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
371 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
374 //==============================================================================
375 //</DMUB_VBIOS>=================================================================
376 //==============================================================================
377 //< DMUB_GPINT>=================================================================
378 //==============================================================================
381 * The shifts and masks below may alternatively be used to format and read
382 * the command register bits.
385 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
386 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
388 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
389 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
391 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
392 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
399 * Return response for DMUB_GPINT__STOP_FW command.
401 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
404 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
406 union dmub_gpint_data_register {
408 uint32_t param : 16; /**< 16-bit parameter */
409 uint32_t command_code : 12; /**< GPINT command */
410 uint32_t status : 4; /**< Command status bit */
411 } bits; /**< GPINT bit access */
412 uint32_t all; /**< GPINT 32-bit access */
416 * enum dmub_gpint_command - GPINT command to DMCUB FW
418 * Command IDs should be treated as stable ABI.
419 * Do not reuse or modify IDs.
421 enum dmub_gpint_command {
423 * Invalid command, ignored.
425 DMUB_GPINT__INVALID_COMMAND = 0,
427 * DESC: Queries the firmware version.
428 * RETURN: Firmware version.
430 DMUB_GPINT__GET_FW_VERSION = 1,
432 * DESC: Halts the firmware.
433 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
435 DMUB_GPINT__STOP_FW = 2,
437 * DESC: Get PSR state from FW.
438 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
440 DMUB_GPINT__GET_PSR_STATE = 7,
442 * DESC: Notifies DMCUB of the currently active streams.
443 * ARGS: Stream mask, 1 bit per active stream index.
445 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
447 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
448 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
449 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
450 * RETURN: PSR residency in milli-percent.
452 DMUB_GPINT__PSR_RESIDENCY = 9,
455 //==============================================================================
456 //</DMUB_GPINT>=================================================================
457 //==============================================================================
458 //< DMUB_CMD>===================================================================
459 //==============================================================================
462 * Size in bytes of each DMUB command.
464 #define DMUB_RB_CMD_SIZE 64
467 * Maximum number of items in the DMUB ringbuffer.
469 #define DMUB_RB_MAX_ENTRY 128
472 * Ringbuffer size in bytes.
474 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
477 * REG_SET mask for reg offload.
479 #define REG_SET_MASK 0xFFFF
482 * enum dmub_cmd_type - DMUB inbox command.
484 * Command IDs should be treated as stable ABI.
485 * Do not reuse or modify IDs.
493 * Read modify write register sequence offload.
495 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
497 * Field update register sequence offload.
499 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
501 * Burst write sequence offload.
503 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
505 * Reg wait sequence offload.
507 DMUB_CMD__REG_REG_WAIT = 4,
509 * Workaround to avoid HUBP underflow during NV12 playback.
511 DMUB_CMD__PLAT_54186_WA = 5,
513 * Command type used to query FW feature caps.
515 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
517 * Command type used for all PSR commands.
521 * Command type used for all MALL commands.
525 * Command type used for all ABM commands.
529 * Command type used for HW locking in FW.
531 DMUB_CMD__HW_LOCK = 69,
533 * Command type used to access DP AUX.
535 DMUB_CMD__DP_AUX_ACCESS = 70,
537 * Command type used for OUTBOX1 notification enable
539 DMUB_CMD__OUTBOX1_ENABLE = 71,
541 * Command type used for all VBIOS interface commands.
543 DMUB_CMD__VBIOS = 128,
547 * enum dmub_out_cmd_type - DMUB outbox commands.
549 enum dmub_out_cmd_type {
551 * Invalid outbox command, ignored.
553 DMUB_OUT_CMD__NULL = 0,
555 * Command type used for DP AUX Reply data notification
557 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
559 * Command type used for DP HPD event notification
561 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
564 #pragma pack(push, 1)
567 * struct dmub_cmd_header - Common command header fields.
569 struct dmub_cmd_header {
570 unsigned int type : 8; /**< command type */
571 unsigned int sub_type : 8; /**< command sub type */
572 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
573 unsigned int reserved0 : 7; /**< reserved bits */
574 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
575 unsigned int reserved1 : 2; /**< reserved bits */
579 * struct dmub_cmd_read_modify_write_sequence - Read modify write
581 * 60 payload bytes can hold up to 5 sets of read modify writes,
582 * each take 3 dwords.
584 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
586 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
587 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
589 struct dmub_cmd_read_modify_write_sequence {
590 uint32_t addr; /**< register address */
591 uint32_t modify_mask; /**< modify mask */
592 uint32_t modify_value; /**< modify value */
596 * Maximum number of ops in read modify write sequence.
598 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
601 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
603 struct dmub_rb_cmd_read_modify_write {
604 struct dmub_cmd_header header; /**< command header */
606 * Read modify write sequence.
608 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
612 * Update a register with specified masks and values sequeunce
614 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
616 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
620 * 1. auto-increment register where additional read would update pointer and produce wrong result
621 * 2. toggle a bit without read in the middle
624 struct dmub_cmd_reg_field_update_sequence {
625 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
626 uint32_t modify_value; /**< value to update with */
630 * Maximum number of ops in field update sequence.
632 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
635 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
637 struct dmub_rb_cmd_reg_field_update_sequence {
638 struct dmub_cmd_header header; /**< command header */
639 uint32_t addr; /**< register address */
641 * Field update sequence.
643 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
648 * Maximum number of burst write values.
650 #define DMUB_BURST_WRITE_VALUES__MAX 14
653 * struct dmub_rb_cmd_burst_write - Burst write
655 * support use case such as writing out LUTs.
657 * 60 payload bytes can hold up to 14 values to write to given address
659 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
661 struct dmub_rb_cmd_burst_write {
662 struct dmub_cmd_header header; /**< command header */
663 uint32_t addr; /**< register start address */
665 * Burst write register values.
667 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
671 * struct dmub_rb_cmd_common - Common command header
673 struct dmub_rb_cmd_common {
674 struct dmub_cmd_header header; /**< command header */
676 * Padding to RB_CMD_SIZE
678 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
682 * struct dmub_cmd_reg_wait_data - Register wait data
684 struct dmub_cmd_reg_wait_data {
685 uint32_t addr; /**< Register address */
686 uint32_t mask; /**< Mask for register bits */
687 uint32_t condition_field_value; /**< Value to wait for */
688 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
692 * struct dmub_rb_cmd_reg_wait - Register wait command
694 struct dmub_rb_cmd_reg_wait {
695 struct dmub_cmd_header header; /**< Command header */
696 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
700 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
702 * Reprograms surface parameters to avoid underflow.
704 struct dmub_cmd_PLAT_54186_wa {
705 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
706 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
707 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
708 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
709 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
711 uint8_t hubp_inst : 4; /**< HUBP instance */
712 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
713 uint8_t immediate :1; /**< Immediate flip */
714 uint8_t vmid : 4; /**< VMID */
715 uint8_t grph_stereo : 1; /**< 1 if stereo */
716 uint32_t reserved : 21; /**< Reserved */
717 } flip_params; /**< Pageflip parameters */
718 uint32_t reserved[9]; /**< Reserved bits */
722 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
724 struct dmub_rb_cmd_PLAT_54186_wa {
725 struct dmub_cmd_header header; /**< Command header */
726 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
730 * struct dmub_rb_cmd_mall - MALL command data.
732 struct dmub_rb_cmd_mall {
733 struct dmub_cmd_header header; /**< Common command header */
734 union dmub_addr cursor_copy_src; /**< Cursor copy address */
735 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
736 uint32_t tmr_delay; /**< Timer delay */
737 uint32_t tmr_scale; /**< Timer scale */
738 uint16_t cursor_width; /**< Cursor width in pixels */
739 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
740 uint16_t cursor_height; /**< Cursor height in pixels */
741 uint8_t cursor_bpp; /**< Cursor bits per pixel */
742 uint8_t debug_bits; /**< Debug bits */
744 uint8_t reserved1; /**< Reserved bits */
745 uint8_t reserved2; /**< Reserved bits */
749 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
751 struct dmub_cmd_digx_encoder_control_data {
752 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
756 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
758 struct dmub_rb_cmd_digx_encoder_control {
759 struct dmub_cmd_header header; /**< header */
760 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
764 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
766 struct dmub_cmd_set_pixel_clock_data {
767 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
771 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
773 struct dmub_rb_cmd_set_pixel_clock {
774 struct dmub_cmd_header header; /**< header */
775 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
779 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
781 struct dmub_cmd_enable_disp_power_gating_data {
782 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
786 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
788 struct dmub_rb_cmd_enable_disp_power_gating {
789 struct dmub_cmd_header header; /**< header */
790 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
794 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
796 struct dmub_dig_transmitter_control_data_v1_7 {
797 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
798 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
800 uint8_t digmode; /**< enum atom_encode_mode_def */
801 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
803 uint8_t lanenum; /**< Number of lanes */
805 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
807 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
808 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
809 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
810 uint8_t reserved0; /**< For future use */
811 uint8_t reserved1; /**< For future use */
812 uint8_t reserved2[3]; /**< For future use */
813 uint32_t reserved3[11]; /**< For future use */
817 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
819 union dmub_cmd_dig1_transmitter_control_data {
820 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
821 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
825 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
827 struct dmub_rb_cmd_dig1_transmitter_control {
828 struct dmub_cmd_header header; /**< header */
829 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
833 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
835 struct dmub_rb_cmd_dpphy_init {
836 struct dmub_cmd_header header; /**< header */
837 uint8_t reserved[60]; /**< reserved bits */
841 * enum dp_aux_request_action - DP AUX request command listing.
843 * 4 AUX request command bits are shifted to high nibble.
845 enum dp_aux_request_action {
846 /** I2C-over-AUX write request */
847 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
848 /** I2C-over-AUX read request */
849 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
850 /** I2C-over-AUX write status request */
851 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
852 /** I2C-over-AUX write request with MOT=1 */
853 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
854 /** I2C-over-AUX read request with MOT=1 */
855 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
856 /** I2C-over-AUX write status request with MOT=1 */
857 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
858 /** Native AUX write request */
859 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
860 /** Native AUX read request */
861 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
865 * enum aux_return_code_type - DP AUX process return code listing.
867 enum aux_return_code_type {
868 /** AUX process succeeded */
870 /** AUX process failed with unknown reason */
871 AUX_RET_ERROR_UNKNOWN,
872 /** AUX process completed with invalid reply */
873 AUX_RET_ERROR_INVALID_REPLY,
874 /** AUX process timed out */
875 AUX_RET_ERROR_TIMEOUT,
876 /** HPD was low during AUX process */
877 AUX_RET_ERROR_HPD_DISCON,
878 /** Failed to acquire AUX engine */
879 AUX_RET_ERROR_ENGINE_ACQUIRE,
880 /** AUX request not supported */
881 AUX_RET_ERROR_INVALID_OPERATION,
882 /** AUX process not available */
883 AUX_RET_ERROR_PROTOCOL_ERROR,
887 * enum aux_channel_type - DP AUX channel type listing.
889 enum aux_channel_type {
890 /** AUX thru Legacy DP AUX */
891 AUX_CHANNEL_LEGACY_DDC,
892 /** AUX thru DPIA DP tunneling */
897 * struct aux_transaction_parameters - DP AUX request transaction data
899 struct aux_transaction_parameters {
900 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
901 uint8_t action; /**< enum dp_aux_request_action */
902 uint8_t length; /**< DP AUX request data length */
903 uint8_t reserved; /**< For future use */
904 uint32_t address; /**< DP AUX address */
905 uint8_t data[16]; /**< DP AUX write data */
909 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
911 struct dmub_cmd_dp_aux_control_data {
912 uint8_t instance; /**< AUX instance or DPIA instance */
913 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
914 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
915 uint8_t reserved0; /**< For future use */
916 uint16_t timeout; /**< timeout time in us */
917 uint16_t reserved1; /**< For future use */
918 enum aux_channel_type type; /**< enum aux_channel_type */
919 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
923 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
925 struct dmub_rb_cmd_dp_aux_access {
929 struct dmub_cmd_header header;
931 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
933 struct dmub_cmd_dp_aux_control_data aux_control;
937 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
939 struct dmub_rb_cmd_outbox1_enable {
943 struct dmub_cmd_header header;
945 * enable: 0x0 -> disable outbox1 notification (default value)
946 * 0x1 -> enable outbox1 notification
951 /* DP AUX Reply command - OutBox Cmd */
953 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
955 struct aux_reply_data {
961 * Aux reply data length (max: 16 bytes)
975 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
977 struct aux_reply_control_data {
979 * Reserved for future use
987 * Aux transaction result: definition in enum aux_return_code_type
997 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
999 struct dmub_rb_cmd_dp_aux_reply {
1003 struct dmub_cmd_header header;
1005 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1007 struct aux_reply_control_data control;
1009 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1011 struct aux_reply_data reply_data;
1014 /* DP HPD Notify command - OutBox Cmd */
1024 * DP HPD short pulse
1032 enum dp_hpd_status {
1038 * DP_HPD status high
1044 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1046 struct dp_hpd_data {
1056 * HPD status: only for type: DP_HPD to indicate status
1066 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1068 struct dmub_rb_cmd_dp_hpd_notify {
1072 struct dmub_cmd_header header;
1074 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1076 struct dp_hpd_data hpd_data;
1080 * Command IDs should be treated as stable ABI.
1081 * Do not reuse or modify IDs.
1085 * PSR command sub-types.
1087 enum dmub_cmd_psr_type {
1089 * Set PSR version support.
1091 DMUB_CMD__PSR_SET_VERSION = 0,
1093 * Copy driver-calculated parameters to PSR state.
1095 DMUB_CMD__PSR_COPY_SETTINGS = 1,
1099 DMUB_CMD__PSR_ENABLE = 2,
1104 DMUB_CMD__PSR_DISABLE = 3,
1108 * PSR level is a 16-bit value dicated by driver that
1109 * will enable/disable different functionality.
1111 DMUB_CMD__PSR_SET_LEVEL = 4,
1114 * Forces PSR enabled until an explicit PSR disable call.
1116 DMUB_CMD__PSR_FORCE_STATIC = 5,
1128 * PSR not supported.
1130 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
1134 * enum dmub_cmd_mall_type - MALL commands
1136 enum dmub_cmd_mall_type {
1138 * Allows display refresh from MALL.
1140 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1142 * Disallows display refresh from MALL.
1144 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1146 * Cursor copy for MALL.
1148 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1150 * Controls DF requests.
1152 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1157 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1159 struct dmub_cmd_psr_copy_settings_data {
1161 * Flags that can be set by driver to change some PSR behaviour.
1163 union dmub_psr_debug_flags debug;
1165 * 16-bit value dicated by driver that will enable/disable different functionality.
1174 * Not used in dmub fw,
1175 * dmub fw will get active opp by reading odm registers.
1180 * Not used in dmub fw,
1181 * dmub fw will get active opp by reading odm registers.
1189 * DIG FE HW instance.
1193 * DIG BE HW instance.
1197 * DP PHY HW instance.
1205 * Determines if SMU optimzations are enabled/disabled.
1207 uint8_t smu_optimizations_en;
1212 uint8_t frame_delay;
1214 * If RFB setup time is greater than the total VBLANK time,
1215 * it is not possible for the sink to capture the video frame
1216 * in the same frame the SDP is sent. In this case,
1217 * the frame capture indication bit should be set and an extra
1218 * static frame should be transmitted to the sink.
1220 uint8_t frame_cap_ind;
1222 * Explicit padding to 4 byte boundary.
1226 * Multi-display optimizations are implemented on certain ASICs.
1228 uint8_t multi_disp_optimizations_en;
1230 * The last possible line SDP may be transmitted without violating
1231 * the RFB setup time or entering the active video frame.
1233 uint16_t init_sdp_deadline;
1235 * Explicit padding to 4 byte boundary.
1239 * Length of each horizontal line in us.
1241 uint32_t line_time_in_us;
1243 * FEC enable status in driver
1245 uint8_t fec_enable_status;
1247 * FEC re-enable delay when PSR exit.
1248 * unit is 100us, range form 0~255(0xFF).
1250 uint8_t fec_enable_delay_in100us;
1252 * Explicit padding to 4 byte boundary.
1258 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
1260 struct dmub_rb_cmd_psr_copy_settings {
1264 struct dmub_cmd_header header;
1266 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1268 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
1272 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
1274 struct dmub_cmd_psr_set_level_data {
1276 * 16-bit value dicated by driver that will enable/disable different functionality.
1280 * Explicit padding to 4 byte boundary.
1286 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1288 struct dmub_rb_cmd_psr_set_level {
1292 struct dmub_cmd_header header;
1294 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1296 struct dmub_cmd_psr_set_level_data psr_set_level_data;
1300 * Definition of a DMUB_CMD__PSR_ENABLE command.
1301 * PSR enable/disable is controlled using the sub_type.
1303 struct dmub_rb_cmd_psr_enable {
1307 struct dmub_cmd_header header;
1311 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1313 struct dmub_cmd_psr_set_version_data {
1315 * PSR version that FW should implement.
1317 enum psr_version version;
1321 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
1323 struct dmub_rb_cmd_psr_set_version {
1327 struct dmub_cmd_header header;
1329 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1331 struct dmub_cmd_psr_set_version_data psr_set_version_data;
1335 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
1337 struct dmub_rb_cmd_psr_force_static {
1341 struct dmub_cmd_header header;
1345 * Set of HW components that can be locked.
1347 union dmub_hw_lock_flags {
1349 * Set of HW components that can be locked.
1353 * Lock/unlock OTG master update lock.
1355 uint8_t lock_pipe : 1;
1357 * Lock/unlock cursor.
1359 uint8_t lock_cursor : 1;
1361 * Lock/unlock global update lock.
1363 uint8_t lock_dig : 1;
1365 * Triple buffer lock requires additional hw programming to usual OTG master lock.
1367 uint8_t triple_buffer_lock : 1;
1371 * Union for HW Lock flags.
1377 * Instances of HW to be locked.
1379 struct dmub_hw_lock_inst_flags {
1381 * OTG HW instance for OTG master update lock.
1385 * OPP instance for cursor lock.
1389 * OTG HW instance for global update lock.
1390 * TODO: Remove, and re-use otg_inst.
1394 * Explicit pad to 4 byte boundary.
1400 * Clients that can acquire the HW Lock Manager.
1402 enum hw_lock_client {
1404 * Driver is the client of HW Lock Manager.
1406 HW_LOCK_CLIENT_DRIVER = 0,
1408 * FW is the client of HW Lock Manager.
1414 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
1418 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1420 struct dmub_cmd_lock_hw_data {
1422 * Specifies the client accessing HW Lock Manager.
1424 enum hw_lock_client client;
1426 * HW instances to be locked.
1428 struct dmub_hw_lock_inst_flags inst_flags;
1430 * Which components to be locked.
1432 union dmub_hw_lock_flags hw_locks;
1434 * Specifies lock/unlock.
1438 * HW can be unlocked separately from releasing the HW Lock Mgr.
1439 * This flag is set if the client wishes to release the object.
1441 uint8_t should_release;
1443 * Explicit padding to 4 byte boundary.
1449 * Definition of a DMUB_CMD__HW_LOCK command.
1450 * Command is used by driver and FW.
1452 struct dmub_rb_cmd_lock_hw {
1456 struct dmub_cmd_header header;
1458 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1460 struct dmub_cmd_lock_hw_data lock_hw_data;
1464 * ABM command sub-types.
1466 enum dmub_cmd_abm_type {
1468 * Initialize parameters for ABM algorithm.
1469 * Data is passed through an indirect buffer.
1471 DMUB_CMD__ABM_INIT_CONFIG = 0,
1473 * Set OTG and panel HW instance.
1475 DMUB_CMD__ABM_SET_PIPE = 1,
1477 * Set user requested backklight level.
1479 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
1481 * Set ABM operating/aggression level.
1483 DMUB_CMD__ABM_SET_LEVEL = 3,
1485 * Set ambient light level.
1487 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
1489 * Enable/disable fractional duty cycle for backlight PWM.
1491 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
1495 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
1497 * - Padded explicitly to 32-bit boundary.
1498 * - Must ensure this structure matches the one on driver-side,
1499 * otherwise it won't be aligned.
1501 struct abm_config_table {
1503 * Gamma curve thresholds, used for crgb conversion.
1505 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
1507 * Gamma curve offsets, used for crgb conversion.
1509 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
1511 * Gamma curve slopes, used for crgb conversion.
1513 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
1515 * Custom backlight curve thresholds.
1517 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
1519 * Custom backlight curve offsets.
1521 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
1523 * Ambient light thresholds.
1525 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
1527 * Minimum programmable backlight.
1529 uint16_t min_abm_backlight; // 122B
1531 * Minimum reduction values.
1533 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
1535 * Maximum reduction values.
1537 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
1539 * Bright positive gain.
1541 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
1543 * Dark negative gain.
1545 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
1549 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
1553 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
1557 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
1561 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
1565 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
1569 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
1571 * Explicit padding to 4 byte boundary.
1573 uint8_t pad3[3]; // 229B
1575 * Backlight ramp reduction.
1577 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
1579 * Backlight ramp start.
1581 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
1585 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1587 struct dmub_cmd_abm_set_pipe_data {
1594 * Panel Control HW instance.
1599 * Controls how ABM will interpret a set pipe or set level command.
1601 uint8_t set_pipe_option;
1607 uint8_t ramping_boundary;
1611 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
1613 struct dmub_rb_cmd_abm_set_pipe {
1617 struct dmub_cmd_header header;
1620 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1622 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
1626 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1628 struct dmub_cmd_abm_set_backlight_data {
1630 * Number of frames to ramp to backlight user level.
1632 uint32_t frame_ramp;
1635 * Requested backlight level from user.
1637 uint32_t backlight_user_level;
1640 * Backlight data version.
1645 * Panel Control HW instance mask.
1646 * Bit 0 is Panel Control HW instance 0.
1647 * Bit 1 is Panel Control HW instance 1.
1652 * Explicit padding to 4 byte boundary.
1658 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
1660 struct dmub_rb_cmd_abm_set_backlight {
1664 struct dmub_cmd_header header;
1667 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1669 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
1673 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1675 struct dmub_cmd_abm_set_level_data {
1677 * Set current ABM operating/aggression level.
1683 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
1685 struct dmub_rb_cmd_abm_set_level {
1689 struct dmub_cmd_header header;
1692 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1694 struct dmub_cmd_abm_set_level_data abm_set_level_data;
1698 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1700 struct dmub_cmd_abm_set_ambient_level_data {
1702 * Ambient light sensor reading from OS.
1704 uint32_t ambient_lux;
1708 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1710 struct dmub_rb_cmd_abm_set_ambient_level {
1714 struct dmub_cmd_header header;
1717 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1719 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
1723 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
1725 struct dmub_cmd_abm_set_pwm_frac_data {
1727 * Enable/disable fractional duty cycle for backlight PWM.
1728 * TODO: Convert to uint8_t.
1730 uint32_t fractional_pwm;
1734 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
1736 struct dmub_rb_cmd_abm_set_pwm_frac {
1740 struct dmub_cmd_header header;
1743 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
1745 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
1749 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
1751 struct dmub_cmd_abm_init_config_data {
1753 * Location of indirect buffer used to pass init data to ABM.
1755 union dmub_addr src;
1758 * Indirect buffer length.
1764 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
1766 struct dmub_rb_cmd_abm_init_config {
1770 struct dmub_cmd_header header;
1773 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
1775 struct dmub_cmd_abm_init_config_data abm_init_config_data;
1779 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
1781 struct dmub_cmd_query_feature_caps_data {
1783 * DMUB feature capabilities.
1784 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
1786 struct dmub_feature_caps feature_caps;
1790 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
1792 struct dmub_rb_cmd_query_feature_caps {
1796 struct dmub_cmd_header header;
1798 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
1800 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
1803 struct dmub_optc_state {
1804 uint32_t v_total_max;
1805 uint32_t v_total_min;
1806 uint32_t v_total_mid;
1807 uint32_t v_total_mid_frame_num;
1809 uint32_t enable_manual_trigger;
1810 uint32_t clear_force_vsync;
1813 struct dmub_rb_cmd_drr_update {
1814 struct dmub_cmd_header header;
1815 struct dmub_optc_state dmub_optc_state_req;
1819 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
1821 struct dmub_cmd_lvtma_control_data {
1822 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
1823 uint8_t reserved_0[3]; /**< For future use */
1824 uint8_t panel_inst; /**< LVTMA control instance */
1825 uint8_t reserved_1[3]; /**< For future use */
1829 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
1831 struct dmub_rb_cmd_lvtma_control {
1835 struct dmub_cmd_header header;
1837 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
1839 struct dmub_cmd_lvtma_control_data data;
1843 * union dmub_rb_cmd - DMUB inbox command.
1846 struct dmub_rb_cmd_lock_hw lock_hw;
1848 * Elements shared with all commands.
1850 struct dmub_rb_cmd_common cmd_common;
1852 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
1854 struct dmub_rb_cmd_read_modify_write read_modify_write;
1856 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
1858 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
1860 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
1862 struct dmub_rb_cmd_burst_write burst_write;
1864 * Definition of a DMUB_CMD__REG_REG_WAIT command.
1866 struct dmub_rb_cmd_reg_wait reg_wait;
1868 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
1870 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
1872 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
1874 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
1876 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
1878 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
1880 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
1882 struct dmub_rb_cmd_dpphy_init dpphy_init;
1884 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
1886 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
1888 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
1890 struct dmub_rb_cmd_psr_set_version psr_set_version;
1892 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
1894 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
1896 * Definition of a DMUB_CMD__PSR_ENABLE command.
1898 struct dmub_rb_cmd_psr_enable psr_enable;
1900 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1902 struct dmub_rb_cmd_psr_set_level psr_set_level;
1904 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
1906 struct dmub_rb_cmd_psr_force_static psr_force_static;
1908 * Definition of a DMUB_CMD__PLAT_54186_WA command.
1910 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
1912 * Definition of a DMUB_CMD__MALL command.
1914 struct dmub_rb_cmd_mall mall;
1916 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
1918 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
1921 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
1923 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
1926 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
1928 struct dmub_rb_cmd_abm_set_level abm_set_level;
1931 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1933 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
1936 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
1938 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
1941 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
1943 struct dmub_rb_cmd_abm_init_config abm_init_config;
1946 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1948 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
1951 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1953 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
1956 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
1958 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
1959 struct dmub_rb_cmd_drr_update drr_update;
1961 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
1963 struct dmub_rb_cmd_lvtma_control lvtma_control;
1967 * union dmub_rb_out_cmd - Outbox command
1969 union dmub_rb_out_cmd {
1971 * Parameters common to every command.
1973 struct dmub_rb_cmd_common cmd_common;
1975 * AUX reply command.
1977 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
1979 * HPD notify command.
1981 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
1986 //==============================================================================
1987 //</DMUB_CMD>===================================================================
1988 //==============================================================================
1989 //< DMUB_RB>====================================================================
1990 //==============================================================================
1992 #if defined(__cplusplus)
1997 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
1999 struct dmub_rb_init_params {
2000 void *ctx; /**< Caller provided context pointer */
2001 void *base_address; /**< CPU base address for ring's data */
2002 uint32_t capacity; /**< Ringbuffer capacity in bytes */
2003 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
2004 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
2008 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
2011 void *base_address; /**< CPU address for the ring's data */
2012 uint32_t rptr; /**< Read pointer for consumer in bytes */
2013 uint32_t wrpt; /**< Write pointer for producer in bytes */
2014 uint32_t capacity; /**< Ringbuffer capacity in bytes */
2016 void *ctx; /**< Caller provided context pointer */
2017 void *dmub; /**< Pointer to the DMUB interface */
2021 * @brief Checks if the ringbuffer is empty.
2023 * @param rb DMUB Ringbuffer
2024 * @return true if empty
2025 * @return false otherwise
2027 static inline bool dmub_rb_empty(struct dmub_rb *rb)
2029 return (rb->wrpt == rb->rptr);
2033 * @brief Checks if the ringbuffer is full
2035 * @param rb DMUB Ringbuffer
2036 * @return true if full
2037 * @return false otherwise
2039 static inline bool dmub_rb_full(struct dmub_rb *rb)
2041 uint32_t data_count;
2043 if (rb->wrpt >= rb->rptr)
2044 data_count = rb->wrpt - rb->rptr;
2046 data_count = rb->capacity - (rb->rptr - rb->wrpt);
2048 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
2052 * @brief Pushes a command into the ringbuffer
2054 * @param rb DMUB ringbuffer
2055 * @param cmd The command to push
2056 * @return true if the ringbuffer was not full
2057 * @return false otherwise
2059 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
2060 const union dmub_rb_cmd *cmd)
2062 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t);
2063 const uint64_t *src = (const uint64_t *)cmd;
2066 if (dmub_rb_full(rb))
2070 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2073 rb->wrpt += DMUB_RB_CMD_SIZE;
2075 if (rb->wrpt >= rb->capacity)
2076 rb->wrpt %= rb->capacity;
2082 * @brief Pushes a command into the DMUB outbox ringbuffer
2084 * @param rb DMUB outbox ringbuffer
2085 * @param cmd Outbox command
2086 * @return true if not full
2087 * @return false otherwise
2089 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
2090 const union dmub_rb_out_cmd *cmd)
2092 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
2093 const uint8_t *src = (uint8_t *)cmd;
2095 if (dmub_rb_full(rb))
2098 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2100 rb->wrpt += DMUB_RB_CMD_SIZE;
2102 if (rb->wrpt >= rb->capacity)
2103 rb->wrpt %= rb->capacity;
2109 * @brief Returns the next unprocessed command in the ringbuffer.
2111 * @param rb DMUB ringbuffer
2112 * @param cmd The command to return
2113 * @return true if not empty
2114 * @return false otherwise
2116 static inline bool dmub_rb_front(struct dmub_rb *rb,
2117 union dmub_rb_cmd **cmd)
2119 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
2121 if (dmub_rb_empty(rb))
2124 *cmd = (union dmub_rb_cmd *)rb_cmd;
2130 * @brief Returns the next unprocessed command in the outbox.
2132 * @param rb DMUB outbox ringbuffer
2133 * @param cmd The outbox command to return
2134 * @return true if not empty
2135 * @return false otherwise
2137 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
2138 union dmub_rb_out_cmd *cmd)
2140 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
2141 uint64_t *dst = (uint64_t *)cmd;
2144 if (dmub_rb_empty(rb))
2148 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2155 * @brief Removes the front entry in the ringbuffer.
2157 * @param rb DMUB ringbuffer
2158 * @return true if the command was removed
2159 * @return false if there were no commands
2161 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
2163 if (dmub_rb_empty(rb))
2166 rb->rptr += DMUB_RB_CMD_SIZE;
2168 if (rb->rptr >= rb->capacity)
2169 rb->rptr %= rb->capacity;
2175 * @brief Flushes commands in the ringbuffer to framebuffer memory.
2177 * Avoids a race condition where DMCUB accesses memory while
2178 * there are still writes in flight to framebuffer.
2180 * @param rb DMUB ringbuffer
2182 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
2184 uint32_t rptr = rb->rptr;
2185 uint32_t wptr = rb->wrpt;
2187 while (rptr != wptr) {
2188 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t);
2191 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2194 rptr += DMUB_RB_CMD_SIZE;
2195 if (rptr >= rb->capacity)
2196 rptr %= rb->capacity;
2201 * @brief Initializes a DMCUB ringbuffer
2203 * @param rb DMUB ringbuffer
2204 * @param init_params initial configuration for the ringbuffer
2206 static inline void dmub_rb_init(struct dmub_rb *rb,
2207 struct dmub_rb_init_params *init_params)
2209 rb->base_address = init_params->base_address;
2210 rb->capacity = init_params->capacity;
2211 rb->rptr = init_params->read_ptr;
2212 rb->wrpt = init_params->write_ptr;
2216 * @brief Copies output data from in/out commands into the given command.
2218 * @param rb DMUB ringbuffer
2219 * @param cmd Command to copy data into
2221 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
2222 union dmub_rb_cmd *cmd)
2224 // Copy rb entry back into command
2225 uint8_t *rd_ptr = (rb->rptr == 0) ?
2226 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
2227 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
2229 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
2232 #if defined(__cplusplus)
2236 //==============================================================================
2237 //</DMUB_RB>====================================================================
2238 //==============================================================================
2240 #endif /* _DMUB_CMD_H_ */