drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* FILE POLICY AND INTENDED USAGE:
  27  * This file implements retrieval and configuration of eDP panel features such
  28  * as PSR and ABM and it also manages specs defined eDP panel power sequences.
  29  */
  30
  31 #include "link_edp_panel_control.h"
  32 #include "link_dpcd.h"
  33 #include "link_dp_capability.h"
  34 #include "dm_helpers.h"
  35 #include "dal_asic_id.h"
  36 #include "link_dp_phy.h"
  37 #include "dce/dmub_psr.h"
  38 #include "dc/dc_dmub_srv.h"
  39 #include "dce/dmub_replay.h"
  40 #include "abm.h"
  41 #define DC_LOGGER \
  42         link->ctx->logger
  43 #define DC_LOGGER_INIT(logger)
  44
  45 #define DP_SINK_PR_ENABLE_AND_CONFIGURATION             0x37B
  46
  47 /* Travis */
  48 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  49 /* Nutmeg */
  50 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  51
  52 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
  53 {
  54         union dpcd_edp_config edp_config_set;
  55         bool panel_mode_edp = false;
  56         enum dc_status result;
  57
  58         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
  59
  60         switch (panel_mode) {
  61         case DP_PANEL_MODE_EDP:
  62         case DP_PANEL_MODE_SPECIAL:
  63                 panel_mode_edp = true;
  64                 break;
  65
  66         default:
  67                 break;
  68         }
  69
  70         /*set edp panel mode in receiver*/
  71         result = core_link_read_dpcd(
  72                 link,
  73                 DP_EDP_CONFIGURATION_SET,
  74                 &edp_config_set.raw,
  75                 sizeof(edp_config_set.raw));
  76
  77         if (result == DC_OK &&
  78                 edp_config_set.bits.PANEL_MODE_EDP
  79                 != panel_mode_edp) {
  80
  81                 edp_config_set.bits.PANEL_MODE_EDP =
  82                 panel_mode_edp;
  83                 result = core_link_write_dpcd(
  84                         link,
  85                         DP_EDP_CONFIGURATION_SET,
  86                         &edp_config_set.raw,
  87                         sizeof(edp_config_set.raw));
  88
  89                 ASSERT(result == DC_OK);
  90         }
  91
  92         link->panel_mode = panel_mode;
  93         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
  94                  "eDP panel mode enabled: %d \n",
  95                  link->link_index,
  96                  link->dpcd_caps.panel_mode_edp,
  97                  panel_mode_edp);
  98 }
  99
 100 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
 101 {
 102         /* We need to explicitly check that connector
 103          * is not DP. Some Travis_VGA get reported
 104          * by video bios as DP.
 105          */
 106         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
 107
 108                 switch (link->dpcd_caps.branch_dev_id) {
 109                 case DP_BRANCH_DEVICE_ID_0022B9:
 110                         /* alternate scrambler reset is required for Travis
 111                          * for the case when external chip does not
 112                          * provide sink device id, alternate scrambler
 113                          * scheme will  be overriden later by querying
 114                          * Encoder features
 115                          */
 116                         if (strncmp(
 117                                 link->dpcd_caps.branch_dev_name,
 118                                 DP_VGA_LVDS_CONVERTER_ID_2,
 119                                 sizeof(
 120                                 link->dpcd_caps.
 121                                 branch_dev_name)) == 0) {
 122                                         return DP_PANEL_MODE_SPECIAL;
 123                         }
 124                         break;
 125                 case DP_BRANCH_DEVICE_ID_00001A:
 126                         /* alternate scrambler reset is required for Travis
 127                          * for the case when external chip does not provide
 128                          * sink device id, alternate scrambler scheme will
 129                          * be overriden later by querying Encoder feature
 130                          */
 131                         if (strncmp(link->dpcd_caps.branch_dev_name,
 132                                 DP_VGA_LVDS_CONVERTER_ID_3,
 133                                 sizeof(
 134                                 link->dpcd_caps.
 135                                 branch_dev_name)) == 0) {
 136                                         return DP_PANEL_MODE_SPECIAL;
 137                         }
 138                         break;
 139                 default:
 140                         break;
 141                 }
 142         }
 143
 144         if (link->dpcd_caps.panel_mode_edp &&
 145                 (link->connector_signal == SIGNAL_TYPE_EDP ||
 146                  (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 147                   link->is_internal_display))) {
 148                 return DP_PANEL_MODE_EDP;
 149         }
 150
 151         return DP_PANEL_MODE_DEFAULT;
 152 }
 153
 154 bool edp_set_backlight_level_nits(struct dc_link *link,
 155                 bool isHDR,
 156                 uint32_t backlight_millinits,
 157                 uint32_t transition_time_in_ms)
 158 {
 159         struct dpcd_source_backlight_set dpcd_backlight_set;
 160         uint8_t backlight_control = isHDR ? 1 : 0;
 161
 162         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
 163                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
 164                 return false;
 165
 166         // OLEDs have no PWM, they can only use AUX
 167         if (link->dpcd_sink_ext_caps.bits.oled == 1)
 168                 backlight_control = 1;
 169
 170         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
 171         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
 172
 173         link->backlight_settings.backlight_millinits = backlight_millinits;
 174
 175         if (!link->dpcd_caps.panel_luminance_control) {
 176                 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
 177                         (uint8_t *)(&dpcd_backlight_set),
 178                         sizeof(dpcd_backlight_set)) != DC_OK)
 179                         return false;
 180
 181                 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
 182                         &backlight_control, 1) != DC_OK)
 183                         return false;
 184         } else {
 185                 const uint8_t backlight_enable = DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
 186                 struct target_luminance_value *target_luminance = NULL;
 187
 188                 //if target luminance value is greater than 24 bits, clip the value to 24 bits
 189                 if (backlight_millinits > 0xFFFFFF)
 190                         backlight_millinits = 0xFFFFFF;
 191
 192                 target_luminance = (struct target_luminance_value *)&backlight_millinits;
 193
 194                 if (core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
 195                         &backlight_enable,
 196                         sizeof(backlight_enable)) != DC_OK)
 197                         return false;
 198
 199                 if (core_link_write_dpcd(link, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
 200                         (uint8_t *)(target_luminance),
 201                         sizeof(struct target_luminance_value)) != DC_OK)
 202                         return false;
 203         }
 204
 205         return true;
 206 }
 207
 208 bool edp_get_backlight_level_nits(struct dc_link *link,
 209                 uint32_t *backlight_millinits_avg,
 210                 uint32_t *backlight_millinits_peak)
 211 {
 212         union dpcd_source_backlight_get dpcd_backlight_get;
 213
 214         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
 215
 216         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
 217                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
 218                 return false;
 219
 220         if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
 221                         dpcd_backlight_get.raw,
 222                         sizeof(union dpcd_source_backlight_get)))
 223                 return false;
 224
 225         *backlight_millinits_avg =
 226                 dpcd_backlight_get.bytes.backlight_millinits_avg;
 227         *backlight_millinits_peak =
 228                 dpcd_backlight_get.bytes.backlight_millinits_peak;
 229
 230         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
 231         if (*backlight_millinits_avg == 0 ||
 232                         *backlight_millinits_avg > *backlight_millinits_peak)
 233                 return false;
 234
 235         return true;
 236 }
 237
 238 bool edp_backlight_enable_aux(struct dc_link *link, bool enable)
 239 {
 240         uint8_t backlight_enable = enable ? 1 : 0;
 241
 242         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
 243                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
 244                 return false;
 245
 246         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
 247                 &backlight_enable, 1) != DC_OK)
 248                 return false;
 249
 250         return true;
 251 }
 252
 253 // we read default from 0x320 because we expect BIOS wrote it there
 254 // regular get_backlight_nit reads from panel set at 0x326
 255 static bool read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
 256 {
 257         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
 258                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
 259                 return false;
 260
 261         if (!link->dpcd_caps.panel_luminance_control) {
 262                 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
 263                         (uint8_t *)backlight_millinits,
 264                         sizeof(uint32_t)))
 265                         return false;
 266         } else {
 267                 //setting to 0 as a precaution, since target_luminance_value is 3 bytes
 268                 memset(backlight_millinits, 0, sizeof(uint32_t));
 269
 270                 if (!core_link_read_dpcd(link, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
 271                         (uint8_t *)backlight_millinits,
 272                         sizeof(struct target_luminance_value)))
 273                         return false;
 274         }
 275
 276         return true;
 277 }
 278
 279 bool set_default_brightness_aux(struct dc_link *link)
 280 {
 281         uint32_t default_backlight;
 282
 283         if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
 284                 if (!read_default_bl_aux(link, &default_backlight))
 285                         default_backlight = 150000;
 286                 // if < 5 nits or > 5000, it might be wrong readback
 287                 if (default_backlight < 5000 || default_backlight > 5000000)
 288                         default_backlight = 150000; //
 289
 290                 return edp_set_backlight_level_nits(link, true,
 291                                 default_backlight, 0);
 292         }
 293         return false;
 294 }
 295
 296 bool set_cached_brightness_aux(struct dc_link *link)
 297 {
 298         if (link->backlight_settings.backlight_millinits)
 299                 return edp_set_backlight_level_nits(link, true,
 300                                                     link->backlight_settings.backlight_millinits, 0);
 301         else
 302                 return set_default_brightness_aux(link);
 303         return false;
 304 }
 305
 306 bool edp_is_ilr_optimization_required(struct dc_link *link,
 307                 struct dc_crtc_timing *crtc_timing)
 308 {
 309         struct dc_link_settings link_setting;
 310         uint8_t link_bw_set;
 311         uint8_t link_rate_set;
 312         uint32_t req_bw;
 313         union lane_count_set lane_count_set = {0};
 314
 315         ASSERT(link || crtc_timing); // invalid input
 316
 317         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
 318                         !link->panel_config.ilr.optimize_edp_link_rate)
 319                 return false;
 320
 321
 322         // Read DPCD 00100h to find if standard link rates are set
 323         core_link_read_dpcd(link, DP_LINK_BW_SET,
 324                                 &link_bw_set, sizeof(link_bw_set));
 325
 326         if (link_bw_set) {
 327                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
 328                 return true;
 329         }
 330
 331         // Read DPCD 00115h to find the edp link rate set used
 332         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 333                             &link_rate_set, sizeof(link_rate_set));
 334
 335         // Read DPCD 00101h to find out the number of lanes currently set
 336         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
 337                                 &lane_count_set.raw, sizeof(lane_count_set));
 338
 339         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link));
 340
 341         if (!crtc_timing->flags.DSC)
 342                 edp_decide_link_settings(link, &link_setting, req_bw);
 343         else
 344                 decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN);
 345
 346         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
 347                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
 348                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
 349                 return true;
 350         }
 351
 352         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
 353         return false;
 354 }
 355
 356 void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd)
 357 {
 358         if (link->connector_signal != SIGNAL_TYPE_EDP)
 359                 return;
 360
 361         link->dc->hwss.edp_power_control(link, true);
 362         if (wait_for_hpd)
 363                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 364         if (link->dc->hwss.edp_backlight_control)
 365                 link->dc->hwss.edp_backlight_control(link, true);
 366 }
 367
 368 void edp_set_panel_power(struct dc_link *link, bool powerOn)
 369 {
 370         if (powerOn) {
 371                 // 1. panel VDD on
 372                 if (!link->dc->config.edp_no_power_sequencing)
 373                         link->dc->hwss.edp_power_control(link, true);
 374                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 375
 376                 // 2. panel BL on
 377                 if (link->dc->hwss.edp_backlight_control)
 378                         link->dc->hwss.edp_backlight_control(link, true);
 379
 380                 // 3. Rx power on
 381                 dpcd_write_rx_power_ctrl(link, true);
 382         } else {
 383                 // 3. Rx power off
 384                 dpcd_write_rx_power_ctrl(link, false);
 385
 386                 // 2. panel BL off
 387                 if (link->dc->hwss.edp_backlight_control)
 388                         link->dc->hwss.edp_backlight_control(link, false);
 389
 390                 // 1. panel VDD off
 391                 if (!link->dc->config.edp_no_power_sequencing)
 392                         link->dc->hwss.edp_power_control(link, false);
 393         }
 394 }
 395
 396 bool edp_wait_for_t12(struct dc_link *link)
 397 {
 398         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 399                 link->dc->hwss.edp_wait_for_T12(link);
 400
 401                 return true;
 402         }
 403
 404         return false;
 405 }
 406
 407 void edp_add_delay_for_T9(struct dc_link *link)
 408 {
 409         if (link && link->panel_config.pps.extra_delay_backlight_off > 0)
 410                 fsleep(link->panel_config.pps.extra_delay_backlight_off * 1000);
 411 }
 412
 413 bool edp_receiver_ready_T9(struct dc_link *link)
 414 {
 415         unsigned int tries = 0;
 416         unsigned char sinkstatus = 0;
 417         unsigned char edpRev = 0;
 418         enum dc_status result = DC_OK;
 419
 420         result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 421
 422         /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 423         if (result == DC_OK && edpRev >= DP_EDP_12) {
 424                 do {
 425                         sinkstatus = 1;
 426                         result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
 427                         if (sinkstatus == 0)
 428                                 break;
 429                         if (result != DC_OK)
 430                                 break;
 431                         udelay(100); //MAx T9
 432                 } while (++tries < 50);
 433         }
 434
 435         return result;
 436 }
 437
 438 bool edp_receiver_ready_T7(struct dc_link *link)
 439 {
 440         unsigned char sinkstatus = 0;
 441         unsigned char edpRev = 0;
 442         enum dc_status result = DC_OK;
 443
 444         /* use absolute time stamp to constrain max T7*/
 445         unsigned long long enter_timestamp = 0;
 446         unsigned long long finish_timestamp = 0;
 447         unsigned long long time_taken_in_ns = 0;
 448
 449         result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 450
 451         if (result == DC_OK && edpRev >= DP_EDP_12) {
 452                 /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 453                 enter_timestamp = dm_get_timestamp(link->ctx);
 454                 do {
 455                         sinkstatus = 0;
 456                         result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
 457                         if (sinkstatus == 1)
 458                                 break;
 459                         if (result != DC_OK)
 460                                 break;
 461                         udelay(25);
 462                         finish_timestamp = dm_get_timestamp(link->ctx);
 463                         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);
 464                 } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
 465         }
 466
 467         if (link && link->panel_config.pps.extra_t7_ms > 0)
 468                 fsleep(link->panel_config.pps.extra_t7_ms * 1000);
 469
 470         return result;
 471 }
 472
 473 bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
 474 {
 475         bool ret = false;
 476         union dpcd_alpm_configuration alpm_config;
 477
 478         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
 479                 memset(&alpm_config, 0, sizeof(alpm_config));
 480
 481                 alpm_config.bits.ENABLE = (enable ? true : false);
 482                 ret = dm_helpers_dp_write_dpcd(link->ctx, link,
 483                                 DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw,
 484                                 sizeof(alpm_config.raw));
 485         }
 486         return ret;
 487 }
 488
 489 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
 490 {
 491         int i;
 492         struct dc *dc = link->ctx->dc;
 493         struct pipe_ctx *pipe_ctx = NULL;
 494
 495         for (i = 0; i < MAX_PIPES; i++) {
 496                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
 497                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
 498                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 499                                 break;
 500                         }
 501                 }
 502         }
 503
 504         return pipe_ctx;
 505 }
 506
 507 bool edp_set_backlight_level(const struct dc_link *link,
 508                 uint32_t backlight_pwm_u16_16,
 509                 uint32_t frame_ramp)
 510 {
 511         struct dc  *dc = link->ctx->dc;
 512
 513         DC_LOGGER_INIT(link->ctx->logger);
 514         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
 515                         backlight_pwm_u16_16, backlight_pwm_u16_16);
 516
 517         if (dc_is_embedded_signal(link->connector_signal)) {
 518                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
 519
 520                 if (pipe_ctx) {
 521                         /* Disable brightness ramping when the display is blanked
 522                          * as it can hang the DMCU
 523                          */
 524                         if (pipe_ctx->plane_state == NULL)
 525                                 frame_ramp = 0;
 526                 } else {
 527                         return false;
 528                 }
 529
 530                 dc->hwss.set_backlight_level(
 531                                 pipe_ctx,
 532                                 backlight_pwm_u16_16,
 533                                 frame_ramp);
 534         }
 535         return true;
 536 }
 537
 538 bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
 539                 bool wait, bool force_static, const unsigned int *power_opts)
 540 {
 541         struct dc  *dc = link->ctx->dc;
 542         struct dmcu *dmcu = dc->res_pool->dmcu;
 543         struct dmub_psr *psr = dc->res_pool->psr;
 544         unsigned int panel_inst;
 545
 546         if (psr == NULL && force_static)
 547                 return false;
 548
 549         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 550                 return false;
 551
 552         if ((allow_active != NULL) && (*allow_active == true) && (link->type == dc_connection_none)) {
 553                 // Don't enter PSR if panel is not connected
 554                 return false;
 555         }
 556
 557         /* Set power optimization flag */
 558         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
 559                 link->psr_settings.psr_power_opt = *power_opts;
 560
 561                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
 562                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
 563         }
 564
 565         if (psr != NULL && link->psr_settings.psr_feature_enabled &&
 566                         force_static && psr->funcs->psr_force_static)
 567                 psr->funcs->psr_force_static(psr, panel_inst);
 568
 569         /* Enable or Disable PSR */
 570         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
 571                 link->psr_settings.psr_allow_active = *allow_active;
 572
 573                 if (!link->psr_settings.psr_allow_active)
 574                         dc_z10_restore(dc);
 575
 576                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
 577                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
 578                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
 579                         link->psr_settings.psr_feature_enabled)
 580                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
 581                 else
 582                         return false;
 583         }
 584         return true;
 585 }
 586
 587 bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
 588 {
 589         struct dc  *dc = link->ctx->dc;
 590         struct dmcu *dmcu = dc->res_pool->dmcu;
 591         struct dmub_psr *psr = dc->res_pool->psr;
 592         unsigned int panel_inst;
 593
 594         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 595                 return false;
 596
 597         if (psr != NULL && link->psr_settings.psr_feature_enabled)
 598                 psr->funcs->psr_get_state(psr, state, panel_inst);
 599         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
 600                 dmcu->funcs->get_psr_state(dmcu, state);
 601
 602         return true;
 603 }
 604
 605 static inline enum physical_phy_id
 606 transmitter_to_phy_id(struct dc_link *link)
 607 {
 608         struct dc_context *dc_ctx = link->ctx;
 609         enum transmitter transmitter_value = link->link_enc->transmitter;
 610
 611         switch (transmitter_value) {
 612         case TRANSMITTER_UNIPHY_A:
 613                 return PHYLD_0;
 614         case TRANSMITTER_UNIPHY_B:
 615                 return PHYLD_1;
 616         case TRANSMITTER_UNIPHY_C:
 617                 return PHYLD_2;
 618         case TRANSMITTER_UNIPHY_D:
 619                 return PHYLD_3;
 620         case TRANSMITTER_UNIPHY_E:
 621                 return PHYLD_4;
 622         case TRANSMITTER_UNIPHY_F:
 623                 return PHYLD_5;
 624         case TRANSMITTER_NUTMEG_CRT:
 625                 return PHYLD_6;
 626         case TRANSMITTER_TRAVIS_CRT:
 627                 return PHYLD_7;
 628         case TRANSMITTER_TRAVIS_LCD:
 629                 return PHYLD_8;
 630         case TRANSMITTER_UNIPHY_G:
 631                 return PHYLD_9;
 632         case TRANSMITTER_COUNT:
 633                 return PHYLD_COUNT;
 634         case TRANSMITTER_UNKNOWN:
 635                 return PHYLD_UNKNOWN;
 636         default:
 637                 DC_ERROR("Unknown transmitter value %d\n", transmitter_value);
 638                 return PHYLD_UNKNOWN;
 639         }
 640 }
 641
 642 bool edp_setup_psr(struct dc_link *link,
 643                 const struct dc_stream_state *stream, struct psr_config *psr_config,
 644                 struct psr_context *psr_context)
 645 {
 646         struct dc *dc;
 647         struct dmcu *dmcu;
 648         struct dmub_psr *psr;
 649         int i;
 650         unsigned int panel_inst;
 651         /* updateSinkPsrDpcdConfig*/
 652         union dpcd_psr_configuration psr_configuration;
 653         union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
 654
 655         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 656
 657         if (!link)
 658                 return false;
 659
 660         dc = link->ctx->dc;
 661         dmcu = dc->res_pool->dmcu;
 662         psr = dc->res_pool->psr;
 663
 664         if (!dmcu && !psr)
 665                 return false;
 666
 667         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 668                 return false;
 669
 670
 671         memset(&psr_configuration, 0, sizeof(psr_configuration));
 672
 673         psr_configuration.bits.ENABLE                    = 1;
 674         psr_configuration.bits.CRC_VERIFICATION          = 1;
 675         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
 676                         psr_config->psr_frame_capture_indication_req;
 677
 678         /* Check for PSR v2*/
 679         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
 680                 /* For PSR v2 selective update.
 681                  * Indicates whether sink should start capturing
 682                  * immediately following active scan line,
 683                  * or starting with the 2nd active scan line.
 684                  */
 685                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
 686                 /*For PSR v2, determines whether Sink should generate
 687                  * IRQ_HPD when CRC mismatch is detected.
 688                  */
 689                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
 690                 /* For PSR v2, set the bit when the Source device will
 691                  * be enabling PSR2 operation.
 692                  */
 693                 psr_configuration.bits.ENABLE_PSR2    = 1;
 694                 /* For PSR v2, the Sink device must be able to receive
 695                  * SU region updates early in the frame time.
 696                  */
 697                 psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
 698         }
 699
 700         dm_helpers_dp_write_dpcd(
 701                 link->ctx,
 702                 link,
 703                 368,
 704                 &psr_configuration.raw,
 705                 sizeof(psr_configuration.raw));
 706
 707         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
 708                 edp_power_alpm_dpcd_enable(link, true);
 709                 psr_context->su_granularity_required =
 710                         psr_config->su_granularity_required;
 711                 psr_context->su_y_granularity =
 712                         psr_config->su_y_granularity;
 713                 psr_context->line_time_in_us = psr_config->line_time_in_us;
 714
 715                 /* linux must be able to expose AMD Source DPCD definition
 716                  * in order to support FreeSync PSR
 717                  */
 718                 if (link->psr_settings.psr_vtotal_control_support) {
 719                         psr_context->rate_control_caps = psr_config->rate_control_caps;
 720                         vtotal_control.bits.ENABLE = true;
 721                         core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
 722                                                         &vtotal_control.raw, sizeof(vtotal_control.raw));
 723                 }
 724         }
 725
 726         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
 727         psr_context->transmitterId = link->link_enc->transmitter;
 728         psr_context->engineId = link->link_enc->preferred_engine;
 729
 730         for (i = 0; i < MAX_PIPES; i++) {
 731                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 732                                 == stream) {
 733                         /* dmcu -1 for all controller id values,
 734                          * therefore +1 here
 735                          */
 736                         psr_context->controllerId =
 737                                 dc->current_state->res_ctx.
 738                                 pipe_ctx[i].stream_res.tg->inst + 1;
 739                         break;
 740                 }
 741         }
 742
 743         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
 744         psr_context->phyType = PHY_TYPE_UNIPHY;
 745         /*PhyId is associated with the transmitter id*/
 746         psr_context->smuPhyId = transmitter_to_phy_id(link);
 747
 748         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
 749         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
 750                                         timing.pix_clk_100hz * 100),
 751                                         stream->timing.v_total),
 752                                         stream->timing.h_total);
 753
 754         psr_context->psrSupportedDisplayConfig = true;
 755         psr_context->psrExitLinkTrainingRequired =
 756                 psr_config->psr_exit_link_training_required;
 757         psr_context->sdpTransmitLineNumDeadline =
 758                 psr_config->psr_sdp_transmit_line_num_deadline;
 759         psr_context->psrFrameCaptureIndicationReq =
 760                 psr_config->psr_frame_capture_indication_req;
 761
 762         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
 763
 764         psr_context->numberOfControllers =
 765                         link->dc->res_pool->timing_generator_count;
 766
 767         psr_context->rfb_update_auto_en = true;
 768
 769         /* 2 frames before enter PSR. */
 770         psr_context->timehyst_frames = 2;
 771         /* half a frame
 772          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
 773          */
 774         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
 775         psr_context->aux_repeats = 10;
 776
 777         psr_context->psr_level.u32all = 0;
 778
 779         /*skip power down the single pipe since it blocks the cstate*/
 780         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
 781                 switch (link->ctx->asic_id.chip_family) {
 782                 case FAMILY_YELLOW_CARP:
 783                 case AMDGPU_FAMILY_GC_10_3_6:
 784                 case AMDGPU_FAMILY_GC_11_0_1:
 785                         if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable)
 786                                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
 787                         break;
 788                 default:
 789                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
 790                         break;
 791                 }
 792         }
 793
 794         /* SMU will perform additional powerdown sequence.
 795          * For unsupported ASICs, set psr_level flag to skip PSR
 796          *  static screen notification to SMU.
 797          *  (Always set for DAL2, did not check ASIC)
 798          */
 799         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
 800         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
 801
 802         /* Complete PSR entry before aborting to prevent intermittent
 803          * freezes on certain eDPs
 804          */
 805         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
 806
 807         /* Disable ALPM first for compatible non-ALPM panel now */
 808         psr_context->psr_level.bits.DISABLE_ALPM = 0;
 809         psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
 810
 811         /* Controls additional delay after remote frame capture before
 812          * continuing power down, default = 0
 813          */
 814         psr_context->frame_delay = 0;
 815
 816         psr_context->dsc_slice_height = psr_config->dsc_slice_height;
 817
 818         if (psr) {
 819                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
 820                         link, psr_context, panel_inst);
 821                 link->psr_settings.psr_power_opt = 0;
 822                 link->psr_settings.psr_allow_active = 0;
 823         } else {
 824                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
 825         }
 826
 827         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
 828          * should not happen since firmware should be running at this point
 829          */
 830         if (link->psr_settings.psr_feature_enabled == 0)
 831                 ASSERT(0);
 832
 833         return true;
 834
 835 }
 836
 837 void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency)
 838 {
 839         struct dc  *dc = link->ctx->dc;
 840         struct dmub_psr *psr = dc->res_pool->psr;
 841         unsigned int panel_inst;
 842
 843         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 844                 return;
 845
 846         // PSR residency measurements only supported on DMCUB
 847         if (psr != NULL && link->psr_settings.psr_feature_enabled)
 848                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
 849         else
 850                 *residency = 0;
 851 }
 852 bool edp_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
 853 {
 854         struct dc *dc = link->ctx->dc;
 855         struct dmub_psr *psr = dc->res_pool->psr;
 856
 857         if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
 858                 return false;
 859
 860         psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
 861
 862         return true;
 863 }
 864
 865 bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active,
 866         bool wait, bool force_static, const unsigned int *power_opts)
 867 {
 868         struct dc  *dc = link->ctx->dc;
 869         struct dmub_replay *replay = dc->res_pool->replay;
 870         unsigned int panel_inst;
 871
 872         if (replay == NULL && force_static)
 873                 return false;
 874
 875         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 876                 return false;
 877
 878         /* Set power optimization flag */
 879         if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts) {
 880                 if (link->replay_settings.replay_feature_enabled && replay->funcs->replay_set_power_opt) {
 881                         replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst);
 882                         link->replay_settings.replay_power_opt_active = *power_opts;
 883                 }
 884         }
 885
 886         /* Activate or deactivate Replay */
 887         if (allow_active && link->replay_settings.replay_allow_active != *allow_active) {
 888                 // TODO: Handle mux change case if force_static is set
 889                 // If force_static is set, just change the replay_allow_active state directly
 890                 if (replay != NULL && link->replay_settings.replay_feature_enabled)
 891                         replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst);
 892                 link->replay_settings.replay_allow_active = *allow_active;
 893         }
 894
 895         return true;
 896 }
 897
 898 bool edp_get_replay_state(const struct dc_link *link, uint64_t *state)
 899 {
 900         struct dc  *dc = link->ctx->dc;
 901         struct dmub_replay *replay = dc->res_pool->replay;
 902         unsigned int panel_inst;
 903         enum replay_state pr_state = REPLAY_STATE_0;
 904
 905         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 906                 return false;
 907
 908         if (replay != NULL && link->replay_settings.replay_feature_enabled)
 909                 replay->funcs->replay_get_state(replay, &pr_state, panel_inst);
 910         *state = pr_state;
 911
 912         return true;
 913 }
 914
 915 bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream)
 916 {
 917         /* To-do: Setup Replay */
 918         struct dc *dc = link->ctx->dc;
 919         struct dmub_replay *replay = dc->res_pool->replay;
 920         int i;
 921         unsigned int panel_inst;
 922         struct replay_context replay_context = { 0 };
 923         unsigned int lineTimeInNs = 0;
 924
 925
 926         union replay_enable_and_configuration replay_config;
 927
 928         union dpcd_alpm_configuration alpm_config;
 929
 930         replay_context.controllerId = CONTROLLER_ID_UNDEFINED;
 931
 932         if (!link)
 933                 return false;
 934
 935         if (!replay)
 936                 return false;
 937
 938         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 939                 return false;
 940
 941         replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel;
 942         replay_context.digbe_inst = link->link_enc->transmitter;
 943         replay_context.digfe_inst = link->link_enc->preferred_engine;
 944
 945         for (i = 0; i < MAX_PIPES; i++) {
 946                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 947                                 == stream) {
 948                         /* dmcu -1 for all controller id values,
 949                          * therefore +1 here
 950                          */
 951                         replay_context.controllerId =
 952                                 dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;
 953                         break;
 954                 }
 955         }
 956
 957         lineTimeInNs =
 958                 ((stream->timing.h_total * 1000000) /
 959                         (stream->timing.pix_clk_100hz / 10)) + 1;
 960
 961         replay_context.line_time_in_ns = lineTimeInNs;
 962
 963         if (replay)
 964                 link->replay_settings.replay_feature_enabled =
 965                         replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst);
 966         if (link->replay_settings.replay_feature_enabled) {
 967
 968                 replay_config.bits.FREESYNC_PANEL_REPLAY_MODE = 1;
 969                 replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION =
 970                         link->replay_settings.config.replay_timing_sync_supported;
 971                 replay_config.bits.STATE_TRANSITION_ERROR_DETECTION = 1;
 972                 dm_helpers_dp_write_dpcd(link->ctx, link,
 973                         DP_SINK_PR_ENABLE_AND_CONFIGURATION,
 974                         (uint8_t *)&(replay_config.raw), sizeof(uint8_t));
 975
 976                 memset(&alpm_config, 0, sizeof(alpm_config));
 977                 alpm_config.bits.ENABLE = 1;
 978                 dm_helpers_dp_write_dpcd(
 979                         link->ctx,
 980                         link,
 981                         DP_RECEIVER_ALPM_CONFIG,
 982                         &alpm_config.raw,
 983                         sizeof(alpm_config.raw));
 984         }
 985         return true;
 986 }
 987
 988 bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal)
 989 {
 990         struct dc *dc = link->ctx->dc;
 991         struct dmub_replay *replay = dc->res_pool->replay;
 992         unsigned int panel_inst;
 993
 994         if (!replay)
 995                 return false;
 996
 997         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
 998                 return false;
 999
1000         if (coasting_vtotal && link->replay_settings.coasting_vtotal != coasting_vtotal) {
1001                 replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst);
1002                 link->replay_settings.coasting_vtotal = coasting_vtotal;
1003         }
1004
1005         return true;
1006 }
1007
1008 bool edp_replay_residency(const struct dc_link *link,
1009         unsigned int *residency, const bool is_start, const bool is_alpm)
1010 {
1011         struct dc  *dc = link->ctx->dc;
1012         struct dmub_replay *replay = dc->res_pool->replay;
1013         unsigned int panel_inst;
1014
1015         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
1016                 return false;
1017
1018         if (replay != NULL && link->replay_settings.replay_feature_enabled)
1019                 replay->funcs->replay_residency(replay, panel_inst, residency, is_start, is_alpm);
1020         else
1021                 *residency = 0;
1022
1023         return true;
1024 }
1025
1026 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
1027 {
1028         int i;
1029         struct dc *dc = link->ctx->dc;
1030         struct abm *abm = NULL;
1031
1032         for (i = 0; i < MAX_PIPES; i++) {
1033                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
1034                 struct dc_stream_state *stream = pipe_ctx.stream;
1035
1036                 if (stream && stream->link == link) {
1037                         abm = pipe_ctx.stream_res.abm;
1038                         break;
1039                 }
1040         }
1041         return abm;
1042 }
1043
1044 int edp_get_backlight_level(const struct dc_link *link)
1045 {
1046         struct abm *abm = get_abm_from_stream_res(link);
1047         struct panel_cntl *panel_cntl = link->panel_cntl;
1048         struct dc  *dc = link->ctx->dc;
1049         struct dmcu *dmcu = dc->res_pool->dmcu;
1050         bool fw_set_brightness = true;
1051
1052         if (dmcu)
1053                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
1054
1055         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
1056                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
1057         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
1058                 return (int) abm->funcs->get_current_backlight(abm);
1059         else
1060                 return DC_ERROR_UNEXPECTED;
1061 }
1062
1063 int edp_get_target_backlight_pwm(const struct dc_link *link)
1064 {
1065         struct abm *abm = get_abm_from_stream_res(link);
1066
1067         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
1068                 return DC_ERROR_UNEXPECTED;
1069
1070         return (int) abm->funcs->get_target_backlight(abm);
1071 }