2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef _CORE_TYPES_H_
27 #define _CORE_TYPES_H_
30 #include "dce_calcs.h"
31 #include "dcn_calcs.h"
32 #include "ddc_service_types.h"
33 #include "dc_bios_types.h"
34 #include "mem_input.h"
36 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
39 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
44 #define MAX_CLOCK_SOURCES 7
46 void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
47 uint32_t controller_id);
49 #include "grph_object_id.h"
50 #include "link_encoder.h"
51 #include "stream_encoder.h"
52 #include "clock_source.h"
54 #include "dm_pp_smu.h"
57 /************ link *****************/
58 struct link_init_data {
60 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
61 uint32_t connector_index; /* this will be mapped to the HPD pins */
62 uint32_t link_index; /* this is mapped to DAL display_index
63 TODO: remove it when DC is complete. */
67 FREE_ACQUIRED_RESOURCE = 0,
68 KEEP_ACQUIRED_RESOURCE = 1,
71 struct dc_link *link_create(const struct link_init_data *init_params);
72 void link_destroy(struct dc_link **link);
74 enum dc_status dc_link_validate_mode_timing(
75 const struct dc_stream_state *stream,
77 const struct dc_crtc_timing *timing);
79 void core_link_resume(struct dc_link *link);
81 void core_link_enable_stream(
82 struct dc_state *state,
83 struct pipe_ctx *pipe_ctx);
85 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option);
87 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
88 /********** DAL Core*********************/
89 #include "transform.h"
94 struct resource_context;
96 struct resource_funcs {
97 void (*destroy)(struct resource_pool **pool);
98 void (*link_init)(struct dc_link *link);
99 struct link_encoder *(*link_enc_create)(
100 const struct encoder_init_data *init);
101 bool (*validate_bandwidth)(
103 struct dc_state *context,
106 int (*populate_dml_pipes)(
108 struct resource_context *res_ctx,
109 display_e2e_pipe_params_st *pipes);
111 enum dc_status (*validate_global)(
113 struct dc_state *context);
115 struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
116 struct dc_state *context,
117 const struct resource_pool *pool,
118 struct dc_stream_state *stream);
120 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
122 enum dc_status (*add_stream_to_ctx)(
124 struct dc_state *new_ctx,
125 struct dc_stream_state *dc_stream);
127 enum dc_status (*remove_stream_from_ctx)(
129 struct dc_state *new_ctx,
130 struct dc_stream_state *stream);
131 enum dc_status (*get_default_swizzle_mode)(
132 struct dc_plane_state *plane_state);
134 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)(
135 struct resource_context *res_ctx,
136 const struct resource_pool *pool,
137 struct dc_stream_state *stream);
138 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
139 void (*populate_dml_writeback_from_context)(
141 struct resource_context *res_ctx,
142 display_e2e_pipe_params_st *pipes);
144 void (*set_mcif_arb_params)(
146 struct dc_state *context,
147 display_e2e_pipe_params_st *pipes,
153 struct audio_support{
155 bool hdmi_audio_on_dongle;
156 bool hdmi_audio_native;
159 #define NO_UNDERLAY_PIPE -1
161 struct resource_pool {
162 struct mem_input *mis[MAX_PIPES];
163 struct hubp *hubps[MAX_PIPES];
164 struct input_pixel_processor *ipps[MAX_PIPES];
165 struct transform *transforms[MAX_PIPES];
166 struct dpp *dpps[MAX_PIPES];
167 struct output_pixel_processor *opps[MAX_PIPES];
168 struct timing_generator *timing_generators[MAX_PIPES];
169 struct stream_encoder *stream_enc[MAX_PIPES * 2];
170 struct hubbub *hubbub;
172 struct pp_smu_funcs *pp_smu;
173 struct dce_aux *engines[MAX_PIPES];
174 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
175 struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
176 bool i2c_hw_buffer_in_use;
178 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
179 struct dwbc *dwbc[MAX_DWB_PIPES];
180 struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
182 unsigned int gsl_0:1;
183 unsigned int gsl_1:1;
184 unsigned int gsl_2:1;
188 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
189 struct display_stream_compressor *dscs[MAX_PIPES];
192 unsigned int pipe_count;
193 unsigned int underlay_pipe_index;
194 unsigned int stream_enc_count;
197 unsigned int xtalin_clock_inKhz;
198 unsigned int dccg_ref_clock_inKhz;
199 unsigned int dchub_ref_clock_inKhz;
201 unsigned int timing_generator_count;
202 unsigned int mpcc_count;
204 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
205 unsigned int writeback_pipe_count;
208 * reserved clock source for DP
210 struct clock_source *dp_clock_source;
212 struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
213 unsigned int clk_src_count;
215 struct audio *audios[MAX_PIPES];
216 unsigned int audio_count;
217 struct audio_support audio_support;
220 struct irq_service *irqs;
225 const struct resource_funcs *funcs;
226 const struct resource_caps *res_cap;
229 struct dcn_fe_bandwidth {
234 struct stream_resource {
235 struct output_pixel_processor *opp;
236 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
237 struct display_stream_compressor *dsc;
240 struct timing_generator *tg;
241 struct stream_encoder *stream_enc;
244 struct pixel_clk_params pix_clk_params;
245 struct encoder_info_frame encoder_info_frame;
248 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
249 /* There are only (num_pipes+1)/2 groups. 0 means unassigned,
250 * otherwise it's using group number 'gsl_group-1'
256 struct plane_resource {
257 struct scaler_data scl_data;
259 struct mem_input *mi;
260 struct input_pixel_processor *ipp;
261 struct transform *xfm;
265 struct dcn_fe_bandwidth bw;
268 union pipe_update_flags {
271 uint32_t disable : 1;
273 uint32_t global_sync : 1;
274 uint32_t opp_changed : 1;
275 uint32_t tg_changed : 1;
278 uint32_t hubp_interdependent : 1;
279 uint32_t hubp_rq_dlg_ttu : 1;
280 uint32_t gamut_remap : 1;
282 uint32_t viewport : 1;
288 struct dc_plane_state *plane_state;
289 struct dc_stream_state *stream;
291 struct plane_resource plane_res;
292 struct stream_resource stream_res;
294 struct clock_source *clock_source;
296 struct pll_settings pll_settings;
300 struct pipe_ctx *top_pipe;
301 struct pipe_ctx *bottom_pipe;
303 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
304 struct _vcs_dpi_display_dlg_regs_st dlg_regs;
305 struct _vcs_dpi_display_ttu_regs_st ttu_regs;
306 struct _vcs_dpi_display_rq_regs_st rq_regs;
307 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
309 union pipe_update_flags update_flags;
310 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
312 struct mcif_wb *mcif_wb;
316 struct resource_context {
317 struct pipe_ctx pipe_ctx[MAX_PIPES];
318 bool is_stream_enc_acquired[MAX_PIPES * 2];
319 bool is_audio_acquired[MAX_PIPES];
320 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
321 uint8_t dp_clock_source_ref_count;
322 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
323 bool is_dsc_acquired[MAX_PIPES];
327 struct dce_bw_output {
328 bool cpuc_state_change_enable;
329 bool cpup_state_change_enable;
330 bool stutter_mode_enable;
331 bool nbp_state_change_enable;
332 bool all_displays_in_sync;
333 struct dce_watermarks urgent_wm_ns[MAX_PIPES];
334 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
335 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
336 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
338 int sclk_deep_sleep_khz;
341 int blackout_recovery_time_us;
344 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
345 struct dcn_bw_writeback {
346 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
350 struct dcn_bw_output {
351 struct dc_clocks clk;
352 struct dcn_watermark_set watermarks;
353 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
354 struct dcn_bw_writeback bw_writeback;
359 struct dcn_bw_output dcn;
360 struct dce_bw_output dce;
365 struct display_mode_lib dml;
368 * struct dc_state - The full description of a state requested by a user
370 * @streams: Stream properties
371 * @stream_status: The planes on a given stream
372 * @res_ctx: Persistent state of resources
373 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
374 * @pp_display_cfg: PowerPlay clocks and settings
375 * @dcn_bw_vars: non-stack memory to support bandwidth calculations
379 struct dc_stream_state *streams[MAX_PIPES];
380 struct dc_stream_status stream_status[MAX_PIPES];
381 uint8_t stream_count;
383 struct resource_context res_ctx;
385 struct bw_context bw_ctx;
387 /* Note: these are big structures, do *not* put on stack! */
388 struct dm_pp_display_configuration pp_display_cfg;
389 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
390 struct dcn_bw_internal_vars dcn_bw_vars;
393 struct clk_mgr *clk_mgr;
396 bool full_update_needed : 1;
399 struct kref refcount;
402 #endif /* _CORE_TYPES_H_ */