2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dm_services.h"
30 #include "dcn31/dcn31_init.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn31_resource.h"
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
39 #include "dml/dcn30/dcn30_fpu.h"
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn30/dcn30_hubbub.h"
43 #include "dcn31/dcn31_hubbub.h"
44 #include "dcn30/dcn30_mpc.h"
45 #include "dcn31/dcn31_hubp.h"
46 #include "irq/dcn31/irq_service_dcn31.h"
47 #include "dcn30/dcn30_dpp.h"
48 #include "dcn31/dcn31_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hw_sequencer.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
59 #include "dcn31/dcn31_apg.h"
60 #include "dcn31/dcn31_dio_link_encoder.h"
61 #include "dcn31/dcn31_vpg.h"
62 #include "dcn31/dcn31_afmt.h"
63 #include "dce/dce_clock_source.h"
64 #include "dce/dce_audio.h"
65 #include "dce/dce_hwseq.h"
67 #include "virtual/virtual_stream_encoder.h"
68 #include "dce110/dce110_resource.h"
69 #include "dml/display_mode_vba.h"
70 #include "dml/dcn31/dcn31_fpu.h"
71 #include "dcn31/dcn31_dccg.h"
72 #include "dcn10/dcn10_resource.h"
73 #include "dcn31_panel_cntl.h"
75 #include "dcn30/dcn30_dwb.h"
76 #include "dcn30/dcn30_mmhubbub.h"
78 // TODO: change include headers /amd/include/asic_reg after upstream
79 #include "yellow_carp_offset.h"
80 #include "dcn/dcn_3_1_2_offset.h"
81 #include "dcn/dcn_3_1_2_sh_mask.h"
82 #include "nbio/nbio_7_2_0_offset.h"
83 #include "dpcs/dpcs_4_2_0_offset.h"
84 #include "dpcs/dpcs_4_2_0_sh_mask.h"
85 #include "mmhub/mmhub_2_3_0_offset.h"
86 #include "mmhub/mmhub_2_3_0_sh_mask.h"
89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
94 #include "reg_helper.h"
95 #include "dce/dmub_abm.h"
96 #include "dce/dmub_psr.h"
97 #include "dce/dce_aux.h"
98 #include "dce/dce_i2c.h"
99 #include "dce/dmub_replay.h"
101 #include "dml/dcn30/display_mode_vba_30.h"
102 #include "vm_helper.h"
103 #include "dcn20/dcn20_vmid.h"
105 #include "link_enc_cfg.h"
107 #define DC_LOGGER_INIT(logger)
109 enum dcn31_clk_src_array_id {
118 /* begin *********************
119 * macros to expend register list macro defined in HW object header file
123 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
125 #define BASE(seg) BASE_INNER(seg)
127 #define SR(reg_name)\
128 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
131 #define SRI(reg_name, block, id)\
132 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
133 reg ## block ## id ## _ ## reg_name
135 #define SRI2(reg_name, block, id)\
136 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
139 #define SRIR(var_name, reg_name, block, id)\
140 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 reg ## block ## id ## _ ## reg_name
143 #define SRII(reg_name, block, id)\
144 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 reg ## block ## id ## _ ## reg_name
147 #define SRII_MPC_RMU(reg_name, block, id)\
148 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 reg ## block ## id ## _ ## reg_name
151 #define SRII_DWB(reg_name, temp_name, block, id)\
152 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
153 reg ## block ## id ## _ ## temp_name
155 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
156 .field_name = reg_name ## __ ## field_name ## post_fix
158 #define DCCG_SRII(reg_name, block, id)\
159 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
160 reg ## block ## id ## _ ## reg_name
162 #define VUPDATE_SRII(reg_name, block, id)\
163 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
164 reg ## reg_name ## _ ## block ## id
167 #define NBIO_BASE_INNER(seg) \
168 NBIO_BASE__INST0_SEG ## seg
170 #define NBIO_BASE(seg) \
173 #define NBIO_SR(reg_name)\
174 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
175 regBIF_BX1_ ## reg_name
178 #define MMHUB_BASE_INNER(seg) \
179 MMHUB_BASE__INST0_SEG ## seg
181 #define MMHUB_BASE(seg) \
182 MMHUB_BASE_INNER(seg)
184 #define MMHUB_SR(reg_name)\
185 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
189 #define CLK_BASE_INNER(seg) \
190 CLK_BASE__INST0_SEG ## seg
192 #define CLK_BASE(seg) \
195 #define CLK_SRI(reg_name, block, inst)\
196 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
197 reg ## block ## _ ## inst ## _ ## reg_name
200 static const struct bios_registers bios_regs = {
201 NBIO_SR(BIOS_SCRATCH_3),
202 NBIO_SR(BIOS_SCRATCH_6)
205 #define clk_src_regs(index, pllid)\
207 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
210 static const struct dce110_clk_src_regs clk_src_regs[] = {
217 /*pll_id being rempped in dmub, in driver it is logical instance*/
218 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
226 static const struct dce110_clk_src_shift cs_shift = {
227 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
230 static const struct dce110_clk_src_mask cs_mask = {
231 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
234 #define abm_regs(id)\
236 ABM_DCN302_REG_LIST(id)\
239 static const struct dce_abm_registers abm_regs[] = {
246 static const struct dce_abm_shift abm_shift = {
247 ABM_MASK_SH_LIST_DCN30(__SHIFT)
250 static const struct dce_abm_mask abm_mask = {
251 ABM_MASK_SH_LIST_DCN30(_MASK)
254 #define audio_regs(id)\
256 AUD_COMMON_REG_LIST(id)\
259 static const struct dce_audio_registers audio_regs[] = {
269 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
270 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
271 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
272 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
274 static const struct dce_audio_shift audio_shift = {
275 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
278 static const struct dce_audio_mask audio_mask = {
279 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
282 #define vpg_regs(id)\
284 VPG_DCN31_REG_LIST(id)\
287 static const struct dcn31_vpg_registers vpg_regs[] = {
300 static const struct dcn31_vpg_shift vpg_shift = {
301 DCN31_VPG_MASK_SH_LIST(__SHIFT)
304 static const struct dcn31_vpg_mask vpg_mask = {
305 DCN31_VPG_MASK_SH_LIST(_MASK)
308 #define afmt_regs(id)\
310 AFMT_DCN31_REG_LIST(id)\
313 static const struct dcn31_afmt_registers afmt_regs[] = {
322 static const struct dcn31_afmt_shift afmt_shift = {
323 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
326 static const struct dcn31_afmt_mask afmt_mask = {
327 DCN31_AFMT_MASK_SH_LIST(_MASK)
330 #define apg_regs(id)\
332 APG_DCN31_REG_LIST(id)\
335 static const struct dcn31_apg_registers apg_regs[] = {
342 static const struct dcn31_apg_shift apg_shift = {
343 DCN31_APG_MASK_SH_LIST(__SHIFT)
346 static const struct dcn31_apg_mask apg_mask = {
347 DCN31_APG_MASK_SH_LIST(_MASK)
350 #define stream_enc_regs(id)\
352 SE_DCN3_REG_LIST(id)\
355 /* Some encoders won't be initialized here - but they're logical, not physical. */
356 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
364 static const struct dcn10_stream_encoder_shift se_shift = {
365 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
368 static const struct dcn10_stream_encoder_mask se_mask = {
369 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
373 #define aux_regs(id)\
375 DCN2_AUX_REG_LIST(id)\
378 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
386 #define hpd_regs(id)\
391 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
399 #define link_regs(id, phyid)\
401 LE_DCN31_REG_LIST(id), \
402 UNIPHY_DCN2_REG_LIST(phyid), \
403 DPCS_DCN31_REG_LIST(id), \
406 static const struct dce110_aux_registers_shift aux_shift = {
407 DCN_AUX_MASK_SH_LIST(__SHIFT)
410 static const struct dce110_aux_registers_mask aux_mask = {
411 DCN_AUX_MASK_SH_LIST(_MASK)
414 static const struct dcn10_link_enc_registers link_enc_regs[] = {
422 static const struct dcn10_link_enc_shift le_shift = {
423 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
424 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
427 static const struct dcn10_link_enc_mask le_mask = {
428 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
429 DPCS_DCN31_MASK_SH_LIST(_MASK)
432 #define hpo_dp_stream_encoder_reg_list(id)\
434 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
437 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
438 hpo_dp_stream_encoder_reg_list(0),
439 hpo_dp_stream_encoder_reg_list(1),
440 hpo_dp_stream_encoder_reg_list(2),
441 hpo_dp_stream_encoder_reg_list(3),
444 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
445 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
448 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
449 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
452 #define hpo_dp_link_encoder_reg_list(id)\
454 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
455 DCN3_1_RDPCSTX_REG_LIST(0),\
456 DCN3_1_RDPCSTX_REG_LIST(1),\
457 DCN3_1_RDPCSTX_REG_LIST(2),\
458 DCN3_1_RDPCSTX_REG_LIST(3),\
459 DCN3_1_RDPCSTX_REG_LIST(4)\
462 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
463 hpo_dp_link_encoder_reg_list(0),
464 hpo_dp_link_encoder_reg_list(1),
467 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
468 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
471 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
472 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
475 #define dpp_regs(id)\
477 DPP_REG_LIST_DCN30(id),\
480 static const struct dcn3_dpp_registers dpp_regs[] = {
487 static const struct dcn3_dpp_shift tf_shift = {
488 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
491 static const struct dcn3_dpp_mask tf_mask = {
492 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
495 #define opp_regs(id)\
497 OPP_REG_LIST_DCN30(id),\
500 static const struct dcn20_opp_registers opp_regs[] = {
507 static const struct dcn20_opp_shift opp_shift = {
508 OPP_MASK_SH_LIST_DCN20(__SHIFT)
511 static const struct dcn20_opp_mask opp_mask = {
512 OPP_MASK_SH_LIST_DCN20(_MASK)
515 #define aux_engine_regs(id)\
517 AUX_COMMON_REG_LIST0(id), \
520 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
523 static const struct dce110_aux_registers aux_engine_regs[] = {
531 #define dwbc_regs_dcn3(id)\
533 DWBC_COMMON_REG_LIST_DCN30(id),\
536 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
540 static const struct dcn30_dwbc_shift dwbc30_shift = {
541 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
544 static const struct dcn30_dwbc_mask dwbc30_mask = {
545 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
548 #define mcif_wb_regs_dcn3(id)\
550 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
553 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
557 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
558 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
561 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
562 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
565 #define dsc_regsDCN20(id)\
567 DSC_REG_LIST_DCN20(id)\
570 static const struct dcn20_dsc_registers dsc_regs[] = {
576 static const struct dcn20_dsc_shift dsc_shift = {
577 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
580 static const struct dcn20_dsc_mask dsc_mask = {
581 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
584 static const struct dcn30_mpc_registers mpc_regs = {
585 MPC_REG_LIST_DCN3_0(0),
586 MPC_REG_LIST_DCN3_0(1),
587 MPC_REG_LIST_DCN3_0(2),
588 MPC_REG_LIST_DCN3_0(3),
589 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
590 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
591 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
592 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
593 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
594 MPC_RMU_REG_LIST_DCN3AG(0),
595 MPC_RMU_REG_LIST_DCN3AG(1),
596 //MPC_RMU_REG_LIST_DCN3AG(2),
597 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
600 static const struct dcn30_mpc_shift mpc_shift = {
601 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
604 static const struct dcn30_mpc_mask mpc_mask = {
605 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
608 #define optc_regs(id)\
609 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
611 static const struct dcn_optc_registers optc_regs[] = {
618 static const struct dcn_optc_shift optc_shift = {
619 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
622 static const struct dcn_optc_mask optc_mask = {
623 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
626 #define hubp_regs(id)\
628 HUBP_REG_LIST_DCN30(id)\
631 static const struct dcn_hubp2_registers hubp_regs[] = {
639 static const struct dcn_hubp2_shift hubp_shift = {
640 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
643 static const struct dcn_hubp2_mask hubp_mask = {
644 HUBP_MASK_SH_LIST_DCN31(_MASK)
646 static const struct dcn_hubbub_registers hubbub_reg = {
647 HUBBUB_REG_LIST_DCN31(0)
650 static const struct dcn_hubbub_shift hubbub_shift = {
651 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
654 static const struct dcn_hubbub_mask hubbub_mask = {
655 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
658 static const struct dccg_registers dccg_regs = {
659 DCCG_REG_LIST_DCN31()
662 static const struct dccg_shift dccg_shift = {
663 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
666 static const struct dccg_mask dccg_mask = {
667 DCCG_MASK_SH_LIST_DCN31(_MASK)
671 #define SRII2(reg_name_pre, reg_name_post, id)\
672 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
673 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
674 reg ## reg_name_pre ## id ## _ ## reg_name_post
677 #define HWSEQ_DCN31_REG_LIST()\
678 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
679 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
680 SR(DIO_MEM_PWR_CTRL), \
681 SR(ODM_MEM_PWR_CTRL3), \
682 SR(DMU_MEM_PWR_CNTL), \
683 SR(MMHUBBUB_MEM_PWR_CNTL), \
684 SR(DCCG_GATE_DISABLE_CNTL), \
685 SR(DCCG_GATE_DISABLE_CNTL2), \
687 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
688 SRII(PIXEL_RATE_CNTL, OTG, 0), \
689 SRII(PIXEL_RATE_CNTL, OTG, 1),\
690 SRII(PIXEL_RATE_CNTL, OTG, 2),\
691 SRII(PIXEL_RATE_CNTL, OTG, 3),\
692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
696 SR(MICROSECOND_TIME_BASE_DIV), \
697 SR(MILLISECOND_TIME_BASE_DIV), \
698 SR(DISPCLK_FREQ_CHANGE_CNTL), \
699 SR(RBBMIF_TIMEOUT_DIS), \
700 SR(RBBMIF_TIMEOUT_DIS_2), \
701 SR(DCHUBBUB_CRC_CTRL), \
702 SR(DPP_TOP0_DPP_CRC_CTRL), \
703 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
704 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
706 SR(MPC_CRC_RESULT_GB), \
707 SR(MPC_CRC_RESULT_C), \
708 SR(MPC_CRC_RESULT_AR), \
709 SR(DOMAIN0_PG_CONFIG), \
710 SR(DOMAIN1_PG_CONFIG), \
711 SR(DOMAIN2_PG_CONFIG), \
712 SR(DOMAIN3_PG_CONFIG), \
713 SR(DOMAIN16_PG_CONFIG), \
714 SR(DOMAIN17_PG_CONFIG), \
715 SR(DOMAIN18_PG_CONFIG), \
716 SR(DOMAIN0_PG_STATUS), \
717 SR(DOMAIN1_PG_STATUS), \
718 SR(DOMAIN2_PG_STATUS), \
719 SR(DOMAIN3_PG_STATUS), \
720 SR(DOMAIN16_PG_STATUS), \
721 SR(DOMAIN17_PG_STATUS), \
722 SR(DOMAIN18_PG_STATUS), \
729 SR(DC_IP_REQUEST_CNTL), \
730 SR(AZALIA_AUDIO_DTO), \
731 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
732 SR(HPO_TOP_HW_CONTROL)
734 static const struct dce_hwseq_registers hwseq_reg = {
735 HWSEQ_DCN31_REG_LIST()
738 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
739 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
740 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
741 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
742 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
743 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
744 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
745 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
746 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
747 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
748 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
749 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
750 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
751 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
752 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
753 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
754 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
755 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
756 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
757 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
758 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
759 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
760 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
761 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
762 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
763 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
764 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
765 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
766 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
767 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
768 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
769 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
770 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
771 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
773 static const struct dce_hwseq_shift hwseq_shift = {
774 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
777 static const struct dce_hwseq_mask hwseq_mask = {
778 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
780 #define vmid_regs(id)\
782 DCN20_VMID_REG_LIST(id)\
785 static const struct dcn_vmid_registers vmid_regs[] = {
804 static const struct dcn20_vmid_shift vmid_shifts = {
805 DCN20_VMID_MASK_SH_LIST(__SHIFT)
808 static const struct dcn20_vmid_mask vmid_masks = {
809 DCN20_VMID_MASK_SH_LIST(_MASK)
812 static const struct resource_caps res_cap_dcn31 = {
813 .num_timing_generator = 4,
815 .num_video_plane = 4,
817 .num_stream_encoder = 5,
818 .num_dig_link_enc = 5,
819 .num_hpo_dp_stream_encoder = 4,
820 .num_hpo_dp_link_encoder = 2,
829 static const struct dc_plane_cap plane_cap = {
830 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
831 .per_pixel_alpha = true,
833 .pixel_format_support = {
841 .max_upscale_factor = {
847 // 6:1 downscaling ratio: 1000/6 = 166.666
848 .max_downscale_factor = {
857 static const struct dc_debug_options debug_defaults_drv = {
858 .disable_dmcu = true,
859 .force_abm_enable = false,
860 .timing_trace = false,
862 .disable_pplib_clock_request = false,
863 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
864 .force_single_disp_pipe_split = false,
865 .disable_dcc = DCC_ENABLE,
867 .performance_trace = false,
868 .max_downscale_src_width = 4096,/*upto true 4K*/
869 .disable_pplib_wm_range = false,
870 .scl_reset_length10 = true,
871 .sanity_checks = true,
872 .underflow_assert_delay_us = 0xFFFFFFFF,
873 .dwb_fi_phase = -1, // -1 = disable,
874 .dmub_command_table = true,
875 .pstate_enabled = true,
877 .enable_mem_low_power = {
881 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
891 .enable_legacy_fast_update = true,
892 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
893 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
896 static const struct dc_panel_config panel_config_defaults = {
898 .disable_psr = false,
899 .disallow_psrsu = false,
900 .disallow_replay = false,
903 .optimize_edp_link_rate = true,
907 static void dcn31_dpp_destroy(struct dpp **dpp)
909 kfree(TO_DCN20_DPP(*dpp));
913 static struct dpp *dcn31_dpp_create(
914 struct dc_context *ctx,
917 struct dcn3_dpp *dpp =
918 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
923 if (dpp3_construct(dpp, ctx, inst,
924 &dpp_regs[inst], &tf_shift, &tf_mask))
932 static struct output_pixel_processor *dcn31_opp_create(
933 struct dc_context *ctx, uint32_t inst)
935 struct dcn20_opp *opp =
936 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
943 dcn20_opp_construct(opp, ctx, inst,
944 &opp_regs[inst], &opp_shift, &opp_mask);
948 static struct dce_aux *dcn31_aux_engine_create(
949 struct dc_context *ctx,
952 struct aux_engine_dce110 *aux_engine =
953 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
958 dce110_aux_engine_construct(aux_engine, ctx, inst,
959 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
960 &aux_engine_regs[inst],
963 ctx->dc->caps.extended_aux_timeout_support);
965 return &aux_engine->base;
967 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
969 static const struct dce_i2c_registers i2c_hw_regs[] = {
977 static const struct dce_i2c_shift i2c_shifts = {
978 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
981 static const struct dce_i2c_mask i2c_masks = {
982 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
985 static struct dce_i2c_hw *dcn31_i2c_hw_create(
986 struct dc_context *ctx,
989 struct dce_i2c_hw *dce_i2c_hw =
990 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
995 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
996 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1000 static struct mpc *dcn31_mpc_create(
1001 struct dc_context *ctx,
1005 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1011 dcn30_mpc_construct(mpc30, ctx,
1018 return &mpc30->base;
1021 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1025 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1031 hubbub31_construct(hubbub3, ctx,
1035 dcn3_1_ip.det_buffer_size_kbytes,
1036 dcn3_1_ip.pixel_chunk_size_kbytes,
1037 dcn3_1_ip.config_return_buffer_size_in_kbytes);
1040 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1041 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1045 vmid->regs = &vmid_regs[i];
1046 vmid->shifts = &vmid_shifts;
1047 vmid->masks = &vmid_masks;
1050 return &hubbub3->base;
1053 static struct timing_generator *dcn31_timing_generator_create(
1054 struct dc_context *ctx,
1057 struct optc *tgn10 =
1058 kzalloc(sizeof(struct optc), GFP_KERNEL);
1063 tgn10->base.inst = instance;
1064 tgn10->base.ctx = ctx;
1066 tgn10->tg_regs = &optc_regs[instance];
1067 tgn10->tg_shift = &optc_shift;
1068 tgn10->tg_mask = &optc_mask;
1070 dcn31_timing_generator_init(tgn10);
1072 return &tgn10->base;
1075 static const struct encoder_feature_support link_enc_feature = {
1076 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1077 .max_hdmi_pixel_clock = 600000,
1078 .hdmi_ycbcr420_supported = true,
1079 .dp_ycbcr420_supported = true,
1080 .fec_supported = true,
1081 .flags.bits.IS_HBR2_CAPABLE = true,
1082 .flags.bits.IS_HBR3_CAPABLE = true,
1083 .flags.bits.IS_TPS3_CAPABLE = true,
1084 .flags.bits.IS_TPS4_CAPABLE = true
1087 static struct link_encoder *dcn31_link_encoder_create(
1088 struct dc_context *ctx,
1089 const struct encoder_init_data *enc_init_data)
1091 struct dcn20_link_encoder *enc20 =
1092 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1097 dcn31_link_encoder_construct(enc20,
1100 &link_enc_regs[enc_init_data->transmitter],
1101 &link_enc_aux_regs[enc_init_data->channel - 1],
1102 &link_enc_hpd_regs[enc_init_data->hpd_source],
1106 return &enc20->enc10.base;
1109 /* Create a minimal link encoder object not associated with a particular
1110 * physical connector.
1111 * resource_funcs.link_enc_create_minimal
1113 static struct link_encoder *dcn31_link_enc_create_minimal(
1114 struct dc_context *ctx, enum engine_id eng_id)
1116 struct dcn20_link_encoder *enc20;
1118 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1121 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1125 dcn31_link_encoder_construct_minimal(
1129 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1132 return &enc20->enc10.base;
1135 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1137 struct dcn31_panel_cntl *panel_cntl =
1138 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1143 dcn31_panel_cntl_construct(panel_cntl, init_data);
1145 return &panel_cntl->base;
1148 static void read_dce_straps(
1149 struct dc_context *ctx,
1150 struct resource_straps *straps)
1152 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1153 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1157 static struct audio *dcn31_create_audio(
1158 struct dc_context *ctx, unsigned int inst)
1160 return dce_audio_create(ctx, inst,
1161 &audio_regs[inst], &audio_shift, &audio_mask);
1164 static struct vpg *dcn31_vpg_create(
1165 struct dc_context *ctx,
1168 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1173 vpg31_construct(vpg31, ctx, inst,
1178 return &vpg31->base;
1181 static struct afmt *dcn31_afmt_create(
1182 struct dc_context *ctx,
1185 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1190 afmt31_construct(afmt31, ctx, inst,
1195 // Light sleep by default, no need to power down here
1197 return &afmt31->base;
1200 static struct apg *dcn31_apg_create(
1201 struct dc_context *ctx,
1204 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1209 apg31_construct(apg31, ctx, inst,
1214 return &apg31->base;
1217 static struct stream_encoder *dcn31_stream_encoder_create(
1218 enum engine_id eng_id,
1219 struct dc_context *ctx)
1221 struct dcn10_stream_encoder *enc1;
1227 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1228 if (eng_id <= ENGINE_ID_DIGF) {
1234 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1235 vpg = dcn31_vpg_create(ctx, vpg_inst);
1236 afmt = dcn31_afmt_create(ctx, afmt_inst);
1238 if (!enc1 || !vpg || !afmt) {
1245 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1247 &stream_enc_regs[eng_id],
1248 &se_shift, &se_mask);
1253 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1254 enum engine_id eng_id,
1255 struct dc_context *ctx)
1257 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1260 uint32_t hpo_dp_inst;
1264 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1265 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1267 /* Mapping of VPG register blocks to HPO DP block instance:
1268 * VPG[6] -> HPO_DP[0]
1269 * VPG[7] -> HPO_DP[1]
1270 * VPG[8] -> HPO_DP[2]
1271 * VPG[9] -> HPO_DP[3]
1273 vpg_inst = hpo_dp_inst + 6;
1275 /* Mapping of APG register blocks to HPO DP block instance:
1276 * APG[0] -> HPO_DP[0]
1277 * APG[1] -> HPO_DP[1]
1278 * APG[2] -> HPO_DP[2]
1279 * APG[3] -> HPO_DP[3]
1281 apg_inst = hpo_dp_inst;
1283 /* allocate HPO stream encoder and create VPG sub-block */
1284 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1285 vpg = dcn31_vpg_create(ctx, vpg_inst);
1286 apg = dcn31_apg_create(ctx, apg_inst);
1288 if (!hpo_dp_enc31 || !vpg || !apg) {
1289 kfree(hpo_dp_enc31);
1295 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1296 hpo_dp_inst, eng_id, vpg, apg,
1297 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1298 &hpo_dp_se_shift, &hpo_dp_se_mask);
1300 return &hpo_dp_enc31->base;
1303 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1305 struct dc_context *ctx)
1307 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1309 /* allocate HPO link encoder */
1310 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1312 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1313 &hpo_dp_link_enc_regs[inst],
1314 &hpo_dp_le_shift, &hpo_dp_le_mask);
1316 return &hpo_dp_enc31->base;
1319 static struct dce_hwseq *dcn31_hwseq_create(
1320 struct dc_context *ctx)
1322 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1326 hws->regs = &hwseq_reg;
1327 hws->shifts = &hwseq_shift;
1328 hws->masks = &hwseq_mask;
1332 static const struct resource_create_funcs res_create_funcs = {
1333 .read_dce_straps = read_dce_straps,
1334 .create_audio = dcn31_create_audio,
1335 .create_stream_encoder = dcn31_stream_encoder_create,
1336 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1337 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1338 .create_hwseq = dcn31_hwseq_create,
1341 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1345 for (i = 0; i < pool->base.stream_enc_count; i++) {
1346 if (pool->base.stream_enc[i] != NULL) {
1347 if (pool->base.stream_enc[i]->vpg != NULL) {
1348 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1349 pool->base.stream_enc[i]->vpg = NULL;
1351 if (pool->base.stream_enc[i]->afmt != NULL) {
1352 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1353 pool->base.stream_enc[i]->afmt = NULL;
1355 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1356 pool->base.stream_enc[i] = NULL;
1360 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1361 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1362 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1363 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1364 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1366 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1367 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1368 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1370 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1371 pool->base.hpo_dp_stream_enc[i] = NULL;
1375 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1376 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1377 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1378 pool->base.hpo_dp_link_enc[i] = NULL;
1382 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1383 if (pool->base.dscs[i] != NULL)
1384 dcn20_dsc_destroy(&pool->base.dscs[i]);
1387 if (pool->base.mpc != NULL) {
1388 kfree(TO_DCN20_MPC(pool->base.mpc));
1389 pool->base.mpc = NULL;
1391 if (pool->base.hubbub != NULL) {
1392 kfree(pool->base.hubbub);
1393 pool->base.hubbub = NULL;
1395 for (i = 0; i < pool->base.pipe_count; i++) {
1396 if (pool->base.dpps[i] != NULL)
1397 dcn31_dpp_destroy(&pool->base.dpps[i]);
1399 if (pool->base.ipps[i] != NULL)
1400 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1402 if (pool->base.hubps[i] != NULL) {
1403 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1404 pool->base.hubps[i] = NULL;
1407 if (pool->base.irqs != NULL) {
1408 dal_irq_service_destroy(&pool->base.irqs);
1412 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1413 if (pool->base.engines[i] != NULL)
1414 dce110_engine_destroy(&pool->base.engines[i]);
1415 if (pool->base.hw_i2cs[i] != NULL) {
1416 kfree(pool->base.hw_i2cs[i]);
1417 pool->base.hw_i2cs[i] = NULL;
1419 if (pool->base.sw_i2cs[i] != NULL) {
1420 kfree(pool->base.sw_i2cs[i]);
1421 pool->base.sw_i2cs[i] = NULL;
1425 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1426 if (pool->base.opps[i] != NULL)
1427 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1430 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1431 if (pool->base.timing_generators[i] != NULL) {
1432 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1433 pool->base.timing_generators[i] = NULL;
1437 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1438 if (pool->base.dwbc[i] != NULL) {
1439 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1440 pool->base.dwbc[i] = NULL;
1442 if (pool->base.mcif_wb[i] != NULL) {
1443 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1444 pool->base.mcif_wb[i] = NULL;
1448 for (i = 0; i < pool->base.audio_count; i++) {
1449 if (pool->base.audios[i])
1450 dce_aud_destroy(&pool->base.audios[i]);
1453 for (i = 0; i < pool->base.clk_src_count; i++) {
1454 if (pool->base.clock_sources[i] != NULL) {
1455 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1456 pool->base.clock_sources[i] = NULL;
1460 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1461 if (pool->base.mpc_lut[i] != NULL) {
1462 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1463 pool->base.mpc_lut[i] = NULL;
1465 if (pool->base.mpc_shaper[i] != NULL) {
1466 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1467 pool->base.mpc_shaper[i] = NULL;
1471 if (pool->base.dp_clock_source != NULL) {
1472 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1473 pool->base.dp_clock_source = NULL;
1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1477 if (pool->base.multiple_abms[i] != NULL)
1478 dce_abm_destroy(&pool->base.multiple_abms[i]);
1481 if (pool->base.psr != NULL)
1482 dmub_psr_destroy(&pool->base.psr);
1484 if (pool->base.replay != NULL)
1485 dmub_replay_destroy(&pool->base.replay);
1487 if (pool->base.dccg != NULL)
1488 dcn_dccg_destroy(&pool->base.dccg);
1491 static struct hubp *dcn31_hubp_create(
1492 struct dc_context *ctx,
1495 struct dcn20_hubp *hubp2 =
1496 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1501 if (hubp31_construct(hubp2, ctx, inst,
1502 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1503 return &hubp2->base;
1505 BREAK_TO_DEBUGGER();
1510 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1513 uint32_t pipe_count = pool->res_cap->num_dwb;
1515 for (i = 0; i < pipe_count; i++) {
1516 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1520 dm_error("DC: failed to create dwbc30!\n");
1524 dcn30_dwbc_construct(dwbc30, ctx,
1530 pool->dwbc[i] = &dwbc30->base;
1535 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1538 uint32_t pipe_count = pool->res_cap->num_dwb;
1540 for (i = 0; i < pipe_count; i++) {
1541 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1545 dm_error("DC: failed to create mcif_wb30!\n");
1549 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1555 pool->mcif_wb[i] = &mcif_wb30->base;
1560 static struct display_stream_compressor *dcn31_dsc_create(
1561 struct dc_context *ctx, uint32_t inst)
1563 struct dcn20_dsc *dsc =
1564 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1567 BREAK_TO_DEBUGGER();
1571 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1575 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1577 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1579 dcn31_resource_destruct(dcn31_pool);
1584 static struct clock_source *dcn31_clock_source_create(
1585 struct dc_context *ctx,
1586 struct dc_bios *bios,
1587 enum clock_source_id id,
1588 const struct dce110_clk_src_regs *regs,
1591 struct dce110_clk_src *clk_src =
1592 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1597 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1598 regs, &cs_shift, &cs_mask)) {
1599 clk_src->base.dp_clk_src = dp_clk_src;
1600 return &clk_src->base;
1604 BREAK_TO_DEBUGGER();
1608 static bool is_dual_plane(enum surface_pixel_format format)
1610 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1613 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
1614 struct dc_state *context,
1615 display_e2e_pipe_params_st *pipes,
1621 dc_assert_fp_enabled();
1623 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1625 for (i = 0; i < pipe_cnt; i++) {
1626 pipes[i].pipe.src.gpuvm = 1;
1627 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {
1628 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1629 pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;
1630 } else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
1631 pipes[i].pipe.src.hostvm = false;
1632 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
1633 pipes[i].pipe.src.hostvm = true;
1638 int dcn31_populate_dml_pipes_from_context(
1639 struct dc *dc, struct dc_state *context,
1640 display_e2e_pipe_params_st *pipes,
1644 struct resource_context *res_ctx = &context->res_ctx;
1645 struct pipe_ctx *pipe;
1646 bool upscaled = false;
1649 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1652 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1653 struct dc_crtc_timing *timing;
1655 if (!res_ctx->pipe_ctx[i].stream)
1657 pipe = &res_ctx->pipe_ctx[i];
1658 timing = &pipe->stream->timing;
1659 if (pipe->plane_state &&
1660 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1661 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1665 * Immediate flip can be set dynamically after enabling the plane.
1666 * We need to require support for immediate flip or underflow can be
1667 * intermittently experienced depending on peak b/w requirements.
1669 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1670 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1671 pipes[pipe_cnt].pipe.src.gpuvm = true;
1672 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1673 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1674 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1676 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1680 if (pipes[pipe_cnt].dout.dsc_enable) {
1681 switch (timing->display_color_depth) {
1682 case COLOR_DEPTH_888:
1683 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1685 case COLOR_DEPTH_101010:
1686 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1688 case COLOR_DEPTH_121212:
1689 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1699 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1700 dc->config.enable_4to1MPC = false;
1701 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1702 if (is_dual_plane(pipe->plane_state->format)
1703 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1704 dc->config.enable_4to1MPC = true;
1705 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1706 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1707 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1708 pipes[0].pipe.src.unbounded_req_mode = true;
1710 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1711 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1712 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1713 } else if (context->stream_count >= 3 && upscaled) {
1714 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1720 void dcn31_calculate_wm_and_dlg(
1721 struct dc *dc, struct dc_state *context,
1722 display_e2e_pipe_params_st *pipes,
1727 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1732 dcn31_populate_dml_writeback_from_context(struct dc *dc,
1733 struct resource_context *res_ctx,
1734 display_e2e_pipe_params_st *pipes)
1737 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1742 dcn31_set_mcif_arb_params(struct dc *dc,
1743 struct dc_state *context,
1744 display_e2e_pipe_params_st *pipes,
1748 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1752 bool dcn31_validate_bandwidth(struct dc *dc,
1753 struct dc_state *context,
1758 BW_VAL_TRACE_SETUP();
1762 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1763 DC_LOGGER_INIT(dc->ctx->logger);
1765 BW_VAL_TRACE_COUNT();
1768 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
1771 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
1773 fast_validate = false;
1778 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1780 if (fast_validate) {
1781 BW_VAL_TRACE_SKIP(fast);
1784 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1785 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1787 BW_VAL_TRACE_END_WATERMARKS();
1792 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1793 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1795 BW_VAL_TRACE_SKIP(fail);
1801 BW_VAL_TRACE_FINISH();
1806 static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config)
1808 *panel_config = panel_config_defaults;
1811 static struct dc_cap_funcs cap_funcs = {
1812 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1815 static struct resource_funcs dcn31_res_pool_funcs = {
1816 .destroy = dcn31_destroy_resource_pool,
1817 .link_enc_create = dcn31_link_encoder_create,
1818 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1819 .link_encs_assign = link_enc_cfg_link_encs_assign,
1820 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1821 .panel_cntl_create = dcn31_panel_cntl_create,
1822 .validate_bandwidth = dcn31_validate_bandwidth,
1823 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1824 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1825 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1826 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1827 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1828 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1829 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1830 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1831 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1832 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1833 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1834 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1835 .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1836 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1837 .get_panel_config_defaults = dcn31_get_panel_config_defaults,
1840 static struct clock_source *dcn30_clock_source_create(
1841 struct dc_context *ctx,
1842 struct dc_bios *bios,
1843 enum clock_source_id id,
1844 const struct dce110_clk_src_regs *regs,
1847 struct dce110_clk_src *clk_src =
1848 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1853 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1854 regs, &cs_shift, &cs_mask)) {
1855 clk_src->base.dp_clk_src = dp_clk_src;
1856 return &clk_src->base;
1859 BREAK_TO_DEBUGGER();
1863 static bool dcn31_resource_construct(
1864 uint8_t num_virtual_links,
1866 struct dcn31_resource_pool *pool)
1869 struct dc_context *ctx = dc->ctx;
1870 struct irq_service_init_data init_data;
1872 ctx->dc_bios->regs = &bios_regs;
1874 pool->base.res_cap = &res_cap_dcn31;
1876 pool->base.funcs = &dcn31_res_pool_funcs;
1878 /*************************************************
1879 * Resource + asic cap harcoding *
1880 *************************************************/
1881 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1882 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1883 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1884 dc->caps.max_downscale_ratio = 600;
1885 dc->caps.i2c_speed_in_khz = 100;
1886 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1887 dc->caps.max_cursor_size = 256;
1888 dc->caps.min_horizontal_blanking_period = 80;
1889 dc->caps.dmdata_alloc_size = 2048;
1891 dc->caps.max_slave_planes = 2;
1892 dc->caps.max_slave_yuv_planes = 2;
1893 dc->caps.max_slave_rgb_planes = 2;
1894 dc->caps.post_blend_color_processing = true;
1895 dc->caps.force_dp_tps4_for_cp2520 = true;
1896 if (dc->config.forceHBR2CP2520)
1897 dc->caps.force_dp_tps4_for_cp2520 = false;
1898 dc->caps.dp_hpo = true;
1899 dc->caps.dp_hdmi21_pcon_support = true;
1900 dc->caps.edp_dsc_support = true;
1901 dc->caps.extended_aux_timeout_support = true;
1902 dc->caps.dmcub_support = true;
1903 dc->caps.is_apu = true;
1904 dc->caps.zstate_support = true;
1906 /* Color pipeline capabilities */
1907 dc->caps.color.dpp.dcn_arch = 1;
1908 dc->caps.color.dpp.input_lut_shared = 0;
1909 dc->caps.color.dpp.icsc = 1;
1910 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1911 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1912 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1913 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1914 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1915 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1916 dc->caps.color.dpp.post_csc = 1;
1917 dc->caps.color.dpp.gamma_corr = 1;
1918 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1920 dc->caps.color.dpp.hw_3d_lut = 1;
1921 dc->caps.color.dpp.ogam_ram = 1;
1922 // no OGAM ROM on DCN301
1923 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1924 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1925 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1926 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1927 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1928 dc->caps.color.dpp.ocsc = 0;
1930 dc->caps.color.mpc.gamut_remap = 1;
1931 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1932 dc->caps.color.mpc.ogam_ram = 1;
1933 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1934 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1935 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1936 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1937 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1938 dc->caps.color.mpc.ocsc = 1;
1940 dc->config.use_old_fixed_vs_sequence = true;
1942 /* Use pipe context based otg sync logic */
1943 dc->config.use_pipe_ctx_sync_logic = true;
1945 /* read VBIOS LTTPR caps */
1947 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1948 enum bp_result bp_query_result;
1949 uint8_t is_vbios_lttpr_enable = 0;
1951 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1952 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1955 /* interop bit is implicit */
1957 dc->caps.vbios_lttpr_aware = true;
1961 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1962 dc->debug = debug_defaults_drv;
1964 // Init the vm_helper
1966 vm_helper_init(dc->vm_helper, 16);
1968 /*************************************************
1969 * Create resources *
1970 *************************************************/
1972 /* Clock Sources for Pixel Clock*/
1973 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1974 dcn30_clock_source_create(ctx, ctx->dc_bios,
1975 CLOCK_SOURCE_COMBO_PHY_PLL0,
1976 &clk_src_regs[0], false);
1977 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1978 dcn30_clock_source_create(ctx, ctx->dc_bios,
1979 CLOCK_SOURCE_COMBO_PHY_PLL1,
1980 &clk_src_regs[1], false);
1981 /*move phypllx_pixclk_resync to dmub next*/
1982 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1983 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1984 dcn30_clock_source_create(ctx, ctx->dc_bios,
1985 CLOCK_SOURCE_COMBO_PHY_PLL2,
1986 &clk_src_regs_b0[2], false);
1987 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1988 dcn30_clock_source_create(ctx, ctx->dc_bios,
1989 CLOCK_SOURCE_COMBO_PHY_PLL3,
1990 &clk_src_regs_b0[3], false);
1992 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1993 dcn30_clock_source_create(ctx, ctx->dc_bios,
1994 CLOCK_SOURCE_COMBO_PHY_PLL2,
1995 &clk_src_regs[2], false);
1996 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1997 dcn30_clock_source_create(ctx, ctx->dc_bios,
1998 CLOCK_SOURCE_COMBO_PHY_PLL3,
1999 &clk_src_regs[3], false);
2002 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2003 dcn30_clock_source_create(ctx, ctx->dc_bios,
2004 CLOCK_SOURCE_COMBO_PHY_PLL4,
2005 &clk_src_regs[4], false);
2007 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2009 /* todo: not reuse phy_pll registers */
2010 pool->base.dp_clock_source =
2011 dcn31_clock_source_create(ctx, ctx->dc_bios,
2012 CLOCK_SOURCE_ID_DP_DTO,
2013 &clk_src_regs[0], true);
2015 for (i = 0; i < pool->base.clk_src_count; i++) {
2016 if (pool->base.clock_sources[i] == NULL) {
2017 dm_error("DC: failed to create clock sources!\n");
2018 BREAK_TO_DEBUGGER();
2024 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2025 if (pool->base.dccg == NULL) {
2026 dm_error("DC: failed to create dccg!\n");
2027 BREAK_TO_DEBUGGER();
2032 init_data.ctx = dc->ctx;
2033 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2034 if (!pool->base.irqs)
2038 pool->base.hubbub = dcn31_hubbub_create(ctx);
2039 if (pool->base.hubbub == NULL) {
2040 BREAK_TO_DEBUGGER();
2041 dm_error("DC: failed to create hubbub!\n");
2045 /* HUBPs, DPPs, OPPs and TGs */
2046 for (i = 0; i < pool->base.pipe_count; i++) {
2047 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2048 if (pool->base.hubps[i] == NULL) {
2049 BREAK_TO_DEBUGGER();
2051 "DC: failed to create hubps!\n");
2055 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2056 if (pool->base.dpps[i] == NULL) {
2057 BREAK_TO_DEBUGGER();
2059 "DC: failed to create dpps!\n");
2064 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2065 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2066 if (pool->base.opps[i] == NULL) {
2067 BREAK_TO_DEBUGGER();
2069 "DC: failed to create output pixel processor!\n");
2074 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2075 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2077 if (pool->base.timing_generators[i] == NULL) {
2078 BREAK_TO_DEBUGGER();
2079 dm_error("DC: failed to create tg!\n");
2083 pool->base.timing_generator_count = i;
2086 pool->base.psr = dmub_psr_create(ctx);
2087 if (pool->base.psr == NULL) {
2088 dm_error("DC: failed to create psr obj!\n");
2089 BREAK_TO_DEBUGGER();
2094 pool->base.replay = dmub_replay_create(ctx);
2095 if (pool->base.replay == NULL) {
2096 dm_error("DC: failed to create replay obj!\n");
2097 BREAK_TO_DEBUGGER();
2102 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2103 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2107 if (pool->base.multiple_abms[i] == NULL) {
2108 dm_error("DC: failed to create abm for pipe %d!\n", i);
2109 BREAK_TO_DEBUGGER();
2115 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2116 if (pool->base.mpc == NULL) {
2117 BREAK_TO_DEBUGGER();
2118 dm_error("DC: failed to create mpc!\n");
2122 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2123 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2124 if (pool->base.dscs[i] == NULL) {
2125 BREAK_TO_DEBUGGER();
2126 dm_error("DC: failed to create display stream compressor %d!\n", i);
2131 /* DWB and MMHUBBUB */
2132 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2133 BREAK_TO_DEBUGGER();
2134 dm_error("DC: failed to create dwbc!\n");
2138 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2139 BREAK_TO_DEBUGGER();
2140 dm_error("DC: failed to create mcif_wb!\n");
2145 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2146 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2147 if (pool->base.engines[i] == NULL) {
2148 BREAK_TO_DEBUGGER();
2150 "DC:failed to create aux engine!!\n");
2153 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2154 if (pool->base.hw_i2cs[i] == NULL) {
2155 BREAK_TO_DEBUGGER();
2157 "DC:failed to create hw i2c!!\n");
2160 pool->base.sw_i2cs[i] = NULL;
2163 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2164 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2165 !dc->debug.dpia_debug.bits.disable_dpia) {
2166 /* YELLOW CARP B0 has 4 DPIA's */
2167 pool->base.usb4_dpia_count = 4;
2170 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)
2171 pool->base.usb4_dpia_count = 4;
2173 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2174 if (!resource_construct(num_virtual_links, dc, &pool->base,
2178 /* HW Sequencer and Plane caps */
2179 dcn31_hw_sequencer_construct(dc);
2181 dc->caps.max_planes = pool->base.pipe_count;
2183 for (i = 0; i < dc->caps.max_planes; ++i)
2184 dc->caps.planes[i] = plane_cap;
2186 dc->cap_funcs = cap_funcs;
2188 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2193 dcn31_resource_destruct(pool);
2198 struct resource_pool *dcn31_create_resource_pool(
2199 const struct dc_init_data *init_data,
2202 struct dcn31_resource_pool *pool =
2203 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2208 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2211 BREAK_TO_DEBUGGER();