drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn31_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn30/dcn30_hubbub.h"
  41 #include "dcn31/dcn31_hubbub.h"
  42 #include "dcn30/dcn30_mpc.h"
  43 #include "dcn31/dcn31_hubp.h"
  44 #include "irq/dcn31/irq_service_dcn31.h"
  45 #include "dcn30/dcn30_dpp.h"
  46 #include "dcn31/dcn31_optc.h"
  47 #include "dcn20/dcn20_hwseq.h"
  48 #include "dcn30/dcn30_hwseq.h"
  49 #include "dce110/dce110_hw_sequencer.h"
  50 #include "dcn30/dcn30_opp.h"
  51 #include "dcn20/dcn20_dsc.h"
  52 #include "dcn30/dcn30_vpg.h"
  53 #include "dcn30/dcn30_afmt.h"
  54 #include "dcn30/dcn30_dio_stream_encoder.h"
  55 #include "dcn31/dcn31_dio_link_encoder.h"
  56 #include "dce/dce_clock_source.h"
  57 #include "dce/dce_audio.h"
  58 #include "dce/dce_hwseq.h"
  59 #include "clk_mgr.h"
  60 #include "virtual/virtual_stream_encoder.h"
  61 #include "dce110/dce110_resource.h"
  62 #include "dml/display_mode_vba.h"
  63 #include "dcn31/dcn31_dccg.h"
  64 #include "dcn10/dcn10_resource.h"
  65 #include "dcn31_panel_cntl.h"
  66
  67 #include "dcn30/dcn30_dwb.h"
  68 #include "dcn30/dcn30_mmhubbub.h"
  69
  70 // TODO: change include headers /amd/include/asic_reg after upstream
  71 #include "yellow_carp_offset.h"
  72 #include "dcn/dcn_3_1_2_offset.h"
  73 #include "dcn/dcn_3_1_2_sh_mask.h"
  74 #include "nbio/nbio_7_2_0_offset.h"
  75 #include "dpcs/dpcs_4_2_0_offset.h"
  76 #include "dpcs/dpcs_4_2_0_sh_mask.h"
  77 #include "mmhub/mmhub_2_3_0_offset.h"
  78 #include "mmhub/mmhub_2_3_0_sh_mask.h"
  79
  80
  81 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
  82 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
  83 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
  84 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
  85
  86 #include "reg_helper.h"
  87 #include "dce/dmub_abm.h"
  88 #include "dce/dmub_psr.h"
  89 #include "dce/dce_aux.h"
  90 #include "dce/dce_i2c.h"
  91
  92 #include "dml/dcn30/display_mode_vba_30.h"
  93 #include "vm_helper.h"
  94 #include "dcn20/dcn20_vmid.h"
  95
  96 #include "link_enc_cfg.h"
  97
  98 #define DC_LOGGER_INIT(logger)
  99 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
 100 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
 101
 102 #define DCN3_1_DEFAULT_DET_SIZE 384
 103
 104 struct _vcs_dpi_ip_params_st dcn3_1_ip = {
 105         .gpuvm_enable = 1,
 106         .gpuvm_max_page_table_levels = 1,
 107         .hostvm_enable = 1,
 108         .hostvm_max_page_table_levels = 2,
 109         .rob_buffer_size_kbytes = 64,
 110         .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
 111         .config_return_buffer_size_in_kbytes = 1792,
 112         .compressed_buffer_segment_size_in_kbytes = 64,
 113         .meta_fifo_size_in_kentries = 32,
 114         .zero_size_buffer_entries = 512,
 115         .compbuf_reserved_space_64b = 256,
 116         .compbuf_reserved_space_zs = 64,
 117         .dpp_output_buffer_pixels = 2560,
 118         .opp_output_buffer_lines = 1,
 119         .pixel_chunk_size_kbytes = 8,
 120         .meta_chunk_size_kbytes = 2,
 121         .min_meta_chunk_size_bytes = 256,
 122         .writeback_chunk_size_kbytes = 8,
 123         .ptoi_supported = false,
 124         .num_dsc = 3,
 125         .maximum_dsc_bits_per_component = 10,
 126         .dsc422_native_support = false,
 127         .is_line_buffer_bpp_fixed = true,
 128         .line_buffer_fixed_bpp = 48,
 129         .line_buffer_size_bits = 789504,
 130         .max_line_buffer_lines = 12,
 131         .writeback_interface_buffer_size_kbytes = 90,
 132         .max_num_dpp = 4,
 133         .max_num_otg = 4,
 134         .max_num_hdmi_frl_outputs = 1,
 135         .max_num_wb = 1,
 136         .max_dchub_pscl_bw_pix_per_clk = 4,
 137         .max_pscl_lb_bw_pix_per_clk = 2,
 138         .max_lb_vscl_bw_pix_per_clk = 4,
 139         .max_vscl_hscl_bw_pix_per_clk = 4,
 140         .max_hscl_ratio = 6,
 141         .max_vscl_ratio = 6,
 142         .max_hscl_taps = 8,
 143         .max_vscl_taps = 8,
 144         .dpte_buffer_size_in_pte_reqs_luma = 64,
 145         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 146         .dispclk_ramp_margin_percent = 1,
 147         .max_inter_dcn_tile_repeaters = 8,
 148         .cursor_buffer_size = 16,
 149         .cursor_chunk_size = 2,
 150         .writeback_line_buffer_buffer_size = 0,
 151         .writeback_min_hscl_ratio = 1,
 152         .writeback_min_vscl_ratio = 1,
 153         .writeback_max_hscl_ratio = 1,
 154         .writeback_max_vscl_ratio = 1,
 155         .writeback_max_hscl_taps = 1,
 156         .writeback_max_vscl_taps = 1,
 157         .dppclk_delay_subtotal = 46,
 158         .dppclk_delay_scl = 50,
 159         .dppclk_delay_scl_lb_only = 16,
 160         .dppclk_delay_cnvc_formatter = 27,
 161         .dppclk_delay_cnvc_cursor = 6,
 162         .dispclk_delay_subtotal = 119,
 163         .dynamic_metadata_vm_enabled = false,
 164         .odm_combine_4to1_supported = false,
 165         .dcc_supported = true,
 166 };
 167
 168 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
 169                 /*TODO: correct dispclk/dppclk voltage level determination*/
 170         .clock_limits = {
 171                 {
 172                         .state = 0,
 173                         .dispclk_mhz = 1200.0,
 174                         .dppclk_mhz = 1200.0,
 175                         .phyclk_mhz = 600.0,
 176                         .phyclk_d18_mhz = 667.0,
 177                         .dscclk_mhz = 186.0,
 178                         .dtbclk_mhz = 625.0,
 179                 },
 180                 {
 181                         .state = 1,
 182                         .dispclk_mhz = 1200.0,
 183                         .dppclk_mhz = 1200.0,
 184                         .phyclk_mhz = 810.0,
 185                         .phyclk_d18_mhz = 667.0,
 186                         .dscclk_mhz = 209.0,
 187                         .dtbclk_mhz = 625.0,
 188                 },
 189                 {
 190                         .state = 2,
 191                         .dispclk_mhz = 1200.0,
 192                         .dppclk_mhz = 1200.0,
 193                         .phyclk_mhz = 810.0,
 194                         .phyclk_d18_mhz = 667.0,
 195                         .dscclk_mhz = 209.0,
 196                         .dtbclk_mhz = 625.0,
 197                 },
 198                 {
 199                         .state = 3,
 200                         .dispclk_mhz = 1200.0,
 201                         .dppclk_mhz = 1200.0,
 202                         .phyclk_mhz = 810.0,
 203                         .phyclk_d18_mhz = 667.0,
 204                         .dscclk_mhz = 371.0,
 205                         .dtbclk_mhz = 625.0,
 206                 },
 207                 {
 208                         .state = 4,
 209                         .dispclk_mhz = 1200.0,
 210                         .dppclk_mhz = 1200.0,
 211                         .phyclk_mhz = 810.0,
 212                         .phyclk_d18_mhz = 667.0,
 213                         .dscclk_mhz = 417.0,
 214                         .dtbclk_mhz = 625.0,
 215                 },
 216         },
 217         .num_states = 5,
 218         .sr_exit_time_us = 9.0,
 219         .sr_enter_plus_exit_time_us = 11.0,
 220         .sr_exit_z8_time_us = 402.0,
 221         .sr_enter_plus_exit_z8_time_us = 520.0,
 222         .writeback_latency_us = 12.0,
 223         .round_trip_ping_latency_dcfclk_cycles = 106,
 224         .urgent_latency_pixel_data_only_us = 4.0,
 225         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 226         .urgent_latency_vm_data_only_us = 4.0,
 227         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 228         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 229         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 230         .pct_ideal_sdp_bw_after_urgent = 80.0,
 231         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 232         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 233         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 234         .max_avg_sdp_bw_use_normal_percent = 60.0,
 235         .max_avg_dram_bw_use_normal_percent = 60.0,
 236         .fabric_datapath_to_dcn_data_return_bytes = 32,
 237         .return_bus_width_bytes = 64,
 238         .downspread_percent = 0.38,
 239         .dcn_downspread_percent = 0.5,
 240         .gpuvm_min_page_size_bytes = 4096,
 241         .hostvm_min_page_size_bytes = 4096,
 242         .do_urgent_latency_adjustment = false,
 243         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 244         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 245 };
 246
 247 enum dcn31_clk_src_array_id {
 248         DCN31_CLK_SRC_PLL0,
 249         DCN31_CLK_SRC_PLL1,
 250         DCN31_CLK_SRC_PLL2,
 251         DCN31_CLK_SRC_PLL3,
 252         DCN31_CLK_SRC_PLL4,
 253         DCN30_CLK_SRC_TOTAL
 254 };
 255
 256 /* begin *********************
 257  * macros to expend register list macro defined in HW object header file
 258  */
 259
 260 /* DCN */
 261 /* TODO awful hack. fixup dcn20_dwb.h */
 262 #undef BASE_INNER
 263 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 264
 265 #define BASE(seg) BASE_INNER(seg)
 266
 267 #define SR(reg_name)\
 268                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 269                                         reg ## reg_name
 270
 271 #define SRI(reg_name, block, id)\
 272         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 273                                         reg ## block ## id ## _ ## reg_name
 274
 275 #define SRI2(reg_name, block, id)\
 276         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 277                                         reg ## reg_name
 278
 279 #define SRIR(var_name, reg_name, block, id)\
 280         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 281                                         reg ## block ## id ## _ ## reg_name
 282
 283 #define SRII(reg_name, block, id)\
 284         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 285                                         reg ## block ## id ## _ ## reg_name
 286
 287 #define SRII_MPC_RMU(reg_name, block, id)\
 288         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 289                                         reg ## block ## id ## _ ## reg_name
 290
 291 #define SRII_DWB(reg_name, temp_name, block, id)\
 292         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 293                                         reg ## block ## id ## _ ## temp_name
 294
 295 #define DCCG_SRII(reg_name, block, id)\
 296         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 297                                         reg ## block ## id ## _ ## reg_name
 298
 299 #define VUPDATE_SRII(reg_name, block, id)\
 300         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 301                                         reg ## reg_name ## _ ## block ## id
 302
 303 /* NBIO */
 304 #define NBIO_BASE_INNER(seg) \
 305         NBIO_BASE__INST0_SEG ## seg
 306
 307 #define NBIO_BASE(seg) \
 308         NBIO_BASE_INNER(seg)
 309
 310 #define NBIO_SR(reg_name)\
 311                 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 312                                         regBIF_BX1_ ## reg_name
 313
 314 /* MMHUB */
 315 #define MMHUB_BASE_INNER(seg) \
 316         MMHUB_BASE__INST0_SEG ## seg
 317
 318 #define MMHUB_BASE(seg) \
 319         MMHUB_BASE_INNER(seg)
 320
 321 #define MMHUB_SR(reg_name)\
 322                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
 323                                         mm ## reg_name
 324
 325 /* CLOCK */
 326 #define CLK_BASE_INNER(seg) \
 327         CLK_BASE__INST0_SEG ## seg
 328
 329 #define CLK_BASE(seg) \
 330         CLK_BASE_INNER(seg)
 331
 332 #define CLK_SRI(reg_name, block, inst)\
 333         .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 334                                         reg ## block ## _ ## inst ## _ ## reg_name
 335
 336
 337 static const struct bios_registers bios_regs = {
 338                 NBIO_SR(BIOS_SCRATCH_3),
 339                 NBIO_SR(BIOS_SCRATCH_6)
 340 };
 341
 342 #define clk_src_regs(index, pllid)\
 343 [index] = {\
 344         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 345 }
 346
 347 static const struct dce110_clk_src_regs clk_src_regs[] = {
 348         clk_src_regs(0, A),
 349         clk_src_regs(1, B),
 350         clk_src_regs(2, C),
 351         clk_src_regs(3, D),
 352         clk_src_regs(4, E)
 353 };
 354
 355 static const struct dce110_clk_src_shift cs_shift = {
 356                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 357 };
 358
 359 static const struct dce110_clk_src_mask cs_mask = {
 360                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 361 };
 362
 363 #define abm_regs(id)\
 364 [id] = {\
 365                 ABM_DCN301_REG_LIST(id)\
 366 }
 367
 368 static const struct dce_abm_registers abm_regs[] = {
 369                 abm_regs(0),
 370                 abm_regs(1),
 371                 abm_regs(2),
 372                 abm_regs(3),
 373 };
 374
 375 static const struct dce_abm_shift abm_shift = {
 376                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 377 };
 378
 379 static const struct dce_abm_mask abm_mask = {
 380                 ABM_MASK_SH_LIST_DCN30(_MASK)
 381 };
 382
 383 #define audio_regs(id)\
 384 [id] = {\
 385                 AUD_COMMON_REG_LIST(id)\
 386 }
 387
 388 static const struct dce_audio_registers audio_regs[] = {
 389         audio_regs(0),
 390         audio_regs(1),
 391         audio_regs(2),
 392         audio_regs(3),
 393         audio_regs(4),
 394         audio_regs(5),
 395         audio_regs(6)
 396 };
 397
 398 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 399                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 400                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 401                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 402
 403 static const struct dce_audio_shift audio_shift = {
 404                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 405 };
 406
 407 static const struct dce_audio_mask audio_mask = {
 408                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 409 };
 410
 411 #define vpg_regs(id)\
 412 [id] = {\
 413         VPG_DCN3_REG_LIST(id)\
 414 }
 415
 416 static const struct dcn30_vpg_registers vpg_regs[] = {
 417         vpg_regs(0),
 418         vpg_regs(1),
 419         vpg_regs(2),
 420         vpg_regs(3),
 421         vpg_regs(4),
 422         vpg_regs(5),
 423         vpg_regs(6),
 424         vpg_regs(7),
 425         vpg_regs(8),
 426         vpg_regs(9),
 427 };
 428
 429 static const struct dcn30_vpg_shift vpg_shift = {
 430         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 431 };
 432
 433 static const struct dcn30_vpg_mask vpg_mask = {
 434         DCN3_VPG_MASK_SH_LIST(_MASK)
 435 };
 436
 437 #define afmt_regs(id)\
 438 [id] = {\
 439         AFMT_DCN3_REG_LIST(id)\
 440 }
 441
 442 static const struct dcn30_afmt_registers afmt_regs[] = {
 443         afmt_regs(0),
 444         afmt_regs(1),
 445         afmt_regs(2),
 446         afmt_regs(3),
 447         afmt_regs(4),
 448         afmt_regs(5)
 449 };
 450
 451 static const struct dcn30_afmt_shift afmt_shift = {
 452         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 453 };
 454
 455 static const struct dcn30_afmt_mask afmt_mask = {
 456         DCN3_AFMT_MASK_SH_LIST(_MASK)
 457 };
 458
 459 #define stream_enc_regs(id)\
 460 [id] = {\
 461         SE_DCN3_REG_LIST(id)\
 462 }
 463
 464 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 465         stream_enc_regs(0),
 466         stream_enc_regs(1),
 467         stream_enc_regs(2),
 468         stream_enc_regs(3),
 469         stream_enc_regs(4)
 470 };
 471
 472 static const struct dcn10_stream_encoder_shift se_shift = {
 473                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 474 };
 475
 476 static const struct dcn10_stream_encoder_mask se_mask = {
 477                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 478 };
 479
 480
 481 #define aux_regs(id)\
 482 [id] = {\
 483         DCN2_AUX_REG_LIST(id)\
 484 }
 485
 486 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 487                 aux_regs(0),
 488                 aux_regs(1),
 489                 aux_regs(2),
 490                 aux_regs(3),
 491                 aux_regs(4)
 492 };
 493
 494 #define hpd_regs(id)\
 495 [id] = {\
 496         HPD_REG_LIST(id)\
 497 }
 498
 499 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 500                 hpd_regs(0),
 501                 hpd_regs(1),
 502                 hpd_regs(2),
 503                 hpd_regs(3),
 504                 hpd_regs(4)
 505 };
 506
 507 #define link_regs(id, phyid)\
 508 [id] = {\
 509         LE_DCN31_REG_LIST(id), \
 510         UNIPHY_DCN2_REG_LIST(phyid), \
 511         DPCS_DCN31_REG_LIST(id), \
 512 }
 513
 514 static const struct dce110_aux_registers_shift aux_shift = {
 515         DCN_AUX_MASK_SH_LIST(__SHIFT)
 516 };
 517
 518 static const struct dce110_aux_registers_mask aux_mask = {
 519         DCN_AUX_MASK_SH_LIST(_MASK)
 520 };
 521
 522 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 523         link_regs(0, A),
 524         link_regs(1, B),
 525         link_regs(2, C),
 526         link_regs(3, D),
 527         link_regs(4, E)
 528 };
 529
 530 static const struct dcn10_link_enc_shift le_shift = {
 531         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 532         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 533 };
 534
 535 static const struct dcn10_link_enc_mask le_mask = {
 536         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 537         DPCS_DCN31_MASK_SH_LIST(_MASK)
 538 };
 539
 540 #define dpp_regs(id)\
 541 [id] = {\
 542         DPP_REG_LIST_DCN30(id),\
 543 }
 544
 545 static const struct dcn3_dpp_registers dpp_regs[] = {
 546         dpp_regs(0),
 547         dpp_regs(1),
 548         dpp_regs(2),
 549         dpp_regs(3)
 550 };
 551
 552 static const struct dcn3_dpp_shift tf_shift = {
 553                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 554 };
 555
 556 static const struct dcn3_dpp_mask tf_mask = {
 557                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 558 };
 559
 560 #define opp_regs(id)\
 561 [id] = {\
 562         OPP_REG_LIST_DCN30(id),\
 563 }
 564
 565 static const struct dcn20_opp_registers opp_regs[] = {
 566         opp_regs(0),
 567         opp_regs(1),
 568         opp_regs(2),
 569         opp_regs(3)
 570 };
 571
 572 static const struct dcn20_opp_shift opp_shift = {
 573         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 574 };
 575
 576 static const struct dcn20_opp_mask opp_mask = {
 577         OPP_MASK_SH_LIST_DCN20(_MASK)
 578 };
 579
 580 #define aux_engine_regs(id)\
 581 [id] = {\
 582         AUX_COMMON_REG_LIST0(id), \
 583         .AUXN_IMPCAL = 0, \
 584         .AUXP_IMPCAL = 0, \
 585         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 586 }
 587
 588 static const struct dce110_aux_registers aux_engine_regs[] = {
 589                 aux_engine_regs(0),
 590                 aux_engine_regs(1),
 591                 aux_engine_regs(2),
 592                 aux_engine_regs(3),
 593                 aux_engine_regs(4)
 594 };
 595
 596 #define dwbc_regs_dcn3(id)\
 597 [id] = {\
 598         DWBC_COMMON_REG_LIST_DCN30(id),\
 599 }
 600
 601 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 602         dwbc_regs_dcn3(0),
 603 };
 604
 605 static const struct dcn30_dwbc_shift dwbc30_shift = {
 606         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 607 };
 608
 609 static const struct dcn30_dwbc_mask dwbc30_mask = {
 610         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 611 };
 612
 613 #define mcif_wb_regs_dcn3(id)\
 614 [id] = {\
 615         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 616 }
 617
 618 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 619         mcif_wb_regs_dcn3(0)
 620 };
 621
 622 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 623         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 624 };
 625
 626 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 627         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 628 };
 629
 630 #define dsc_regsDCN20(id)\
 631 [id] = {\
 632         DSC_REG_LIST_DCN20(id)\
 633 }
 634
 635 static const struct dcn20_dsc_registers dsc_regs[] = {
 636         dsc_regsDCN20(0),
 637         dsc_regsDCN20(1),
 638         dsc_regsDCN20(2)
 639 };
 640
 641 static const struct dcn20_dsc_shift dsc_shift = {
 642         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 643 };
 644
 645 static const struct dcn20_dsc_mask dsc_mask = {
 646         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 647 };
 648
 649 static const struct dcn30_mpc_registers mpc_regs = {
 650                 MPC_REG_LIST_DCN3_0(0),
 651                 MPC_REG_LIST_DCN3_0(1),
 652                 MPC_REG_LIST_DCN3_0(2),
 653                 MPC_REG_LIST_DCN3_0(3),
 654                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 655                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 656                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 657                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 658                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 659                 MPC_RMU_REG_LIST_DCN3AG(0),
 660                 MPC_RMU_REG_LIST_DCN3AG(1),
 661                 //MPC_RMU_REG_LIST_DCN3AG(2),
 662                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 663 };
 664
 665 static const struct dcn30_mpc_shift mpc_shift = {
 666         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 667 };
 668
 669 static const struct dcn30_mpc_mask mpc_mask = {
 670         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 671 };
 672
 673 #define optc_regs(id)\
 674 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 675
 676 static const struct dcn_optc_registers optc_regs[] = {
 677         optc_regs(0),
 678         optc_regs(1),
 679         optc_regs(2),
 680         optc_regs(3)
 681 };
 682
 683 static const struct dcn_optc_shift optc_shift = {
 684         OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 685 };
 686
 687 static const struct dcn_optc_mask optc_mask = {
 688         OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 689 };
 690
 691 #define hubp_regs(id)\
 692 [id] = {\
 693         HUBP_REG_LIST_DCN30(id)\
 694 }
 695
 696 static const struct dcn_hubp2_registers hubp_regs[] = {
 697                 hubp_regs(0),
 698                 hubp_regs(1),
 699                 hubp_regs(2),
 700                 hubp_regs(3)
 701 };
 702
 703
 704 static const struct dcn_hubp2_shift hubp_shift = {
 705                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 706 };
 707
 708 static const struct dcn_hubp2_mask hubp_mask = {
 709                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 710 };
 711 static const struct dcn_hubbub_registers hubbub_reg = {
 712                 HUBBUB_REG_LIST_DCN31(0)
 713 };
 714
 715 static const struct dcn_hubbub_shift hubbub_shift = {
 716                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 717 };
 718
 719 static const struct dcn_hubbub_mask hubbub_mask = {
 720                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 721 };
 722
 723 static const struct dccg_registers dccg_regs = {
 724                 DCCG_REG_LIST_DCN31()
 725 };
 726
 727 static const struct dccg_shift dccg_shift = {
 728                 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 729 };
 730
 731 static const struct dccg_mask dccg_mask = {
 732                 DCCG_MASK_SH_LIST_DCN31(_MASK)
 733 };
 734
 735
 736 #define SRII2(reg_name_pre, reg_name_post, id)\
 737         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 738                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 739                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 740
 741
 742 #define HWSEQ_DCN31_REG_LIST()\
 743         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 744         SR(DIO_MEM_PWR_CTRL), \
 745         SR(ODM_MEM_PWR_CTRL3), \
 746         SR(DMU_MEM_PWR_CNTL), \
 747         SR(MMHUBBUB_MEM_PWR_CNTL), \
 748         SR(DCCG_GATE_DISABLE_CNTL), \
 749         SR(DCCG_GATE_DISABLE_CNTL2), \
 750         SR(DCFCLK_CNTL),\
 751         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 752         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 753         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 754         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 755         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 756         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 757         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 758         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 759         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 760         SR(MICROSECOND_TIME_BASE_DIV), \
 761         SR(MILLISECOND_TIME_BASE_DIV), \
 762         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 763         SR(RBBMIF_TIMEOUT_DIS), \
 764         SR(RBBMIF_TIMEOUT_DIS_2), \
 765         SR(DCHUBBUB_CRC_CTRL), \
 766         SR(DPP_TOP0_DPP_CRC_CTRL), \
 767         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 768         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 769         SR(MPC_CRC_CTRL), \
 770         SR(MPC_CRC_RESULT_GB), \
 771         SR(MPC_CRC_RESULT_C), \
 772         SR(MPC_CRC_RESULT_AR), \
 773         SR(DOMAIN0_PG_CONFIG), \
 774         SR(DOMAIN1_PG_CONFIG), \
 775         SR(DOMAIN2_PG_CONFIG), \
 776         SR(DOMAIN3_PG_CONFIG), \
 777         SR(DOMAIN16_PG_CONFIG), \
 778         SR(DOMAIN17_PG_CONFIG), \
 779         SR(DOMAIN18_PG_CONFIG), \
 780         SR(DOMAIN0_PG_STATUS), \
 781         SR(DOMAIN1_PG_STATUS), \
 782         SR(DOMAIN2_PG_STATUS), \
 783         SR(DOMAIN3_PG_STATUS), \
 784         SR(DOMAIN16_PG_STATUS), \
 785         SR(DOMAIN17_PG_STATUS), \
 786         SR(DOMAIN18_PG_STATUS), \
 787         SR(D1VGA_CONTROL), \
 788         SR(D2VGA_CONTROL), \
 789         SR(D3VGA_CONTROL), \
 790         SR(D4VGA_CONTROL), \
 791         SR(D5VGA_CONTROL), \
 792         SR(D6VGA_CONTROL), \
 793         SR(DC_IP_REQUEST_CNTL), \
 794         SR(AZALIA_AUDIO_DTO), \
 795         SR(AZALIA_CONTROLLER_CLOCK_GATING)
 796
 797 static const struct dce_hwseq_registers hwseq_reg = {
 798                 HWSEQ_DCN31_REG_LIST()
 799 };
 800
 801 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 802         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 803         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 804         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 805         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 806         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 807         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 808         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 809         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 810         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 811         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 812         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 813         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 814         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 815         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 816         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 817         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 818         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 819         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 820         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 821         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 822         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 823         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 824         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 825         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 826         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 827         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 828         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 829         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 830         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 831         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
 832
 833 static const struct dce_hwseq_shift hwseq_shift = {
 834                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 835 };
 836
 837 static const struct dce_hwseq_mask hwseq_mask = {
 838                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 839 };
 840 #define vmid_regs(id)\
 841 [id] = {\
 842                 DCN20_VMID_REG_LIST(id)\
 843 }
 844
 845 static const struct dcn_vmid_registers vmid_regs[] = {
 846         vmid_regs(0),
 847         vmid_regs(1),
 848         vmid_regs(2),
 849         vmid_regs(3),
 850         vmid_regs(4),
 851         vmid_regs(5),
 852         vmid_regs(6),
 853         vmid_regs(7),
 854         vmid_regs(8),
 855         vmid_regs(9),
 856         vmid_regs(10),
 857         vmid_regs(11),
 858         vmid_regs(12),
 859         vmid_regs(13),
 860         vmid_regs(14),
 861         vmid_regs(15)
 862 };
 863
 864 static const struct dcn20_vmid_shift vmid_shifts = {
 865                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 866 };
 867
 868 static const struct dcn20_vmid_mask vmid_masks = {
 869                 DCN20_VMID_MASK_SH_LIST(_MASK)
 870 };
 871
 872 static const struct resource_caps res_cap_dcn31 = {
 873         .num_timing_generator = 4,
 874         .num_opp = 4,
 875         .num_video_plane = 4,
 876         .num_audio = 5,
 877         .num_stream_encoder = 5,
 878         .num_dig_link_enc = 5,
 879         .num_pll = 5,
 880         .num_dwb = 1,
 881         .num_ddc = 5,
 882         .num_vmid = 16,
 883         .num_mpc_3dlut = 2,
 884         .num_dsc = 3,
 885 };
 886
 887 static const struct dc_plane_cap plane_cap = {
 888         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 889         .blends_with_above = true,
 890         .blends_with_below = true,
 891         .per_pixel_alpha = true,
 892
 893         .pixel_format_support = {
 894                         .argb8888 = true,
 895                         .nv12 = true,
 896                         .fp16 = true,
 897                         .p010 = false,
 898                         .ayuv = false,
 899         },
 900
 901         .max_upscale_factor = {
 902                         .argb8888 = 16000,
 903                         .nv12 = 16000,
 904                         .fp16 = 16000
 905         },
 906
 907         // 6:1 downscaling ratio: 1000/6 = 166.666
 908         .max_downscale_factor = {
 909                         .argb8888 = 167,
 910                         .nv12 = 167,
 911                         .fp16 = 167
 912         },
 913         64,
 914         64
 915 };
 916
 917 static const struct dc_debug_options debug_defaults_drv = {
 918         .disable_dmcu = true,
 919         .force_abm_enable = false,
 920         .timing_trace = false,
 921         .clock_trace = true,
 922         .disable_pplib_clock_request = false,
 923         .pipe_split_policy = MPC_SPLIT_AVOID,
 924         .force_single_disp_pipe_split = false,
 925         .disable_dcc = DCC_ENABLE,
 926         .vsr_support = true,
 927         .performance_trace = false,
 928         .max_downscale_src_width = 7680,/*upto 8K*/
 929         .disable_pplib_wm_range = false,
 930         .scl_reset_length10 = true,
 931         .sanity_checks = false,
 932         .underflow_assert_delay_us = 0xFFFFFFFF,
 933         .dwb_fi_phase = -1, // -1 = disable,
 934         .dmub_command_table = true,
 935         .pstate_enabled = true,
 936         .use_max_lb = true,
 937         .enable_mem_low_power = {
 938                 .bits = {
 939                         .vga = false,
 940                         .i2c = false,
 941                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 942                         .dscl = false,
 943                         .cm = false,
 944                         .mpc = false,
 945                         .optc = false,
 946                 }
 947         },
 948         .optimize_edp_link_rate = true,
 949         .enable_sw_cntl_psr = true,
 950 };
 951
 952 static const struct dc_debug_options debug_defaults_diags = {
 953         .disable_dmcu = true,
 954         .force_abm_enable = false,
 955         .timing_trace = true,
 956         .clock_trace = true,
 957         .disable_dpp_power_gate = true,
 958         .disable_hubp_power_gate = true,
 959         .disable_clock_gate = true,
 960         .disable_pplib_clock_request = true,
 961         .disable_pplib_wm_range = true,
 962         .disable_stutter = false,
 963         .scl_reset_length10 = true,
 964         .dwb_fi_phase = -1, // -1 = disable
 965         .dmub_command_table = true,
 966         .enable_tri_buf = true,
 967         .use_max_lb = true
 968 };
 969
 970 static void dcn31_dpp_destroy(struct dpp **dpp)
 971 {
 972         kfree(TO_DCN20_DPP(*dpp));
 973         *dpp = NULL;
 974 }
 975
 976 static struct dpp *dcn31_dpp_create(
 977         struct dc_context *ctx,
 978         uint32_t inst)
 979 {
 980         struct dcn3_dpp *dpp =
 981                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 982
 983         if (!dpp)
 984                 return NULL;
 985
 986         if (dpp3_construct(dpp, ctx, inst,
 987                         &dpp_regs[inst], &tf_shift, &tf_mask))
 988                 return &dpp->base;
 989
 990         BREAK_TO_DEBUGGER();
 991         kfree(dpp);
 992         return NULL;
 993 }
 994
 995 static struct output_pixel_processor *dcn31_opp_create(
 996         struct dc_context *ctx, uint32_t inst)
 997 {
 998         struct dcn20_opp *opp =
 999                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1000
1001         if (!opp) {
1002                 BREAK_TO_DEBUGGER();
1003                 return NULL;
1004         }
1005
1006         dcn20_opp_construct(opp, ctx, inst,
1007                         &opp_regs[inst], &opp_shift, &opp_mask);
1008         return &opp->base;
1009 }
1010
1011 static struct dce_aux *dcn31_aux_engine_create(
1012         struct dc_context *ctx,
1013         uint32_t inst)
1014 {
1015         struct aux_engine_dce110 *aux_engine =
1016                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1017
1018         if (!aux_engine)
1019                 return NULL;
1020
1021         dce110_aux_engine_construct(aux_engine, ctx, inst,
1022                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1023                                     &aux_engine_regs[inst],
1024                                         &aux_mask,
1025                                         &aux_shift,
1026                                         ctx->dc->caps.extended_aux_timeout_support);
1027
1028         return &aux_engine->base;
1029 }
1030 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1031
1032 static const struct dce_i2c_registers i2c_hw_regs[] = {
1033                 i2c_inst_regs(1),
1034                 i2c_inst_regs(2),
1035                 i2c_inst_regs(3),
1036                 i2c_inst_regs(4),
1037                 i2c_inst_regs(5),
1038 };
1039
1040 static const struct dce_i2c_shift i2c_shifts = {
1041                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1042 };
1043
1044 static const struct dce_i2c_mask i2c_masks = {
1045                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1046 };
1047
1048 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1049         struct dc_context *ctx,
1050         uint32_t inst)
1051 {
1052         struct dce_i2c_hw *dce_i2c_hw =
1053                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1054
1055         if (!dce_i2c_hw)
1056                 return NULL;
1057
1058         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1059                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1060
1061         return dce_i2c_hw;
1062 }
1063 static struct mpc *dcn31_mpc_create(
1064                 struct dc_context *ctx,
1065                 int num_mpcc,
1066                 int num_rmu)
1067 {
1068         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1069                                           GFP_KERNEL);
1070
1071         if (!mpc30)
1072                 return NULL;
1073
1074         dcn30_mpc_construct(mpc30, ctx,
1075                         &mpc_regs,
1076                         &mpc_shift,
1077                         &mpc_mask,
1078                         num_mpcc,
1079                         num_rmu);
1080
1081         return &mpc30->base;
1082 }
1083
1084 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1085 {
1086         int i;
1087
1088         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1089                                           GFP_KERNEL);
1090
1091         if (!hubbub3)
1092                 return NULL;
1093
1094         hubbub31_construct(hubbub3, ctx,
1095                         &hubbub_reg,
1096                         &hubbub_shift,
1097                         &hubbub_mask,
1098                         dcn3_1_ip.det_buffer_size_kbytes,
1099                         dcn3_1_ip.pixel_chunk_size_kbytes,
1100                         dcn3_1_ip.config_return_buffer_size_in_kbytes);
1101
1102
1103         for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1104                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1105
1106                 vmid->ctx = ctx;
1107
1108                 vmid->regs = &vmid_regs[i];
1109                 vmid->shifts = &vmid_shifts;
1110                 vmid->masks = &vmid_masks;
1111         }
1112
1113         return &hubbub3->base;
1114 }
1115
1116 static struct timing_generator *dcn31_timing_generator_create(
1117                 struct dc_context *ctx,
1118                 uint32_t instance)
1119 {
1120         struct optc *tgn10 =
1121                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1122
1123         if (!tgn10)
1124                 return NULL;
1125
1126         tgn10->base.inst = instance;
1127         tgn10->base.ctx = ctx;
1128
1129         tgn10->tg_regs = &optc_regs[instance];
1130         tgn10->tg_shift = &optc_shift;
1131         tgn10->tg_mask = &optc_mask;
1132
1133         dcn31_timing_generator_init(tgn10);
1134
1135         return &tgn10->base;
1136 }
1137
1138 static const struct encoder_feature_support link_enc_feature = {
1139                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1140                 .max_hdmi_pixel_clock = 600000,
1141                 .hdmi_ycbcr420_supported = true,
1142                 .dp_ycbcr420_supported = true,
1143                 .fec_supported = true,
1144                 .flags.bits.IS_HBR2_CAPABLE = true,
1145                 .flags.bits.IS_HBR3_CAPABLE = true,
1146                 .flags.bits.IS_TPS3_CAPABLE = true,
1147                 .flags.bits.IS_TPS4_CAPABLE = true
1148 };
1149
1150 static struct link_encoder *dcn31_link_encoder_create(
1151         const struct encoder_init_data *enc_init_data)
1152 {
1153         struct dcn20_link_encoder *enc20 =
1154                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1155
1156         if (!enc20)
1157                 return NULL;
1158
1159         dcn31_link_encoder_construct(enc20,
1160                         enc_init_data,
1161                         &link_enc_feature,
1162                         &link_enc_regs[enc_init_data->transmitter],
1163                         &link_enc_aux_regs[enc_init_data->channel - 1],
1164                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1165                         &le_shift,
1166                         &le_mask);
1167
1168         return &enc20->enc10.base;
1169 }
1170
1171 /* Create a minimal link encoder object not associated with a particular
1172  * physical connector.
1173  * resource_funcs.link_enc_create_minimal
1174  */
1175 static struct link_encoder *dcn31_link_enc_create_minimal(
1176                 struct dc_context *ctx, enum engine_id eng_id)
1177 {
1178         struct dcn20_link_encoder *enc20;
1179
1180         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1181                 return NULL;
1182
1183         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1184         if (!enc20)
1185                 return NULL;
1186
1187         dcn31_link_encoder_construct_minimal(
1188                         enc20,
1189                         ctx,
1190                         &link_enc_feature,
1191                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1192                         eng_id);
1193
1194         return &enc20->enc10.base;
1195 }
1196
1197 struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1198 {
1199         struct dcn31_panel_cntl *panel_cntl =
1200                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1201
1202         if (!panel_cntl)
1203                 return NULL;
1204
1205         dcn31_panel_cntl_construct(panel_cntl, init_data);
1206
1207         return &panel_cntl->base;
1208 }
1209
1210 static void read_dce_straps(
1211         struct dc_context *ctx,
1212         struct resource_straps *straps)
1213 {
1214         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1215                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1216
1217 }
1218
1219 static struct audio *dcn31_create_audio(
1220                 struct dc_context *ctx, unsigned int inst)
1221 {
1222         return dce_audio_create(ctx, inst,
1223                         &audio_regs[inst], &audio_shift, &audio_mask);
1224 }
1225
1226 static struct vpg *dcn31_vpg_create(
1227         struct dc_context *ctx,
1228         uint32_t inst)
1229 {
1230         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1231
1232         if (!vpg3)
1233                 return NULL;
1234
1235         vpg3_construct(vpg3, ctx, inst,
1236                         &vpg_regs[inst],
1237                         &vpg_shift,
1238                         &vpg_mask);
1239
1240         return &vpg3->base;
1241 }
1242
1243 static struct afmt *dcn31_afmt_create(
1244         struct dc_context *ctx,
1245         uint32_t inst)
1246 {
1247         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1248
1249         if (!afmt3)
1250                 return NULL;
1251
1252         afmt3_construct(afmt3, ctx, inst,
1253                         &afmt_regs[inst],
1254                         &afmt_shift,
1255                         &afmt_mask);
1256
1257         return &afmt3->base;
1258 }
1259
1260 static struct stream_encoder *dcn31_stream_encoder_create(
1261         enum engine_id eng_id,
1262         struct dc_context *ctx)
1263 {
1264         struct dcn10_stream_encoder *enc1;
1265         struct vpg *vpg;
1266         struct afmt *afmt;
1267         int vpg_inst;
1268         int afmt_inst;
1269
1270         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1271         if (eng_id <= ENGINE_ID_DIGF) {
1272                 vpg_inst = eng_id;
1273                 afmt_inst = eng_id;
1274         } else
1275                 return NULL;
1276
1277         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1278         vpg = dcn31_vpg_create(ctx, vpg_inst);
1279         afmt = dcn31_afmt_create(ctx, afmt_inst);
1280
1281         if (!enc1 || !vpg || !afmt)
1282                 return NULL;
1283
1284         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1285                                         eng_id, vpg, afmt,
1286                                         &stream_enc_regs[eng_id],
1287                                         &se_shift, &se_mask);
1288
1289         return &enc1->base;
1290 }
1291
1292 static struct dce_hwseq *dcn31_hwseq_create(
1293         struct dc_context *ctx)
1294 {
1295         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1296
1297         if (hws) {
1298                 hws->ctx = ctx;
1299                 hws->regs = &hwseq_reg;
1300                 hws->shifts = &hwseq_shift;
1301                 hws->masks = &hwseq_mask;
1302         }
1303         return hws;
1304 }
1305 static const struct resource_create_funcs res_create_funcs = {
1306         .read_dce_straps = read_dce_straps,
1307         .create_audio = dcn31_create_audio,
1308         .create_stream_encoder = dcn31_stream_encoder_create,
1309         .create_hwseq = dcn31_hwseq_create,
1310 };
1311
1312 static const struct resource_create_funcs res_create_maximus_funcs = {
1313         .read_dce_straps = NULL,
1314         .create_audio = NULL,
1315         .create_stream_encoder = NULL,
1316         .create_hwseq = dcn31_hwseq_create,
1317 };
1318
1319 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1320 {
1321         unsigned int i;
1322
1323         for (i = 0; i < pool->base.stream_enc_count; i++) {
1324                 if (pool->base.stream_enc[i] != NULL) {
1325                         if (pool->base.stream_enc[i]->vpg != NULL) {
1326                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1327                                 pool->base.stream_enc[i]->vpg = NULL;
1328                         }
1329                         if (pool->base.stream_enc[i]->afmt != NULL) {
1330                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1331                                 pool->base.stream_enc[i]->afmt = NULL;
1332                         }
1333                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1334                         pool->base.stream_enc[i] = NULL;
1335                 }
1336         }
1337
1338         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1339                 if (pool->base.dscs[i] != NULL)
1340                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1341         }
1342
1343         if (pool->base.mpc != NULL) {
1344                 kfree(TO_DCN20_MPC(pool->base.mpc));
1345                 pool->base.mpc = NULL;
1346         }
1347         if (pool->base.hubbub != NULL) {
1348                 kfree(pool->base.hubbub);
1349                 pool->base.hubbub = NULL;
1350         }
1351         for (i = 0; i < pool->base.pipe_count; i++) {
1352                 if (pool->base.dpps[i] != NULL)
1353                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1354
1355                 if (pool->base.ipps[i] != NULL)
1356                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1357
1358                 if (pool->base.hubps[i] != NULL) {
1359                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1360                         pool->base.hubps[i] = NULL;
1361                 }
1362
1363                 if (pool->base.irqs != NULL) {
1364                         dal_irq_service_destroy(&pool->base.irqs);
1365                 }
1366         }
1367
1368         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1369                 if (pool->base.engines[i] != NULL)
1370                         dce110_engine_destroy(&pool->base.engines[i]);
1371                 if (pool->base.hw_i2cs[i] != NULL) {
1372                         kfree(pool->base.hw_i2cs[i]);
1373                         pool->base.hw_i2cs[i] = NULL;
1374                 }
1375                 if (pool->base.sw_i2cs[i] != NULL) {
1376                         kfree(pool->base.sw_i2cs[i]);
1377                         pool->base.sw_i2cs[i] = NULL;
1378                 }
1379         }
1380
1381         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1382                 if (pool->base.opps[i] != NULL)
1383                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1384         }
1385
1386         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1387                 if (pool->base.timing_generators[i] != NULL)    {
1388                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1389                         pool->base.timing_generators[i] = NULL;
1390                 }
1391         }
1392
1393         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1394                 if (pool->base.dwbc[i] != NULL) {
1395                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1396                         pool->base.dwbc[i] = NULL;
1397                 }
1398                 if (pool->base.mcif_wb[i] != NULL) {
1399                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1400                         pool->base.mcif_wb[i] = NULL;
1401                 }
1402         }
1403
1404         for (i = 0; i < pool->base.audio_count; i++) {
1405                 if (pool->base.audios[i])
1406                         dce_aud_destroy(&pool->base.audios[i]);
1407         }
1408
1409         for (i = 0; i < pool->base.clk_src_count; i++) {
1410                 if (pool->base.clock_sources[i] != NULL) {
1411                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1412                         pool->base.clock_sources[i] = NULL;
1413                 }
1414         }
1415
1416         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1417                 if (pool->base.mpc_lut[i] != NULL) {
1418                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1419                         pool->base.mpc_lut[i] = NULL;
1420                 }
1421                 if (pool->base.mpc_shaper[i] != NULL) {
1422                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1423                         pool->base.mpc_shaper[i] = NULL;
1424                 }
1425         }
1426
1427         if (pool->base.dp_clock_source != NULL) {
1428                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1429                 pool->base.dp_clock_source = NULL;
1430         }
1431
1432         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1433                 if (pool->base.multiple_abms[i] != NULL)
1434                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1435         }
1436
1437         if (pool->base.psr != NULL)
1438                 dmub_psr_destroy(&pool->base.psr);
1439
1440         if (pool->base.dccg != NULL)
1441                 dcn_dccg_destroy(&pool->base.dccg);
1442 }
1443
1444 static struct hubp *dcn31_hubp_create(
1445         struct dc_context *ctx,
1446         uint32_t inst)
1447 {
1448         struct dcn20_hubp *hubp2 =
1449                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1450
1451         if (!hubp2)
1452                 return NULL;
1453
1454         if (hubp31_construct(hubp2, ctx, inst,
1455                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1456                 return &hubp2->base;
1457
1458         BREAK_TO_DEBUGGER();
1459         kfree(hubp2);
1460         return NULL;
1461 }
1462
1463 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1464 {
1465         int i;
1466         uint32_t pipe_count = pool->res_cap->num_dwb;
1467
1468         for (i = 0; i < pipe_count; i++) {
1469                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1470                                                     GFP_KERNEL);
1471
1472                 if (!dwbc30) {
1473                         dm_error("DC: failed to create dwbc30!\n");
1474                         return false;
1475                 }
1476
1477                 dcn30_dwbc_construct(dwbc30, ctx,
1478                                 &dwbc30_regs[i],
1479                                 &dwbc30_shift,
1480                                 &dwbc30_mask,
1481                                 i);
1482
1483                 pool->dwbc[i] = &dwbc30->base;
1484         }
1485         return true;
1486 }
1487
1488 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1489 {
1490         int i;
1491         uint32_t pipe_count = pool->res_cap->num_dwb;
1492
1493         for (i = 0; i < pipe_count; i++) {
1494                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1495                                                     GFP_KERNEL);
1496
1497                 if (!mcif_wb30) {
1498                         dm_error("DC: failed to create mcif_wb30!\n");
1499                         return false;
1500                 }
1501
1502                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1503                                 &mcif_wb30_regs[i],
1504                                 &mcif_wb30_shift,
1505                                 &mcif_wb30_mask,
1506                                 i);
1507
1508                 pool->mcif_wb[i] = &mcif_wb30->base;
1509         }
1510         return true;
1511 }
1512
1513 static struct display_stream_compressor *dcn31_dsc_create(
1514         struct dc_context *ctx, uint32_t inst)
1515 {
1516         struct dcn20_dsc *dsc =
1517                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1518
1519         if (!dsc) {
1520                 BREAK_TO_DEBUGGER();
1521                 return NULL;
1522         }
1523
1524         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1525         return &dsc->base;
1526 }
1527
1528 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1529 {
1530         struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1531
1532         dcn31_resource_destruct(dcn31_pool);
1533         kfree(dcn31_pool);
1534         *pool = NULL;
1535 }
1536
1537 static struct clock_source *dcn31_clock_source_create(
1538                 struct dc_context *ctx,
1539                 struct dc_bios *bios,
1540                 enum clock_source_id id,
1541                 const struct dce110_clk_src_regs *regs,
1542                 bool dp_clk_src)
1543 {
1544         struct dce110_clk_src *clk_src =
1545                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1546
1547         if (!clk_src)
1548                 return NULL;
1549
1550         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1551                         regs, &cs_shift, &cs_mask)) {
1552                 clk_src->base.dp_clk_src = dp_clk_src;
1553                 return &clk_src->base;
1554         }
1555
1556         BREAK_TO_DEBUGGER();
1557         return NULL;
1558 }
1559
1560 static bool is_dual_plane(enum surface_pixel_format format)
1561 {
1562         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1563 }
1564
1565 static int dcn31_populate_dml_pipes_from_context(
1566         struct dc *dc, struct dc_state *context,
1567         display_e2e_pipe_params_st *pipes,
1568         bool fast_validate)
1569 {
1570         int i, pipe_cnt;
1571         struct resource_context *res_ctx = &context->res_ctx;
1572         struct pipe_ctx *pipe;
1573
1574         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1575
1576         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1577                 struct dc_crtc_timing *timing;
1578
1579                 if (!res_ctx->pipe_ctx[i].stream)
1580                         continue;
1581                 pipe = &res_ctx->pipe_ctx[i];
1582                 timing = &pipe->stream->timing;
1583
1584                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1585                 pipes[pipe_cnt].pipe.src.gpuvm = true;
1586                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1587                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1588                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1589                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1590                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1591
1592                 if (pipes[pipe_cnt].dout.dsc_enable) {
1593                         switch (timing->display_color_depth) {
1594                         case COLOR_DEPTH_888:
1595                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1596                                 break;
1597                         case COLOR_DEPTH_101010:
1598                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1599                                 break;
1600                         case COLOR_DEPTH_121212:
1601                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1602                                 break;
1603                         default:
1604                                 ASSERT(0);
1605                                 break;
1606                         }
1607                 }
1608
1609                 pipe_cnt++;
1610         }
1611         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1612         dc->config.enable_4to1MPC = false;
1613         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1614                 if (is_dual_plane(pipe->plane_state->format)
1615                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1616                         dc->config.enable_4to1MPC = true;
1617                 } else if (!is_dual_plane(pipe->plane_state->format)) {
1618                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1619                         pipes[0].pipe.src.unbounded_req_mode = true;
1620                 }
1621         }
1622
1623         return pipe_cnt;
1624 }
1625
1626 static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
1627 {
1628         if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
1629                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
1630                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
1631                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
1632         }
1633 }
1634
1635 static void dcn31_calculate_wm_and_dlg_fp(
1636                 struct dc *dc, struct dc_state *context,
1637                 display_e2e_pipe_params_st *pipes,
1638                 int pipe_cnt,
1639                 int vlevel)
1640 {
1641         int i, pipe_idx;
1642         double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1643
1644         if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
1645                 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
1646
1647         pipes[0].clks_cfg.voltage = vlevel;
1648         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1649         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1650
1651 #if 0 // TODO
1652         /* Set B:
1653          * TODO
1654          */
1655         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
1656                 if (vlevel == 0) {
1657                         pipes[0].clks_cfg.voltage = 1;
1658                         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
1659                 }
1660                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
1661                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
1662                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
1663         }
1664         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1665         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1666         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1667         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1668         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1669         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1670         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1671         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1672         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1673         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1674
1675         pipes[0].clks_cfg.voltage = vlevel;
1676         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1677
1678         /* Set C:
1679          * TODO
1680          */
1681         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
1682                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
1683                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
1684                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
1685         }
1686         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1687         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1688         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1689         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1690         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1691         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1692         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1693         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1694         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1695         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1696
1697         /* Set D:
1698          * TODO
1699          */
1700         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
1701                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
1702                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
1703                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
1704         }
1705         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1706         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1707         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1708         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1709         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1710         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1711         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1712         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1713         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1714         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1715 #endif
1716
1717         /* Set A:
1718          * All clocks min required
1719          *
1720          * Set A calculated last so that following calculations are based on Set A
1721          */
1722         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1723         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1724         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1725         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1726         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1727         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1728         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1729         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1730         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1731         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1732         context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1733         /* TODO: remove: */
1734         context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1735         context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1736         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1737         /* end remove*/
1738
1739         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1740                 if (!context->res_ctx.pipe_ctx[i].stream)
1741                         continue;
1742
1743                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1744                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1745
1746                 if (dc->config.forced_clocks) {
1747                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1748                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1749                 }
1750                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1751                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1752                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1753                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1754
1755                 pipe_idx++;
1756         }
1757
1758         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1759 }
1760
1761 static void dcn31_calculate_wm_and_dlg(
1762                 struct dc *dc, struct dc_state *context,
1763                 display_e2e_pipe_params_st *pipes,
1764                 int pipe_cnt,
1765                 int vlevel)
1766 {
1767         DC_FP_START();
1768         dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1769         DC_FP_END();
1770 }
1771
1772 static struct dc_cap_funcs cap_funcs = {
1773         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1774 };
1775
1776 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1777 {
1778         struct clk_limit_table *clk_table = &bw_params->clk_table;
1779         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1780         unsigned int i, closest_clk_lvl;
1781         int j;
1782
1783         // Default clock levels are used for diags, which may lead to overclocking.
1784         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
1785                 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
1786
1787                 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
1788                 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
1789                 dcn3_1_soc.num_chans = bw_params->num_channels;
1790
1791                 ASSERT(clk_table->num_entries);
1792
1793                 /* Prepass to find max clocks independent of voltage level. */
1794                 for (i = 0; i < clk_table->num_entries; ++i) {
1795                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
1796                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
1797                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
1798                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
1799                 }
1800
1801                 for (i = 0; i < clk_table->num_entries; i++) {
1802                         /* loop backwards*/
1803                         for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
1804                                 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1805                                         closest_clk_lvl = j;
1806                                         break;
1807                                 }
1808                         }
1809
1810                         clock_limits[i].state = i;
1811
1812                         /* Clocks dependent on voltage level. */
1813                         clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1814                         clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1815                         clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1816                         clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
1817
1818                         /* Clocks independent of voltage level. */
1819                         clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
1820                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1821
1822                         clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
1823                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1824
1825                         clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1826                         clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1827                         clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1828                         clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1829                         clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1830                 }
1831                 for (i = 0; i < clk_table->num_entries; i++)
1832                         dcn3_1_soc.clock_limits[i] = clock_limits[i];
1833                 if (clk_table->num_entries) {
1834                         dcn3_1_soc.num_states = clk_table->num_entries;
1835                 }
1836         }
1837
1838         dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1839         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1840
1841         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1842                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
1843         else
1844                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
1845 }
1846
1847 static struct resource_funcs dcn31_res_pool_funcs = {
1848         .destroy = dcn31_destroy_resource_pool,
1849         .link_enc_create = dcn31_link_encoder_create,
1850         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1851         .link_encs_assign = link_enc_cfg_link_encs_assign,
1852         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1853         .panel_cntl_create = dcn31_panel_cntl_create,
1854         .validate_bandwidth = dcn30_validate_bandwidth,
1855         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1856         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1857         .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1858         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1859         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1860         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1861         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1862         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1863         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1864         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1865         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1866         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1867         .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1868         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1869 };
1870
1871 static struct clock_source *dcn30_clock_source_create(
1872                 struct dc_context *ctx,
1873                 struct dc_bios *bios,
1874                 enum clock_source_id id,
1875                 const struct dce110_clk_src_regs *regs,
1876                 bool dp_clk_src)
1877 {
1878         struct dce110_clk_src *clk_src =
1879                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1880
1881         if (!clk_src)
1882                 return NULL;
1883
1884         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1885                         regs, &cs_shift, &cs_mask)) {
1886                 clk_src->base.dp_clk_src = dp_clk_src;
1887                 return &clk_src->base;
1888         }
1889
1890         BREAK_TO_DEBUGGER();
1891         return NULL;
1892 }
1893
1894 static bool dcn31_resource_construct(
1895         uint8_t num_virtual_links,
1896         struct dc *dc,
1897         struct dcn31_resource_pool *pool)
1898 {
1899         int i;
1900         struct dc_context *ctx = dc->ctx;
1901         struct irq_service_init_data init_data;
1902
1903         DC_FP_START();
1904
1905         ctx->dc_bios->regs = &bios_regs;
1906
1907         pool->base.res_cap = &res_cap_dcn31;
1908
1909         pool->base.funcs = &dcn31_res_pool_funcs;
1910
1911         /*************************************************
1912          *  Resource + asic cap harcoding                *
1913          *************************************************/
1914         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1915         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1916         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1917         dc->caps.max_downscale_ratio = 600;
1918         dc->caps.i2c_speed_in_khz = 100;
1919         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1920         dc->caps.max_cursor_size = 256;
1921         dc->caps.min_horizontal_blanking_period = 80;
1922         dc->caps.dmdata_alloc_size = 2048;
1923
1924         dc->caps.max_slave_planes = 1;
1925         dc->caps.max_slave_yuv_planes = 1;
1926         dc->caps.max_slave_rgb_planes = 1;
1927         dc->caps.post_blend_color_processing = true;
1928         dc->caps.force_dp_tps4_for_cp2520 = true;
1929         dc->caps.extended_aux_timeout_support = true;
1930         dc->caps.dmcub_support = true;
1931         dc->caps.is_apu = true;
1932
1933         /* Color pipeline capabilities */
1934         dc->caps.color.dpp.dcn_arch = 1;
1935         dc->caps.color.dpp.input_lut_shared = 0;
1936         dc->caps.color.dpp.icsc = 1;
1937         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1938         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1939         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1940         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1941         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1942         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1943         dc->caps.color.dpp.post_csc = 1;
1944         dc->caps.color.dpp.gamma_corr = 1;
1945         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1946
1947         dc->caps.color.dpp.hw_3d_lut = 1;
1948         dc->caps.color.dpp.ogam_ram = 1;
1949         // no OGAM ROM on DCN301
1950         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1951         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1952         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1953         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1954         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1955         dc->caps.color.dpp.ocsc = 0;
1956
1957         dc->caps.color.mpc.gamut_remap = 1;
1958         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1959         dc->caps.color.mpc.ogam_ram = 1;
1960         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1961         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1962         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1963         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1964         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1965         dc->caps.color.mpc.ocsc = 1;
1966
1967         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1968                 dc->debug = debug_defaults_drv;
1969         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1970                 dc->debug = debug_defaults_diags;
1971         } else
1972                 dc->debug = debug_defaults_diags;
1973         // Init the vm_helper
1974         if (dc->vm_helper)
1975                 vm_helper_init(dc->vm_helper, 16);
1976
1977         /*************************************************
1978          *  Create resources                             *
1979          *************************************************/
1980
1981         /* Clock Sources for Pixel Clock*/
1982         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1983                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1984                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1985                                 &clk_src_regs[0], false);
1986         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1987                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1988                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1989                                 &clk_src_regs[1], false);
1990         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1991                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1992                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1993                                 &clk_src_regs[2], false);
1994         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1995                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1996                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1997                                 &clk_src_regs[3], false);
1998         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1999                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2000                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2001                                 &clk_src_regs[4], false);
2002
2003         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2004
2005         /* todo: not reuse phy_pll registers */
2006         pool->base.dp_clock_source =
2007                         dcn31_clock_source_create(ctx, ctx->dc_bios,
2008                                 CLOCK_SOURCE_ID_DP_DTO,
2009                                 &clk_src_regs[0], true);
2010
2011         for (i = 0; i < pool->base.clk_src_count; i++) {
2012                 if (pool->base.clock_sources[i] == NULL) {
2013                         dm_error("DC: failed to create clock sources!\n");
2014                         BREAK_TO_DEBUGGER();
2015                         goto create_fail;
2016                 }
2017         }
2018
2019         /* TODO: DCCG */
2020         pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2021         if (pool->base.dccg == NULL) {
2022                 dm_error("DC: failed to create dccg!\n");
2023                 BREAK_TO_DEBUGGER();
2024                 goto create_fail;
2025         }
2026
2027         /* TODO: IRQ */
2028         init_data.ctx = dc->ctx;
2029         pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2030         if (!pool->base.irqs)
2031                 goto create_fail;
2032
2033         /* HUBBUB */
2034         pool->base.hubbub = dcn31_hubbub_create(ctx);
2035         if (pool->base.hubbub == NULL) {
2036                 BREAK_TO_DEBUGGER();
2037                 dm_error("DC: failed to create hubbub!\n");
2038                 goto create_fail;
2039         }
2040
2041         /* HUBPs, DPPs, OPPs and TGs */
2042         for (i = 0; i < pool->base.pipe_count; i++) {
2043                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2044                 if (pool->base.hubps[i] == NULL) {
2045                         BREAK_TO_DEBUGGER();
2046                         dm_error(
2047                                 "DC: failed to create hubps!\n");
2048                         goto create_fail;
2049                 }
2050
2051                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2052                 if (pool->base.dpps[i] == NULL) {
2053                         BREAK_TO_DEBUGGER();
2054                         dm_error(
2055                                 "DC: failed to create dpps!\n");
2056                         goto create_fail;
2057                 }
2058         }
2059
2060         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2061                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2062                 if (pool->base.opps[i] == NULL) {
2063                         BREAK_TO_DEBUGGER();
2064                         dm_error(
2065                                 "DC: failed to create output pixel processor!\n");
2066                         goto create_fail;
2067                 }
2068         }
2069
2070         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2071                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2072                                 ctx, i);
2073                 if (pool->base.timing_generators[i] == NULL) {
2074                         BREAK_TO_DEBUGGER();
2075                         dm_error("DC: failed to create tg!\n");
2076                         goto create_fail;
2077                 }
2078         }
2079         pool->base.timing_generator_count = i;
2080
2081         /* PSR */
2082         pool->base.psr = dmub_psr_create(ctx);
2083         if (pool->base.psr == NULL) {
2084                 dm_error("DC: failed to create psr obj!\n");
2085                 BREAK_TO_DEBUGGER();
2086                 goto create_fail;
2087         }
2088
2089         /* ABM */
2090         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2091                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2092                                 &abm_regs[i],
2093                                 &abm_shift,
2094                                 &abm_mask);
2095                 if (pool->base.multiple_abms[i] == NULL) {
2096                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2097                         BREAK_TO_DEBUGGER();
2098                         goto create_fail;
2099                 }
2100         }
2101
2102         /* MPC and DSC */
2103         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2104         if (pool->base.mpc == NULL) {
2105                 BREAK_TO_DEBUGGER();
2106                 dm_error("DC: failed to create mpc!\n");
2107                 goto create_fail;
2108         }
2109
2110         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2111                 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2112                 if (pool->base.dscs[i] == NULL) {
2113                         BREAK_TO_DEBUGGER();
2114                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2115                         goto create_fail;
2116                 }
2117         }
2118
2119         /* DWB and MMHUBBUB */
2120         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2121                 BREAK_TO_DEBUGGER();
2122                 dm_error("DC: failed to create dwbc!\n");
2123                 goto create_fail;
2124         }
2125
2126         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2127                 BREAK_TO_DEBUGGER();
2128                 dm_error("DC: failed to create mcif_wb!\n");
2129                 goto create_fail;
2130         }
2131
2132         /* AUX and I2C */
2133         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2134                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2135                 if (pool->base.engines[i] == NULL) {
2136                         BREAK_TO_DEBUGGER();
2137                         dm_error(
2138                                 "DC:failed to create aux engine!!\n");
2139                         goto create_fail;
2140                 }
2141                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2142                 if (pool->base.hw_i2cs[i] == NULL) {
2143                         BREAK_TO_DEBUGGER();
2144                         dm_error(
2145                                 "DC:failed to create hw i2c!!\n");
2146                         goto create_fail;
2147                 }
2148                 pool->base.sw_i2cs[i] = NULL;
2149         }
2150
2151         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2152         if (!resource_construct(num_virtual_links, dc, &pool->base,
2153                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2154                         &res_create_funcs : &res_create_maximus_funcs)))
2155                         goto create_fail;
2156
2157         /* HW Sequencer and Plane caps */
2158         dcn31_hw_sequencer_construct(dc);
2159
2160         dc->caps.max_planes =  pool->base.pipe_count;
2161
2162         for (i = 0; i < dc->caps.max_planes; ++i)
2163                 dc->caps.planes[i] = plane_cap;
2164
2165         dc->cap_funcs = cap_funcs;
2166
2167         DC_FP_END();
2168
2169         return true;
2170
2171 create_fail:
2172
2173         DC_FP_END();
2174         dcn31_resource_destruct(pool);
2175
2176         return false;
2177 }
2178
2179 struct resource_pool *dcn31_create_resource_pool(
2180                 const struct dc_init_data *init_data,
2181                 struct dc *dc)
2182 {
2183         struct dcn31_resource_pool *pool =
2184                 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2185
2186         if (!pool)
2187                 return NULL;
2188
2189         if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2190                 return &pool->base;
2191
2192         BREAK_TO_DEBUGGER();
2193         kfree(pool);
2194         return NULL;
2195 }