2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/delay.h>
27 #include <linux/slab.h>
29 #include "reg_helper.h"
31 #include "core_types.h"
32 #include "link_encoder.h"
33 #include "dcn10_link_encoder.h"
34 #include "stream_encoder.h"
35 #include "i2caux_interface.h"
36 #include "dc_bios_types.h"
38 #include "gpio_service_interface.h"
43 enc10->base.ctx->logger
46 (enc10->link_regs->reg)
49 #define FN(reg_name, field_name) \
50 enc10->link_shift->field_name, enc10->link_mask->field_name
55 * Trigger Source Select
56 * ASIC-dependent, actual values for register programming
58 #define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
59 #define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
60 #define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
61 #define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
62 #define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
63 #define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
64 #define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
65 #define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
68 DP_MST_UPDATE_MAX_RETRY = 50
71 static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
72 .validate_output_with_stream =
73 dcn10_link_encoder_validate_output_with_stream,
74 .hw_init = dcn10_link_encoder_hw_init,
75 .setup = dcn10_link_encoder_setup,
76 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
77 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
78 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
79 .disable_output = dcn10_link_encoder_disable_output,
80 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
81 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
82 .update_mst_stream_allocation_table =
83 dcn10_link_encoder_update_mst_stream_allocation_table,
84 .psr_program_dp_dphy_fast_training =
85 dcn10_psr_program_dp_dphy_fast_training,
86 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
87 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
88 .enable_hpd = dcn10_link_encoder_enable_hpd,
89 .disable_hpd = dcn10_link_encoder_disable_hpd,
90 .is_dig_enabled = dcn10_is_dig_enabled,
91 .get_dig_frontend = dcn10_get_dig_frontend,
92 .get_dig_mode = dcn10_get_dig_mode,
93 .destroy = dcn10_link_encoder_destroy,
94 .get_max_link_cap = dcn10_link_encoder_get_max_link_cap,
97 static enum bp_result link_transmitter_control(
98 struct dcn10_link_encoder *enc10,
99 struct bp_transmitter_control *cntl)
101 enum bp_result result;
102 struct dc_bios *bp = enc10->base.ctx->dc_bios;
104 result = bp->funcs->transmitter_control(bp, cntl);
109 static void enable_phy_bypass_mode(
110 struct dcn10_link_encoder *enc10,
113 /* This register resides in DP back end block;
114 * transmitter is used for the offset
116 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
120 static void disable_prbs_symbols(
121 struct dcn10_link_encoder *enc10,
124 /* This register resides in DP back end block;
125 * transmitter is used for the offset
127 REG_UPDATE_4(DP_DPHY_CNTL,
128 DPHY_ATEST_SEL_LANE0, disable,
129 DPHY_ATEST_SEL_LANE1, disable,
130 DPHY_ATEST_SEL_LANE2, disable,
131 DPHY_ATEST_SEL_LANE3, disable);
134 static void disable_prbs_mode(
135 struct dcn10_link_encoder *enc10)
137 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
140 static void program_pattern_symbols(
141 struct dcn10_link_encoder *enc10,
142 uint16_t pattern_symbols[8])
144 /* This register resides in DP back end block;
145 * transmitter is used for the offset
147 REG_SET_3(DP_DPHY_SYM0, 0,
148 DPHY_SYM1, pattern_symbols[0],
149 DPHY_SYM2, pattern_symbols[1],
150 DPHY_SYM3, pattern_symbols[2]);
152 /* This register resides in DP back end block;
153 * transmitter is used for the offset
155 REG_SET_3(DP_DPHY_SYM1, 0,
156 DPHY_SYM4, pattern_symbols[3],
157 DPHY_SYM5, pattern_symbols[4],
158 DPHY_SYM6, pattern_symbols[5]);
160 /* This register resides in DP back end block;
161 * transmitter is used for the offset
163 REG_SET_2(DP_DPHY_SYM2, 0,
164 DPHY_SYM7, pattern_symbols[6],
165 DPHY_SYM8, pattern_symbols[7]);
168 static void set_dp_phy_pattern_d102(
169 struct dcn10_link_encoder *enc10)
171 /* Disable PHY Bypass mode to setup the test pattern */
172 enable_phy_bypass_mode(enc10, false);
174 /* For 10-bit PRBS or debug symbols
175 * please use the following sequence:
177 * Enable debug symbols on the lanes
179 disable_prbs_symbols(enc10, true);
181 /* Disable PRBS mode */
182 disable_prbs_mode(enc10);
184 /* Program debug symbols to be output */
186 uint16_t pattern_symbols[8] = {
187 0x2AA, 0x2AA, 0x2AA, 0x2AA,
188 0x2AA, 0x2AA, 0x2AA, 0x2AA
191 program_pattern_symbols(enc10, pattern_symbols);
194 /* Enable phy bypass mode to enable the test pattern */
196 enable_phy_bypass_mode(enc10, true);
199 static void set_link_training_complete(
200 struct dcn10_link_encoder *enc10,
203 /* This register resides in DP back end block;
204 * transmitter is used for the offset
206 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
210 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
211 struct link_encoder *enc,
214 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
215 /* Write Training Pattern */
217 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
219 /* Set HW Register Training Complete to false */
221 set_link_training_complete(enc10, false);
223 /* Disable PHY Bypass mode to output Training Pattern */
225 enable_phy_bypass_mode(enc10, false);
227 /* Disable PRBS mode */
228 disable_prbs_mode(enc10);
231 static void setup_panel_mode(
232 struct dcn10_link_encoder *enc10,
233 enum dp_panel_mode panel_mode)
237 if (!REG(DP_DPHY_INTERNAL_CTRL))
240 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
242 switch (panel_mode) {
243 case DP_PANEL_MODE_EDP:
246 case DP_PANEL_MODE_SPECIAL:
254 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
257 static void set_dp_phy_pattern_symbol_error(
258 struct dcn10_link_encoder *enc10)
260 /* Disable PHY Bypass mode to setup the test pattern */
261 enable_phy_bypass_mode(enc10, false);
263 /* program correct panel mode*/
264 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
266 /* A PRBS23 pattern is used for most DP electrical measurements. */
268 /* Enable PRBS symbols on the lanes */
269 disable_prbs_symbols(enc10, false);
271 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
272 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
276 /* Enable phy bypass mode to enable the test pattern */
277 enable_phy_bypass_mode(enc10, true);
280 static void set_dp_phy_pattern_prbs7(
281 struct dcn10_link_encoder *enc10)
283 /* Disable PHY Bypass mode to setup the test pattern */
284 enable_phy_bypass_mode(enc10, false);
286 /* A PRBS7 pattern is used for most DP electrical measurements. */
288 /* Enable PRBS symbols on the lanes */
289 disable_prbs_symbols(enc10, false);
291 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
292 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
296 /* Enable phy bypass mode to enable the test pattern */
297 enable_phy_bypass_mode(enc10, true);
300 static void set_dp_phy_pattern_80bit_custom(
301 struct dcn10_link_encoder *enc10,
302 const uint8_t *pattern)
304 /* Disable PHY Bypass mode to setup the test pattern */
305 enable_phy_bypass_mode(enc10, false);
307 /* Enable debug symbols on the lanes */
309 disable_prbs_symbols(enc10, true);
311 /* Enable PHY bypass mode to enable the test pattern */
312 /* TODO is it really needed ? */
314 enable_phy_bypass_mode(enc10, true);
316 /* Program 80 bit custom pattern */
318 uint16_t pattern_symbols[8];
321 ((pattern[1] & 0x03) << 8) | pattern[0];
323 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
325 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
327 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
329 ((pattern[6] & 0x03) << 8) | pattern[5];
331 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
333 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
335 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
337 program_pattern_symbols(enc10, pattern_symbols);
340 /* Enable phy bypass mode to enable the test pattern */
342 enable_phy_bypass_mode(enc10, true);
345 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
346 struct dcn10_link_encoder *enc10,
347 unsigned int cp2520_pattern)
350 /* previously there is a register DP_HBR2_EYE_PATTERN
351 * that is enabled to get the pattern.
352 * But it does not work with the latest spec change,
353 * so we are programming the following registers manually.
355 * The following settings have been confirmed
356 * by Nick Chorney and Sandra Liu
359 /* Disable PHY Bypass mode to setup the test pattern */
361 enable_phy_bypass_mode(enc10, false);
363 /* Setup DIG encoder in DP SST mode */
364 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
366 /* ensure normal panel mode. */
367 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
369 /* no vbid after BS (SR)
370 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
371 * 11000260 / 11000104 / 110000FC
373 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
374 DP_IDLE_BS_INTERVAL, 0xFC,
376 DP_VID_ENHANCED_FRAME_MODE, 1);
378 /* swap every BS with SR */
379 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
381 /* select cp2520 patterns */
382 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
383 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
384 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
386 /* pre-DCE11 can only generate CP2520 pattern 2 */
387 ASSERT(cp2520_pattern == 2);
389 /* set link training complete */
390 set_link_training_complete(enc10, true);
392 /* disable video stream */
393 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
395 /* Disable PHY Bypass mode to setup the test pattern */
396 enable_phy_bypass_mode(enc10, false);
399 static void set_dp_phy_pattern_passthrough_mode(
400 struct dcn10_link_encoder *enc10,
401 enum dp_panel_mode panel_mode)
403 /* program correct panel mode */
404 setup_panel_mode(enc10, panel_mode);
406 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
407 * in case we were doing HBR2 compliance pattern before
409 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
410 DP_IDLE_BS_INTERVAL, 0x2000,
412 DP_VID_ENHANCED_FRAME_MODE, 1);
414 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
416 /* set link training complete */
417 set_link_training_complete(enc10, true);
419 /* Disable PHY Bypass mode to setup the test pattern */
420 enable_phy_bypass_mode(enc10, false);
422 /* Disable PRBS mode */
423 disable_prbs_mode(enc10);
426 /* return value is bit-vector */
427 static uint8_t get_frontend_source(
428 enum engine_id engine)
432 return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
434 return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
436 return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
438 return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
440 return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
442 return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
444 return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
446 ASSERT_CRITICAL(false);
447 return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
451 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
453 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
455 enum engine_id result;
457 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
460 case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
461 result = ENGINE_ID_DIGA;
463 case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
464 result = ENGINE_ID_DIGB;
466 case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
467 result = ENGINE_ID_DIGC;
469 case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
470 result = ENGINE_ID_DIGD;
472 case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
473 result = ENGINE_ID_DIGE;
475 case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
476 result = ENGINE_ID_DIGF;
478 case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
479 result = ENGINE_ID_DIGG;
482 // invalid source select DIG
483 result = ENGINE_ID_UNKNOWN;
490 void enc1_configure_encoder(
491 struct dcn10_link_encoder *enc10,
492 const struct dc_link_settings *link_settings)
494 /* set number of lanes */
495 REG_SET(DP_CONFIG, 0,
496 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
498 /* setup scrambler */
499 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
502 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
503 bool exit_link_training_required)
505 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
507 if (exit_link_training_required)
508 REG_UPDATE(DP_DPHY_FAST_TRAINING,
509 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
511 REG_UPDATE(DP_DPHY_FAST_TRAINING,
512 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
513 /*In DCE 11, we are able to pre-program a Force SR register
514 * to be able to trigger SR symbol after 5 idle patterns
515 * transmitted. Upon PSR Exit, DMCU can trigger
516 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
517 * DPHY_LOAD_BS_COUNT_START and the internal counter
518 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
519 * replaced by SR symbol once.
522 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
526 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
527 unsigned int sdp_transmit_line_num_deadline)
529 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
531 REG_UPDATE_2(DP_SEC_CNTL1,
532 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
533 DP_SEC_GSP0_PRIORITY, 1);
536 bool dcn10_is_dig_enabled(struct link_encoder *enc)
538 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
541 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
545 static void link_encoder_disable(struct dcn10_link_encoder *enc10)
547 /* reset training pattern */
548 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
549 DPHY_TRAINING_PATTERN_SEL, 0);
551 /* reset training complete */
552 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
554 /* reset panel mode */
555 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
558 static void hpd_initialize(
559 struct dcn10_link_encoder *enc10)
561 /* Associate HPD with DIG_BE */
562 enum hpd_source_id hpd_source = enc10->base.hpd_source;
564 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
567 bool dcn10_link_encoder_validate_dvi_output(
568 const struct dcn10_link_encoder *enc10,
569 enum signal_type connector_signal,
570 enum signal_type signal,
571 const struct dc_crtc_timing *crtc_timing)
573 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
575 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
576 max_pixel_clock *= 2;
578 /* This handles the case of HDMI downgrade to DVI we don't want to
579 * we don't want to cap the pixel clock if the DDI is not DVI.
581 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
582 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
583 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
585 /* DVI only support RGB pixel encoding */
586 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
589 /*connect DVI via adpater's HDMI connector*/
590 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
591 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
592 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
593 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
595 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
598 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
601 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
602 switch (crtc_timing->display_color_depth) {
603 case COLOR_DEPTH_666:
604 case COLOR_DEPTH_888:
606 case COLOR_DEPTH_101010:
607 case COLOR_DEPTH_161616:
608 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
618 static bool dcn10_link_encoder_validate_hdmi_output(
619 const struct dcn10_link_encoder *enc10,
620 const struct dc_crtc_timing *crtc_timing,
621 const struct dc_edid_caps *edid_caps,
622 int adjusted_pix_clk_100hz)
624 enum dc_color_depth max_deep_color =
625 enc10->base.features.max_hdmi_deep_color;
627 // check pixel clock against edid specified max TMDS clk
628 if (edid_caps->max_tmds_clk_mhz != 0 &&
629 adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
632 if (max_deep_color < crtc_timing->display_color_depth)
635 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
637 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
640 if ((adjusted_pix_clk_100hz == 0) ||
641 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
644 /* DCE11 HW does not support 420 */
645 if (!enc10->base.features.hdmi_ycbcr420_supported &&
646 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
649 if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
650 adjusted_pix_clk_100hz >= 3000000)
652 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
653 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
658 bool dcn10_link_encoder_validate_dp_output(
659 const struct dcn10_link_encoder *enc10,
660 const struct dc_crtc_timing *crtc_timing)
662 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
663 if (!enc10->base.features.dp_ycbcr420_supported)
670 void dcn10_link_encoder_construct(
671 struct dcn10_link_encoder *enc10,
672 const struct encoder_init_data *init_data,
673 const struct encoder_feature_support *enc_features,
674 const struct dcn10_link_enc_registers *link_regs,
675 const struct dcn10_link_enc_aux_registers *aux_regs,
676 const struct dcn10_link_enc_hpd_registers *hpd_regs,
677 const struct dcn10_link_enc_shift *link_shift,
678 const struct dcn10_link_enc_mask *link_mask)
680 struct bp_encoder_cap_info bp_cap_info = {0};
681 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
682 enum bp_result result = BP_RESULT_OK;
684 enc10->base.funcs = &dcn10_lnk_enc_funcs;
685 enc10->base.ctx = init_data->ctx;
686 enc10->base.id = init_data->encoder;
688 enc10->base.hpd_source = init_data->hpd_source;
689 enc10->base.connector = init_data->connector;
691 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
693 enc10->base.features = *enc_features;
695 enc10->base.transmitter = init_data->transmitter;
697 /* set the flag to indicate whether driver poll the I2C data pin
698 * while doing the DP sink detect
701 /* if (dal_adapter_service_is_feature_supported(as,
702 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
703 enc10->base.features.flags.bits.
704 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
706 enc10->base.output_signals =
707 SIGNAL_TYPE_DVI_SINGLE_LINK |
708 SIGNAL_TYPE_DVI_DUAL_LINK |
710 SIGNAL_TYPE_DISPLAY_PORT |
711 SIGNAL_TYPE_DISPLAY_PORT_MST |
713 SIGNAL_TYPE_HDMI_TYPE_A;
715 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
716 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
717 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
718 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
719 * Prefer DIG assignment is decided by board design.
720 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
721 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
722 * By this, adding DIGG should not hurt DCE 8.0.
723 * This will let DCE 8.1 share DCE 8.0 as much as possible
726 enc10->link_regs = link_regs;
727 enc10->aux_regs = aux_regs;
728 enc10->hpd_regs = hpd_regs;
729 enc10->link_shift = link_shift;
730 enc10->link_mask = link_mask;
732 switch (enc10->base.transmitter) {
733 case TRANSMITTER_UNIPHY_A:
734 enc10->base.preferred_engine = ENGINE_ID_DIGA;
736 case TRANSMITTER_UNIPHY_B:
737 enc10->base.preferred_engine = ENGINE_ID_DIGB;
739 case TRANSMITTER_UNIPHY_C:
740 enc10->base.preferred_engine = ENGINE_ID_DIGC;
742 case TRANSMITTER_UNIPHY_D:
743 enc10->base.preferred_engine = ENGINE_ID_DIGD;
745 case TRANSMITTER_UNIPHY_E:
746 enc10->base.preferred_engine = ENGINE_ID_DIGE;
748 case TRANSMITTER_UNIPHY_F:
749 enc10->base.preferred_engine = ENGINE_ID_DIGF;
751 case TRANSMITTER_UNIPHY_G:
752 enc10->base.preferred_engine = ENGINE_ID_DIGG;
755 ASSERT_CRITICAL(false);
756 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
759 /* default to one to mirror Windows behavior */
760 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
762 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
763 enc10->base.id, &bp_cap_info);
765 /* Override features with DCE-specific values */
766 if (result == BP_RESULT_OK) {
767 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
768 bp_cap_info.DP_HBR2_EN;
769 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
770 bp_cap_info.DP_HBR3_EN;
771 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
772 enc10->base.features.flags.bits.DP_IS_USB_C =
773 bp_cap_info.DP_IS_USB_C;
775 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
779 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
780 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
784 bool dcn10_link_encoder_validate_output_with_stream(
785 struct link_encoder *enc,
786 const struct dc_stream_state *stream)
788 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
791 //if SCDC (340-600MHz) is disabled, set to HDMI 1.4 timing limit
792 if (stream->sink->edid_caps.panel_patch.skip_scdc_overwrite &&
793 enc10->base.features.max_hdmi_pixel_clock > 300000)
794 enc10->base.features.max_hdmi_pixel_clock = 300000;
796 switch (stream->signal) {
797 case SIGNAL_TYPE_DVI_SINGLE_LINK:
798 case SIGNAL_TYPE_DVI_DUAL_LINK:
799 is_valid = dcn10_link_encoder_validate_dvi_output(
801 stream->link->connector_signal,
805 case SIGNAL_TYPE_HDMI_TYPE_A:
806 is_valid = dcn10_link_encoder_validate_hdmi_output(
809 &stream->sink->edid_caps,
810 stream->phy_pix_clk * 10);
812 case SIGNAL_TYPE_DISPLAY_PORT:
813 case SIGNAL_TYPE_DISPLAY_PORT_MST:
814 is_valid = dcn10_link_encoder_validate_dp_output(
815 enc10, &stream->timing);
817 case SIGNAL_TYPE_EDP:
818 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
820 case SIGNAL_TYPE_VIRTUAL:
831 void dcn10_link_encoder_hw_init(
832 struct link_encoder *enc)
834 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
835 struct bp_transmitter_control cntl = { 0 };
836 enum bp_result result;
838 cntl.action = TRANSMITTER_CONTROL_INIT;
839 cntl.engine_id = ENGINE_ID_UNKNOWN;
840 cntl.transmitter = enc10->base.transmitter;
841 cntl.connector_obj_id = enc10->base.connector;
842 cntl.lanes_number = LANE_COUNT_FOUR;
843 cntl.coherent = false;
844 cntl.hpd_sel = enc10->base.hpd_source;
846 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
847 cntl.signal = SIGNAL_TYPE_EDP;
849 result = link_transmitter_control(enc10, &cntl);
851 if (result != BP_RESULT_OK) {
852 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
858 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
859 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
861 result = link_transmitter_control(enc10, &cntl);
863 ASSERT(result == BP_RESULT_OK);
866 dcn10_aux_initialize(enc10);
869 * hpd_initialize() will pass DIG_FE id to HW context.
870 * All other routine within HW context will use fe_engine_offset
871 * as DIG_FE id even caller pass DIG_FE id.
872 * So this routine must be called first.
874 hpd_initialize(enc10);
877 void dcn10_link_encoder_destroy(struct link_encoder **enc)
879 kfree(TO_DCN10_LINK_ENC(*enc));
883 void dcn10_link_encoder_setup(
884 struct link_encoder *enc,
885 enum signal_type signal)
887 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
890 case SIGNAL_TYPE_EDP:
891 case SIGNAL_TYPE_DISPLAY_PORT:
893 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
895 case SIGNAL_TYPE_LVDS:
897 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
899 case SIGNAL_TYPE_DVI_SINGLE_LINK:
900 case SIGNAL_TYPE_DVI_DUAL_LINK:
902 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
904 case SIGNAL_TYPE_HDMI_TYPE_A:
906 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
908 case SIGNAL_TYPE_DISPLAY_PORT_MST:
910 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
913 ASSERT_CRITICAL(false);
920 /* TODO: still need depth or just pass in adjusted pixel clock? */
921 void dcn10_link_encoder_enable_tmds_output(
922 struct link_encoder *enc,
923 enum clock_source_id clock_source,
924 enum dc_color_depth color_depth,
925 enum signal_type signal,
926 uint32_t pixel_clock)
928 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
929 struct bp_transmitter_control cntl = { 0 };
930 enum bp_result result;
934 cntl.action = TRANSMITTER_CONTROL_ENABLE;
935 cntl.engine_id = enc->preferred_engine;
936 cntl.transmitter = enc10->base.transmitter;
937 cntl.pll_id = clock_source;
938 cntl.signal = signal;
939 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
940 cntl.lanes_number = 8;
942 cntl.lanes_number = 4;
944 cntl.hpd_sel = enc10->base.hpd_source;
946 cntl.pixel_clock = pixel_clock;
947 cntl.color_depth = color_depth;
949 result = link_transmitter_control(enc10, &cntl);
951 if (result != BP_RESULT_OK) {
952 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
958 void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa(
959 struct link_encoder *enc,
960 enum clock_source_id clock_source,
961 enum dc_color_depth color_depth,
962 enum signal_type signal,
963 uint32_t pixel_clock)
965 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
967 dcn10_link_encoder_enable_tmds_output(
968 enc, clock_source, color_depth, signal, pixel_clock);
970 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
973 /* enables DP PHY output */
974 void dcn10_link_encoder_enable_dp_output(
975 struct link_encoder *enc,
976 const struct dc_link_settings *link_settings,
977 enum clock_source_id clock_source)
979 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
980 struct bp_transmitter_control cntl = { 0 };
981 enum bp_result result;
985 /* number_of_lanes is used for pixel clock adjust,
986 * but it's not passed to asic_control.
987 * We need to set number of lanes manually.
989 enc1_configure_encoder(enc10, link_settings);
991 cntl.action = TRANSMITTER_CONTROL_ENABLE;
992 cntl.engine_id = enc->preferred_engine;
993 cntl.transmitter = enc10->base.transmitter;
994 cntl.pll_id = clock_source;
995 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
996 cntl.lanes_number = link_settings->lane_count;
997 cntl.hpd_sel = enc10->base.hpd_source;
998 cntl.pixel_clock = link_settings->link_rate
999 * LINK_RATE_REF_FREQ_IN_KHZ;
1000 /* TODO: check if undefined works */
1001 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1003 result = link_transmitter_control(enc10, &cntl);
1005 if (result != BP_RESULT_OK) {
1006 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1008 BREAK_TO_DEBUGGER();
1012 /* enables DP PHY output in MST mode */
1013 void dcn10_link_encoder_enable_dp_mst_output(
1014 struct link_encoder *enc,
1015 const struct dc_link_settings *link_settings,
1016 enum clock_source_id clock_source)
1018 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1019 struct bp_transmitter_control cntl = { 0 };
1020 enum bp_result result;
1022 /* Enable the PHY */
1024 /* number_of_lanes is used for pixel clock adjust,
1025 * but it's not passed to asic_control.
1026 * We need to set number of lanes manually.
1028 enc1_configure_encoder(enc10, link_settings);
1030 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1031 cntl.engine_id = ENGINE_ID_UNKNOWN;
1032 cntl.transmitter = enc10->base.transmitter;
1033 cntl.pll_id = clock_source;
1034 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1035 cntl.lanes_number = link_settings->lane_count;
1036 cntl.hpd_sel = enc10->base.hpd_source;
1037 cntl.pixel_clock = link_settings->link_rate
1038 * LINK_RATE_REF_FREQ_IN_KHZ;
1039 /* TODO: check if undefined works */
1040 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1042 result = link_transmitter_control(enc10, &cntl);
1044 if (result != BP_RESULT_OK) {
1045 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1047 BREAK_TO_DEBUGGER();
1052 * Disable transmitter and its encoder
1054 void dcn10_link_encoder_disable_output(
1055 struct link_encoder *enc,
1056 enum signal_type signal)
1058 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1059 struct bp_transmitter_control cntl = { 0 };
1060 enum bp_result result;
1062 if (!dcn10_is_dig_enabled(enc)) {
1063 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1064 /*in DP_Alt_No_Connect case, we turn off the dig already,
1065 after excuation the PHY w/a sequence, not allow touch PHY any more*/
1068 /* Power-down RX and disable GPU PHY should be paired.
1069 * Disabling PHY without powering down RX may cause
1070 * symbol lock loss, on which we will get DP Sink interrupt.
1073 /* There is a case for the DP active dongles
1074 * where we want to disable the PHY but keep RX powered,
1075 * for those we need to ignore DP Sink interrupt
1076 * by checking lane count that has been set
1077 * on the last do_enable_output().
1080 /* disable transmitter */
1081 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1082 cntl.transmitter = enc10->base.transmitter;
1083 cntl.hpd_sel = enc10->base.hpd_source;
1084 cntl.signal = signal;
1085 cntl.connector_obj_id = enc10->base.connector;
1087 result = link_transmitter_control(enc10, &cntl);
1089 if (result != BP_RESULT_OK) {
1090 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1092 BREAK_TO_DEBUGGER();
1096 /* disable encoder */
1097 if (dc_is_dp_signal(signal))
1098 link_encoder_disable(enc10);
1101 void dcn10_link_encoder_dp_set_lane_settings(
1102 struct link_encoder *enc,
1103 const struct link_training_settings *link_settings)
1105 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1106 union dpcd_training_lane_set training_lane_set = { { 0 } };
1108 struct bp_transmitter_control cntl = { 0 };
1110 if (!link_settings) {
1111 BREAK_TO_DEBUGGER();
1115 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1116 cntl.transmitter = enc10->base.transmitter;
1117 cntl.connector_obj_id = enc10->base.connector;
1118 cntl.lanes_number = link_settings->link_settings.lane_count;
1119 cntl.hpd_sel = enc10->base.hpd_source;
1120 cntl.pixel_clock = link_settings->link_settings.link_rate *
1121 LINK_RATE_REF_FREQ_IN_KHZ;
1123 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1124 /* translate lane settings */
1126 training_lane_set.bits.VOLTAGE_SWING_SET =
1127 link_settings->lane_settings[lane].VOLTAGE_SWING;
1128 training_lane_set.bits.PRE_EMPHASIS_SET =
1129 link_settings->lane_settings[lane].PRE_EMPHASIS;
1131 /* post cursor 2 setting only applies to HBR2 link rate */
1132 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1133 /* this is passed to VBIOS
1134 * to program post cursor 2 level
1136 training_lane_set.bits.POST_CURSOR2_SET =
1137 link_settings->lane_settings[lane].POST_CURSOR2;
1140 cntl.lane_select = lane;
1141 cntl.lane_settings = training_lane_set.raw;
1143 /* call VBIOS table to set voltage swing and pre-emphasis */
1144 link_transmitter_control(enc10, &cntl);
1148 /* set DP PHY test and training patterns */
1149 void dcn10_link_encoder_dp_set_phy_pattern(
1150 struct link_encoder *enc,
1151 const struct encoder_set_dp_phy_pattern_param *param)
1153 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1155 switch (param->dp_phy_pattern) {
1156 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1157 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1159 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1160 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1162 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1163 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1165 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1166 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1168 case DP_TEST_PATTERN_D102:
1169 set_dp_phy_pattern_d102(enc10);
1171 case DP_TEST_PATTERN_SYMBOL_ERROR:
1172 set_dp_phy_pattern_symbol_error(enc10);
1174 case DP_TEST_PATTERN_PRBS7:
1175 set_dp_phy_pattern_prbs7(enc10);
1177 case DP_TEST_PATTERN_80BIT_CUSTOM:
1178 set_dp_phy_pattern_80bit_custom(
1179 enc10, param->custom_pattern);
1181 case DP_TEST_PATTERN_CP2520_1:
1182 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
1184 case DP_TEST_PATTERN_CP2520_2:
1185 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
1187 case DP_TEST_PATTERN_CP2520_3:
1188 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
1190 case DP_TEST_PATTERN_VIDEO_MODE: {
1191 set_dp_phy_pattern_passthrough_mode(
1192 enc10, param->dp_panel_mode);
1197 /* invalid phy pattern */
1198 ASSERT_CRITICAL(false);
1203 static void fill_stream_allocation_row_info(
1204 const struct link_mst_stream_allocation *stream_allocation,
1208 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1211 *src = stream_enc->id;
1212 *slots = stream_allocation->slot_count;
1219 /* programs DP MST VC payload allocation */
1220 void dcn10_link_encoder_update_mst_stream_allocation_table(
1221 struct link_encoder *enc,
1222 const struct link_mst_stream_allocation_table *table)
1224 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1225 uint32_t value0 = 0;
1226 uint32_t value1 = 0;
1227 uint32_t value2 = 0;
1230 uint32_t retries = 0;
1232 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1234 /* --- Set MSE Stream Attribute -
1235 * Setup VC Payload Table on Tx Side,
1236 * Issue allocation change trigger
1237 * to commit payload on both tx and rx side
1240 /* we should clean-up table each time */
1242 if (table->stream_count >= 1) {
1243 fill_stream_allocation_row_info(
1244 &table->stream_allocations[0],
1252 REG_UPDATE_2(DP_MSE_SAT0,
1253 DP_MSE_SAT_SRC0, src,
1254 DP_MSE_SAT_SLOT_COUNT0, slots);
1256 if (table->stream_count >= 2) {
1257 fill_stream_allocation_row_info(
1258 &table->stream_allocations[1],
1266 REG_UPDATE_2(DP_MSE_SAT0,
1267 DP_MSE_SAT_SRC1, src,
1268 DP_MSE_SAT_SLOT_COUNT1, slots);
1270 if (table->stream_count >= 3) {
1271 fill_stream_allocation_row_info(
1272 &table->stream_allocations[2],
1280 REG_UPDATE_2(DP_MSE_SAT1,
1281 DP_MSE_SAT_SRC2, src,
1282 DP_MSE_SAT_SLOT_COUNT2, slots);
1284 if (table->stream_count >= 4) {
1285 fill_stream_allocation_row_info(
1286 &table->stream_allocations[3],
1294 REG_UPDATE_2(DP_MSE_SAT1,
1295 DP_MSE_SAT_SRC3, src,
1296 DP_MSE_SAT_SLOT_COUNT3, slots);
1298 /* --- wait for transaction finish */
1300 /* send allocation change trigger (ACT) ?
1301 * this step first sends the ACT,
1302 * then double buffers the SAT into the hardware
1303 * making the new allocation active on the DP MST mode link
1306 /* DP_MSE_SAT_UPDATE:
1308 * 1 - Update SAT with trigger
1309 * 2 - Update SAT without trigger
1311 REG_UPDATE(DP_MSE_SAT_UPDATE,
1312 DP_MSE_SAT_UPDATE, 1);
1314 /* wait for update to complete
1315 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1316 * then wait for the transmission
1317 * of at least 16 MTP headers on immediate local link.
1318 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1319 * a value of 1 indicates that DP MST mode
1320 * is in the 16 MTP keepout region after a VC has been added.
1321 * MST stream bandwidth (VC rate) can be configured
1322 * after this bit is cleared
1327 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1329 REG_GET(DP_MSE_SAT_UPDATE,
1330 DP_MSE_SAT_UPDATE, &value1);
1332 REG_GET(DP_MSE_SAT_UPDATE,
1333 DP_MSE_16_MTP_KEEPOUT, &value2);
1335 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1336 if (!value1 && !value2)
1339 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1342 void dcn10_link_encoder_connect_dig_be_to_fe(
1343 struct link_encoder *enc,
1344 enum engine_id engine,
1347 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1350 if (engine != ENGINE_ID_UNKNOWN) {
1352 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1355 field |= get_frontend_source(engine);
1357 field &= ~get_frontend_source(engine);
1359 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1364 #define HPD_REG(reg)\
1365 (enc10->hpd_regs->reg)
1367 #define HPD_REG_READ(reg_name) \
1368 dm_read_reg(CTX, HPD_REG(reg_name))
1370 #define HPD_REG_UPDATE_N(reg_name, n, ...) \
1371 generic_reg_update_ex(CTX, \
1372 HPD_REG(reg_name), \
1375 #define HPD_REG_UPDATE(reg_name, field, val) \
1376 HPD_REG_UPDATE_N(reg_name, 1, \
1377 FN(reg_name, field), val)
1379 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1381 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1383 HPD_REG_UPDATE(DC_HPD_CONTROL,
1387 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1389 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1391 HPD_REG_UPDATE(DC_HPD_CONTROL,
1395 #define AUX_REG(reg)\
1396 (enc10->aux_regs->reg)
1398 #define AUX_REG_READ(reg_name) \
1399 dm_read_reg(CTX, AUX_REG(reg_name))
1401 #define AUX_REG_UPDATE_N(reg_name, n, ...) \
1402 generic_reg_update_ex(CTX, \
1403 AUX_REG(reg_name), \
1406 #define AUX_REG_UPDATE(reg_name, field, val) \
1407 AUX_REG_UPDATE_N(reg_name, 1, \
1408 FN(reg_name, field), val)
1410 #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
1411 AUX_REG_UPDATE_N(reg, 2,\
1415 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
1417 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1419 AUX_REG_UPDATE_2(AUX_CONTROL,
1420 AUX_HPD_SEL, hpd_source,
1423 /* 1/4 window (the maximum allowed) */
1424 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1425 AUX_RX_RECEIVE_WINDOW, 0);
1428 enum signal_type dcn10_get_dig_mode(
1429 struct link_encoder *enc)
1431 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1433 REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
1436 return SIGNAL_TYPE_DISPLAY_PORT;
1438 return SIGNAL_TYPE_DVI_SINGLE_LINK;
1440 return SIGNAL_TYPE_HDMI_TYPE_A;
1442 return SIGNAL_TYPE_DISPLAY_PORT_MST;
1444 return SIGNAL_TYPE_NONE;
1446 return SIGNAL_TYPE_NONE;
1449 void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
1450 struct dc_link_settings *link_settings)
1452 /* Set Default link settings */
1453 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1454 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
1456 /* Higher link settings based on feature supported */
1457 if (enc->features.flags.bits.IS_HBR2_CAPABLE)
1458 max_link_cap.link_rate = LINK_RATE_HIGH2;
1460 if (enc->features.flags.bits.IS_HBR3_CAPABLE)
1461 max_link_cap.link_rate = LINK_RATE_HIGH3;
1463 *link_settings = max_link_cap;