2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/delay.h>
27 #include <linux/slab.h>
29 #include "reg_helper.h"
31 #include "core_types.h"
32 #include "link_encoder.h"
33 #include "dcn10_link_encoder.h"
34 #include "stream_encoder.h"
35 #include "i2caux_interface.h"
36 #include "dc_bios_types.h"
38 #include "gpio_service_interface.h"
43 enc10->base.ctx->logger
46 (enc10->link_regs->reg)
49 #define FN(reg_name, field_name) \
50 enc10->link_shift->field_name, enc10->link_mask->field_name
55 * Trigger Source Select
56 * ASIC-dependent, actual values for register programming
58 #define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
59 #define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
60 #define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
61 #define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
62 #define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
63 #define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
64 #define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
65 #define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
68 DP_MST_UPDATE_MAX_RETRY = 50
71 static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
72 .validate_output_with_stream =
73 dcn10_link_encoder_validate_output_with_stream,
74 .hw_init = dcn10_link_encoder_hw_init,
75 .setup = dcn10_link_encoder_setup,
76 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
77 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
78 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
79 .disable_output = dcn10_link_encoder_disable_output,
80 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
81 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
82 .update_mst_stream_allocation_table =
83 dcn10_link_encoder_update_mst_stream_allocation_table,
84 .psr_program_dp_dphy_fast_training =
85 dcn10_psr_program_dp_dphy_fast_training,
86 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
87 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
88 .enable_hpd = dcn10_link_encoder_enable_hpd,
89 .disable_hpd = dcn10_link_encoder_disable_hpd,
90 .is_dig_enabled = dcn10_is_dig_enabled,
91 .get_dig_frontend = dcn10_get_dig_frontend,
92 .get_dig_mode = dcn10_get_dig_mode,
93 .destroy = dcn10_link_encoder_destroy,
94 .get_max_link_cap = dcn10_link_encoder_get_max_link_cap,
97 static enum bp_result link_transmitter_control(
98 struct dcn10_link_encoder *enc10,
99 struct bp_transmitter_control *cntl)
101 enum bp_result result;
102 struct dc_bios *bp = enc10->base.ctx->dc_bios;
104 result = bp->funcs->transmitter_control(bp, cntl);
109 static void enable_phy_bypass_mode(
110 struct dcn10_link_encoder *enc10,
113 /* This register resides in DP back end block;
114 * transmitter is used for the offset
116 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
120 static void disable_prbs_symbols(
121 struct dcn10_link_encoder *enc10,
124 /* This register resides in DP back end block;
125 * transmitter is used for the offset
127 REG_UPDATE_4(DP_DPHY_CNTL,
128 DPHY_ATEST_SEL_LANE0, disable,
129 DPHY_ATEST_SEL_LANE1, disable,
130 DPHY_ATEST_SEL_LANE2, disable,
131 DPHY_ATEST_SEL_LANE3, disable);
134 static void disable_prbs_mode(
135 struct dcn10_link_encoder *enc10)
137 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
140 static void program_pattern_symbols(
141 struct dcn10_link_encoder *enc10,
142 uint16_t pattern_symbols[8])
144 /* This register resides in DP back end block;
145 * transmitter is used for the offset
147 REG_SET_3(DP_DPHY_SYM0, 0,
148 DPHY_SYM1, pattern_symbols[0],
149 DPHY_SYM2, pattern_symbols[1],
150 DPHY_SYM3, pattern_symbols[2]);
152 /* This register resides in DP back end block;
153 * transmitter is used for the offset
155 REG_SET_3(DP_DPHY_SYM1, 0,
156 DPHY_SYM4, pattern_symbols[3],
157 DPHY_SYM5, pattern_symbols[4],
158 DPHY_SYM6, pattern_symbols[5]);
160 /* This register resides in DP back end block;
161 * transmitter is used for the offset
163 REG_SET_2(DP_DPHY_SYM2, 0,
164 DPHY_SYM7, pattern_symbols[6],
165 DPHY_SYM8, pattern_symbols[7]);
168 static void set_dp_phy_pattern_d102(
169 struct dcn10_link_encoder *enc10)
171 /* Disable PHY Bypass mode to setup the test pattern */
172 enable_phy_bypass_mode(enc10, false);
174 /* For 10-bit PRBS or debug symbols
175 * please use the following sequence:
177 * Enable debug symbols on the lanes
179 disable_prbs_symbols(enc10, true);
181 /* Disable PRBS mode */
182 disable_prbs_mode(enc10);
184 /* Program debug symbols to be output */
186 uint16_t pattern_symbols[8] = {
187 0x2AA, 0x2AA, 0x2AA, 0x2AA,
188 0x2AA, 0x2AA, 0x2AA, 0x2AA
191 program_pattern_symbols(enc10, pattern_symbols);
194 /* Enable phy bypass mode to enable the test pattern */
196 enable_phy_bypass_mode(enc10, true);
199 static void set_link_training_complete(
200 struct dcn10_link_encoder *enc10,
203 /* This register resides in DP back end block;
204 * transmitter is used for the offset
206 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
210 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
211 struct link_encoder *enc,
214 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
215 /* Write Training Pattern */
217 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
219 /* Set HW Register Training Complete to false */
221 set_link_training_complete(enc10, false);
223 /* Disable PHY Bypass mode to output Training Pattern */
225 enable_phy_bypass_mode(enc10, false);
227 /* Disable PRBS mode */
228 disable_prbs_mode(enc10);
231 static void setup_panel_mode(
232 struct dcn10_link_encoder *enc10,
233 enum dp_panel_mode panel_mode)
237 if (!REG(DP_DPHY_INTERNAL_CTRL))
240 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
242 switch (panel_mode) {
243 case DP_PANEL_MODE_EDP:
246 case DP_PANEL_MODE_SPECIAL:
254 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
257 static void set_dp_phy_pattern_symbol_error(
258 struct dcn10_link_encoder *enc10)
260 /* Disable PHY Bypass mode to setup the test pattern */
261 enable_phy_bypass_mode(enc10, false);
263 /* program correct panel mode*/
264 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
266 /* A PRBS23 pattern is used for most DP electrical measurements. */
268 /* Enable PRBS symbols on the lanes */
269 disable_prbs_symbols(enc10, false);
271 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
272 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
276 /* Enable phy bypass mode to enable the test pattern */
277 enable_phy_bypass_mode(enc10, true);
280 static void set_dp_phy_pattern_prbs7(
281 struct dcn10_link_encoder *enc10)
283 /* Disable PHY Bypass mode to setup the test pattern */
284 enable_phy_bypass_mode(enc10, false);
286 /* A PRBS7 pattern is used for most DP electrical measurements. */
288 /* Enable PRBS symbols on the lanes */
289 disable_prbs_symbols(enc10, false);
291 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
292 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
296 /* Enable phy bypass mode to enable the test pattern */
297 enable_phy_bypass_mode(enc10, true);
300 static void set_dp_phy_pattern_80bit_custom(
301 struct dcn10_link_encoder *enc10,
302 const uint8_t *pattern)
304 /* Disable PHY Bypass mode to setup the test pattern */
305 enable_phy_bypass_mode(enc10, false);
307 /* Enable debug symbols on the lanes */
309 disable_prbs_symbols(enc10, true);
311 /* Enable PHY bypass mode to enable the test pattern */
312 /* TODO is it really needed ? */
314 enable_phy_bypass_mode(enc10, true);
316 /* Program 80 bit custom pattern */
318 uint16_t pattern_symbols[8];
321 ((pattern[1] & 0x03) << 8) | pattern[0];
323 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
325 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
327 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
329 ((pattern[6] & 0x03) << 8) | pattern[5];
331 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
333 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
335 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
337 program_pattern_symbols(enc10, pattern_symbols);
340 /* Enable phy bypass mode to enable the test pattern */
342 enable_phy_bypass_mode(enc10, true);
345 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
346 struct dcn10_link_encoder *enc10,
347 unsigned int cp2520_pattern)
350 /* previously there is a register DP_HBR2_EYE_PATTERN
351 * that is enabled to get the pattern.
352 * But it does not work with the latest spec change,
353 * so we are programming the following registers manually.
355 * The following settings have been confirmed
356 * by Nick Chorney and Sandra Liu
359 /* Disable PHY Bypass mode to setup the test pattern */
361 enable_phy_bypass_mode(enc10, false);
363 /* Setup DIG encoder in DP SST mode */
364 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
366 /* ensure normal panel mode. */
367 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
369 /* no vbid after BS (SR)
370 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
371 * 11000260 / 11000104 / 110000FC
373 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
374 DP_IDLE_BS_INTERVAL, 0xFC,
376 DP_VID_ENHANCED_FRAME_MODE, 1);
378 /* swap every BS with SR */
379 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
381 /* select cp2520 patterns */
382 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
383 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
384 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
386 /* pre-DCE11 can only generate CP2520 pattern 2 */
387 ASSERT(cp2520_pattern == 2);
389 /* set link training complete */
390 set_link_training_complete(enc10, true);
392 /* disable video stream */
393 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
395 /* Disable PHY Bypass mode to setup the test pattern */
396 enable_phy_bypass_mode(enc10, false);
399 static void set_dp_phy_pattern_passthrough_mode(
400 struct dcn10_link_encoder *enc10,
401 enum dp_panel_mode panel_mode)
403 /* program correct panel mode */
404 setup_panel_mode(enc10, panel_mode);
406 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
407 * in case we were doing HBR2 compliance pattern before
409 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
410 DP_IDLE_BS_INTERVAL, 0x2000,
412 DP_VID_ENHANCED_FRAME_MODE, 1);
414 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
416 /* set link training complete */
417 set_link_training_complete(enc10, true);
419 /* Disable PHY Bypass mode to setup the test pattern */
420 enable_phy_bypass_mode(enc10, false);
422 /* Disable PRBS mode */
423 disable_prbs_mode(enc10);
426 /* return value is bit-vector */
427 static uint8_t get_frontend_source(
428 enum engine_id engine)
432 return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
434 return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
436 return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
438 return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
440 return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
442 return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
444 return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
446 ASSERT_CRITICAL(false);
447 return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
451 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
453 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
455 enum engine_id result;
457 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
460 case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
461 result = ENGINE_ID_DIGA;
463 case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
464 result = ENGINE_ID_DIGB;
466 case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
467 result = ENGINE_ID_DIGC;
469 case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
470 result = ENGINE_ID_DIGD;
472 case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
473 result = ENGINE_ID_DIGE;
475 case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
476 result = ENGINE_ID_DIGF;
478 case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
479 result = ENGINE_ID_DIGG;
482 // invalid source select DIG
484 result = ENGINE_ID_UNKNOWN;
491 void enc1_configure_encoder(
492 struct dcn10_link_encoder *enc10,
493 const struct dc_link_settings *link_settings)
495 /* set number of lanes */
496 REG_SET(DP_CONFIG, 0,
497 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
499 /* setup scrambler */
500 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
503 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
504 bool exit_link_training_required)
506 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
508 if (exit_link_training_required)
509 REG_UPDATE(DP_DPHY_FAST_TRAINING,
510 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
512 REG_UPDATE(DP_DPHY_FAST_TRAINING,
513 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
514 /*In DCE 11, we are able to pre-program a Force SR register
515 * to be able to trigger SR symbol after 5 idle patterns
516 * transmitted. Upon PSR Exit, DMCU can trigger
517 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
518 * DPHY_LOAD_BS_COUNT_START and the internal counter
519 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
520 * replaced by SR symbol once.
523 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
527 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
528 unsigned int sdp_transmit_line_num_deadline)
530 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
532 REG_UPDATE_2(DP_SEC_CNTL1,
533 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
534 DP_SEC_GSP0_PRIORITY, 1);
537 bool dcn10_is_dig_enabled(struct link_encoder *enc)
539 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
542 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
546 static void link_encoder_disable(struct dcn10_link_encoder *enc10)
548 /* reset training pattern */
549 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
550 DPHY_TRAINING_PATTERN_SEL, 0);
552 /* reset training complete */
553 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
555 /* reset panel mode */
556 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
559 static void hpd_initialize(
560 struct dcn10_link_encoder *enc10)
562 /* Associate HPD with DIG_BE */
563 enum hpd_source_id hpd_source = enc10->base.hpd_source;
565 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
568 bool dcn10_link_encoder_validate_dvi_output(
569 const struct dcn10_link_encoder *enc10,
570 enum signal_type connector_signal,
571 enum signal_type signal,
572 const struct dc_crtc_timing *crtc_timing)
574 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
576 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
577 max_pixel_clock *= 2;
579 /* This handles the case of HDMI downgrade to DVI we don't want to
580 * we don't want to cap the pixel clock if the DDI is not DVI.
582 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
583 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
584 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
586 /* DVI only support RGB pixel encoding */
587 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
590 /*connect DVI via adpater's HDMI connector*/
591 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
592 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
593 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
594 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
596 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
599 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
602 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
603 switch (crtc_timing->display_color_depth) {
604 case COLOR_DEPTH_666:
605 case COLOR_DEPTH_888:
607 case COLOR_DEPTH_101010:
608 case COLOR_DEPTH_161616:
609 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
619 static bool dcn10_link_encoder_validate_hdmi_output(
620 const struct dcn10_link_encoder *enc10,
621 const struct dc_crtc_timing *crtc_timing,
622 const struct dc_edid_caps *edid_caps,
623 int adjusted_pix_clk_100hz)
625 enum dc_color_depth max_deep_color =
626 enc10->base.features.max_hdmi_deep_color;
628 // check pixel clock against edid specified max TMDS clk
629 if (edid_caps->max_tmds_clk_mhz != 0 &&
630 adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
633 if (max_deep_color < crtc_timing->display_color_depth)
636 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
638 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
641 if ((adjusted_pix_clk_100hz == 0) ||
642 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
645 /* DCE11 HW does not support 420 */
646 if (!enc10->base.features.hdmi_ycbcr420_supported &&
647 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
650 if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
651 adjusted_pix_clk_100hz >= 3000000)
653 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
654 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
659 bool dcn10_link_encoder_validate_dp_output(
660 const struct dcn10_link_encoder *enc10,
661 const struct dc_crtc_timing *crtc_timing)
663 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
664 if (!enc10->base.features.dp_ycbcr420_supported)
671 void dcn10_link_encoder_construct(
672 struct dcn10_link_encoder *enc10,
673 const struct encoder_init_data *init_data,
674 const struct encoder_feature_support *enc_features,
675 const struct dcn10_link_enc_registers *link_regs,
676 const struct dcn10_link_enc_aux_registers *aux_regs,
677 const struct dcn10_link_enc_hpd_registers *hpd_regs,
678 const struct dcn10_link_enc_shift *link_shift,
679 const struct dcn10_link_enc_mask *link_mask)
681 struct bp_encoder_cap_info bp_cap_info = {0};
682 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
683 enum bp_result result = BP_RESULT_OK;
685 enc10->base.funcs = &dcn10_lnk_enc_funcs;
686 enc10->base.ctx = init_data->ctx;
687 enc10->base.id = init_data->encoder;
689 enc10->base.hpd_source = init_data->hpd_source;
690 enc10->base.connector = init_data->connector;
692 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
694 enc10->base.features = *enc_features;
696 enc10->base.transmitter = init_data->transmitter;
698 /* set the flag to indicate whether driver poll the I2C data pin
699 * while doing the DP sink detect
702 /* if (dal_adapter_service_is_feature_supported(as,
703 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
704 enc10->base.features.flags.bits.
705 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
707 enc10->base.output_signals =
708 SIGNAL_TYPE_DVI_SINGLE_LINK |
709 SIGNAL_TYPE_DVI_DUAL_LINK |
711 SIGNAL_TYPE_DISPLAY_PORT |
712 SIGNAL_TYPE_DISPLAY_PORT_MST |
714 SIGNAL_TYPE_HDMI_TYPE_A;
716 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
717 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
718 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
719 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
720 * Prefer DIG assignment is decided by board design.
721 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
722 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
723 * By this, adding DIGG should not hurt DCE 8.0.
724 * This will let DCE 8.1 share DCE 8.0 as much as possible
727 enc10->link_regs = link_regs;
728 enc10->aux_regs = aux_regs;
729 enc10->hpd_regs = hpd_regs;
730 enc10->link_shift = link_shift;
731 enc10->link_mask = link_mask;
733 switch (enc10->base.transmitter) {
734 case TRANSMITTER_UNIPHY_A:
735 enc10->base.preferred_engine = ENGINE_ID_DIGA;
737 case TRANSMITTER_UNIPHY_B:
738 enc10->base.preferred_engine = ENGINE_ID_DIGB;
740 case TRANSMITTER_UNIPHY_C:
741 enc10->base.preferred_engine = ENGINE_ID_DIGC;
743 case TRANSMITTER_UNIPHY_D:
744 enc10->base.preferred_engine = ENGINE_ID_DIGD;
746 case TRANSMITTER_UNIPHY_E:
747 enc10->base.preferred_engine = ENGINE_ID_DIGE;
749 case TRANSMITTER_UNIPHY_F:
750 enc10->base.preferred_engine = ENGINE_ID_DIGF;
752 case TRANSMITTER_UNIPHY_G:
753 enc10->base.preferred_engine = ENGINE_ID_DIGG;
756 ASSERT_CRITICAL(false);
757 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
760 /* default to one to mirror Windows behavior */
761 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
763 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
764 enc10->base.id, &bp_cap_info);
766 /* Override features with DCE-specific values */
767 if (result == BP_RESULT_OK) {
768 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
769 bp_cap_info.DP_HBR2_EN;
770 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
771 bp_cap_info.DP_HBR3_EN;
772 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
773 enc10->base.features.flags.bits.DP_IS_USB_C =
774 bp_cap_info.DP_IS_USB_C;
776 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
780 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
781 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
785 bool dcn10_link_encoder_validate_output_with_stream(
786 struct link_encoder *enc,
787 const struct dc_stream_state *stream)
789 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
792 //if SCDC (340-600MHz) is disabled, set to HDMI 1.4 timing limit
793 if (stream->sink->edid_caps.panel_patch.skip_scdc_overwrite &&
794 enc10->base.features.max_hdmi_pixel_clock > 300000)
795 enc10->base.features.max_hdmi_pixel_clock = 300000;
797 switch (stream->signal) {
798 case SIGNAL_TYPE_DVI_SINGLE_LINK:
799 case SIGNAL_TYPE_DVI_DUAL_LINK:
800 is_valid = dcn10_link_encoder_validate_dvi_output(
802 stream->link->connector_signal,
806 case SIGNAL_TYPE_HDMI_TYPE_A:
807 is_valid = dcn10_link_encoder_validate_hdmi_output(
810 &stream->sink->edid_caps,
811 stream->phy_pix_clk * 10);
813 case SIGNAL_TYPE_DISPLAY_PORT:
814 case SIGNAL_TYPE_DISPLAY_PORT_MST:
815 is_valid = dcn10_link_encoder_validate_dp_output(
816 enc10, &stream->timing);
818 case SIGNAL_TYPE_EDP:
819 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
821 case SIGNAL_TYPE_VIRTUAL:
832 void dcn10_link_encoder_hw_init(
833 struct link_encoder *enc)
835 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
836 struct bp_transmitter_control cntl = { 0 };
837 enum bp_result result;
839 cntl.action = TRANSMITTER_CONTROL_INIT;
840 cntl.engine_id = ENGINE_ID_UNKNOWN;
841 cntl.transmitter = enc10->base.transmitter;
842 cntl.connector_obj_id = enc10->base.connector;
843 cntl.lanes_number = LANE_COUNT_FOUR;
844 cntl.coherent = false;
845 cntl.hpd_sel = enc10->base.hpd_source;
847 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
848 cntl.signal = SIGNAL_TYPE_EDP;
850 result = link_transmitter_control(enc10, &cntl);
852 if (result != BP_RESULT_OK) {
853 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
859 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
860 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
862 result = link_transmitter_control(enc10, &cntl);
864 ASSERT(result == BP_RESULT_OK);
867 dcn10_aux_initialize(enc10);
870 * hpd_initialize() will pass DIG_FE id to HW context.
871 * All other routine within HW context will use fe_engine_offset
872 * as DIG_FE id even caller pass DIG_FE id.
873 * So this routine must be called first.
875 hpd_initialize(enc10);
878 void dcn10_link_encoder_destroy(struct link_encoder **enc)
880 kfree(TO_DCN10_LINK_ENC(*enc));
884 void dcn10_link_encoder_setup(
885 struct link_encoder *enc,
886 enum signal_type signal)
888 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
891 case SIGNAL_TYPE_EDP:
892 case SIGNAL_TYPE_DISPLAY_PORT:
894 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
896 case SIGNAL_TYPE_LVDS:
898 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
900 case SIGNAL_TYPE_DVI_SINGLE_LINK:
901 case SIGNAL_TYPE_DVI_DUAL_LINK:
903 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
905 case SIGNAL_TYPE_HDMI_TYPE_A:
907 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
909 case SIGNAL_TYPE_DISPLAY_PORT_MST:
911 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
914 ASSERT_CRITICAL(false);
921 /* TODO: still need depth or just pass in adjusted pixel clock? */
922 void dcn10_link_encoder_enable_tmds_output(
923 struct link_encoder *enc,
924 enum clock_source_id clock_source,
925 enum dc_color_depth color_depth,
926 enum signal_type signal,
927 uint32_t pixel_clock)
929 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
930 struct bp_transmitter_control cntl = { 0 };
931 enum bp_result result;
935 cntl.action = TRANSMITTER_CONTROL_ENABLE;
936 cntl.engine_id = enc->preferred_engine;
937 cntl.transmitter = enc10->base.transmitter;
938 cntl.pll_id = clock_source;
939 cntl.signal = signal;
940 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
941 cntl.lanes_number = 8;
943 cntl.lanes_number = 4;
945 cntl.hpd_sel = enc10->base.hpd_source;
947 cntl.pixel_clock = pixel_clock;
948 cntl.color_depth = color_depth;
950 result = link_transmitter_control(enc10, &cntl);
952 if (result != BP_RESULT_OK) {
953 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
959 void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa(
960 struct link_encoder *enc,
961 enum clock_source_id clock_source,
962 enum dc_color_depth color_depth,
963 enum signal_type signal,
964 uint32_t pixel_clock)
966 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
968 dcn10_link_encoder_enable_tmds_output(
969 enc, clock_source, color_depth, signal, pixel_clock);
971 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
974 /* enables DP PHY output */
975 void dcn10_link_encoder_enable_dp_output(
976 struct link_encoder *enc,
977 const struct dc_link_settings *link_settings,
978 enum clock_source_id clock_source)
980 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
981 struct bp_transmitter_control cntl = { 0 };
982 enum bp_result result;
986 /* number_of_lanes is used for pixel clock adjust,
987 * but it's not passed to asic_control.
988 * We need to set number of lanes manually.
990 enc1_configure_encoder(enc10, link_settings);
992 cntl.action = TRANSMITTER_CONTROL_ENABLE;
993 cntl.engine_id = enc->preferred_engine;
994 cntl.transmitter = enc10->base.transmitter;
995 cntl.pll_id = clock_source;
996 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
997 cntl.lanes_number = link_settings->lane_count;
998 cntl.hpd_sel = enc10->base.hpd_source;
999 cntl.pixel_clock = link_settings->link_rate
1000 * LINK_RATE_REF_FREQ_IN_KHZ;
1001 /* TODO: check if undefined works */
1002 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1004 result = link_transmitter_control(enc10, &cntl);
1006 if (result != BP_RESULT_OK) {
1007 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1009 BREAK_TO_DEBUGGER();
1013 /* enables DP PHY output in MST mode */
1014 void dcn10_link_encoder_enable_dp_mst_output(
1015 struct link_encoder *enc,
1016 const struct dc_link_settings *link_settings,
1017 enum clock_source_id clock_source)
1019 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1020 struct bp_transmitter_control cntl = { 0 };
1021 enum bp_result result;
1023 /* Enable the PHY */
1025 /* number_of_lanes is used for pixel clock adjust,
1026 * but it's not passed to asic_control.
1027 * We need to set number of lanes manually.
1029 enc1_configure_encoder(enc10, link_settings);
1031 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1032 cntl.engine_id = ENGINE_ID_UNKNOWN;
1033 cntl.transmitter = enc10->base.transmitter;
1034 cntl.pll_id = clock_source;
1035 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1036 cntl.lanes_number = link_settings->lane_count;
1037 cntl.hpd_sel = enc10->base.hpd_source;
1038 cntl.pixel_clock = link_settings->link_rate
1039 * LINK_RATE_REF_FREQ_IN_KHZ;
1040 /* TODO: check if undefined works */
1041 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1043 result = link_transmitter_control(enc10, &cntl);
1045 if (result != BP_RESULT_OK) {
1046 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1048 BREAK_TO_DEBUGGER();
1053 * Disable transmitter and its encoder
1055 void dcn10_link_encoder_disable_output(
1056 struct link_encoder *enc,
1057 enum signal_type signal)
1059 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1060 struct bp_transmitter_control cntl = { 0 };
1061 enum bp_result result;
1063 if (!dcn10_is_dig_enabled(enc)) {
1064 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1065 /*in DP_Alt_No_Connect case, we turn off the dig already,
1066 after excuation the PHY w/a sequence, not allow touch PHY any more*/
1069 /* Power-down RX and disable GPU PHY should be paired.
1070 * Disabling PHY without powering down RX may cause
1071 * symbol lock loss, on which we will get DP Sink interrupt.
1074 /* There is a case for the DP active dongles
1075 * where we want to disable the PHY but keep RX powered,
1076 * for those we need to ignore DP Sink interrupt
1077 * by checking lane count that has been set
1078 * on the last do_enable_output().
1081 /* disable transmitter */
1082 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1083 cntl.transmitter = enc10->base.transmitter;
1084 cntl.hpd_sel = enc10->base.hpd_source;
1085 cntl.signal = signal;
1086 cntl.connector_obj_id = enc10->base.connector;
1088 result = link_transmitter_control(enc10, &cntl);
1090 if (result != BP_RESULT_OK) {
1091 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1093 BREAK_TO_DEBUGGER();
1097 /* disable encoder */
1098 if (dc_is_dp_signal(signal))
1099 link_encoder_disable(enc10);
1102 void dcn10_link_encoder_dp_set_lane_settings(
1103 struct link_encoder *enc,
1104 const struct link_training_settings *link_settings)
1106 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1107 union dpcd_training_lane_set training_lane_set = { { 0 } };
1109 struct bp_transmitter_control cntl = { 0 };
1111 if (!link_settings) {
1112 BREAK_TO_DEBUGGER();
1116 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1117 cntl.transmitter = enc10->base.transmitter;
1118 cntl.connector_obj_id = enc10->base.connector;
1119 cntl.lanes_number = link_settings->link_settings.lane_count;
1120 cntl.hpd_sel = enc10->base.hpd_source;
1121 cntl.pixel_clock = link_settings->link_settings.link_rate *
1122 LINK_RATE_REF_FREQ_IN_KHZ;
1124 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1125 /* translate lane settings */
1127 training_lane_set.bits.VOLTAGE_SWING_SET =
1128 link_settings->lane_settings[lane].VOLTAGE_SWING;
1129 training_lane_set.bits.PRE_EMPHASIS_SET =
1130 link_settings->lane_settings[lane].PRE_EMPHASIS;
1132 /* post cursor 2 setting only applies to HBR2 link rate */
1133 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1134 /* this is passed to VBIOS
1135 * to program post cursor 2 level
1137 training_lane_set.bits.POST_CURSOR2_SET =
1138 link_settings->lane_settings[lane].POST_CURSOR2;
1141 cntl.lane_select = lane;
1142 cntl.lane_settings = training_lane_set.raw;
1144 /* call VBIOS table to set voltage swing and pre-emphasis */
1145 link_transmitter_control(enc10, &cntl);
1149 /* set DP PHY test and training patterns */
1150 void dcn10_link_encoder_dp_set_phy_pattern(
1151 struct link_encoder *enc,
1152 const struct encoder_set_dp_phy_pattern_param *param)
1154 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1156 switch (param->dp_phy_pattern) {
1157 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1158 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1160 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1161 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1163 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1164 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1166 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1167 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1169 case DP_TEST_PATTERN_D102:
1170 set_dp_phy_pattern_d102(enc10);
1172 case DP_TEST_PATTERN_SYMBOL_ERROR:
1173 set_dp_phy_pattern_symbol_error(enc10);
1175 case DP_TEST_PATTERN_PRBS7:
1176 set_dp_phy_pattern_prbs7(enc10);
1178 case DP_TEST_PATTERN_80BIT_CUSTOM:
1179 set_dp_phy_pattern_80bit_custom(
1180 enc10, param->custom_pattern);
1182 case DP_TEST_PATTERN_CP2520_1:
1183 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
1185 case DP_TEST_PATTERN_CP2520_2:
1186 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
1188 case DP_TEST_PATTERN_CP2520_3:
1189 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
1191 case DP_TEST_PATTERN_VIDEO_MODE: {
1192 set_dp_phy_pattern_passthrough_mode(
1193 enc10, param->dp_panel_mode);
1198 /* invalid phy pattern */
1199 ASSERT_CRITICAL(false);
1204 static void fill_stream_allocation_row_info(
1205 const struct link_mst_stream_allocation *stream_allocation,
1209 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1212 *src = stream_enc->id;
1213 *slots = stream_allocation->slot_count;
1220 /* programs DP MST VC payload allocation */
1221 void dcn10_link_encoder_update_mst_stream_allocation_table(
1222 struct link_encoder *enc,
1223 const struct link_mst_stream_allocation_table *table)
1225 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1226 uint32_t value0 = 0;
1227 uint32_t value1 = 0;
1228 uint32_t value2 = 0;
1231 uint32_t retries = 0;
1233 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1235 /* --- Set MSE Stream Attribute -
1236 * Setup VC Payload Table on Tx Side,
1237 * Issue allocation change trigger
1238 * to commit payload on both tx and rx side
1241 /* we should clean-up table each time */
1243 if (table->stream_count >= 1) {
1244 fill_stream_allocation_row_info(
1245 &table->stream_allocations[0],
1253 REG_UPDATE_2(DP_MSE_SAT0,
1254 DP_MSE_SAT_SRC0, src,
1255 DP_MSE_SAT_SLOT_COUNT0, slots);
1257 if (table->stream_count >= 2) {
1258 fill_stream_allocation_row_info(
1259 &table->stream_allocations[1],
1267 REG_UPDATE_2(DP_MSE_SAT0,
1268 DP_MSE_SAT_SRC1, src,
1269 DP_MSE_SAT_SLOT_COUNT1, slots);
1271 if (table->stream_count >= 3) {
1272 fill_stream_allocation_row_info(
1273 &table->stream_allocations[2],
1281 REG_UPDATE_2(DP_MSE_SAT1,
1282 DP_MSE_SAT_SRC2, src,
1283 DP_MSE_SAT_SLOT_COUNT2, slots);
1285 if (table->stream_count >= 4) {
1286 fill_stream_allocation_row_info(
1287 &table->stream_allocations[3],
1295 REG_UPDATE_2(DP_MSE_SAT1,
1296 DP_MSE_SAT_SRC3, src,
1297 DP_MSE_SAT_SLOT_COUNT3, slots);
1299 /* --- wait for transaction finish */
1301 /* send allocation change trigger (ACT) ?
1302 * this step first sends the ACT,
1303 * then double buffers the SAT into the hardware
1304 * making the new allocation active on the DP MST mode link
1307 /* DP_MSE_SAT_UPDATE:
1309 * 1 - Update SAT with trigger
1310 * 2 - Update SAT without trigger
1312 REG_UPDATE(DP_MSE_SAT_UPDATE,
1313 DP_MSE_SAT_UPDATE, 1);
1315 /* wait for update to complete
1316 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1317 * then wait for the transmission
1318 * of at least 16 MTP headers on immediate local link.
1319 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1320 * a value of 1 indicates that DP MST mode
1321 * is in the 16 MTP keepout region after a VC has been added.
1322 * MST stream bandwidth (VC rate) can be configured
1323 * after this bit is cleared
1328 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1330 REG_GET(DP_MSE_SAT_UPDATE,
1331 DP_MSE_SAT_UPDATE, &value1);
1333 REG_GET(DP_MSE_SAT_UPDATE,
1334 DP_MSE_16_MTP_KEEPOUT, &value2);
1336 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1337 if (!value1 && !value2)
1340 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1343 void dcn10_link_encoder_connect_dig_be_to_fe(
1344 struct link_encoder *enc,
1345 enum engine_id engine,
1348 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1351 if (engine != ENGINE_ID_UNKNOWN) {
1353 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1356 field |= get_frontend_source(engine);
1358 field &= ~get_frontend_source(engine);
1360 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1365 #define HPD_REG(reg)\
1366 (enc10->hpd_regs->reg)
1368 #define HPD_REG_READ(reg_name) \
1369 dm_read_reg(CTX, HPD_REG(reg_name))
1371 #define HPD_REG_UPDATE_N(reg_name, n, ...) \
1372 generic_reg_update_ex(CTX, \
1373 HPD_REG(reg_name), \
1376 #define HPD_REG_UPDATE(reg_name, field, val) \
1377 HPD_REG_UPDATE_N(reg_name, 1, \
1378 FN(reg_name, field), val)
1380 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1382 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1384 HPD_REG_UPDATE(DC_HPD_CONTROL,
1388 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1390 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1392 HPD_REG_UPDATE(DC_HPD_CONTROL,
1396 #define AUX_REG(reg)\
1397 (enc10->aux_regs->reg)
1399 #define AUX_REG_READ(reg_name) \
1400 dm_read_reg(CTX, AUX_REG(reg_name))
1402 #define AUX_REG_UPDATE_N(reg_name, n, ...) \
1403 generic_reg_update_ex(CTX, \
1404 AUX_REG(reg_name), \
1407 #define AUX_REG_UPDATE(reg_name, field, val) \
1408 AUX_REG_UPDATE_N(reg_name, 1, \
1409 FN(reg_name, field), val)
1411 #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
1412 AUX_REG_UPDATE_N(reg, 2,\
1416 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
1418 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1420 AUX_REG_UPDATE_2(AUX_CONTROL,
1421 AUX_HPD_SEL, hpd_source,
1424 /* 1/4 window (the maximum allowed) */
1425 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1426 AUX_RX_RECEIVE_WINDOW, 0);
1429 enum signal_type dcn10_get_dig_mode(
1430 struct link_encoder *enc)
1432 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1434 REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
1437 return SIGNAL_TYPE_DISPLAY_PORT;
1439 return SIGNAL_TYPE_DVI_SINGLE_LINK;
1441 return SIGNAL_TYPE_HDMI_TYPE_A;
1443 return SIGNAL_TYPE_DISPLAY_PORT_MST;
1445 return SIGNAL_TYPE_NONE;
1447 return SIGNAL_TYPE_NONE;
1450 void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
1451 struct dc_link_settings *link_settings)
1453 /* Set Default link settings */
1454 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1455 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
1457 /* Higher link settings based on feature supported */
1458 if (enc->features.flags.bits.IS_HBR2_CAPABLE)
1459 max_link_cap.link_rate = LINK_RATE_HIGH2;
1461 if (enc->features.flags.bits.IS_HBR3_CAPABLE)
1462 max_link_cap.link_rate = LINK_RATE_HIGH3;
1464 *link_settings = max_link_cap;