2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "dc_dmub_srv.h"
29 #include "dmub/dmub_srv.h"
30 #include "core_types.h"
32 #define DC_TRACE_LEVEL_MESSAGE(...) do {} while (0) /* do nothing */
36 static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3};
37 static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5};
40 * Convert dmcub psr state to dmcu psr state.
42 static enum dc_psr_state convert_psr_state(uint32_t raw_state)
44 enum dc_psr_state state = PSR_STATE0;
48 else if (raw_state == 0x10)
50 else if (raw_state == 0x11)
52 else if (raw_state == 0x20)
54 else if (raw_state == 0x21)
56 else if (raw_state == 0x22)
58 else if (raw_state == 0x30)
60 else if (raw_state == 0x31)
61 state = PSR_STATE3Init;
62 else if (raw_state == 0x40)
64 else if (raw_state == 0x41)
66 else if (raw_state == 0x42)
68 else if (raw_state == 0x43)
70 else if (raw_state == 0x44)
72 else if (raw_state == 0x50)
74 else if (raw_state == 0x51)
76 else if (raw_state == 0x52)
78 else if (raw_state == 0x53)
80 else if (raw_state == 0x4A)
81 state = PSR_STATE4_FULL_FRAME;
82 else if (raw_state == 0x4B)
83 state = PSR_STATE4a_FULL_FRAME;
84 else if (raw_state == 0x4C)
85 state = PSR_STATE4b_FULL_FRAME;
86 else if (raw_state == 0x4D)
87 state = PSR_STATE4c_FULL_FRAME;
88 else if (raw_state == 0x4E)
89 state = PSR_STATE4_FULL_FRAME_POWERUP;
90 else if (raw_state == 0x4F)
91 state = PSR_STATE4_FULL_FRAME_HW_LOCK;
92 else if (raw_state == 0x60)
93 state = PSR_STATE_HWLOCK_MGR;
94 else if (raw_state == 0x61)
95 state = PSR_STATE_POLLVUPDATE;
97 state = PSR_STATE_INVALID;
103 * Get PSR state from firmware.
105 static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)
107 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
108 uint32_t raw_state = 0;
109 uint32_t retry_count = 0;
110 enum dmub_status status;
113 // Send gpint command and wait for ack
114 status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);
116 if (status == DMUB_STATUS_OK) {
117 // GPINT was executed, get response
118 dmub_srv_get_gpint_response(srv, &raw_state);
119 *state = convert_psr_state(raw_state);
121 // Return invalid state when GPINT times out
122 *state = PSR_STATE_INVALID;
124 } while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
126 // Assert if max retry hit
127 if (retry_count >= 1000 && *state == PSR_STATE_INVALID) {
129 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
130 WPP_BIT_FLAG_Firmware_PsrState,
131 "Unable to get PSR state from FW.");
133 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
134 WPP_BIT_FLAG_Firmware_PsrState,
135 "Got PSR state from FW. PSR state: %d, Retry count: %d",
136 *state, retry_count);
142 static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
144 union dmub_rb_cmd cmd;
145 struct dc_context *dc = dmub->ctx;
147 if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)
150 memset(&cmd, 0, sizeof(cmd));
151 cmd.psr_set_version.header.type = DMUB_CMD__PSR;
152 cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION;
153 switch (stream->link->psr_settings.psr_version) {
154 case DC_PSR_VERSION_1:
155 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
157 case DC_PSR_VERSION_SU_1:
158 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1;
160 case DC_PSR_VERSION_UNSUPPORTED:
162 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
166 if (cmd.psr_set_version.psr_set_version_data.version == PSR_VERSION_UNSUPPORTED)
169 cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
170 cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
171 cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);
173 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
179 * Enable/Disable PSR.
181 static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
183 union dmub_rb_cmd cmd;
184 struct dc_context *dc = dmub->ctx;
185 uint32_t retry_count;
186 enum dc_psr_state state = PSR_STATE0;
188 memset(&cmd, 0, sizeof(cmd));
189 cmd.psr_enable.header.type = DMUB_CMD__PSR;
191 cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
192 cmd.psr_enable.data.panel_inst = panel_inst;
195 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
197 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE;
199 cmd.psr_enable.header.payload_bytes = 0; // Send header only
201 dm_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
203 /* Below loops 1000 x 500us = 500 ms.
204 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at
205 * least a few frames. Should never hit the max retry assert below.
208 for (retry_count = 0; retry_count <= 1000; retry_count++) {
209 dmub_psr_get_state(dmub, &state, panel_inst);
212 if (state != PSR_STATE0)
215 if (state == PSR_STATE0)
222 /* assert if max retry hit */
223 if (retry_count >= 1000)
231 static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)
233 union dmub_rb_cmd cmd;
234 enum dc_psr_state state = PSR_STATE0;
235 struct dc_context *dc = dmub->ctx;
237 dmub_psr_get_state(dmub, &state, panel_inst);
239 if (state == PSR_STATE0)
242 memset(&cmd, 0, sizeof(cmd));
243 cmd.psr_set_level.header.type = DMUB_CMD__PSR;
244 cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
245 cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
246 cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
247 cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
248 cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;
249 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
253 * Set PSR vtotal requirement for FreeSync PSR.
255 static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
256 uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
258 union dmub_rb_cmd cmd;
259 struct dc_context *dc = dmub->ctx;
261 memset(&cmd, 0, sizeof(cmd));
262 cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
263 cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
264 cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
265 cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
266 cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
268 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
272 * Set PSR power optimization flags.
274 static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst)
276 union dmub_rb_cmd cmd;
277 struct dc_context *dc = dmub->ctx;
279 memset(&cmd, 0, sizeof(cmd));
280 cmd.psr_set_power_opt.header.type = DMUB_CMD__PSR;
281 cmd.psr_set_power_opt.header.sub_type = DMUB_CMD__SET_PSR_POWER_OPT;
282 cmd.psr_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_power_opt_data);
283 cmd.psr_set_power_opt.psr_set_power_opt_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
284 cmd.psr_set_power_opt.psr_set_power_opt_data.power_opt = power_opt;
285 cmd.psr_set_power_opt.psr_set_power_opt_data.panel_inst = panel_inst;
287 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
291 * Setup PSR by programming phy registers and sending psr hw context values to firmware.
293 static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
294 struct dc_link *link,
295 struct psr_context *psr_context,
298 union dmub_rb_cmd cmd;
299 struct dc_context *dc = dmub->ctx;
300 struct dmub_cmd_psr_copy_settings_data *copy_settings_data
301 = &cmd.psr_copy_settings.psr_copy_settings_data;
302 struct pipe_ctx *pipe_ctx = NULL;
303 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
306 for (i = 0; i < MAX_PIPES; i++) {
307 if (res_ctx->pipe_ctx[i].stream &&
308 res_ctx->pipe_ctx[i].stream->link == link &&
309 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
310 pipe_ctx = &res_ctx->pipe_ctx[i];
311 //TODO: refactor for multi edp support
319 // First, set the psr version
320 if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))
323 // Program DP DPHY fast training registers
324 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
325 psr_context->psrExitLinkTrainingRequired);
327 // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high
328 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
329 psr_context->sdpTransmitLineNumDeadline);
331 memset(&cmd, 0, sizeof(cmd));
332 cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;
333 cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;
334 cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
337 copy_settings_data->dpphy_inst = psr_context->transmitterId;
338 copy_settings_data->aux_inst = psr_context->channel;
339 copy_settings_data->digfe_inst = psr_context->engineId;
340 copy_settings_data->digbe_inst = psr_context->transmitterId;
342 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
344 if (pipe_ctx->plane_res.dpp)
345 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
347 copy_settings_data->dpp_inst = 0;
348 if (pipe_ctx->stream_res.opp)
349 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;
351 copy_settings_data->opp_inst = 0;
352 if (pipe_ctx->stream_res.tg)
353 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
355 copy_settings_data->otg_inst = 0;
358 copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm;
359 copy_settings_data->psr_level = psr_context->psr_level.u32all;
360 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
361 copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;
362 copy_settings_data->frame_delay = psr_context->frame_delay;
363 copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
364 copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline;
365 copy_settings_data->debug.u32All = 0;
366 copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
367 copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1;
368 copy_settings_data->debug.bitfields.force_full_frame_update = 0;
370 if (psr_context->su_granularity_required == 0)
371 copy_settings_data->su_y_granularity = 0;
373 copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
375 copy_settings_data->line_capture_indication = 0;
376 copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
377 copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
378 copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
379 copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
380 copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
381 copy_settings_data->panel_inst = panel_inst;
382 copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
385 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
386 * Note that PSRSU+DSC is still under development.
388 if (copy_settings_data->dsc_enable_status &&
389 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
390 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
391 sizeof(DP_SINK_DEVICE_STR_ID_1)))
392 link->psr_settings.force_ffu_mode = 1;
394 link->psr_settings.force_ffu_mode = 0;
395 copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode;
397 if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
398 !link->dc->debug.disable_fec) &&
399 (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
400 !link->panel_config.dsc.disable_dsc_edp &&
401 link->dc->caps.edp_dsc_support)) &&
402 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
403 (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
404 sizeof(DP_SINK_DEVICE_STR_ID_1)) ||
405 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2,
406 sizeof(DP_SINK_DEVICE_STR_ID_2))))
407 copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1;
409 copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0;
411 //WA for PSR1 on specific TCON, require frame delay for frame re-lock
412 copy_settings_data->relock_delay_frame_cnt = 0;
413 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
414 copy_settings_data->relock_delay_frame_cnt = 2;
415 copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height;
417 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
423 * Send command to PSR to force static ENTER and ignore all state changes until exit
425 static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)
427 union dmub_rb_cmd cmd;
428 struct dc_context *dc = dmub->ctx;
430 memset(&cmd, 0, sizeof(cmd));
432 cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst;
433 cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
434 cmd.psr_force_static.header.type = DMUB_CMD__PSR;
435 cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;
436 cmd.psr_enable.header.payload_bytes = 0;
438 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
442 * Get PSR residency from firmware.
444 static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)
446 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
447 uint16_t param = (uint16_t)(panel_inst << 8);
449 /* Send gpint command and wait for ack */
450 dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
452 dmub_srv_get_gpint_response(srv, residency);
455 static const struct dmub_psr_funcs psr_funcs = {
456 .psr_copy_settings = dmub_psr_copy_settings,
457 .psr_enable = dmub_psr_enable,
458 .psr_get_state = dmub_psr_get_state,
459 .psr_set_level = dmub_psr_set_level,
460 .psr_force_static = dmub_psr_force_static,
461 .psr_get_residency = dmub_psr_get_residency,
462 .psr_set_sink_vtotal_in_psr_active = dmub_psr_set_sink_vtotal_in_psr_active,
463 .psr_set_power_opt = dmub_psr_set_power_opt,
467 * Construct PSR object.
469 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
472 psr->funcs = &psr_funcs;
476 * Allocate and initialize PSR object.
478 struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
480 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
487 dmub_psr_construct(psr, ctx);
493 * Deallocate PSR object.
495 void dmub_psr_destroy(struct dmub_psr **dmub)