2 * Copyright 2012-15 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "reg_helper.h"
27 #include "dce_audio.h"
28 #include "dce/dce_11_0_d.h"
29 #include "dce/dce_11_0_sh_mask.h"
31 #define DCE_AUD(audio)\
32 container_of(audio, struct dce_audio, base)
40 #define FN(reg_name, field_name) \
41 aud->shifts->field_name, aud->masks->field_name
46 #define AZ_REG_READ(reg_name) \
47 read_indirect_azalia_reg(audio, IX_REG(reg_name))
49 #define AZ_REG_WRITE(reg_name, value) \
50 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
52 static void write_indirect_azalia_reg(struct audio *audio,
56 struct dce_audio *aud = DCE_AUD(audio);
58 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
59 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
60 AZALIA_ENDPOINT_REG_INDEX, reg_index);
62 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
63 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
64 AZALIA_ENDPOINT_REG_DATA, reg_data);
66 dm_logger_write(CTX->logger, LOG_HW_AUDIO,
67 "AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
71 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
73 struct dce_audio *aud = DCE_AUD(audio);
77 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
78 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
79 AZALIA_ENDPOINT_REG_INDEX, reg_index);
81 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
82 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
84 dm_logger_write(CTX->logger, LOG_HW_AUDIO,
85 "AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
91 static bool is_audio_format_supported(
92 const struct audio_info *audio_info,
93 enum audio_format_code audio_format_code,
94 uint32_t *format_index)
97 uint32_t max_channe_index = 0;
100 if (audio_info == NULL)
103 /* pass through whole array */
104 for (index = 0; index < audio_info->mode_count; index++) {
105 if (audio_info->modes[index].format_code == audio_format_code) {
107 /* format has multiply entries, choose one with
108 * highst number of channels */
109 if (audio_info->modes[index].channel_count >
110 audio_info->modes[max_channe_index].channel_count) {
111 max_channe_index = index;
114 /* format found, save it's index */
116 max_channe_index = index;
122 if (found && format_index != NULL)
123 *format_index = max_channe_index;
128 /*For HDMI, calculate if specified sample rates can fit into a given timing */
129 static void check_audio_bandwidth_hdmi(
130 const struct audio_crtc_info *crtc_info,
131 uint32_t channel_count,
132 union audio_sample_rates *sample_rates)
136 bool limit_freq_to_48_khz = false;
137 bool limit_freq_to_88_2_khz = false;
138 bool limit_freq_to_96_khz = false;
139 bool limit_freq_to_174_4_khz = false;
141 /* For two channels supported return whatever sink support,unmodified*/
142 if (channel_count > 2) {
144 /* Based on HDMI spec 1.3 Table 7.5 */
145 if ((crtc_info->requested_pixel_clock <= 27000) &&
146 (crtc_info->v_active <= 576) &&
147 !(crtc_info->interlaced) &&
148 !(crtc_info->pixel_repetition == 2 ||
149 crtc_info->pixel_repetition == 4)) {
150 limit_freq_to_48_khz = true;
152 } else if ((crtc_info->requested_pixel_clock <= 27000) &&
153 (crtc_info->v_active <= 576) &&
154 (crtc_info->interlaced) &&
155 (crtc_info->pixel_repetition == 2)) {
156 limit_freq_to_88_2_khz = true;
158 } else if ((crtc_info->requested_pixel_clock <= 54000) &&
159 (crtc_info->v_active <= 576) &&
160 !(crtc_info->interlaced)) {
161 limit_freq_to_174_4_khz = true;
165 /* Also do some calculation for the available Audio Bandwidth for the
166 * 8 ch (i.e. for the Layout 1 => ch > 2)
168 h_blank = crtc_info->h_total - crtc_info->h_active;
170 if (crtc_info->pixel_repetition)
171 h_blank *= crtc_info->pixel_repetition;
173 /*based on HDMI spec 1.3 Table 7.5 */
175 /*for Control Period */
178 samples = h_blank * 10;
179 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
180 * of Audio samples per line multiplied by 10 - Layout 1)
183 samples *= crtc_info->v_active;
184 /*Number of samples multiplied by 10, per second */
185 samples *= crtc_info->refresh_rate;
186 /*Number of Audio samples per second */
189 /* @todo do it after deep color is implemented
190 * 8xx - deep color bandwidth scaling
191 * Extra bandwidth is avaliable in deep color b/c link runs faster than
192 * pixel rate. This has the effect of allowing more tmds characters to
193 * be transmitted during blank
196 switch (crtc_info->color_depth) {
197 case COLOR_DEPTH_888:
200 case COLOR_DEPTH_101010:
203 case COLOR_DEPTH_121212:
215 limit_freq_to_48_khz = true;
216 else if (samples < 96000)
217 limit_freq_to_88_2_khz = true;
218 else if (samples < 176400)
219 limit_freq_to_96_khz = true;
220 else if (samples < 192000)
221 limit_freq_to_174_4_khz = true;
223 if (sample_rates != NULL) {
224 /* limit frequencies */
225 if (limit_freq_to_174_4_khz)
226 sample_rates->rate.RATE_192 = 0;
228 if (limit_freq_to_96_khz) {
229 sample_rates->rate.RATE_192 = 0;
230 sample_rates->rate.RATE_176_4 = 0;
232 if (limit_freq_to_88_2_khz) {
233 sample_rates->rate.RATE_192 = 0;
234 sample_rates->rate.RATE_176_4 = 0;
235 sample_rates->rate.RATE_96 = 0;
237 if (limit_freq_to_48_khz) {
238 sample_rates->rate.RATE_192 = 0;
239 sample_rates->rate.RATE_176_4 = 0;
240 sample_rates->rate.RATE_96 = 0;
241 sample_rates->rate.RATE_88_2 = 0;
246 /*For DP SST, calculate if specified sample rates can fit into a given timing */
247 static void check_audio_bandwidth_dpsst(
248 const struct audio_crtc_info *crtc_info,
249 uint32_t channel_count,
250 union audio_sample_rates *sample_rates)
255 /*For DP MST, calculate if specified sample rates can fit into a given timing */
256 static void check_audio_bandwidth_dpmst(
257 const struct audio_crtc_info *crtc_info,
258 uint32_t channel_count,
259 union audio_sample_rates *sample_rates)
264 static void check_audio_bandwidth(
265 const struct audio_crtc_info *crtc_info,
266 uint32_t channel_count,
267 enum signal_type signal,
268 union audio_sample_rates *sample_rates)
271 case SIGNAL_TYPE_HDMI_TYPE_A:
272 check_audio_bandwidth_hdmi(
273 crtc_info, channel_count, sample_rates);
275 case SIGNAL_TYPE_EDP:
276 case SIGNAL_TYPE_DISPLAY_PORT:
277 check_audio_bandwidth_dpsst(
278 crtc_info, channel_count, sample_rates);
280 case SIGNAL_TYPE_DISPLAY_PORT_MST:
281 check_audio_bandwidth_dpmst(
282 crtc_info, channel_count, sample_rates);
289 /* expose/not expose HBR capability to Audio driver */
290 static void set_high_bit_rate_capable(
296 /* set high bit rate audio capable*/
297 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
299 set_reg_field_value(value, capable,
300 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
303 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
306 /* set video latency in in ms/2+1 */
307 static void set_video_latency(
313 if ((latency_in_ms < 0) || (latency_in_ms > 255))
316 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
318 set_reg_field_value(value, latency_in_ms,
319 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
322 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
326 /* set audio latency in in ms/2+1 */
327 static void set_audio_latency(
333 if (latency_in_ms < 0)
336 if (latency_in_ms > 255)
339 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
341 set_reg_field_value(value, latency_in_ms,
342 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
345 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
349 void dce_aud_az_enable(struct audio *audio)
351 struct dce_audio *aud = DCE_AUD(audio);
352 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
354 set_reg_field_value(value, 1,
355 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
356 CLOCK_GATING_DISABLE);
357 set_reg_field_value(value, 1,
358 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
361 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
362 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
364 dm_logger_write(CTX->logger, LOG_HW_AUDIO,
365 "\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n",
369 void dce_aud_az_disable(struct audio *audio)
372 struct dce_audio *aud = DCE_AUD(audio);
374 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
376 set_reg_field_value(value, 0,
377 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
379 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
381 set_reg_field_value(value, 0,
382 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
383 CLOCK_GATING_DISABLE);
384 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
385 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
386 dm_logger_write(CTX->logger, LOG_HW_AUDIO,
387 "\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n",
391 void dce_aud_az_configure(
393 enum signal_type signal,
394 const struct audio_crtc_info *crtc_info,
395 const struct audio_info *audio_info)
397 struct dce_audio *aud = DCE_AUD(audio);
399 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
402 enum audio_format_code audio_format_code;
403 uint32_t format_index;
405 bool is_ac3_supported = false;
406 union audio_sample_rates sample_rate;
408 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
409 set_reg_field_value(value, 1,
410 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
411 CLOCK_GATING_DISABLE);
412 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
414 /* Speaker Allocation */
417 uint32_t field = 0;*/
418 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
420 set_reg_field_value(value,
422 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
425 /* LFE_PLAYBACK_LEVEL = LFEPBL
426 * LFEPBL = 0 : Unknown or refer to other information
427 * LFEPBL = 1 : 0dB playback
428 * LFEPBL = 2 : +10dB playback
429 * LFE_BL = 3 : Reserved
431 set_reg_field_value(value,
433 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
435 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
436 * why are we writing to it? DCE8 does not write this */
439 set_reg_field_value(value,
441 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
444 set_reg_field_value(value,
446 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
449 field = get_reg_field_value(value,
450 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
451 EXTRA_CONNECTION_INFO);
455 set_reg_field_value(value,
457 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
458 EXTRA_CONNECTION_INFO);
460 /* set audio for output signal */
462 case SIGNAL_TYPE_HDMI_TYPE_A:
463 set_reg_field_value(value,
465 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
470 case SIGNAL_TYPE_EDP:
471 case SIGNAL_TYPE_DISPLAY_PORT:
472 case SIGNAL_TYPE_DISPLAY_PORT_MST:
473 set_reg_field_value(value,
475 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
483 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
485 /* Audio Descriptors */
486 /* pass through all formats */
487 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
490 (AUDIO_FORMAT_CODE_FIRST + format_index);
492 /* those are unsupported, skip programming */
493 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
494 audio_format_code == AUDIO_FORMAT_CODE_DST)
499 /* check if supported */
500 if (is_audio_format_supported(
501 audio_info, audio_format_code, &index)) {
502 const struct audio_mode *audio_mode =
503 &audio_info->modes[index];
504 union audio_sample_rates sample_rates =
505 audio_mode->sample_rates;
506 uint8_t byte2 = audio_mode->max_bit_rate;
508 /* adjust specific properties */
509 switch (audio_format_code) {
510 case AUDIO_FORMAT_CODE_LINEARPCM: {
511 check_audio_bandwidth(
513 audio_mode->channel_count,
517 byte2 = audio_mode->sample_size;
519 set_reg_field_value(value,
521 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
522 SUPPORTED_FREQUENCIES_STEREO);
525 case AUDIO_FORMAT_CODE_AC3:
526 is_ac3_supported = true;
528 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
529 case AUDIO_FORMAT_CODE_DTS_HD:
530 case AUDIO_FORMAT_CODE_MAT_MLP:
531 case AUDIO_FORMAT_CODE_DST:
532 case AUDIO_FORMAT_CODE_WMAPRO:
533 byte2 = audio_mode->vendor_specific;
539 /* fill audio format data */
540 set_reg_field_value(value,
541 audio_mode->channel_count - 1,
542 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
545 set_reg_field_value(value,
547 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
548 SUPPORTED_FREQUENCIES);
550 set_reg_field_value(value,
552 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
557 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
561 if (is_ac3_supported)
562 /* todo: this reg global. why program global register? */
563 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
566 /* check for 192khz/8-Ch support for HBR requirements */
568 sample_rate.rate.RATE_192 = 1;
570 check_audio_bandwidth(
576 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
578 /* Audio and Video Lipsync */
579 set_video_latency(audio, audio_info->video_latency);
580 set_audio_latency(audio, audio_info->audio_latency);
583 set_reg_field_value(value, audio_info->manufacture_id,
584 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
587 set_reg_field_value(value, audio_info->product_id,
588 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
591 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
596 /*get display name string length */
597 while (audio_info->display_name[strlen++] != '\0') {
599 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
602 set_reg_field_value(value, strlen,
603 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
604 SINK_DESCRIPTION_LEN);
606 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
611 *PORT_ID0 = display index
612 *PORT_ID1 = 16bit BDF
613 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
618 set_reg_field_value(value, audio_info->port_id[0],
619 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
622 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
625 set_reg_field_value(value, audio_info->port_id[1],
626 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
629 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
631 /*write the 18 char monitor string */
634 set_reg_field_value(value, audio_info->display_name[0],
635 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
638 set_reg_field_value(value, audio_info->display_name[1],
639 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
642 set_reg_field_value(value, audio_info->display_name[2],
643 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
646 set_reg_field_value(value, audio_info->display_name[3],
647 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
650 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
653 set_reg_field_value(value, audio_info->display_name[4],
654 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
657 set_reg_field_value(value, audio_info->display_name[5],
658 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
661 set_reg_field_value(value, audio_info->display_name[6],
662 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
665 set_reg_field_value(value, audio_info->display_name[7],
666 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
669 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
672 set_reg_field_value(value, audio_info->display_name[8],
673 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
676 set_reg_field_value(value, audio_info->display_name[9],
677 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
680 set_reg_field_value(value, audio_info->display_name[10],
681 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
684 set_reg_field_value(value, audio_info->display_name[11],
685 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
688 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
691 set_reg_field_value(value, audio_info->display_name[12],
692 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
695 set_reg_field_value(value, audio_info->display_name[13],
696 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
699 set_reg_field_value(value, audio_info->display_name[14],
700 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
703 set_reg_field_value(value, audio_info->display_name[15],
704 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
707 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
710 set_reg_field_value(value, audio_info->display_name[16],
711 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
714 set_reg_field_value(value, audio_info->display_name[17],
715 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
718 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
722 * todo: wall clk related functionality probably belong to clock_src.
725 /* search pixel clock value for Azalia HDMI Audio */
726 static void get_azalia_clock_info_hdmi(
727 uint32_t crtc_pixel_clock_in_khz,
728 uint32_t actual_pixel_clock_in_khz,
729 struct azalia_clock_info *azalia_clock_info)
731 /* audio_dto_phase= 24 * 10,000;
732 * 24MHz in [100Hz] units */
733 azalia_clock_info->audio_dto_phase =
736 /* audio_dto_module = PCLKFrequency * 10,000;
737 * [khz] -> [100Hz] */
738 azalia_clock_info->audio_dto_module =
739 actual_pixel_clock_in_khz * 10;
742 static void get_azalia_clock_info_dp(
743 uint32_t requested_pixel_clock_in_khz,
744 const struct audio_pll_info *pll_info,
745 struct azalia_clock_info *azalia_clock_info)
747 /* Reported dpDtoSourceClockInkhz value for
748 * DCE8 already adjusted for SS, do not need any
749 * adjustment here anymore
752 /*audio_dto_phase = 24 * 10,000;
753 * 24MHz in [100Hz] units */
754 azalia_clock_info->audio_dto_phase = 24 * 10000;
756 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
758 azalia_clock_info->audio_dto_module =
759 pll_info->dp_dto_source_clock_in_khz * 10;
762 void dce_aud_wall_dto_setup(
764 enum signal_type signal,
765 const struct audio_crtc_info *crtc_info,
766 const struct audio_pll_info *pll_info)
768 struct dce_audio *aud = DCE_AUD(audio);
770 struct azalia_clock_info clock_info = { 0 };
772 if (dc_is_hdmi_signal(signal)) {
775 /*DTO0 Programming goal:
776 -generate 24MHz, 128*Fs from 24MHz
777 -use DTO0 when an active HDMI port is connected
778 (optionally a DP is connected) */
780 /* calculate DTO settings */
781 get_azalia_clock_info_hdmi(
782 crtc_info->requested_pixel_clock,
783 crtc_info->calculated_pixel_clock,
786 dm_logger_write(audio->ctx->logger, LOG_HW_AUDIO,\
787 "\n%s:Input::requested_pixel_clock = %d"\
788 "calculated_pixel_clock =%d\n"\
789 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
790 crtc_info->requested_pixel_clock,\
791 crtc_info->calculated_pixel_clock,\
792 clock_info.audio_dto_module,\
793 clock_info.audio_dto_phase);
795 /* On TN/SI, Program DTO source select and DTO select before
796 programming DTO modulo and DTO phase. These bits must be
797 programmed first, otherwise there will be no HDMI audio at boot
798 up. This is a HW sequence change (different from old ASICs).
799 Caution when changing this programming sequence.
801 HDMI enabled, using DTO0
802 program master CRTC for DTO0 */
803 src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
804 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
805 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
806 DCCG_AUDIO_DTO_SEL, 0);
809 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
810 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
813 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
814 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
816 /*DTO1 Programming goal:
817 -generate 24MHz, 512*Fs, 128*Fs from 24MHz
818 -default is to used DTO1, and switch to DTO0 when an audio
819 master HDMI port is connected
820 -use as default for DP
822 calculate DTO settings */
823 get_azalia_clock_info_dp(
824 crtc_info->requested_pixel_clock,
828 /* Program DTO select before programming DTO modulo and DTO
829 phase. default to use DTO1 */
831 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
832 DCCG_AUDIO_DTO_SEL, 1);
834 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
835 DCCG_AUDIO_DTO_SEL, 1);
836 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
837 * Select 512fs for DP TODO: web register definition
838 * does not match register header file
839 * DCE11 version it's commented out while DCE8 it's set to 1
843 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
844 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
847 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
848 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
850 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
851 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
856 static bool dce_aud_endpoint_valid(struct audio *audio)
859 uint32_t port_connectivity;
862 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
864 port_connectivity = get_reg_field_value(value,
865 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
868 return !(port_connectivity == 1);
871 /* initialize HW state */
872 void dce_aud_hw_init(
876 struct dce_audio *aud = DCE_AUD(audio);
878 /* we only need to program the following registers once, so we only do
880 if (audio->inst != 0)
884 * Suport R6 - 44.1khz
887 /*disable clock gating before write to endpoint register*/
888 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
889 set_reg_field_value(value, 1,
890 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
891 CLOCK_GATING_DISABLE);
892 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
893 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
894 AUDIO_RATE_CAPABILITIES, 0x70);
896 /*Keep alive bit to verify HW block in BU. */
897 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
902 static const struct audio_funcs funcs = {
903 .endpoint_valid = dce_aud_endpoint_valid,
904 .hw_init = dce_aud_hw_init,
905 .wall_dto_setup = dce_aud_wall_dto_setup,
906 .az_enable = dce_aud_az_enable,
907 .az_disable = dce_aud_az_disable,
908 .az_configure = dce_aud_az_configure,
909 .destroy = dce_aud_destroy,
912 void dce_aud_destroy(struct audio **audio)
914 struct dce_audio *aud = DCE_AUD(*audio);
920 struct audio *dce_audio_create(
921 struct dc_context *ctx,
923 const struct dce_audio_registers *reg,
924 const struct dce_audio_shift *shifts,
925 const struct dce_aduio_mask *masks
928 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
931 ASSERT_CRITICAL(audio);
935 audio->base.ctx = ctx;
936 audio->base.inst = inst;
937 audio->base.funcs = &funcs;
940 audio->shifts = shifts;
941 audio->masks = masks;