2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
27 #include "core_types.h"
30 #include "atomfirmware.h"
32 #include "dc_bios_types.h"
33 #include "include/grph_object_ctrl_defs.h"
34 #include "include/bios_parser_interface.h"
35 #include "include/logger_interface.h"
37 #include "command_table2.h"
39 #include "bios_parser_helper.h"
40 #include "command_table_helper2.h"
41 #include "bios_parser2.h"
42 #include "bios_parser_types_internal2.h"
43 #include "bios_parser_interface.h"
45 #include "bios_parser_common.h"
50 #define LAST_RECORD_TYPE 0xff
51 #define SMU9_SYSPLL0_ID 0
53 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
54 struct atom_i2c_record *record,
55 struct graphics_object_i2c_info *info);
57 static enum bp_result bios_parser_get_firmware_info(
59 struct dc_firmware_info *info);
61 static enum bp_result bios_parser_get_encoder_cap_info(
63 struct graphics_object_id object_id,
64 struct bp_encoder_cap_info *info);
66 static enum bp_result get_firmware_info_v3_1(
67 struct bios_parser *bp,
68 struct dc_firmware_info *info);
70 static enum bp_result get_firmware_info_v3_2(
71 struct bios_parser *bp,
72 struct dc_firmware_info *info);
74 static enum bp_result get_firmware_info_v3_4(
75 struct bios_parser *bp,
76 struct dc_firmware_info *info);
78 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
79 struct atom_display_object_path_v2 *object);
81 static struct atom_encoder_caps_record *get_encoder_cap_record(
82 struct bios_parser *bp,
83 struct atom_display_object_path_v2 *object);
85 #define BIOS_IMAGE_SIZE_OFFSET 2
86 #define BIOS_IMAGE_SIZE_UNIT 512
88 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
90 static void bios_parser2_destruct(struct bios_parser *bp)
92 kfree(bp->base.bios_local_image);
93 kfree(bp->base.integrated_info);
96 static void firmware_parser_destroy(struct dc_bios **dcb)
98 struct bios_parser *bp = BP_FROM_DCB(*dcb);
105 bios_parser2_destruct(bp);
111 static void get_atom_data_table_revision(
112 struct atom_common_table_header *atom_data_tbl,
113 struct atom_data_revision *tbl_revision)
118 /* initialize the revision to 0 which is invalid revision */
119 tbl_revision->major = 0;
120 tbl_revision->minor = 0;
125 tbl_revision->major =
126 (uint32_t) atom_data_tbl->format_revision & 0x3f;
127 tbl_revision->minor =
128 (uint32_t) atom_data_tbl->content_revision & 0x3f;
131 /* BIOS oject table displaypath is per connector.
132 * There is extra path not for connector. BIOS fill its encoderid as 0
134 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
136 struct bios_parser *bp = BP_FROM_DCB(dcb);
137 unsigned int count = 0;
140 switch (bp->object_info_tbl.revision.minor) {
143 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++)
144 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
150 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++)
151 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0)
159 static struct graphics_object_id bios_parser_get_connector_id(
163 struct bios_parser *bp = BP_FROM_DCB(dcb);
164 struct graphics_object_id object_id = dal_graphics_object_id_init(
165 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
166 struct object_info_table *tbl = &bp->object_info_tbl;
167 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
169 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5;
171 switch (bp->object_info_tbl.revision.minor) {
174 if (v1_4->number_of_path > i) {
175 /* If display_objid is generic object id, the encoderObj
176 * /extencoderobjId should be 0
178 if (v1_4->display_path[i].encoderobjid != 0 &&
179 v1_4->display_path[i].display_objid != 0)
180 object_id = object_id_from_bios_object_id(
181 v1_4->display_path[i].display_objid);
186 if (v1_5->number_of_path > i) {
187 /* If display_objid is generic object id, the encoderObjId
190 if (v1_5->display_path[i].encoderobjid != 0 &&
191 v1_5->display_path[i].display_objid != 0)
192 object_id = object_id_from_bios_object_id(
193 v1_5->display_path[i].display_objid);
200 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
201 struct graphics_object_id object_id, uint32_t index,
202 struct graphics_object_id *src_object_id)
204 struct bios_parser *bp = BP_FROM_DCB(dcb);
206 enum bp_result bp_result = BP_RESULT_BADINPUT;
207 struct graphics_object_id obj_id = { 0 };
208 struct object_info_table *tbl = &bp->object_info_tbl;
213 switch (object_id.type) {
214 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
215 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
217 case OBJECT_TYPE_ENCODER:
218 /* TODO: since num of src must be less than 2.
219 * If found in for loop, should break.
220 * DAL2 implementation may be changed too
222 switch (bp->object_info_tbl.revision.minor) {
225 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
226 obj_id = object_id_from_bios_object_id(
227 tbl->v1_4->display_path[i].encoderobjid);
228 if (object_id.type == obj_id.type &&
229 object_id.id == obj_id.id &&
230 object_id.enum_id == obj_id.enum_id) {
232 object_id_from_bios_object_id(
237 bp_result = BP_RESULT_OK;
241 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
242 obj_id = object_id_from_bios_object_id(
243 tbl->v1_5->display_path[i].encoderobjid);
244 if (object_id.type == obj_id.type &&
245 object_id.id == obj_id.id &&
246 object_id.enum_id == obj_id.enum_id) {
248 object_id_from_bios_object_id(
253 bp_result = BP_RESULT_OK;
257 case OBJECT_TYPE_CONNECTOR:
258 switch (bp->object_info_tbl.revision.minor) {
261 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
262 obj_id = object_id_from_bios_object_id(
263 tbl->v1_4->display_path[i]
266 if (object_id.type == obj_id.type &&
267 object_id.id == obj_id.id &&
268 object_id.enum_id == obj_id.enum_id) {
270 object_id_from_bios_object_id(
277 bp_result = BP_RESULT_OK;
280 bp_result = BP_RESULT_OK;
283 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
284 obj_id = object_id_from_bios_object_id(
285 tbl->v1_5->display_path[i].display_objid);
287 if (object_id.type == obj_id.type &&
288 object_id.id == obj_id.id &&
289 object_id.enum_id == obj_id.enum_id) {
290 *src_object_id = object_id_from_bios_object_id(
291 tbl->v1_5->display_path[i].encoderobjid);
295 bp_result = BP_RESULT_OK;
299 bp_result = BP_RESULT_OK;
306 /* from graphics_object_id, find display path which includes the object_id */
307 static struct atom_display_object_path_v2 *get_bios_object(
308 struct bios_parser *bp,
309 struct graphics_object_id id)
312 struct graphics_object_id obj_id = {0};
315 case OBJECT_TYPE_ENCODER:
316 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
317 obj_id = object_id_from_bios_object_id(
318 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
319 if (id.type == obj_id.type && id.id == obj_id.id
320 && id.enum_id == obj_id.enum_id)
321 return &bp->object_info_tbl.v1_4->display_path[i];
324 case OBJECT_TYPE_CONNECTOR:
325 case OBJECT_TYPE_GENERIC:
326 /* Both Generic and Connector Object ID
327 * will be stored on display_objid
329 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
330 obj_id = object_id_from_bios_object_id(
331 bp->object_info_tbl.v1_4->display_path[i].display_objid);
332 if (id.type == obj_id.type && id.id == obj_id.id
333 && id.enum_id == obj_id.enum_id)
334 return &bp->object_info_tbl.v1_4->display_path[i];
342 /* from graphics_object_id, find display path which includes the object_id */
343 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(struct bios_parser *bp,
344 struct graphics_object_id id)
347 struct graphics_object_id obj_id = {0};
350 case OBJECT_TYPE_ENCODER:
351 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
352 obj_id = object_id_from_bios_object_id(
353 bp->object_info_tbl.v1_5->display_path[i].encoderobjid);
354 if (id.type == obj_id.type && id.id == obj_id.id
355 && id.enum_id == obj_id.enum_id)
356 return &bp->object_info_tbl.v1_5->display_path[i];
360 case OBJECT_TYPE_CONNECTOR:
361 case OBJECT_TYPE_GENERIC:
362 /* Both Generic and Connector Object ID
363 * will be stored on display_objid
365 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
366 obj_id = object_id_from_bios_object_id(
367 bp->object_info_tbl.v1_5->display_path[i].display_objid);
368 if (id.type == obj_id.type && id.id == obj_id.id
369 && id.enum_id == obj_id.enum_id)
370 return &bp->object_info_tbl.v1_5->display_path[i];
381 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
382 struct graphics_object_id id,
383 struct graphics_object_i2c_info *info)
386 struct atom_display_object_path_v2 *object;
388 struct atom_display_object_path_v3 *object_path_v3;
390 struct atom_common_record_header *header;
391 struct atom_i2c_record *record;
392 struct atom_i2c_record dummy_record = {0};
393 struct bios_parser *bp = BP_FROM_DCB(dcb);
396 return BP_RESULT_BADINPUT;
398 if (id.type == OBJECT_TYPE_GENERIC) {
399 dummy_record.i2c_id = id.id;
401 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
404 return BP_RESULT_NORECORD;
407 switch (bp->object_info_tbl.revision.minor) {
410 object = get_bios_object(bp, id);
413 return BP_RESULT_BADINPUT;
415 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
418 object_path_v3 = get_bios_object_from_path_v3(bp, id);
421 return BP_RESULT_BADINPUT;
423 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset;
428 header = GET_IMAGE(struct atom_common_record_header, offset);
431 return BP_RESULT_BADBIOSTABLE;
433 if (header->record_type == LAST_RECORD_TYPE ||
434 !header->record_size)
437 if (header->record_type == ATOM_I2C_RECORD_TYPE
438 && sizeof(struct atom_i2c_record) <=
439 header->record_size) {
440 /* get the I2C info */
441 record = (struct atom_i2c_record *) header;
443 if (get_gpio_i2c_info(bp, record, info) ==
448 offset += header->record_size;
451 return BP_RESULT_NORECORD;
454 static enum bp_result get_gpio_i2c_info(
455 struct bios_parser *bp,
456 struct atom_i2c_record *record,
457 struct graphics_object_i2c_info *info)
459 struct atom_gpio_pin_lut_v2_1 *header;
461 unsigned int table_index = 0;
462 bool find_valid = false;
463 struct atom_gpio_pin_assignment *pin;
466 return BP_RESULT_BADINPUT;
468 /* get the GPIO_I2C info */
469 if (!DATA_TABLES(gpio_pin_lut))
470 return BP_RESULT_BADBIOSTABLE;
472 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
473 DATA_TABLES(gpio_pin_lut));
475 return BP_RESULT_BADBIOSTABLE;
477 if (sizeof(struct atom_common_table_header) +
478 sizeof(struct atom_gpio_pin_assignment) >
479 le16_to_cpu(header->table_header.structuresize))
480 return BP_RESULT_BADBIOSTABLE;
482 /* TODO: is version change? */
483 if (header->table_header.content_revision != 1)
484 return BP_RESULT_UNSUPPORTED;
487 count = (le16_to_cpu(header->table_header.structuresize)
488 - sizeof(struct atom_common_table_header))
489 / sizeof(struct atom_gpio_pin_assignment);
491 pin = (struct atom_gpio_pin_assignment *) header->gpio_pin;
493 for (table_index = 0; table_index < count; table_index++) {
494 if (((record->i2c_id & I2C_HW_CAP) == (pin->gpio_id & I2C_HW_CAP)) &&
495 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == (pin->gpio_id & I2C_HW_ENGINE_ID_MASK)) &&
496 ((record->i2c_id & I2C_HW_LANE_MUX) == (pin->gpio_id & I2C_HW_LANE_MUX))) {
501 pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment));
504 /* If we don't find the entry that we are looking for then
505 * we will return BP_Result_BadBiosTable.
507 if (find_valid == false)
508 return BP_RESULT_BADBIOSTABLE;
510 /* get the GPIO_I2C_INFO */
511 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
512 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
513 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
514 info->i2c_slave_address = record->i2c_slave_addr;
516 /* TODO: check how to get register offset for en, Y, etc. */
517 info->gpio_info.clk_a_register_index = le16_to_cpu(pin->data_a_reg_index);
518 info->gpio_info.clk_a_shift = pin->gpio_bitshift;
523 static struct atom_hpd_int_record *get_hpd_record_for_path_v3(struct bios_parser *bp,
524 struct atom_display_object_path_v3 *object)
526 struct atom_common_record_header *header;
530 BREAK_TO_DEBUGGER(); /* Invalid object */
534 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
537 header = GET_IMAGE(struct atom_common_record_header, offset);
542 if (header->record_type == ATOM_RECORD_END_TYPE ||
543 !header->record_size)
546 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
547 && sizeof(struct atom_hpd_int_record) <=
549 return (struct atom_hpd_int_record *) header;
551 offset += header->record_size;
557 static enum bp_result bios_parser_get_hpd_info(
559 struct graphics_object_id id,
560 struct graphics_object_hpd_info *info)
562 struct bios_parser *bp = BP_FROM_DCB(dcb);
563 struct atom_display_object_path_v2 *object;
564 struct atom_display_object_path_v3 *object_path_v3;
565 struct atom_hpd_int_record *record = NULL;
568 return BP_RESULT_BADINPUT;
570 switch (bp->object_info_tbl.revision.minor) {
573 object = get_bios_object(bp, id);
576 return BP_RESULT_BADINPUT;
578 record = get_hpd_record(bp, object);
581 object_path_v3 = get_bios_object_from_path_v3(bp, id);
584 return BP_RESULT_BADINPUT;
586 record = get_hpd_record_for_path_v3(bp, object_path_v3);
590 if (record != NULL) {
591 info->hpd_int_gpio_uid = record->pin_id;
592 info->hpd_active = record->plugin_pin_state;
596 return BP_RESULT_NORECORD;
599 static struct atom_hpd_int_record *get_hpd_record(
600 struct bios_parser *bp,
601 struct atom_display_object_path_v2 *object)
603 struct atom_common_record_header *header;
607 BREAK_TO_DEBUGGER(); /* Invalid object */
611 offset = le16_to_cpu(object->disp_recordoffset)
612 + bp->object_info_tbl_offset;
615 header = GET_IMAGE(struct atom_common_record_header, offset);
620 if (header->record_type == LAST_RECORD_TYPE ||
621 !header->record_size)
624 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
625 && sizeof(struct atom_hpd_int_record) <=
627 return (struct atom_hpd_int_record *) header;
629 offset += header->record_size;
636 * bios_parser_get_gpio_pin_info
637 * Get GpioPin information of input gpio id
639 * @dcb: pointer to the DC BIOS
641 * @info: GpioPin information structure
642 * return: Bios parser result code
644 * to get the GPIO PIN INFO, we need:
645 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
646 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
647 * to get the registerA offset/mask
649 static enum bp_result bios_parser_get_gpio_pin_info(
652 struct gpio_pin_info *info)
654 struct bios_parser *bp = BP_FROM_DCB(dcb);
655 struct atom_gpio_pin_lut_v2_1 *header;
659 if (!DATA_TABLES(gpio_pin_lut))
660 return BP_RESULT_BADBIOSTABLE;
662 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
663 DATA_TABLES(gpio_pin_lut));
665 return BP_RESULT_BADBIOSTABLE;
667 if (sizeof(struct atom_common_table_header) +
668 sizeof(struct atom_gpio_pin_assignment)
669 > le16_to_cpu(header->table_header.structuresize))
670 return BP_RESULT_BADBIOSTABLE;
672 if (header->table_header.content_revision != 1)
673 return BP_RESULT_UNSUPPORTED;
675 /* Temporary hard code gpio pin info */
676 count = (le16_to_cpu(header->table_header.structuresize)
677 - sizeof(struct atom_common_table_header))
678 / sizeof(struct atom_gpio_pin_assignment);
679 for (i = 0; i < count; ++i) {
680 if (header->gpio_pin[i].gpio_id != gpio_id)
684 (uint32_t) le16_to_cpu(
685 header->gpio_pin[i].data_a_reg_index);
686 info->offset_y = info->offset + 2;
687 info->offset_en = info->offset + 1;
688 info->offset_mask = info->offset - 1;
690 info->mask = (uint32_t) (1 <<
691 header->gpio_pin[i].gpio_bitshift);
692 info->mask_y = info->mask + 2;
693 info->mask_en = info->mask + 1;
694 info->mask_mask = info->mask - 1;
699 return BP_RESULT_NORECORD;
702 static struct device_id device_type_from_device_id(uint16_t device_id)
705 struct device_id result_device_id;
707 result_device_id.raw_device_tag = device_id;
710 case ATOM_DISPLAY_LCD1_SUPPORT:
711 result_device_id.device_type = DEVICE_TYPE_LCD;
712 result_device_id.enum_id = 1;
715 case ATOM_DISPLAY_LCD2_SUPPORT:
716 result_device_id.device_type = DEVICE_TYPE_LCD;
717 result_device_id.enum_id = 2;
720 case ATOM_DISPLAY_DFP1_SUPPORT:
721 result_device_id.device_type = DEVICE_TYPE_DFP;
722 result_device_id.enum_id = 1;
725 case ATOM_DISPLAY_DFP2_SUPPORT:
726 result_device_id.device_type = DEVICE_TYPE_DFP;
727 result_device_id.enum_id = 2;
730 case ATOM_DISPLAY_DFP3_SUPPORT:
731 result_device_id.device_type = DEVICE_TYPE_DFP;
732 result_device_id.enum_id = 3;
735 case ATOM_DISPLAY_DFP4_SUPPORT:
736 result_device_id.device_type = DEVICE_TYPE_DFP;
737 result_device_id.enum_id = 4;
740 case ATOM_DISPLAY_DFP5_SUPPORT:
741 result_device_id.device_type = DEVICE_TYPE_DFP;
742 result_device_id.enum_id = 5;
745 case ATOM_DISPLAY_DFP6_SUPPORT:
746 result_device_id.device_type = DEVICE_TYPE_DFP;
747 result_device_id.enum_id = 6;
751 BREAK_TO_DEBUGGER(); /* Invalid device Id */
752 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
753 result_device_id.enum_id = 0;
755 return result_device_id;
758 static enum bp_result bios_parser_get_device_tag(
760 struct graphics_object_id connector_object_id,
761 uint32_t device_tag_index,
762 struct connector_device_tag_info *info)
764 struct bios_parser *bp = BP_FROM_DCB(dcb);
765 struct atom_display_object_path_v2 *object;
767 struct atom_display_object_path_v3 *object_path_v3;
771 return BP_RESULT_BADINPUT;
773 switch (bp->object_info_tbl.revision.minor) {
776 /* getBiosObject will return MXM object */
777 object = get_bios_object(bp, connector_object_id);
780 BREAK_TO_DEBUGGER(); /* Invalid object id */
781 return BP_RESULT_BADINPUT;
784 info->acpi_device = 0; /* BIOS no longer provides this */
785 info->dev_id = device_type_from_device_id(object->device_tag);
788 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id);
790 if (!object_path_v3) {
791 BREAK_TO_DEBUGGER(); /* Invalid object id */
792 return BP_RESULT_BADINPUT;
794 info->acpi_device = 0; /* BIOS no longer provides this */
795 info->dev_id = device_type_from_device_id(object_path_v3->device_tag);
802 static enum bp_result get_ss_info_v4_1(
803 struct bios_parser *bp,
806 struct spread_spectrum_info *ss_info)
808 enum bp_result result = BP_RESULT_OK;
809 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
810 struct atom_smu_info_v3_3 *smu_info = NULL;
813 return BP_RESULT_BADINPUT;
815 if (!DATA_TABLES(dce_info))
816 return BP_RESULT_BADBIOSTABLE;
818 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
819 DATA_TABLES(dce_info));
821 return BP_RESULT_BADBIOSTABLE;
824 ss_info->type.STEP_AND_DELAY_INFO = false;
825 ss_info->spread_percentage_divider = 1000;
826 /* BIOS no longer uses target clock. Always enable for now */
827 ss_info->target_clock_range = 0xffffffff;
830 case AS_SIGNAL_TYPE_DVI:
831 ss_info->spread_spectrum_percentage =
832 disp_cntl_tbl->dvi_ss_percentage;
833 ss_info->spread_spectrum_range =
834 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
835 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
836 ss_info->type.CENTER_MODE = true;
838 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
840 case AS_SIGNAL_TYPE_HDMI:
841 ss_info->spread_spectrum_percentage =
842 disp_cntl_tbl->hdmi_ss_percentage;
843 ss_info->spread_spectrum_range =
844 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
845 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
846 ss_info->type.CENTER_MODE = true;
848 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
850 /* TODO LVDS not support anymore? */
851 case AS_SIGNAL_TYPE_DISPLAY_PORT:
852 ss_info->spread_spectrum_percentage =
853 disp_cntl_tbl->dp_ss_percentage;
854 ss_info->spread_spectrum_range =
855 disp_cntl_tbl->dp_ss_rate_10hz * 10;
856 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
857 ss_info->type.CENTER_MODE = true;
859 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
861 case AS_SIGNAL_TYPE_GPU_PLL:
862 /* atom_firmware: DAL only get data from dce_info table.
863 * if data within smu_info is needed for DAL, VBIOS should
864 * copy it into dce_info
866 result = BP_RESULT_UNSUPPORTED;
868 case AS_SIGNAL_TYPE_XGMI:
869 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
870 DATA_TABLES(smu_info));
872 return BP_RESULT_BADBIOSTABLE;
873 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
874 ss_info->spread_spectrum_percentage =
875 smu_info->waflclk_ss_percentage;
876 ss_info->spread_spectrum_range =
877 smu_info->gpuclk_ss_rate_10hz * 10;
878 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
879 ss_info->type.CENTER_MODE = true;
881 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
884 result = BP_RESULT_UNSUPPORTED;
890 static enum bp_result get_ss_info_v4_2(
891 struct bios_parser *bp,
894 struct spread_spectrum_info *ss_info)
896 enum bp_result result = BP_RESULT_OK;
897 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
898 struct atom_smu_info_v3_1 *smu_info = NULL;
901 return BP_RESULT_BADINPUT;
903 if (!DATA_TABLES(dce_info))
904 return BP_RESULT_BADBIOSTABLE;
906 if (!DATA_TABLES(smu_info))
907 return BP_RESULT_BADBIOSTABLE;
909 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
910 DATA_TABLES(dce_info));
912 return BP_RESULT_BADBIOSTABLE;
914 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
916 return BP_RESULT_BADBIOSTABLE;
918 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
919 ss_info->type.STEP_AND_DELAY_INFO = false;
920 ss_info->spread_percentage_divider = 1000;
921 /* BIOS no longer uses target clock. Always enable for now */
922 ss_info->target_clock_range = 0xffffffff;
925 case AS_SIGNAL_TYPE_DVI:
926 ss_info->spread_spectrum_percentage =
927 disp_cntl_tbl->dvi_ss_percentage;
928 ss_info->spread_spectrum_range =
929 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
930 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
931 ss_info->type.CENTER_MODE = true;
933 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
935 case AS_SIGNAL_TYPE_HDMI:
936 ss_info->spread_spectrum_percentage =
937 disp_cntl_tbl->hdmi_ss_percentage;
938 ss_info->spread_spectrum_range =
939 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
940 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
941 ss_info->type.CENTER_MODE = true;
943 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
945 /* TODO LVDS not support anymore? */
946 case AS_SIGNAL_TYPE_DISPLAY_PORT:
947 ss_info->spread_spectrum_percentage =
948 smu_info->gpuclk_ss_percentage;
949 ss_info->spread_spectrum_range =
950 smu_info->gpuclk_ss_rate_10hz * 10;
951 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
952 ss_info->type.CENTER_MODE = true;
954 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
956 case AS_SIGNAL_TYPE_GPU_PLL:
957 /* atom_firmware: DAL only get data from dce_info table.
958 * if data within smu_info is needed for DAL, VBIOS should
959 * copy it into dce_info
961 result = BP_RESULT_UNSUPPORTED;
964 result = BP_RESULT_UNSUPPORTED;
970 static enum bp_result get_ss_info_v4_5(
971 struct bios_parser *bp,
974 struct spread_spectrum_info *ss_info)
976 enum bp_result result = BP_RESULT_OK;
977 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
980 return BP_RESULT_BADINPUT;
982 if (!DATA_TABLES(dce_info))
983 return BP_RESULT_BADBIOSTABLE;
985 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
986 DATA_TABLES(dce_info));
988 return BP_RESULT_BADBIOSTABLE;
990 ss_info->type.STEP_AND_DELAY_INFO = false;
991 ss_info->spread_percentage_divider = 1000;
992 /* BIOS no longer uses target clock. Always enable for now */
993 ss_info->target_clock_range = 0xffffffff;
996 case AS_SIGNAL_TYPE_DVI:
997 ss_info->spread_spectrum_percentage =
998 disp_cntl_tbl->dvi_ss_percentage;
999 ss_info->spread_spectrum_range =
1000 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
1001 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1002 ss_info->type.CENTER_MODE = true;
1004 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1006 case AS_SIGNAL_TYPE_HDMI:
1007 ss_info->spread_spectrum_percentage =
1008 disp_cntl_tbl->hdmi_ss_percentage;
1009 ss_info->spread_spectrum_range =
1010 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
1011 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1012 ss_info->type.CENTER_MODE = true;
1014 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1016 case AS_SIGNAL_TYPE_DISPLAY_PORT:
1017 if (bp->base.integrated_info) {
1018 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
1019 ss_info->spread_spectrum_percentage =
1020 bp->base.integrated_info->gpuclk_ss_percentage;
1021 ss_info->type.CENTER_MODE =
1022 bp->base.integrated_info->gpuclk_ss_type;
1024 ss_info->spread_spectrum_percentage =
1025 disp_cntl_tbl->dp_ss_percentage;
1026 ss_info->spread_spectrum_range =
1027 disp_cntl_tbl->dp_ss_rate_10hz * 10;
1028 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1029 ss_info->type.CENTER_MODE = true;
1031 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1033 case AS_SIGNAL_TYPE_GPU_PLL:
1034 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore.
1035 * SMU Display PLL supposed to be without spread.
1036 * Better place for it would be in atom_display_controller_info_v4_5 table.
1038 result = BP_RESULT_UNSUPPORTED;
1041 result = BP_RESULT_UNSUPPORTED;
1049 * bios_parser_get_spread_spectrum_info
1050 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
1051 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
1052 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
1054 * there is only one entry for each signal /ss id. However, there is
1055 * no planning of supporting multiple spread Sprectum entry for EverGreen
1056 * @dcb: pointer to the DC BIOS
1057 * @signal: ASSignalType to be converted to info index
1058 * @index: number of entries that match the converted info index
1059 * @ss_info: sprectrum information structure,
1060 * return: Bios parser result code
1062 static enum bp_result bios_parser_get_spread_spectrum_info(
1063 struct dc_bios *dcb,
1064 enum as_signal_type signal,
1066 struct spread_spectrum_info *ss_info)
1068 struct bios_parser *bp = BP_FROM_DCB(dcb);
1069 enum bp_result result = BP_RESULT_UNSUPPORTED;
1070 struct atom_common_table_header *header;
1071 struct atom_data_revision tbl_revision;
1073 if (!ss_info) /* check for bad input */
1074 return BP_RESULT_BADINPUT;
1076 if (!DATA_TABLES(dce_info))
1077 return BP_RESULT_UNSUPPORTED;
1079 header = GET_IMAGE(struct atom_common_table_header,
1080 DATA_TABLES(dce_info));
1081 get_atom_data_table_revision(header, &tbl_revision);
1083 switch (tbl_revision.major) {
1085 switch (tbl_revision.minor) {
1087 return get_ss_info_v4_1(bp, signal, index, ss_info);
1091 return get_ss_info_v4_2(bp, signal, index, ss_info);
1093 return get_ss_info_v4_5(bp, signal, index, ss_info);
1103 /* there can not be more then one entry for SS Info table */
1107 static enum bp_result get_soc_bb_info_v4_4(
1108 struct bios_parser *bp,
1109 struct bp_soc_bb_info *soc_bb_info)
1111 enum bp_result result = BP_RESULT_OK;
1112 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1115 return BP_RESULT_BADINPUT;
1117 if (!DATA_TABLES(dce_info))
1118 return BP_RESULT_BADBIOSTABLE;
1120 if (!DATA_TABLES(smu_info))
1121 return BP_RESULT_BADBIOSTABLE;
1123 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1124 DATA_TABLES(dce_info));
1126 return BP_RESULT_BADBIOSTABLE;
1128 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1129 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1130 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1135 static enum bp_result get_soc_bb_info_v4_5(
1136 struct bios_parser *bp,
1137 struct bp_soc_bb_info *soc_bb_info)
1139 enum bp_result result = BP_RESULT_OK;
1140 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1143 return BP_RESULT_BADINPUT;
1145 if (!DATA_TABLES(dce_info))
1146 return BP_RESULT_BADBIOSTABLE;
1148 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1149 DATA_TABLES(dce_info));
1151 return BP_RESULT_BADBIOSTABLE;
1153 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1154 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1155 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1160 static enum bp_result bios_parser_get_soc_bb_info(
1161 struct dc_bios *dcb,
1162 struct bp_soc_bb_info *soc_bb_info)
1164 struct bios_parser *bp = BP_FROM_DCB(dcb);
1165 enum bp_result result = BP_RESULT_UNSUPPORTED;
1166 struct atom_common_table_header *header;
1167 struct atom_data_revision tbl_revision;
1169 if (!soc_bb_info) /* check for bad input */
1170 return BP_RESULT_BADINPUT;
1172 if (!DATA_TABLES(dce_info))
1173 return BP_RESULT_UNSUPPORTED;
1175 header = GET_IMAGE(struct atom_common_table_header,
1176 DATA_TABLES(dce_info));
1177 get_atom_data_table_revision(header, &tbl_revision);
1179 switch (tbl_revision.major) {
1181 switch (tbl_revision.minor) {
1187 result = get_soc_bb_info_v4_4(bp, soc_bb_info);
1190 result = get_soc_bb_info_v4_5(bp, soc_bb_info);
1203 static enum bp_result get_disp_caps_v4_1(
1204 struct bios_parser *bp,
1207 enum bp_result result = BP_RESULT_OK;
1208 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
1211 return BP_RESULT_BADINPUT;
1213 if (!DATA_TABLES(dce_info))
1214 return BP_RESULT_BADBIOSTABLE;
1216 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
1217 DATA_TABLES(dce_info));
1220 return BP_RESULT_BADBIOSTABLE;
1222 *dce_caps = disp_cntl_tbl->display_caps;
1227 static enum bp_result get_disp_caps_v4_2(
1228 struct bios_parser *bp,
1231 enum bp_result result = BP_RESULT_OK;
1232 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
1235 return BP_RESULT_BADINPUT;
1237 if (!DATA_TABLES(dce_info))
1238 return BP_RESULT_BADBIOSTABLE;
1240 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
1241 DATA_TABLES(dce_info));
1244 return BP_RESULT_BADBIOSTABLE;
1246 *dce_caps = disp_cntl_tbl->display_caps;
1251 static enum bp_result get_disp_caps_v4_3(
1252 struct bios_parser *bp,
1255 enum bp_result result = BP_RESULT_OK;
1256 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
1259 return BP_RESULT_BADINPUT;
1261 if (!DATA_TABLES(dce_info))
1262 return BP_RESULT_BADBIOSTABLE;
1264 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
1265 DATA_TABLES(dce_info));
1268 return BP_RESULT_BADBIOSTABLE;
1270 *dce_caps = disp_cntl_tbl->display_caps;
1275 static enum bp_result get_disp_caps_v4_4(
1276 struct bios_parser *bp,
1279 enum bp_result result = BP_RESULT_OK;
1280 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1283 return BP_RESULT_BADINPUT;
1285 if (!DATA_TABLES(dce_info))
1286 return BP_RESULT_BADBIOSTABLE;
1288 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1289 DATA_TABLES(dce_info));
1292 return BP_RESULT_BADBIOSTABLE;
1294 *dce_caps = disp_cntl_tbl->display_caps;
1299 static enum bp_result get_disp_caps_v4_5(
1300 struct bios_parser *bp,
1303 enum bp_result result = BP_RESULT_OK;
1304 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1307 return BP_RESULT_BADINPUT;
1309 if (!DATA_TABLES(dce_info))
1310 return BP_RESULT_BADBIOSTABLE;
1312 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1313 DATA_TABLES(dce_info));
1316 return BP_RESULT_BADBIOSTABLE;
1318 *dce_caps = disp_cntl_tbl->display_caps;
1323 static enum bp_result bios_parser_get_lttpr_interop(
1324 struct dc_bios *dcb,
1327 struct bios_parser *bp = BP_FROM_DCB(dcb);
1328 enum bp_result result = BP_RESULT_UNSUPPORTED;
1329 struct atom_common_table_header *header;
1330 struct atom_data_revision tbl_revision;
1332 if (!DATA_TABLES(dce_info))
1333 return BP_RESULT_UNSUPPORTED;
1335 header = GET_IMAGE(struct atom_common_table_header,
1336 DATA_TABLES(dce_info));
1337 get_atom_data_table_revision(header, &tbl_revision);
1338 switch (tbl_revision.major) {
1340 switch (tbl_revision.minor) {
1342 result = get_disp_caps_v4_1(bp, dce_caps);
1343 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1346 result = get_disp_caps_v4_2(bp, dce_caps);
1347 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1350 result = get_disp_caps_v4_3(bp, dce_caps);
1351 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1354 result = get_disp_caps_v4_4(bp, dce_caps);
1355 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1358 result = get_disp_caps_v4_5(bp, dce_caps);
1359 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1369 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1373 static enum bp_result bios_parser_get_lttpr_caps(
1374 struct dc_bios *dcb,
1377 struct bios_parser *bp = BP_FROM_DCB(dcb);
1378 enum bp_result result = BP_RESULT_UNSUPPORTED;
1379 struct atom_common_table_header *header;
1380 struct atom_data_revision tbl_revision;
1382 if (!DATA_TABLES(dce_info))
1383 return BP_RESULT_UNSUPPORTED;
1386 header = GET_IMAGE(struct atom_common_table_header,
1387 DATA_TABLES(dce_info));
1388 get_atom_data_table_revision(header, &tbl_revision);
1389 switch (tbl_revision.major) {
1391 switch (tbl_revision.minor) {
1393 result = get_disp_caps_v4_1(bp, dce_caps);
1394 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1397 result = get_disp_caps_v4_2(bp, dce_caps);
1398 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1401 result = get_disp_caps_v4_3(bp, dce_caps);
1402 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1405 result = get_disp_caps_v4_4(bp, dce_caps);
1406 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1409 result = get_disp_caps_v4_5(bp, dce_caps);
1410 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1419 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1420 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {
1422 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled");
1427 static enum bp_result get_embedded_panel_info_v2_1(
1428 struct bios_parser *bp,
1429 struct embedded_panel_info *info)
1431 struct lcd_info_v2_1 *lvds;
1434 return BP_RESULT_BADINPUT;
1436 if (!DATA_TABLES(lcd_info))
1437 return BP_RESULT_UNSUPPORTED;
1439 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
1442 return BP_RESULT_BADBIOSTABLE;
1444 /* TODO: previous vv1_3, should v2_1 */
1445 if (!((lvds->table_header.format_revision == 2)
1446 && (lvds->table_header.content_revision >= 1)))
1447 return BP_RESULT_UNSUPPORTED;
1449 memset(info, 0, sizeof(struct embedded_panel_info));
1451 /* We need to convert from 10KHz units into KHz units */
1452 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
1453 /* usHActive does not include borders, according to VBIOS team */
1454 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
1455 /* usHBlanking_Time includes borders, so we should really be
1456 * subtractingborders duing this translation, but LVDS generally
1457 * doesn't have borders, so we should be okay leaving this as is for
1458 * now. May need to revisit if we ever have LVDS with borders
1460 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
1461 /* usVActive does not include borders, according to VBIOS team*/
1462 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
1463 /* usVBlanking_Time includes borders, so we should really be
1464 * subtracting borders duing this translation, but LVDS generally
1465 * doesn't have borders, so we should be okay leaving this as is for
1466 * now. May need to revisit if we ever have LVDS with borders
1468 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
1469 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
1470 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
1471 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
1472 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
1473 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
1474 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
1476 /* not provided by VBIOS */
1477 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
1479 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1480 & ATOM_HSYNC_POLARITY);
1481 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1482 & ATOM_VSYNC_POLARITY);
1484 /* not provided by VBIOS */
1485 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
1487 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1488 & ATOM_H_REPLICATIONBY2);
1489 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1490 & ATOM_V_REPLICATIONBY2);
1491 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
1492 & ATOM_COMPOSITESYNC);
1493 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
1495 /* not provided by VBIOS*/
1496 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
1497 /* not provided by VBIOS*/
1500 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
1502 return BP_RESULT_OK;
1505 static enum bp_result bios_parser_get_embedded_panel_info(
1506 struct dc_bios *dcb,
1507 struct embedded_panel_info *info)
1510 *bp = BP_FROM_DCB(dcb);
1511 struct atom_common_table_header *header;
1512 struct atom_data_revision tbl_revision;
1514 if (!DATA_TABLES(lcd_info))
1515 return BP_RESULT_FAILURE;
1517 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
1520 return BP_RESULT_BADBIOSTABLE;
1522 get_atom_data_table_revision(header, &tbl_revision);
1524 switch (tbl_revision.major) {
1526 switch (tbl_revision.minor) {
1528 return get_embedded_panel_info_v2_1(bp, info);
1537 return BP_RESULT_FAILURE;
1540 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1542 enum dal_device_type device_type = device_id.device_type;
1543 uint32_t enum_id = device_id.enum_id;
1545 switch (device_type) {
1546 case DEVICE_TYPE_LCD:
1549 return ATOM_DISPLAY_LCD1_SUPPORT;
1554 case DEVICE_TYPE_DFP:
1557 return ATOM_DISPLAY_DFP1_SUPPORT;
1559 return ATOM_DISPLAY_DFP2_SUPPORT;
1561 return ATOM_DISPLAY_DFP3_SUPPORT;
1563 return ATOM_DISPLAY_DFP4_SUPPORT;
1565 return ATOM_DISPLAY_DFP5_SUPPORT;
1567 return ATOM_DISPLAY_DFP6_SUPPORT;
1576 /* Unidentified device ID, return empty support mask. */
1580 static bool bios_parser_is_device_id_supported(
1581 struct dc_bios *dcb,
1582 struct device_id id)
1584 struct bios_parser *bp = BP_FROM_DCB(dcb);
1586 uint32_t mask = get_support_mask_for_device_id(id);
1588 switch (bp->object_info_tbl.revision.minor) {
1591 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;
1594 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;
1599 static uint32_t bios_parser_get_ss_entry_number(
1600 struct dc_bios *dcb,
1601 enum as_signal_type signal)
1603 /* TODO: DAL2 atomfirmware implementation does not need this.
1604 * why DAL3 need this?
1609 static enum bp_result bios_parser_transmitter_control(
1610 struct dc_bios *dcb,
1611 struct bp_transmitter_control *cntl)
1613 struct bios_parser *bp = BP_FROM_DCB(dcb);
1615 if (!bp->cmd_tbl.transmitter_control)
1616 return BP_RESULT_FAILURE;
1618 return bp->cmd_tbl.transmitter_control(bp, cntl);
1621 static enum bp_result bios_parser_encoder_control(
1622 struct dc_bios *dcb,
1623 struct bp_encoder_control *cntl)
1625 struct bios_parser *bp = BP_FROM_DCB(dcb);
1627 if (!bp->cmd_tbl.dig_encoder_control)
1628 return BP_RESULT_FAILURE;
1630 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1633 static enum bp_result bios_parser_set_pixel_clock(
1634 struct dc_bios *dcb,
1635 struct bp_pixel_clock_parameters *bp_params)
1637 struct bios_parser *bp = BP_FROM_DCB(dcb);
1639 if (!bp->cmd_tbl.set_pixel_clock)
1640 return BP_RESULT_FAILURE;
1642 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1645 static enum bp_result bios_parser_set_dce_clock(
1646 struct dc_bios *dcb,
1647 struct bp_set_dce_clock_parameters *bp_params)
1649 struct bios_parser *bp = BP_FROM_DCB(dcb);
1651 if (!bp->cmd_tbl.set_dce_clock)
1652 return BP_RESULT_FAILURE;
1654 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1657 static enum bp_result bios_parser_program_crtc_timing(
1658 struct dc_bios *dcb,
1659 struct bp_hw_crtc_timing_parameters *bp_params)
1661 struct bios_parser *bp = BP_FROM_DCB(dcb);
1663 if (!bp->cmd_tbl.set_crtc_timing)
1664 return BP_RESULT_FAILURE;
1666 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1669 static enum bp_result bios_parser_enable_crtc(
1670 struct dc_bios *dcb,
1671 enum controller_id id,
1674 struct bios_parser *bp = BP_FROM_DCB(dcb);
1676 if (!bp->cmd_tbl.enable_crtc)
1677 return BP_RESULT_FAILURE;
1679 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1682 static enum bp_result bios_parser_enable_disp_power_gating(
1683 struct dc_bios *dcb,
1684 enum controller_id controller_id,
1685 enum bp_pipe_control_action action)
1687 struct bios_parser *bp = BP_FROM_DCB(dcb);
1689 if (!bp->cmd_tbl.enable_disp_power_gating)
1690 return BP_RESULT_FAILURE;
1692 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1696 static enum bp_result bios_parser_enable_lvtma_control(
1697 struct dc_bios *dcb,
1699 uint8_t pwrseq_instance,
1700 uint8_t bypass_panel_control_wait)
1702 struct bios_parser *bp = BP_FROM_DCB(dcb);
1704 if (!bp->cmd_tbl.enable_lvtma_control)
1705 return BP_RESULT_FAILURE;
1707 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, pwrseq_instance, bypass_panel_control_wait);
1710 static bool bios_parser_is_accelerated_mode(
1711 struct dc_bios *dcb)
1713 return bios_is_accelerated_mode(dcb);
1717 * bios_parser_set_scratch_critical_state - update critical state bit
1718 * in VBIOS scratch register
1720 * @dcb: pointer to the DC BIO
1721 * @state: set or reset state
1723 static void bios_parser_set_scratch_critical_state(
1724 struct dc_bios *dcb,
1727 bios_set_scratch_critical_state(dcb, state);
1730 static enum bp_result bios_parser_get_firmware_info(
1731 struct dc_bios *dcb,
1732 struct dc_firmware_info *info)
1734 struct bios_parser *bp = BP_FROM_DCB(dcb);
1735 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
1736 struct atom_common_table_header *header;
1738 struct atom_data_revision revision;
1740 if (info && DATA_TABLES(firmwareinfo)) {
1741 header = GET_IMAGE(struct atom_common_table_header,
1742 DATA_TABLES(firmwareinfo));
1743 get_atom_data_table_revision(header, &revision);
1744 switch (revision.major) {
1746 switch (revision.minor) {
1748 result = get_firmware_info_v3_1(bp, info);
1752 result = get_firmware_info_v3_2(bp, info);
1755 result = get_firmware_info_v3_4(bp, info);
1769 static enum bp_result get_firmware_info_v3_1(
1770 struct bios_parser *bp,
1771 struct dc_firmware_info *info)
1773 struct atom_firmware_info_v3_1 *firmware_info;
1774 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1777 return BP_RESULT_BADINPUT;
1779 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1780 DATA_TABLES(firmwareinfo));
1782 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1783 DATA_TABLES(dce_info));
1785 if (!firmware_info || !dce_info)
1786 return BP_RESULT_BADBIOSTABLE;
1788 memset(info, 0, sizeof(*info));
1790 /* Pixel clock pll information. */
1791 /* We need to convert from 10KHz units into KHz units */
1792 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1793 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1795 /* 27MHz for Vega10: */
1796 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1798 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1799 if (info->pll_info.crystal_frequency == 0)
1800 info->pll_info.crystal_frequency = 27000;
1801 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1802 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1803 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1805 /* Get GPU PLL VCO Clock */
1807 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1808 /* VBIOS gives in 10KHz */
1809 info->smu_gpu_pll_output_freq =
1810 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1813 info->oem_i2c_present = false;
1815 return BP_RESULT_OK;
1818 static enum bp_result get_firmware_info_v3_2(
1819 struct bios_parser *bp,
1820 struct dc_firmware_info *info)
1822 struct atom_firmware_info_v3_2 *firmware_info;
1823 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1824 struct atom_common_table_header *header;
1825 struct atom_data_revision revision;
1826 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1827 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1830 return BP_RESULT_BADINPUT;
1832 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1833 DATA_TABLES(firmwareinfo));
1835 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1836 DATA_TABLES(dce_info));
1838 if (!firmware_info || !dce_info)
1839 return BP_RESULT_BADBIOSTABLE;
1841 memset(info, 0, sizeof(*info));
1843 header = GET_IMAGE(struct atom_common_table_header,
1844 DATA_TABLES(smu_info));
1845 get_atom_data_table_revision(header, &revision);
1847 if (revision.minor == 2) {
1849 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1850 DATA_TABLES(smu_info));
1852 return BP_RESULT_BADBIOSTABLE;
1854 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage);
1856 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1857 } else if (revision.minor == 3) {
1859 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1860 DATA_TABLES(smu_info));
1862 return BP_RESULT_BADBIOSTABLE;
1864 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage);
1866 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1869 // We need to convert from 10KHz units into KHz units.
1870 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1872 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1873 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1874 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1875 if (info->pll_info.crystal_frequency == 0) {
1876 if (revision.minor == 2)
1877 info->pll_info.crystal_frequency = 27000;
1878 else if (revision.minor == 3)
1879 info->pll_info.crystal_frequency = 100000;
1881 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1882 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1883 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1885 /* Get GPU PLL VCO Clock */
1886 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1887 if (revision.minor == 2)
1888 info->smu_gpu_pll_output_freq =
1889 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1890 else if (revision.minor == 3)
1891 info->smu_gpu_pll_output_freq =
1892 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1895 if (firmware_info->board_i2c_feature_id == 0x2) {
1896 info->oem_i2c_present = true;
1897 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1899 info->oem_i2c_present = false;
1902 return BP_RESULT_OK;
1905 static enum bp_result get_firmware_info_v3_4(
1906 struct bios_parser *bp,
1907 struct dc_firmware_info *info)
1909 struct atom_firmware_info_v3_4 *firmware_info;
1910 struct atom_common_table_header *header;
1911 struct atom_data_revision revision;
1912 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
1913 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
1915 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL;
1916 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
1917 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL;
1920 return BP_RESULT_BADINPUT;
1922 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4,
1923 DATA_TABLES(firmwareinfo));
1926 return BP_RESULT_BADBIOSTABLE;
1928 memset(info, 0, sizeof(*info));
1930 header = GET_IMAGE(struct atom_common_table_header,
1931 DATA_TABLES(dce_info));
1933 get_atom_data_table_revision(header, &revision);
1935 switch (revision.major) {
1937 switch (revision.minor) {
1939 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
1940 DATA_TABLES(dce_info));
1943 return BP_RESULT_BADBIOSTABLE;
1945 /* 100MHz expected */
1946 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
1947 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10;
1948 /* 50MHz expected */
1949 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10;
1951 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */
1955 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
1956 DATA_TABLES(dce_info));
1959 return BP_RESULT_BADBIOSTABLE;
1961 /* 100MHz expected */
1962 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;
1963 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10;
1964 /* 50MHz expected */
1965 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10;
1967 /* Get SMU Display PLL VCO Frequency in KHz*/
1968 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10;
1972 /* should not come here, keep as backup, as was before */
1973 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1,
1974 DATA_TABLES(dce_info));
1977 return BP_RESULT_BADBIOSTABLE;
1979 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;
1980 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10;
1981 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10;
1991 header = GET_IMAGE(struct atom_common_table_header,
1992 DATA_TABLES(smu_info));
1993 get_atom_data_table_revision(header, &revision);
1995 switch (revision.major) {
1997 switch (revision.minor) {
1999 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5,
2000 DATA_TABLES(smu_info));
2003 return BP_RESULT_BADBIOSTABLE;
2004 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage);
2005 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10;
2014 switch (revision.minor) {
2016 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0,
2017 DATA_TABLES(smu_info));
2020 return BP_RESULT_BADBIOSTABLE;
2022 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */
2034 // We need to convert from 10KHz units into KHz units.
2035 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
2037 if (firmware_info->board_i2c_feature_id == 0x2) {
2038 info->oem_i2c_present = true;
2039 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
2041 info->oem_i2c_present = false;
2044 return BP_RESULT_OK;
2047 static enum bp_result bios_parser_get_encoder_cap_info(
2048 struct dc_bios *dcb,
2049 struct graphics_object_id object_id,
2050 struct bp_encoder_cap_info *info)
2052 struct bios_parser *bp = BP_FROM_DCB(dcb);
2053 struct atom_display_object_path_v2 *object;
2054 struct atom_encoder_caps_record *record = NULL;
2057 return BP_RESULT_BADINPUT;
2059 #if defined(CONFIG_DRM_AMD_DC_FP)
2060 /* encoder cap record not available in v1_5 */
2061 if (bp->object_info_tbl.revision.minor == 5)
2062 return BP_RESULT_NORECORD;
2065 object = get_bios_object(bp, object_id);
2068 return BP_RESULT_BADINPUT;
2070 record = get_encoder_cap_record(bp, object);
2072 return BP_RESULT_NORECORD;
2073 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id);
2075 info->DP_HBR2_CAP = (record->encodercaps &
2076 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
2077 info->DP_HBR2_EN = (record->encodercaps &
2078 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
2079 info->DP_HBR3_EN = (record->encodercaps &
2080 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
2081 info->HDMI_6GB_EN = (record->encodercaps &
2082 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
2083 info->IS_DP2_CAPABLE = (record->encodercaps &
2084 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;
2085 info->DP_UHBR10_EN = (record->encodercaps &
2086 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0;
2087 info->DP_UHBR13_5_EN = (record->encodercaps &
2088 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;
2089 info->DP_UHBR20_EN = (record->encodercaps &
2090 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
2091 info->DP_IS_USB_C = (record->encodercaps &
2092 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
2093 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C);
2095 return BP_RESULT_OK;
2099 static struct atom_encoder_caps_record *get_encoder_cap_record(
2100 struct bios_parser *bp,
2101 struct atom_display_object_path_v2 *object)
2103 struct atom_common_record_header *header;
2107 BREAK_TO_DEBUGGER(); /* Invalid object */
2111 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
2114 header = GET_IMAGE(struct atom_common_record_header, offset);
2119 offset += header->record_size;
2121 if (header->record_type == LAST_RECORD_TYPE ||
2122 !header->record_size)
2125 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
2128 if (sizeof(struct atom_encoder_caps_record) <=
2129 header->record_size)
2130 return (struct atom_encoder_caps_record *)header;
2136 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
2137 struct bios_parser *bp,
2138 struct atom_display_object_path_v2 *object)
2140 struct atom_common_record_header *header;
2144 BREAK_TO_DEBUGGER(); /* Invalid object */
2148 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2151 header = GET_IMAGE(struct atom_common_record_header, offset);
2156 offset += header->record_size;
2158 if (header->record_type == LAST_RECORD_TYPE ||
2159 !header->record_size)
2162 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE)
2165 if (sizeof(struct atom_disp_connector_caps_record) <=
2166 header->record_size)
2167 return (struct atom_disp_connector_caps_record *)header;
2173 static struct atom_connector_caps_record *get_connector_caps_record(struct bios_parser *bp,
2174 struct atom_display_object_path_v3 *object)
2176 struct atom_common_record_header *header;
2180 BREAK_TO_DEBUGGER(); /* Invalid object */
2184 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2187 header = GET_IMAGE(struct atom_common_record_header, offset);
2192 offset += header->record_size;
2194 if (header->record_type == ATOM_RECORD_END_TYPE ||
2195 !header->record_size)
2198 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE)
2201 if (sizeof(struct atom_connector_caps_record) <= header->record_size)
2202 return (struct atom_connector_caps_record *)header;
2208 static enum bp_result bios_parser_get_disp_connector_caps_info(
2209 struct dc_bios *dcb,
2210 struct graphics_object_id object_id,
2211 struct bp_disp_connector_caps_info *info)
2213 struct bios_parser *bp = BP_FROM_DCB(dcb);
2214 struct atom_display_object_path_v2 *object;
2215 struct atom_display_object_path_v3 *object_path_v3;
2216 struct atom_connector_caps_record *record_path_v3;
2217 struct atom_disp_connector_caps_record *record = NULL;
2220 return BP_RESULT_BADINPUT;
2222 switch (bp->object_info_tbl.revision.minor) {
2225 object = get_bios_object(bp, object_id);
2228 return BP_RESULT_BADINPUT;
2230 record = get_disp_connector_caps_record(bp, object);
2232 return BP_RESULT_NORECORD;
2234 info->INTERNAL_DISPLAY =
2235 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;
2236 info->INTERNAL_DISPLAY_BL =
2237 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;
2240 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2242 if (!object_path_v3)
2243 return BP_RESULT_BADINPUT;
2245 record_path_v3 = get_connector_caps_record(bp, object_path_v3);
2246 if (!record_path_v3)
2247 return BP_RESULT_NORECORD;
2249 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
2251 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
2256 return BP_RESULT_OK;
2259 static struct atom_connector_speed_record *get_connector_speed_cap_record(struct bios_parser *bp,
2260 struct atom_display_object_path_v3 *object)
2262 struct atom_common_record_header *header;
2266 BREAK_TO_DEBUGGER(); /* Invalid object */
2270 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2273 header = GET_IMAGE(struct atom_common_record_header, offset);
2278 offset += header->record_size;
2280 if (header->record_type == ATOM_RECORD_END_TYPE ||
2281 !header->record_size)
2284 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO)
2287 if (sizeof(struct atom_connector_speed_record) <= header->record_size)
2288 return (struct atom_connector_speed_record *)header;
2294 static enum bp_result bios_parser_get_connector_speed_cap_info(
2295 struct dc_bios *dcb,
2296 struct graphics_object_id object_id,
2297 struct bp_connector_speed_cap_info *info)
2299 struct bios_parser *bp = BP_FROM_DCB(dcb);
2300 struct atom_display_object_path_v3 *object_path_v3;
2301 //struct atom_connector_speed_record *record = NULL;
2302 struct atom_connector_speed_record *record;
2305 return BP_RESULT_BADINPUT;
2307 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2309 if (!object_path_v3)
2310 return BP_RESULT_BADINPUT;
2312 record = get_connector_speed_cap_record(bp, object_path_v3);
2314 return BP_RESULT_NORECORD;
2316 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0;
2317 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0;
2318 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0;
2319 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0;
2320 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0;
2321 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0;
2322 return BP_RESULT_OK;
2325 static enum bp_result get_vram_info_v23(
2326 struct bios_parser *bp,
2327 struct dc_vram_info *info)
2329 struct atom_vram_info_header_v2_3 *info_v23;
2330 static enum bp_result result = BP_RESULT_OK;
2332 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
2333 DATA_TABLES(vram_info));
2335 if (info_v23 == NULL)
2336 return BP_RESULT_BADBIOSTABLE;
2338 info->num_chans = info_v23->vram_module[0].channel_num;
2339 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
2344 static enum bp_result get_vram_info_v24(
2345 struct bios_parser *bp,
2346 struct dc_vram_info *info)
2348 struct atom_vram_info_header_v2_4 *info_v24;
2349 static enum bp_result result = BP_RESULT_OK;
2351 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
2352 DATA_TABLES(vram_info));
2354 if (info_v24 == NULL)
2355 return BP_RESULT_BADBIOSTABLE;
2357 info->num_chans = info_v24->vram_module[0].channel_num;
2358 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
2363 static enum bp_result get_vram_info_v25(
2364 struct bios_parser *bp,
2365 struct dc_vram_info *info)
2367 struct atom_vram_info_header_v2_5 *info_v25;
2368 static enum bp_result result = BP_RESULT_OK;
2370 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
2371 DATA_TABLES(vram_info));
2373 if (info_v25 == NULL)
2374 return BP_RESULT_BADBIOSTABLE;
2376 info->num_chans = info_v25->vram_module[0].channel_num;
2377 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
2382 static enum bp_result get_vram_info_v30(
2383 struct bios_parser *bp,
2384 struct dc_vram_info *info)
2386 struct atom_vram_info_header_v3_0 *info_v30;
2387 enum bp_result result = BP_RESULT_OK;
2389 info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0,
2390 DATA_TABLES(vram_info));
2392 if (info_v30 == NULL)
2393 return BP_RESULT_BADBIOSTABLE;
2395 info->num_chans = info_v30->channel_num;
2396 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2402 * get_integrated_info_v11
2405 * Get V8 integrated BIOS information
2408 * bios_parser *bp - [in]BIOS parser handler to get master data table
2409 * integrated_info *info - [out] store and output integrated info
2412 * static enum bp_result - BP_RESULT_OK if information is available,
2413 * BP_RESULT_BADBIOSTABLE otherwise.
2415 static enum bp_result get_integrated_info_v11(
2416 struct bios_parser *bp,
2417 struct integrated_info *info)
2419 struct atom_integrated_system_info_v1_11 *info_v11;
2422 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
2423 DATA_TABLES(integratedsysteminfo));
2425 if (info_v11 == NULL)
2426 return BP_RESULT_BADBIOSTABLE;
2428 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage);
2430 info->gpu_cap_info =
2431 le32_to_cpu(info_v11->gpucapinfo);
2433 * system_config: Bit[0] = 0 : PCIE power gating disabled
2434 * = 1 : PCIE power gating enabled
2435 * Bit[1] = 0 : DDR-PLL shut down disabled
2436 * = 1 : DDR-PLL shut down enabled
2437 * Bit[2] = 0 : DDR-PLL power down disabled
2438 * = 1 : DDR-PLL power down enabled
2440 info->system_config = le32_to_cpu(info_v11->system_config);
2441 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
2442 info->memory_type = info_v11->memorytype;
2443 info->ma_channel_number = info_v11->umachannelnumber;
2444 info->lvds_ss_percentage =
2445 le16_to_cpu(info_v11->lvds_ss_percentage);
2446 info->dp_ss_control =
2447 le16_to_cpu(info_v11->reserved1);
2448 info->lvds_sspread_rate_in_10hz =
2449 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
2450 info->hdmi_ss_percentage =
2451 le16_to_cpu(info_v11->hdmi_ss_percentage);
2452 info->hdmi_sspread_rate_in_10hz =
2453 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
2454 info->dvi_ss_percentage =
2455 le16_to_cpu(info_v11->dvi_ss_percentage);
2456 info->dvi_sspread_rate_in_10_hz =
2457 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
2458 info->lvds_misc = info_v11->lvds_misc;
2459 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2460 info->ext_disp_conn_info.gu_id[i] =
2461 info_v11->extdispconninfo.guid[i];
2464 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2465 info->ext_disp_conn_info.path[i].device_connector_id =
2466 object_id_from_bios_object_id(
2467 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
2469 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2470 object_id_from_bios_object_id(
2472 info_v11->extdispconninfo.path[i].ext_encoder_objid));
2474 info->ext_disp_conn_info.path[i].device_tag =
2476 info_v11->extdispconninfo.path[i].device_tag);
2477 info->ext_disp_conn_info.path[i].device_acpi_enum =
2479 info_v11->extdispconninfo.path[i].device_acpi_enum);
2480 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2481 info_v11->extdispconninfo.path[i].auxddclut_index;
2482 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2483 info_v11->extdispconninfo.path[i].hpdlut_index;
2484 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2485 info_v11->extdispconninfo.path[i].channelmapping;
2486 info->ext_disp_conn_info.path[i].caps =
2487 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
2489 info->ext_disp_conn_info.checksum =
2490 info_v11->extdispconninfo.checksum;
2492 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
2493 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
2494 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2495 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2496 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2497 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2498 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2500 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
2501 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2502 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2503 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2504 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2505 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2508 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
2509 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
2510 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2511 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2512 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2513 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2514 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2516 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
2517 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2518 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2519 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2520 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2521 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2524 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
2525 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
2526 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2527 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2528 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2529 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2530 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2532 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
2533 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2534 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2535 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2536 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2537 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2540 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
2541 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
2542 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2543 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2544 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2545 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2546 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2548 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
2549 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2550 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2551 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2552 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2553 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2557 /** TODO - review **/
2559 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
2561 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
2562 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
2564 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
2565 /* Convert [10KHz] into [KHz] */
2566 info->disp_clk_voltage[i].max_supported_clk =
2567 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
2568 ulMaximumSupportedCLK) * 10;
2569 info->disp_clk_voltage[i].voltage_index =
2570 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
2573 info->boot_up_req_display_vector =
2574 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
2575 info->boot_up_nb_voltage =
2576 le16_to_cpu(info_v11->usBootUpNBVoltage);
2577 info->ext_disp_conn_info_offset =
2578 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
2579 info->gmc_restore_reset_time =
2580 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
2581 info->minimum_n_clk =
2582 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
2583 for (i = 1; i < 4; ++i)
2584 info->minimum_n_clk =
2585 info->minimum_n_clk <
2586 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
2587 info->minimum_n_clk : le32_to_cpu(
2588 info_v11->ulNbpStateNClkFreq[i]);
2590 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
2591 info->ddr_dll_power_up_time =
2592 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
2593 info->ddr_pll_power_up_time =
2594 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
2595 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
2596 info->max_lvds_pclk_freq_in_single_link =
2597 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2598 info->max_lvds_pclk_freq_in_single_link =
2599 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2600 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
2601 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
2602 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
2603 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
2604 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
2605 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
2606 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
2607 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
2608 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
2609 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
2610 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
2611 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
2612 info->lvds_off_to_on_delay_in_4ms =
2613 info_v11->ucLVDSOffToOnDelay_in4Ms;
2614 info->lvds_bit_depth_control_val =
2615 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
2617 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
2618 /* Convert [10KHz] into [KHz] */
2619 info->avail_s_clk[i].supported_s_clk =
2620 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
2622 info->avail_s_clk[i].voltage_index =
2623 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
2624 info->avail_s_clk[i].voltage_id =
2625 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
2629 return BP_RESULT_OK;
2632 static enum bp_result get_integrated_info_v2_1(
2633 struct bios_parser *bp,
2634 struct integrated_info *info)
2636 struct atom_integrated_system_info_v2_1 *info_v2_1;
2639 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
2640 DATA_TABLES(integratedsysteminfo));
2642 if (info_v2_1 == NULL)
2643 return BP_RESULT_BADBIOSTABLE;
2645 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage);
2647 info->gpu_cap_info =
2648 le32_to_cpu(info_v2_1->gpucapinfo);
2650 * system_config: Bit[0] = 0 : PCIE power gating disabled
2651 * = 1 : PCIE power gating enabled
2652 * Bit[1] = 0 : DDR-PLL shut down disabled
2653 * = 1 : DDR-PLL shut down enabled
2654 * Bit[2] = 0 : DDR-PLL power down disabled
2655 * = 1 : DDR-PLL power down enabled
2657 info->system_config = le32_to_cpu(info_v2_1->system_config);
2658 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
2659 info->memory_type = info_v2_1->memorytype;
2660 info->ma_channel_number = info_v2_1->umachannelnumber;
2661 info->dp_ss_control =
2662 le16_to_cpu(info_v2_1->reserved1);
2664 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2665 info->ext_disp_conn_info.gu_id[i] =
2666 info_v2_1->extdispconninfo.guid[i];
2669 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2670 info->ext_disp_conn_info.path[i].device_connector_id =
2671 object_id_from_bios_object_id(
2672 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
2674 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2675 object_id_from_bios_object_id(
2677 info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
2679 info->ext_disp_conn_info.path[i].device_tag =
2681 info_v2_1->extdispconninfo.path[i].device_tag);
2682 info->ext_disp_conn_info.path[i].device_acpi_enum =
2684 info_v2_1->extdispconninfo.path[i].device_acpi_enum);
2685 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2686 info_v2_1->extdispconninfo.path[i].auxddclut_index;
2687 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2688 info_v2_1->extdispconninfo.path[i].hpdlut_index;
2689 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2690 info_v2_1->extdispconninfo.path[i].channelmapping;
2691 info->ext_disp_conn_info.path[i].caps =
2692 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
2695 info->ext_disp_conn_info.checksum =
2696 info_v2_1->extdispconninfo.checksum;
2697 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
2698 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
2699 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2700 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2701 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2702 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2703 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2705 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
2706 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2707 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2708 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2709 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2710 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2712 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
2713 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
2714 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2715 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2716 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2717 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2718 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2720 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
2721 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2722 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2723 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2724 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2725 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2727 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
2728 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
2729 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2730 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2731 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2732 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2733 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2735 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
2736 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2737 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2738 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2739 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2740 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2742 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
2743 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
2744 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2745 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2746 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2747 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2748 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2750 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
2751 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2752 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2753 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2754 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2755 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2758 info->edp1_info.edp_backlight_pwm_hz =
2759 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
2760 info->edp1_info.edp_ss_percentage =
2761 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
2762 info->edp1_info.edp_ss_rate_10hz =
2763 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
2764 info->edp1_info.edp_pwr_on_off_delay =
2765 info_v2_1->edp1_info.edp_pwr_on_off_delay;
2766 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2767 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
2768 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2769 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2770 info->edp1_info.edp_panel_bpc =
2771 info_v2_1->edp1_info.edp_panel_bpc;
2772 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level;
2774 info->edp2_info.edp_backlight_pwm_hz =
2775 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
2776 info->edp2_info.edp_ss_percentage =
2777 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
2778 info->edp2_info.edp_ss_rate_10hz =
2779 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
2780 info->edp2_info.edp_pwr_on_off_delay =
2781 info_v2_1->edp2_info.edp_pwr_on_off_delay;
2782 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2783 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
2784 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2785 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2786 info->edp2_info.edp_panel_bpc =
2787 info_v2_1->edp2_info.edp_panel_bpc;
2788 info->edp2_info.edp_bootup_bl_level =
2789 info_v2_1->edp2_info.edp_bootup_bl_level;
2791 return BP_RESULT_OK;
2794 static enum bp_result get_integrated_info_v2_2(
2795 struct bios_parser *bp,
2796 struct integrated_info *info)
2798 struct atom_integrated_system_info_v2_2 *info_v2_2;
2801 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
2802 DATA_TABLES(integratedsysteminfo));
2804 if (info_v2_2 == NULL)
2805 return BP_RESULT_BADBIOSTABLE;
2807 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage);
2809 info->gpu_cap_info =
2810 le32_to_cpu(info_v2_2->gpucapinfo);
2812 * system_config: Bit[0] = 0 : PCIE power gating disabled
2813 * = 1 : PCIE power gating enabled
2814 * Bit[1] = 0 : DDR-PLL shut down disabled
2815 * = 1 : DDR-PLL shut down enabled
2816 * Bit[2] = 0 : DDR-PLL power down disabled
2817 * = 1 : DDR-PLL power down enabled
2819 info->system_config = le32_to_cpu(info_v2_2->system_config);
2820 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo);
2821 info->memory_type = info_v2_2->memorytype;
2822 info->ma_channel_number = info_v2_2->umachannelnumber;
2823 info->dp_ss_control =
2824 le16_to_cpu(info_v2_2->reserved1);
2825 info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage;
2826 info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type;
2828 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2829 info->ext_disp_conn_info.gu_id[i] =
2830 info_v2_2->extdispconninfo.guid[i];
2833 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2834 info->ext_disp_conn_info.path[i].device_connector_id =
2835 object_id_from_bios_object_id(
2836 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid));
2838 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2839 object_id_from_bios_object_id(
2841 info_v2_2->extdispconninfo.path[i].ext_encoder_objid));
2843 info->ext_disp_conn_info.path[i].device_tag =
2845 info_v2_2->extdispconninfo.path[i].device_tag);
2846 info->ext_disp_conn_info.path[i].device_acpi_enum =
2848 info_v2_2->extdispconninfo.path[i].device_acpi_enum);
2849 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2850 info_v2_2->extdispconninfo.path[i].auxddclut_index;
2851 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2852 info_v2_2->extdispconninfo.path[i].hpdlut_index;
2853 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2854 info_v2_2->extdispconninfo.path[i].channelmapping;
2855 info->ext_disp_conn_info.path[i].caps =
2856 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
2859 info->ext_disp_conn_info.checksum =
2860 info_v2_2->extdispconninfo.checksum;
2861 info->ext_disp_conn_info.fixdpvoltageswing =
2862 info_v2_2->extdispconninfo.fixdpvoltageswing;
2864 info->edp1_info.edp_backlight_pwm_hz =
2865 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);
2866 info->edp1_info.edp_ss_percentage =
2867 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage);
2868 info->edp1_info.edp_ss_rate_10hz =
2869 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz);
2870 info->edp1_info.edp_pwr_on_off_delay =
2871 info_v2_2->edp1_info.edp_pwr_on_off_delay;
2872 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2873 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon;
2874 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2875 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2876 info->edp1_info.edp_panel_bpc =
2877 info_v2_2->edp1_info.edp_panel_bpc;
2878 info->edp1_info.edp_bootup_bl_level =
2880 info->edp2_info.edp_backlight_pwm_hz =
2881 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
2882 info->edp2_info.edp_ss_percentage =
2883 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage);
2884 info->edp2_info.edp_ss_rate_10hz =
2885 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz);
2886 info->edp2_info.edp_pwr_on_off_delay =
2887 info_v2_2->edp2_info.edp_pwr_on_off_delay;
2888 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2889 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon;
2890 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2891 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2892 info->edp2_info.edp_panel_bpc =
2893 info_v2_2->edp2_info.edp_panel_bpc;
2894 info->edp2_info.edp_bootup_bl_level =
2895 info_v2_2->edp2_info.edp_bootup_bl_level;
2897 return BP_RESULT_OK;
2901 * construct_integrated_info
2904 * Get integrated BIOS information based on table revision
2907 * bios_parser *bp - [in]BIOS parser handler to get master data table
2908 * integrated_info *info - [out] store and output integrated info
2911 * static enum bp_result - BP_RESULT_OK if information is available,
2912 * BP_RESULT_BADBIOSTABLE otherwise.
2914 static enum bp_result construct_integrated_info(
2915 struct bios_parser *bp,
2916 struct integrated_info *info)
2918 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
2920 struct atom_common_table_header *header;
2921 struct atom_data_revision revision;
2926 if (info && DATA_TABLES(integratedsysteminfo)) {
2927 header = GET_IMAGE(struct atom_common_table_header,
2928 DATA_TABLES(integratedsysteminfo));
2930 get_atom_data_table_revision(header, &revision);
2932 switch (revision.major) {
2934 switch (revision.minor) {
2937 result = get_integrated_info_v11(bp, info);
2944 switch (revision.minor) {
2946 result = get_integrated_info_v2_1(bp, info);
2950 result = get_integrated_info_v2_2(bp, info);
2959 if (result == BP_RESULT_OK) {
2961 DC_LOG_BIOS("edp1:\n"
2962 "\tedp_pwr_on_off_delay = %d\n"
2963 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
2964 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
2965 "\tedp_bootup_bl_level = %d\n",
2966 info->edp1_info.edp_pwr_on_off_delay,
2967 info->edp1_info.edp_pwr_on_vary_bl_to_blon,
2968 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff,
2969 info->edp1_info.edp_bootup_bl_level);
2970 DC_LOG_BIOS("edp2:\n"
2971 "\tedp_pwr_on_off_delayv = %d\n"
2972 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
2973 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
2974 "\tedp_bootup_bl_level = %d\n",
2975 info->edp2_info.edp_pwr_on_off_delay,
2976 info->edp2_info.edp_pwr_on_vary_bl_to_blon,
2977 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff,
2978 info->edp2_info.edp_bootup_bl_level);
2982 if (result != BP_RESULT_OK)
2985 // Log each external path
2986 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
2987 if (info->ext_disp_conn_info.path[i].device_tag != 0)
2988 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n"
2989 "DEVICE_TAG: 0x%x\n"
2990 "DEVICE_ACPI_ENUM: 0x%x\n"
2991 "DEVICE_CONNECTOR_ID: 0x%x\n"
2992 "EXT_AUX_DDC_LUT_INDEX: %d\n"
2993 "EXT_HPD_PIN_LUT_INDEX: %d\n"
2994 "EXT_ENCODER_OBJ_ID: 0x%x\n"
2995 "Encoder CAPS: 0x%x\n",
2997 info->ext_disp_conn_info.path[i].device_tag,
2998 info->ext_disp_conn_info.path[i].device_acpi_enum,
2999 info->ext_disp_conn_info.path[i].device_connector_id.id,
3000 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index,
3001 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index,
3002 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id,
3003 info->ext_disp_conn_info.path[i].caps
3005 if (info->ext_disp_conn_info.path[i].caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
3006 DC_LOG_BIOS("BIOS EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3007 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {
3008 info->ext_disp_conn_info.path[i].caps |= EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;
3009 DC_LOG_BIOS("driver forced EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3012 // Log the Checksum and Voltage Swing
3013 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n"
3014 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n",
3015 info->ext_disp_conn_info.checksum,
3016 info->ext_disp_conn_info.fixdpvoltageswing);
3017 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {
3018 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;
3019 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing);
3022 /* Sort voltage table from low to high*/
3023 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
3024 for (j = i; j > 0; --j) {
3025 if (info->disp_clk_voltage[j].max_supported_clk <
3026 info->disp_clk_voltage[j-1].max_supported_clk)
3027 swap(info->disp_clk_voltage[j-1], info->disp_clk_voltage[j]);
3034 static enum bp_result bios_parser_get_vram_info(
3035 struct dc_bios *dcb,
3036 struct dc_vram_info *info)
3038 struct bios_parser *bp = BP_FROM_DCB(dcb);
3039 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
3040 struct atom_common_table_header *header;
3041 struct atom_data_revision revision;
3043 if (info && DATA_TABLES(vram_info)) {
3044 header = GET_IMAGE(struct atom_common_table_header,
3045 DATA_TABLES(vram_info));
3047 get_atom_data_table_revision(header, &revision);
3049 switch (revision.major) {
3051 switch (revision.minor) {
3053 result = get_vram_info_v23(bp, info);
3056 result = get_vram_info_v24(bp, info);
3059 result = get_vram_info_v25(bp, info);
3067 switch (revision.minor) {
3069 result = get_vram_info_v30(bp, info);
3084 static struct integrated_info *bios_parser_create_integrated_info(
3085 struct dc_bios *dcb)
3087 struct bios_parser *bp = BP_FROM_DCB(dcb);
3088 struct integrated_info *info;
3090 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
3097 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
3105 static enum bp_result update_slot_layout_info(
3106 struct dc_bios *dcb,
3108 struct slot_layout_info *slot_layout_info)
3110 unsigned int record_offset;
3112 struct atom_display_object_path_v2 *object;
3113 struct atom_bracket_layout_record *record;
3114 struct atom_common_record_header *record_header;
3115 static enum bp_result result;
3116 struct bios_parser *bp;
3117 struct object_info_table *tbl;
3118 struct display_object_info_table_v1_4 *v1_4;
3121 record_header = NULL;
3122 result = BP_RESULT_NORECORD;
3124 bp = BP_FROM_DCB(dcb);
3125 tbl = &bp->object_info_tbl;
3128 object = &v1_4->display_path[i];
3129 record_offset = (unsigned int)
3130 (object->disp_recordoffset) +
3131 (unsigned int)(bp->object_info_tbl_offset);
3135 record_header = (struct atom_common_record_header *)
3136 GET_IMAGE(struct atom_common_record_header,
3138 if (record_header == NULL) {
3139 result = BP_RESULT_BADBIOSTABLE;
3143 /* the end of the list */
3144 if (record_header->record_type == 0xff ||
3145 record_header->record_size == 0) {
3149 if (record_header->record_type ==
3150 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
3151 sizeof(struct atom_bracket_layout_record)
3152 <= record_header->record_size) {
3153 record = (struct atom_bracket_layout_record *)
3155 result = BP_RESULT_OK;
3159 record_offset += record_header->record_size;
3162 /* return if the record not found */
3163 if (result != BP_RESULT_OK)
3166 /* get slot sizes */
3167 slot_layout_info->length = record->bracketlen;
3168 slot_layout_info->width = record->bracketwidth;
3170 /* get info for each connector in the slot */
3171 slot_layout_info->num_of_connectors = record->conn_num;
3172 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
3173 slot_layout_info->connectors[j].connector_type =
3174 (enum connector_layout_type)
3175 (record->conn_info[j].connector_type);
3176 switch (record->conn_info[j].connector_type) {
3177 case CONNECTOR_TYPE_DVI_D:
3178 slot_layout_info->connectors[j].connector_type =
3179 CONNECTOR_LAYOUT_TYPE_DVI_D;
3180 slot_layout_info->connectors[j].length =
3184 case CONNECTOR_TYPE_HDMI:
3185 slot_layout_info->connectors[j].connector_type =
3186 CONNECTOR_LAYOUT_TYPE_HDMI;
3187 slot_layout_info->connectors[j].length =
3188 CONNECTOR_SIZE_HDMI;
3191 case CONNECTOR_TYPE_DISPLAY_PORT:
3192 slot_layout_info->connectors[j].connector_type =
3193 CONNECTOR_LAYOUT_TYPE_DP;
3194 slot_layout_info->connectors[j].length =
3198 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
3199 slot_layout_info->connectors[j].connector_type =
3200 CONNECTOR_LAYOUT_TYPE_MINI_DP;
3201 slot_layout_info->connectors[j].length =
3202 CONNECTOR_SIZE_MINI_DP;
3206 slot_layout_info->connectors[j].connector_type =
3207 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3208 slot_layout_info->connectors[j].length =
3209 CONNECTOR_SIZE_UNKNOWN;
3212 slot_layout_info->connectors[j].position =
3213 record->conn_info[j].position;
3214 slot_layout_info->connectors[j].connector_id =
3215 object_id_from_bios_object_id(
3216 record->conn_info[j].connectorobjid);
3221 static enum bp_result update_slot_layout_info_v2(
3222 struct dc_bios *dcb,
3224 struct slot_layout_info *slot_layout_info)
3226 unsigned int record_offset;
3227 struct atom_display_object_path_v3 *object;
3228 struct atom_bracket_layout_record_v2 *record;
3229 struct atom_common_record_header *record_header;
3230 static enum bp_result result;
3231 struct bios_parser *bp;
3232 struct object_info_table *tbl;
3233 struct display_object_info_table_v1_5 *v1_5;
3234 struct graphics_object_id connector_id;
3237 record_header = NULL;
3238 result = BP_RESULT_NORECORD;
3240 bp = BP_FROM_DCB(dcb);
3241 tbl = &bp->object_info_tbl;
3244 object = &v1_5->display_path[i];
3245 record_offset = (unsigned int)
3246 (object->disp_recordoffset) +
3247 (unsigned int)(bp->object_info_tbl_offset);
3251 record_header = (struct atom_common_record_header *)
3252 GET_IMAGE(struct atom_common_record_header,
3254 if (record_header == NULL) {
3255 result = BP_RESULT_BADBIOSTABLE;
3259 /* the end of the list */
3260 if (record_header->record_type == ATOM_RECORD_END_TYPE ||
3261 record_header->record_size == 0) {
3265 if (record_header->record_type ==
3266 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE &&
3267 sizeof(struct atom_bracket_layout_record_v2)
3268 <= record_header->record_size) {
3269 record = (struct atom_bracket_layout_record_v2 *)
3271 result = BP_RESULT_OK;
3275 record_offset += record_header->record_size;
3278 /* return if the record not found */
3279 if (result != BP_RESULT_OK)
3282 /* get slot sizes */
3283 connector_id = object_id_from_bios_object_id(object->display_objid);
3285 slot_layout_info->length = record->bracketlen;
3286 slot_layout_info->width = record->bracketwidth;
3287 slot_layout_info->num_of_connectors = v1_5->number_of_path;
3288 slot_layout_info->connectors[i].position = record->conn_num;
3289 slot_layout_info->connectors[i].connector_id = connector_id;
3291 switch (connector_id.id) {
3292 case CONNECTOR_ID_SINGLE_LINK_DVID:
3293 case CONNECTOR_ID_DUAL_LINK_DVID:
3294 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D;
3295 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI;
3298 case CONNECTOR_ID_HDMI_TYPE_A:
3299 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI;
3300 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI;
3303 case CONNECTOR_ID_DISPLAY_PORT:
3304 case CONNECTOR_ID_USBC:
3305 if (record->mini_type == MINI_TYPE_NORMAL) {
3306 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
3307 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
3309 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP;
3310 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP;
3315 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3316 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN;
3321 static enum bp_result get_bracket_layout_record(
3322 struct dc_bios *dcb,
3323 unsigned int bracket_layout_id,
3324 struct slot_layout_info *slot_layout_info)
3327 struct bios_parser *bp = BP_FROM_DCB(dcb);
3328 static enum bp_result result;
3329 struct object_info_table *tbl;
3330 struct display_object_info_table_v1_4 *v1_4;
3331 struct display_object_info_table_v1_5 *v1_5;
3333 if (slot_layout_info == NULL) {
3334 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
3335 return BP_RESULT_BADINPUT;
3338 tbl = &bp->object_info_tbl;
3342 result = BP_RESULT_NORECORD;
3343 switch (bp->object_info_tbl.revision.minor) {
3346 for (i = 0; i < v1_4->number_of_path; ++i) {
3347 if (bracket_layout_id == v1_4->display_path[i].display_objid) {
3348 result = update_slot_layout_info(dcb, i, slot_layout_info);
3354 for (i = 0; i < v1_5->number_of_path; ++i)
3355 result = update_slot_layout_info_v2(dcb, i, slot_layout_info);
3362 static enum bp_result bios_get_board_layout_info(
3363 struct dc_bios *dcb,
3364 struct board_layout_info *board_layout_info)
3367 struct bios_parser *bp;
3368 static enum bp_result record_result;
3369 unsigned int max_slots;
3371 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
3372 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
3373 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
3377 bp = BP_FROM_DCB(dcb);
3379 if (board_layout_info == NULL) {
3380 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
3381 return BP_RESULT_BADINPUT;
3384 board_layout_info->num_of_slots = 0;
3385 max_slots = MAX_BOARD_SLOTS;
3387 // Assume single slot on v1_5
3388 if (bp->object_info_tbl.revision.minor == 5) {
3392 for (i = 0; i < max_slots; ++i) {
3393 record_result = get_bracket_layout_record(dcb,
3394 slot_index_to_vbios_id[i],
3395 &board_layout_info->slots[i]);
3397 if (record_result == BP_RESULT_NORECORD && i > 0)
3398 break; /* no more slots present in bios */
3399 else if (record_result != BP_RESULT_OK)
3400 return record_result; /* fail */
3402 ++board_layout_info->num_of_slots;
3405 /* all data is valid */
3406 board_layout_info->is_number_of_slots_valid = 1;
3407 board_layout_info->is_slots_size_valid = 1;
3408 board_layout_info->is_connector_offsets_valid = 1;
3409 board_layout_info->is_connector_lengths_valid = 1;
3411 return BP_RESULT_OK;
3415 static uint16_t bios_parser_pack_data_tables(
3416 struct dc_bios *dcb,
3419 // TODO: There is data bytes alignment issue, disable it for now.
3423 static struct atom_dc_golden_table_v1 *bios_get_golden_table(
3424 struct bios_parser *bp,
3427 uint16_t *dc_golden_table_ver)
3429 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;
3430 uint32_t dc_golden_offset = 0;
3431 *dc_golden_table_ver = 0;
3433 if (!DATA_TABLES(dce_info))
3436 /* ver.4.4 or higher */
3437 switch (rev_major) {
3439 switch (rev_minor) {
3441 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
3442 DATA_TABLES(dce_info));
3443 if (!disp_cntl_tbl_4_4)
3445 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
3446 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
3450 /* For atom_display_controller_info_v4_5 there is no need to get golden table from
3451 * dc_golden_table_offset as all these fields previously in golden table used for AUX
3452 * pre-charge settings are now available directly in atom_display_controller_info_v4_5.
3459 if (!dc_golden_offset)
3462 if (*dc_golden_table_ver != 1)
3465 return GET_IMAGE(struct atom_dc_golden_table_v1,
3469 static enum bp_result bios_get_atom_dc_golden_table(
3470 struct dc_bios *dcb)
3472 struct bios_parser *bp = BP_FROM_DCB(dcb);
3473 enum bp_result result = BP_RESULT_OK;
3474 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;
3475 struct atom_common_table_header *header;
3476 struct atom_data_revision tbl_revision;
3477 uint16_t dc_golden_table_ver = 0;
3479 header = GET_IMAGE(struct atom_common_table_header,
3480 DATA_TABLES(dce_info));
3482 return BP_RESULT_UNSUPPORTED;
3484 get_atom_data_table_revision(header, &tbl_revision);
3486 atom_dc_golden_table = bios_get_golden_table(bp,
3489 &dc_golden_table_ver);
3491 if (!atom_dc_golden_table)
3492 return BP_RESULT_UNSUPPORTED;
3494 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;
3495 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;
3496 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;
3497 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;
3498 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;
3499 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;
3500 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;
3501 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;
3502 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;
3503 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;
3509 static const struct dc_vbios_funcs vbios_funcs = {
3510 .get_connectors_number = bios_parser_get_connectors_number,
3512 .get_connector_id = bios_parser_get_connector_id,
3514 .get_src_obj = bios_parser_get_src_obj,
3516 .get_i2c_info = bios_parser_get_i2c_info,
3518 .get_hpd_info = bios_parser_get_hpd_info,
3520 .get_device_tag = bios_parser_get_device_tag,
3522 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
3524 .get_ss_entry_number = bios_parser_get_ss_entry_number,
3526 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
3528 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
3530 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
3532 .is_device_id_supported = bios_parser_is_device_id_supported,
3534 .is_accelerated_mode = bios_parser_is_accelerated_mode,
3536 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
3540 .encoder_control = bios_parser_encoder_control,
3542 .transmitter_control = bios_parser_transmitter_control,
3544 .enable_crtc = bios_parser_enable_crtc,
3546 .set_pixel_clock = bios_parser_set_pixel_clock,
3548 .set_dce_clock = bios_parser_set_dce_clock,
3550 .program_crtc_timing = bios_parser_program_crtc_timing,
3552 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
3554 .bios_parser_destroy = firmware_parser_destroy,
3556 .get_board_layout_info = bios_get_board_layout_info,
3557 .pack_data_tables = bios_parser_pack_data_tables,
3559 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
3561 .enable_lvtma_control = bios_parser_enable_lvtma_control,
3563 .get_soc_bb_info = bios_parser_get_soc_bb_info,
3565 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
3567 .get_lttpr_caps = bios_parser_get_lttpr_caps,
3569 .get_lttpr_interop = bios_parser_get_lttpr_interop,
3571 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info,
3574 static bool bios_parser2_construct(
3575 struct bios_parser *bp,
3576 struct bp_init_data *init,
3577 enum dce_version dce_version)
3579 uint16_t *rom_header_offset = NULL;
3580 struct atom_rom_header_v2_2 *rom_header = NULL;
3581 struct display_object_info_table_v1_4 *object_info_tbl;
3582 struct atom_data_revision tbl_rev = {0};
3590 bp->base.funcs = &vbios_funcs;
3591 bp->base.bios = init->bios;
3592 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
3594 bp->base.ctx = init->ctx;
3596 bp->base.bios_local_image = NULL;
3599 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
3601 if (!rom_header_offset)
3604 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
3609 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
3610 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
3613 bp->master_data_tbl =
3614 GET_IMAGE(struct atom_master_data_table_v2_1,
3615 rom_header->masterdatatable_offset);
3617 if (!bp->master_data_tbl)
3620 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
3622 if (!bp->object_info_tbl_offset)
3626 GET_IMAGE(struct display_object_info_table_v1_4,
3627 bp->object_info_tbl_offset);
3629 if (!object_info_tbl)
3632 get_atom_data_table_revision(&object_info_tbl->table_header,
3633 &bp->object_info_tbl.revision);
3635 if (bp->object_info_tbl.revision.major == 1
3636 && bp->object_info_tbl.revision.minor == 4) {
3637 struct display_object_info_table_v1_4 *tbl_v1_4;
3639 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
3640 bp->object_info_tbl_offset);
3644 bp->object_info_tbl.v1_4 = tbl_v1_4;
3645 } else if (bp->object_info_tbl.revision.major == 1
3646 && bp->object_info_tbl.revision.minor == 5) {
3647 struct display_object_info_table_v1_5 *tbl_v1_5;
3649 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5,
3650 bp->object_info_tbl_offset);
3654 bp->object_info_tbl.v1_5 = tbl_v1_5;
3660 dal_firmware_parser_init_cmd_tbl(bp);
3661 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
3663 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
3664 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
3665 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
3670 struct dc_bios *firmware_parser_create(
3671 struct bp_init_data *init,
3672 enum dce_version dce_version)
3674 struct bios_parser *bp;
3676 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
3680 if (bios_parser2_construct(bp, init, dce_version))