2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "dc/dc_state.h"
41 #include "amdgpu_dm_trace.h"
42 #include "dpcd_defs.h"
43 #include "link/protocols/link_dpcd.h"
44 #include "link_service_types.h"
45 #include "link/protocols/link_dp_capability.h"
46 #include "link/protocols/link_ddc.h"
50 #include "amdgpu_display.h"
51 #include "amdgpu_ucode.h"
53 #include "amdgpu_dm.h"
54 #include "amdgpu_dm_plane.h"
55 #include "amdgpu_dm_crtc.h"
56 #include "amdgpu_dm_hdcp.h"
57 #include <drm/display/drm_hdcp_helper.h>
58 #include "amdgpu_dm_wb.h"
59 #include "amdgpu_pm.h"
60 #include "amdgpu_atombios.h"
62 #include "amd_shared.h"
63 #include "amdgpu_dm_irq.h"
64 #include "dm_helpers.h"
65 #include "amdgpu_dm_mst_types.h"
66 #if defined(CONFIG_DEBUG_FS)
67 #include "amdgpu_dm_debugfs.h"
69 #include "amdgpu_dm_psr.h"
71 #include "ivsrcid/ivsrcid_vislands30.h"
73 #include <linux/backlight.h>
74 #include <linux/module.h>
75 #include <linux/moduleparam.h>
76 #include <linux/types.h>
77 #include <linux/pm_runtime.h>
78 #include <linux/pci.h>
79 #include <linux/firmware.h>
80 #include <linux/component.h>
81 #include <linux/dmi.h>
83 #include <drm/display/drm_dp_mst_helper.h>
84 #include <drm/display/drm_hdmi_helper.h>
85 #include <drm/drm_atomic.h>
86 #include <drm/drm_atomic_uapi.h>
87 #include <drm/drm_atomic_helper.h>
88 #include <drm/drm_blend.h>
89 #include <drm/drm_fixed.h>
90 #include <drm/drm_fourcc.h>
91 #include <drm/drm_edid.h>
92 #include <drm/drm_eld.h>
93 #include <drm/drm_vblank.h>
94 #include <drm/drm_audio_component.h>
95 #include <drm/drm_gem_atomic_helper.h>
97 #include <acpi/video.h>
99 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
101 #include "dcn/dcn_1_0_offset.h"
102 #include "dcn/dcn_1_0_sh_mask.h"
103 #include "soc15_hw_ip.h"
104 #include "soc15_common.h"
105 #include "vega10_ip_offset.h"
107 #include "gc/gc_11_0_0_offset.h"
108 #include "gc/gc_11_0_0_sh_mask.h"
110 #include "modules/inc/mod_freesync.h"
111 #include "modules/power/power_helpers.h"
113 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
114 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
115 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
116 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
117 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
118 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
119 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
120 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
121 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
122 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
123 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
124 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
125 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
126 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
127 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
128 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
129 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
130 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
131 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
132 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
133 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
134 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
136 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
138 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
139 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
141 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
142 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
144 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
145 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
147 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
148 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
150 /* Number of bytes in PSP header for firmware. */
151 #define PSP_HEADER_BYTES 0x100
153 /* Number of bytes in PSP footer for firmware. */
154 #define PSP_FOOTER_BYTES 0x100
159 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
160 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
161 * requests into DC requests, and DC responses into DRM responses.
163 * The root control structure is &struct amdgpu_display_manager.
166 /* basic init/fini API */
167 static int amdgpu_dm_init(struct amdgpu_device *adev);
168 static void amdgpu_dm_fini(struct amdgpu_device *adev);
169 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
171 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
173 switch (link->dpcd_caps.dongle_type) {
174 case DISPLAY_DONGLE_NONE:
175 return DRM_MODE_SUBCONNECTOR_Native;
176 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
177 return DRM_MODE_SUBCONNECTOR_VGA;
178 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
179 case DISPLAY_DONGLE_DP_DVI_DONGLE:
180 return DRM_MODE_SUBCONNECTOR_DVID;
181 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
182 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
183 return DRM_MODE_SUBCONNECTOR_HDMIA;
184 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
186 return DRM_MODE_SUBCONNECTOR_Unknown;
190 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
192 struct dc_link *link = aconnector->dc_link;
193 struct drm_connector *connector = &aconnector->base;
194 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
196 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
199 if (aconnector->dc_sink)
200 subconnector = get_subconnector_type(link);
202 drm_object_property_set_value(&connector->base,
203 connector->dev->mode_config.dp_subconnector_property,
208 * initializes drm_device display related structures, based on the information
209 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
210 * drm_encoder, drm_mode_config
212 * Returns 0 on success
214 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
215 /* removes and deallocates the drm structures, created by the above function */
216 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
218 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
219 struct amdgpu_dm_connector *amdgpu_dm_connector,
221 struct amdgpu_encoder *amdgpu_encoder);
222 static int amdgpu_dm_encoder_init(struct drm_device *dev,
223 struct amdgpu_encoder *aencoder,
224 uint32_t link_index);
226 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
228 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
230 static int amdgpu_dm_atomic_check(struct drm_device *dev,
231 struct drm_atomic_state *state);
233 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
234 static void handle_hpd_rx_irq(void *param);
237 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
238 struct drm_crtc_state *new_crtc_state);
240 * dm_vblank_get_counter
243 * Get counter for number of vertical blanks
246 * struct amdgpu_device *adev - [in] desired amdgpu device
247 * int disp_idx - [in] which CRTC to get the counter from
250 * Counter for vertical blanks
252 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
254 struct amdgpu_crtc *acrtc = NULL;
256 if (crtc >= adev->mode_info.num_crtc)
259 acrtc = adev->mode_info.crtcs[crtc];
261 if (!acrtc->dm_irq_params.stream) {
262 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
267 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
270 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
271 u32 *vbl, u32 *position)
273 u32 v_blank_start, v_blank_end, h_position, v_position;
274 struct amdgpu_crtc *acrtc = NULL;
276 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
279 acrtc = adev->mode_info.crtcs[crtc];
281 if (!acrtc->dm_irq_params.stream) {
282 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
288 * TODO rework base driver to use values directly.
289 * for now parse it back into reg-format
291 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
297 *position = v_position | (h_position << 16);
298 *vbl = v_blank_start | (v_blank_end << 16);
303 static bool dm_is_idle(void *handle)
309 static int dm_wait_for_idle(void *handle)
315 static bool dm_check_soft_reset(void *handle)
320 static int dm_soft_reset(void *handle)
326 static struct amdgpu_crtc *
327 get_crtc_by_otg_inst(struct amdgpu_device *adev,
330 struct drm_device *dev = adev_to_drm(adev);
331 struct drm_crtc *crtc;
332 struct amdgpu_crtc *amdgpu_crtc;
334 if (WARN_ON(otg_inst == -1))
335 return adev->mode_info.crtcs[0];
337 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
338 amdgpu_crtc = to_amdgpu_crtc(crtc);
340 if (amdgpu_crtc->otg_inst == otg_inst)
347 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
348 struct dm_crtc_state *new_state)
350 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
352 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
358 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
363 for (i = 0, j = planes_count - 1; i < j; i++, j--)
364 swap(array_of_surface_update[i], array_of_surface_update[j]);
368 * update_planes_and_stream_adapter() - Send planes to be updated in DC
370 * DC has a generic way to update planes and stream via
371 * dc_update_planes_and_stream function; however, DM might need some
372 * adjustments and preparation before calling it. This function is a wrapper
373 * for the dc_update_planes_and_stream that does any required configuration
374 * before passing control to DC.
376 * @dc: Display Core control structure
377 * @update_type: specify whether it is FULL/MEDIUM/FAST update
378 * @planes_count: planes count to update
379 * @stream: stream state
380 * @stream_update: stream update
381 * @array_of_surface_update: dc surface update pointer
384 static inline bool update_planes_and_stream_adapter(struct dc *dc,
387 struct dc_stream_state *stream,
388 struct dc_stream_update *stream_update,
389 struct dc_surface_update *array_of_surface_update)
391 reverse_planes_order(array_of_surface_update, planes_count);
394 * Previous frame finished and HW is ready for optimization.
396 if (update_type == UPDATE_TYPE_FAST)
397 dc_post_update_surfaces_to_stream(dc);
399 return dc_update_planes_and_stream(dc,
400 array_of_surface_update,
407 * dm_pflip_high_irq() - Handle pageflip interrupt
408 * @interrupt_params: ignored
410 * Handles the pageflip interrupt by notifying all interested parties
411 * that the pageflip has been completed.
413 static void dm_pflip_high_irq(void *interrupt_params)
415 struct amdgpu_crtc *amdgpu_crtc;
416 struct common_irq_params *irq_params = interrupt_params;
417 struct amdgpu_device *adev = irq_params->adev;
418 struct drm_device *dev = adev_to_drm(adev);
420 struct drm_pending_vblank_event *e;
421 u32 vpos, hpos, v_blank_start, v_blank_end;
424 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
426 /* IRQ could occur when in initial stage */
427 /* TODO work and BO cleanup */
428 if (amdgpu_crtc == NULL) {
429 drm_dbg_state(dev, "CRTC is null, returning.\n");
433 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
435 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
437 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
438 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
439 amdgpu_crtc->crtc_id, amdgpu_crtc);
440 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
444 /* page flip completed. */
445 e = amdgpu_crtc->event;
446 amdgpu_crtc->event = NULL;
450 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
452 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
454 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
455 &v_blank_end, &hpos, &vpos) ||
456 (vpos < v_blank_start)) {
457 /* Update to correct count and vblank timestamp if racing with
458 * vblank irq. This also updates to the correct vblank timestamp
459 * even in VRR mode, as scanout is past the front-porch atm.
461 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
463 /* Wake up userspace by sending the pageflip event with proper
464 * count and timestamp of vblank of flip completion.
467 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
469 /* Event sent, so done with vblank for this flip */
470 drm_crtc_vblank_put(&amdgpu_crtc->base);
473 /* VRR active and inside front-porch: vblank count and
474 * timestamp for pageflip event will only be up to date after
475 * drm_crtc_handle_vblank() has been executed from late vblank
476 * irq handler after start of back-porch (vline 0). We queue the
477 * pageflip event for send-out by drm_crtc_handle_vblank() with
478 * updated timestamp and count, once it runs after us.
480 * We need to open-code this instead of using the helper
481 * drm_crtc_arm_vblank_event(), as that helper would
482 * call drm_crtc_accurate_vblank_count(), which we must
483 * not call in VRR mode while we are in front-porch!
486 /* sequence will be replaced by real count during send-out. */
487 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
488 e->pipe = amdgpu_crtc->crtc_id;
490 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
494 /* Keep track of vblank of this flip for flip throttling. We use the
495 * cooked hw counter, as that one incremented at start of this vblank
496 * of pageflip completion, so last_flip_vblank is the forbidden count
497 * for queueing new pageflips if vsync + VRR is enabled.
499 amdgpu_crtc->dm_irq_params.last_flip_vblank =
500 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
502 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
503 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
506 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
507 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
510 static void dm_vupdate_high_irq(void *interrupt_params)
512 struct common_irq_params *irq_params = interrupt_params;
513 struct amdgpu_device *adev = irq_params->adev;
514 struct amdgpu_crtc *acrtc;
515 struct drm_device *drm_dev;
516 struct drm_vblank_crtc *vblank;
517 ktime_t frame_duration_ns, previous_timestamp;
521 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
524 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
525 drm_dev = acrtc->base.dev;
526 vblank = &drm_dev->vblank[acrtc->base.index];
527 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
528 frame_duration_ns = vblank->time - previous_timestamp;
530 if (frame_duration_ns > 0) {
531 trace_amdgpu_refresh_rate_track(acrtc->base.index,
533 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
534 atomic64_set(&irq_params->previous_timestamp, vblank->time);
538 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
541 /* Core vblank handling is done here after end of front-porch in
542 * vrr mode, as vblank timestamping will give valid results
543 * while now done after front-porch. This will also deliver
544 * page-flip completion events that have been queued to us
545 * if a pageflip happened inside front-porch.
548 amdgpu_dm_crtc_handle_vblank(acrtc);
550 /* BTR processing for pre-DCE12 ASICs */
551 if (acrtc->dm_irq_params.stream &&
552 adev->family < AMDGPU_FAMILY_AI) {
553 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
554 mod_freesync_handle_v_update(
555 adev->dm.freesync_module,
556 acrtc->dm_irq_params.stream,
557 &acrtc->dm_irq_params.vrr_params);
559 dc_stream_adjust_vmin_vmax(
561 acrtc->dm_irq_params.stream,
562 &acrtc->dm_irq_params.vrr_params.adjust);
563 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
570 * dm_crtc_high_irq() - Handles CRTC interrupt
571 * @interrupt_params: used for determining the CRTC instance
573 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
576 static void dm_crtc_high_irq(void *interrupt_params)
578 struct common_irq_params *irq_params = interrupt_params;
579 struct amdgpu_device *adev = irq_params->adev;
580 struct drm_writeback_job *job;
581 struct amdgpu_crtc *acrtc;
585 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
589 if (acrtc->wb_pending) {
590 if (acrtc->wb_conn) {
591 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags);
592 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue,
593 struct drm_writeback_job,
595 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
598 unsigned int v_total, refresh_hz;
599 struct dc_stream_state *stream = acrtc->dm_irq_params.stream;
601 v_total = stream->adjust.v_total_max ?
602 stream->adjust.v_total_max : stream->timing.v_total;
603 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
604 100LL, (v_total * stream->timing.h_total));
605 mdelay(1000 / refresh_hz);
607 drm_writeback_signal_completion(acrtc->wb_conn, 0);
608 dc_stream_fc_disable_writeback(adev->dm.dc,
609 acrtc->dm_irq_params.stream, 0);
612 DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__);
613 acrtc->wb_pending = false;
616 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
618 drm_dbg_vbl(adev_to_drm(adev),
619 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
620 vrr_active, acrtc->dm_irq_params.active_planes);
623 * Core vblank handling at start of front-porch is only possible
624 * in non-vrr mode, as only there vblank timestamping will give
625 * valid results while done in front-porch. Otherwise defer it
626 * to dm_vupdate_high_irq after end of front-porch.
629 amdgpu_dm_crtc_handle_vblank(acrtc);
632 * Following stuff must happen at start of vblank, for crc
633 * computation and below-the-range btr support in vrr mode.
635 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
637 /* BTR updates need to happen before VUPDATE on Vega and above. */
638 if (adev->family < AMDGPU_FAMILY_AI)
641 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
643 if (acrtc->dm_irq_params.stream &&
644 acrtc->dm_irq_params.vrr_params.supported &&
645 acrtc->dm_irq_params.freesync_config.state ==
646 VRR_STATE_ACTIVE_VARIABLE) {
647 mod_freesync_handle_v_update(adev->dm.freesync_module,
648 acrtc->dm_irq_params.stream,
649 &acrtc->dm_irq_params.vrr_params);
651 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
652 &acrtc->dm_irq_params.vrr_params.adjust);
656 * If there aren't any active_planes then DCH HUBP may be clock-gated.
657 * In that case, pageflip completion interrupts won't fire and pageflip
658 * completion events won't get delivered. Prevent this by sending
659 * pending pageflip events from here if a flip is still pending.
661 * If any planes are enabled, use dm_pflip_high_irq() instead, to
662 * avoid race conditions between flip programming and completion,
663 * which could cause too early flip completion events.
665 if (adev->family >= AMDGPU_FAMILY_RV &&
666 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
667 acrtc->dm_irq_params.active_planes == 0) {
669 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
671 drm_crtc_vblank_put(&acrtc->base);
673 acrtc->pflip_status = AMDGPU_FLIP_NONE;
676 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
679 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
681 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
682 * DCN generation ASICs
683 * @interrupt_params: interrupt parameters
685 * Used to set crc window/read out crc value at vertical line 0 position
687 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
689 struct common_irq_params *irq_params = interrupt_params;
690 struct amdgpu_device *adev = irq_params->adev;
691 struct amdgpu_crtc *acrtc;
693 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
698 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
700 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
703 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
704 * @adev: amdgpu_device pointer
705 * @notify: dmub notification structure
707 * Dmub AUX or SET_CONFIG command completion processing callback
708 * Copies dmub notification to DM which is to be read by AUX command.
709 * issuing thread and also signals the event to wake up the thread.
711 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
712 struct dmub_notification *notify)
714 if (adev->dm.dmub_notify)
715 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
716 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
717 complete(&adev->dm.dmub_aux_transfer_done);
721 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
722 * @adev: amdgpu_device pointer
723 * @notify: dmub notification structure
725 * Dmub Hpd interrupt processing callback. Gets displayindex through the
726 * ink index and calls helper to do the processing.
728 static void dmub_hpd_callback(struct amdgpu_device *adev,
729 struct dmub_notification *notify)
731 struct amdgpu_dm_connector *aconnector;
732 struct amdgpu_dm_connector *hpd_aconnector = NULL;
733 struct drm_connector *connector;
734 struct drm_connector_list_iter iter;
735 struct dc_link *link;
737 struct drm_device *dev;
742 if (notify == NULL) {
743 DRM_ERROR("DMUB HPD callback notification was NULL");
747 if (notify->link_index > adev->dm.dc->link_count) {
748 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
752 link_index = notify->link_index;
753 link = adev->dm.dc->links[link_index];
756 drm_connector_list_iter_begin(dev, &iter);
757 drm_for_each_connector_iter(connector, &iter) {
759 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
762 aconnector = to_amdgpu_dm_connector(connector);
763 if (link && aconnector->dc_link == link) {
764 if (notify->type == DMUB_NOTIFICATION_HPD)
765 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
766 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
767 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
769 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
770 notify->type, link_index);
772 hpd_aconnector = aconnector;
776 drm_connector_list_iter_end(&iter);
778 if (hpd_aconnector) {
779 if (notify->type == DMUB_NOTIFICATION_HPD)
780 handle_hpd_irq_helper(hpd_aconnector);
781 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
782 handle_hpd_rx_irq(hpd_aconnector);
787 * register_dmub_notify_callback - Sets callback for DMUB notify
788 * @adev: amdgpu_device pointer
789 * @type: Type of dmub notification
790 * @callback: Dmub interrupt callback function
791 * @dmub_int_thread_offload: offload indicator
793 * API to register a dmub callback handler for a dmub notification
794 * Also sets indicator whether callback processing to be offloaded.
795 * to dmub interrupt handling thread
796 * Return: true if successfully registered, false if there is existing registration
798 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
799 enum dmub_notification_type type,
800 dmub_notify_interrupt_callback_t callback,
801 bool dmub_int_thread_offload)
803 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
804 adev->dm.dmub_callback[type] = callback;
805 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
812 static void dm_handle_hpd_work(struct work_struct *work)
814 struct dmub_hpd_work *dmub_hpd_wrk;
816 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
818 if (!dmub_hpd_wrk->dmub_notify) {
819 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
823 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
824 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
825 dmub_hpd_wrk->dmub_notify);
828 kfree(dmub_hpd_wrk->dmub_notify);
833 #define DMUB_TRACE_MAX_READ 64
835 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
836 * @interrupt_params: used for determining the Outbox instance
838 * Handles the Outbox Interrupt
841 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
843 struct dmub_notification notify;
844 struct common_irq_params *irq_params = interrupt_params;
845 struct amdgpu_device *adev = irq_params->adev;
846 struct amdgpu_display_manager *dm = &adev->dm;
847 struct dmcub_trace_buf_entry entry = { 0 };
849 struct dmub_hpd_work *dmub_hpd_wrk;
850 struct dc_link *plink = NULL;
852 if (dc_enable_dmub_notifications(adev->dm.dc) &&
853 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
856 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);
857 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
858 DRM_ERROR("DM: notify type %d invalid!", notify.type);
861 if (!dm->dmub_callback[notify.type]) {
862 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
865 if (dm->dmub_thread_offload[notify.type] == true) {
866 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
868 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
871 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification),
873 if (!dmub_hpd_wrk->dmub_notify) {
875 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
878 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
879 dmub_hpd_wrk->adev = adev;
880 if (notify.type == DMUB_NOTIFICATION_HPD) {
881 plink = adev->dm.dc->links[notify.link_index];
884 notify.hpd_status == DP_HPD_PLUG;
887 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
889 dm->dmub_callback[notify.type](adev, ¬ify);
891 } while (notify.pending_notification);
896 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
897 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
898 entry.param0, entry.param1);
900 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
901 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
907 } while (count <= DMUB_TRACE_MAX_READ);
909 if (count > DMUB_TRACE_MAX_READ)
910 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
913 static int dm_set_clockgating_state(void *handle,
914 enum amd_clockgating_state state)
919 static int dm_set_powergating_state(void *handle,
920 enum amd_powergating_state state)
925 /* Prototypes of private functions */
926 static int dm_early_init(void *handle);
928 /* Allocate memory for FBC compressed data */
929 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
931 struct amdgpu_device *adev = drm_to_adev(connector->dev);
932 struct dm_compressor_info *compressor = &adev->dm.compressor;
933 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
934 struct drm_display_mode *mode;
935 unsigned long max_size = 0;
937 if (adev->dm.dc->fbc_compressor == NULL)
940 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
943 if (compressor->bo_ptr)
947 list_for_each_entry(mode, &connector->modes, head) {
948 if (max_size < mode->htotal * mode->vtotal)
949 max_size = mode->htotal * mode->vtotal;
953 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
954 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
955 &compressor->gpu_addr, &compressor->cpu_addr);
958 DRM_ERROR("DM: Failed to initialize FBC\n");
960 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
961 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
968 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
969 int pipe, bool *enabled,
970 unsigned char *buf, int max_bytes)
972 struct drm_device *dev = dev_get_drvdata(kdev);
973 struct amdgpu_device *adev = drm_to_adev(dev);
974 struct drm_connector *connector;
975 struct drm_connector_list_iter conn_iter;
976 struct amdgpu_dm_connector *aconnector;
981 mutex_lock(&adev->dm.audio_lock);
983 drm_connector_list_iter_begin(dev, &conn_iter);
984 drm_for_each_connector_iter(connector, &conn_iter) {
986 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
989 aconnector = to_amdgpu_dm_connector(connector);
990 if (aconnector->audio_inst != port)
994 ret = drm_eld_size(connector->eld);
995 memcpy(buf, connector->eld, min(max_bytes, ret));
999 drm_connector_list_iter_end(&conn_iter);
1001 mutex_unlock(&adev->dm.audio_lock);
1003 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
1008 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
1009 .get_eld = amdgpu_dm_audio_component_get_eld,
1012 static int amdgpu_dm_audio_component_bind(struct device *kdev,
1013 struct device *hda_kdev, void *data)
1015 struct drm_device *dev = dev_get_drvdata(kdev);
1016 struct amdgpu_device *adev = drm_to_adev(dev);
1017 struct drm_audio_component *acomp = data;
1019 acomp->ops = &amdgpu_dm_audio_component_ops;
1021 adev->dm.audio_component = acomp;
1026 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
1027 struct device *hda_kdev, void *data)
1029 struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));
1030 struct drm_audio_component *acomp = data;
1034 adev->dm.audio_component = NULL;
1037 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1038 .bind = amdgpu_dm_audio_component_bind,
1039 .unbind = amdgpu_dm_audio_component_unbind,
1042 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1049 adev->mode_info.audio.enabled = true;
1051 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1053 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1054 adev->mode_info.audio.pin[i].channels = -1;
1055 adev->mode_info.audio.pin[i].rate = -1;
1056 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1057 adev->mode_info.audio.pin[i].status_bits = 0;
1058 adev->mode_info.audio.pin[i].category_code = 0;
1059 adev->mode_info.audio.pin[i].connected = false;
1060 adev->mode_info.audio.pin[i].id =
1061 adev->dm.dc->res_pool->audios[i]->inst;
1062 adev->mode_info.audio.pin[i].offset = 0;
1065 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1069 adev->dm.audio_registered = true;
1074 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1079 if (!adev->mode_info.audio.enabled)
1082 if (adev->dm.audio_registered) {
1083 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1084 adev->dm.audio_registered = false;
1087 /* TODO: Disable audio? */
1089 adev->mode_info.audio.enabled = false;
1092 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1094 struct drm_audio_component *acomp = adev->dm.audio_component;
1096 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1097 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1099 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1104 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1106 const struct dmcub_firmware_header_v1_0 *hdr;
1107 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1108 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1109 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1110 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1111 struct abm *abm = adev->dm.dc->res_pool->abm;
1112 struct dc_context *ctx = adev->dm.dc->ctx;
1113 struct dmub_srv_hw_params hw_params;
1114 enum dmub_status status;
1115 const unsigned char *fw_inst_const, *fw_bss_data;
1116 u32 i, fw_inst_const_size, fw_bss_data_size;
1117 bool has_hw_support;
1120 /* DMUB isn't supported on the ASIC. */
1124 DRM_ERROR("No framebuffer info for DMUB service.\n");
1129 /* Firmware required for DMUB support. */
1130 DRM_ERROR("No firmware provided for DMUB.\n");
1134 /* initialize register offsets for ASICs with runtime initialization available */
1135 if (dmub_srv->hw_funcs.init_reg_offsets)
1136 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1138 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1139 if (status != DMUB_STATUS_OK) {
1140 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1144 if (!has_hw_support) {
1145 DRM_INFO("DMUB unsupported on ASIC\n");
1149 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1150 status = dmub_srv_hw_reset(dmub_srv);
1151 if (status != DMUB_STATUS_OK)
1152 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1154 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1156 fw_inst_const = dmub_fw->data +
1157 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1160 fw_bss_data = dmub_fw->data +
1161 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1162 le32_to_cpu(hdr->inst_const_bytes);
1164 /* Copy firmware and bios info into FB memory. */
1165 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1166 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1168 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1170 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1171 * amdgpu_ucode_init_single_fw will load dmub firmware
1172 * fw_inst_const part to cw0; otherwise, the firmware back door load
1173 * will be done by dm_dmub_hw_init
1175 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1176 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1177 fw_inst_const_size);
1180 if (fw_bss_data_size)
1181 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1182 fw_bss_data, fw_bss_data_size);
1184 /* Copy firmware bios info into FB memory. */
1185 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1188 /* Reset regions that need to be reset. */
1189 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1190 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1192 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1193 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1195 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1196 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1198 /* Initialize hardware. */
1199 memset(&hw_params, 0, sizeof(hw_params));
1200 hw_params.fb_base = adev->gmc.fb_start;
1201 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1203 /* backdoor load firmware and trigger dmub running */
1204 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1205 hw_params.load_inst_const = true;
1208 hw_params.psp_version = dmcu->psp_version;
1210 for (i = 0; i < fb_info->num_fb; ++i)
1211 hw_params.fb[i] = &fb_info->fb[i];
1213 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1214 case IP_VERSION(3, 1, 3):
1215 case IP_VERSION(3, 1, 4):
1216 case IP_VERSION(3, 5, 0):
1217 hw_params.dpia_supported = true;
1218 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1224 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1225 if (status != DMUB_STATUS_OK) {
1226 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1230 /* Wait for firmware load to finish. */
1231 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1232 if (status != DMUB_STATUS_OK)
1233 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1235 /* Init DMCU and ABM if available. */
1237 dmcu->funcs->dmcu_init(dmcu);
1238 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1241 if (!adev->dm.dc->ctx->dmub_srv)
1242 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1243 if (!adev->dm.dc->ctx->dmub_srv) {
1244 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1248 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1249 adev->dm.dmcub_fw_version);
1254 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1256 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1257 enum dmub_status status;
1261 /* DMUB isn't supported on the ASIC. */
1265 status = dmub_srv_is_hw_init(dmub_srv, &init);
1266 if (status != DMUB_STATUS_OK)
1267 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1269 if (status == DMUB_STATUS_OK && init) {
1270 /* Wait for firmware load to finish. */
1271 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1272 if (status != DMUB_STATUS_OK)
1273 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1275 /* Perform the full hardware initialization. */
1276 dm_dmub_hw_init(adev);
1280 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1283 u32 logical_addr_low;
1284 u32 logical_addr_high;
1285 u32 agp_base, agp_bot, agp_top;
1286 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1288 memset(pa_config, 0, sizeof(*pa_config));
1291 agp_bot = adev->gmc.agp_start >> 24;
1292 agp_top = adev->gmc.agp_end >> 24;
1294 /* AGP aperture is disabled */
1295 if (agp_bot > agp_top) {
1296 logical_addr_low = adev->gmc.fb_start >> 18;
1297 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1299 AMD_APU_IS_GREEN_SARDINE))
1301 * Raven2 has a HW issue that it is unable to use the vram which
1302 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1303 * workaround that increase system aperture high address (add 1)
1304 * to get rid of the VM fault and hardware hang.
1306 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1308 logical_addr_high = adev->gmc.fb_end >> 18;
1310 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1311 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1313 AMD_APU_IS_GREEN_SARDINE))
1315 * Raven2 has a HW issue that it is unable to use the vram which
1316 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1317 * workaround that increase system aperture high address (add 1)
1318 * to get rid of the VM fault and hardware hang.
1320 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1322 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1325 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1327 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1328 AMDGPU_GPU_PAGE_SHIFT);
1329 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1330 AMDGPU_GPU_PAGE_SHIFT);
1331 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1332 AMDGPU_GPU_PAGE_SHIFT);
1333 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1334 AMDGPU_GPU_PAGE_SHIFT);
1335 page_table_base.high_part = upper_32_bits(pt_base);
1336 page_table_base.low_part = lower_32_bits(pt_base);
1338 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1339 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1341 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1342 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1343 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1345 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1346 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1347 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1349 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1350 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1351 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1353 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1357 static void force_connector_state(
1358 struct amdgpu_dm_connector *aconnector,
1359 enum drm_connector_force force_state)
1361 struct drm_connector *connector = &aconnector->base;
1363 mutex_lock(&connector->dev->mode_config.mutex);
1364 aconnector->base.force = force_state;
1365 mutex_unlock(&connector->dev->mode_config.mutex);
1367 mutex_lock(&aconnector->hpd_lock);
1368 drm_kms_helper_connector_hotplug_event(connector);
1369 mutex_unlock(&aconnector->hpd_lock);
1372 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1374 struct hpd_rx_irq_offload_work *offload_work;
1375 struct amdgpu_dm_connector *aconnector;
1376 struct dc_link *dc_link;
1377 struct amdgpu_device *adev;
1378 enum dc_connection_type new_connection_type = dc_connection_none;
1379 unsigned long flags;
1380 union test_response test_response;
1382 memset(&test_response, 0, sizeof(test_response));
1384 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1385 aconnector = offload_work->offload_wq->aconnector;
1388 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1392 adev = drm_to_adev(aconnector->base.dev);
1393 dc_link = aconnector->dc_link;
1395 mutex_lock(&aconnector->hpd_lock);
1396 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1397 DRM_ERROR("KMS: Failed to detect connector\n");
1398 mutex_unlock(&aconnector->hpd_lock);
1400 if (new_connection_type == dc_connection_none)
1403 if (amdgpu_in_reset(adev))
1406 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1407 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1408 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1409 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1410 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1411 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1415 mutex_lock(&adev->dm.dc_lock);
1416 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1417 dc_link_dp_handle_automated_test(dc_link);
1419 if (aconnector->timing_changed) {
1420 /* force connector disconnect and reconnect */
1421 force_connector_state(aconnector, DRM_FORCE_OFF);
1423 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1426 test_response.bits.ACK = 1;
1428 core_link_write_dpcd(
1432 sizeof(test_response));
1433 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1434 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1435 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1436 /* offload_work->data is from handle_hpd_rx_irq->
1437 * schedule_hpd_rx_offload_work.this is defer handle
1438 * for hpd short pulse. upon here, link status may be
1439 * changed, need get latest link status from dpcd
1440 * registers. if link status is good, skip run link
1443 union hpd_irq_data irq_data;
1445 memset(&irq_data, 0, sizeof(irq_data));
1447 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1448 * request be added to work queue if link lost at end of dc_link_
1449 * dp_handle_link_loss
1451 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1452 offload_work->offload_wq->is_handling_link_loss = false;
1453 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1455 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1456 dc_link_check_link_loss_status(dc_link, &irq_data))
1457 dc_link_dp_handle_link_loss(dc_link);
1459 mutex_unlock(&adev->dm.dc_lock);
1462 kfree(offload_work);
1466 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1468 int max_caps = dc->caps.max_links;
1470 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1472 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1474 if (!hpd_rx_offload_wq)
1478 for (i = 0; i < max_caps; i++) {
1479 hpd_rx_offload_wq[i].wq =
1480 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1482 if (hpd_rx_offload_wq[i].wq == NULL) {
1483 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1487 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1490 return hpd_rx_offload_wq;
1493 for (i = 0; i < max_caps; i++) {
1494 if (hpd_rx_offload_wq[i].wq)
1495 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1497 kfree(hpd_rx_offload_wq);
1501 struct amdgpu_stutter_quirk {
1509 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1510 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1511 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1515 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1517 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1519 while (p && p->chip_device != 0) {
1520 if (pdev->vendor == p->chip_vendor &&
1521 pdev->device == p->chip_device &&
1522 pdev->subsystem_vendor == p->subsys_vendor &&
1523 pdev->subsystem_device == p->subsys_device &&
1524 pdev->revision == p->revision) {
1532 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1535 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1536 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1541 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1542 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1547 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1548 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1553 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1554 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1559 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1560 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1565 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1566 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1571 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1572 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1577 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1578 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1583 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1584 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1588 /* TODO: refactor this from a fixed table to a dynamic option */
1591 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1593 const struct dmi_system_id *dmi_id;
1595 dm->aux_hpd_discon_quirk = false;
1597 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1599 dm->aux_hpd_discon_quirk = true;
1600 DRM_INFO("aux_hpd_discon_quirk attached\n");
1604 static int amdgpu_dm_init(struct amdgpu_device *adev)
1606 struct dc_init_data init_data;
1607 struct dc_callback_init init_params;
1610 adev->dm.ddev = adev_to_drm(adev);
1611 adev->dm.adev = adev;
1613 /* Zero all the fields */
1614 memset(&init_data, 0, sizeof(init_data));
1615 memset(&init_params, 0, sizeof(init_params));
1617 mutex_init(&adev->dm.dpia_aux_lock);
1618 mutex_init(&adev->dm.dc_lock);
1619 mutex_init(&adev->dm.audio_lock);
1621 if (amdgpu_dm_irq_init(adev)) {
1622 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1626 init_data.asic_id.chip_family = adev->family;
1628 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1629 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1630 init_data.asic_id.chip_id = adev->pdev->device;
1632 init_data.asic_id.vram_width = adev->gmc.vram_width;
1633 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1634 init_data.asic_id.atombios_base_address =
1635 adev->mode_info.atom_context->bios;
1637 init_data.driver = adev;
1639 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1641 if (!adev->dm.cgs_device) {
1642 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1646 init_data.cgs_device = adev->dm.cgs_device;
1648 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1650 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1651 case IP_VERSION(2, 1, 0):
1652 switch (adev->dm.dmcub_fw_version) {
1653 case 0: /* development */
1654 case 0x1: /* linux-firmware.git hash 6d9f399 */
1655 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1656 init_data.flags.disable_dmcu = false;
1659 init_data.flags.disable_dmcu = true;
1662 case IP_VERSION(2, 0, 3):
1663 init_data.flags.disable_dmcu = true;
1669 /* APU support S/G display by default except:
1670 * ASICs before Carrizo,
1671 * RAVEN1 (Users reported stability issue)
1674 if (adev->asic_type < CHIP_CARRIZO) {
1675 init_data.flags.gpu_vm_support = false;
1676 } else if (adev->asic_type == CHIP_RAVEN) {
1677 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1678 init_data.flags.gpu_vm_support = false;
1680 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1682 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1685 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1687 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1688 init_data.flags.fbc_support = true;
1690 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1691 init_data.flags.multi_mon_pp_mclk_switch = true;
1693 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1694 init_data.flags.disable_fractional_pwm = true;
1696 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1697 init_data.flags.edp_no_power_sequencing = true;
1699 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1700 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1701 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1702 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1704 init_data.flags.seamless_boot_edp_requested = false;
1706 if (amdgpu_device_seamless_boot_supported(adev)) {
1707 init_data.flags.seamless_boot_edp_requested = true;
1708 init_data.flags.allow_seamless_boot_optimization = true;
1709 DRM_INFO("Seamless boot condition check passed\n");
1712 init_data.flags.enable_mipi_converter_optimization = true;
1714 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1715 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1716 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1718 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
1720 /* Enable DWB for tested platforms only */
1721 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
1722 init_data.num_virtual_links = 1;
1724 INIT_LIST_HEAD(&adev->dm.da_list);
1726 retrieve_dmi_info(&adev->dm);
1728 /* Display Core create. */
1729 adev->dm.dc = dc_create(&init_data);
1732 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1733 dce_version_to_string(adev->dm.dc->ctx->dce_version));
1735 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1739 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1740 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1741 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1744 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1745 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1746 if (dm_should_disable_stutter(adev->pdev))
1747 adev->dm.dc->debug.disable_stutter = true;
1749 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1750 adev->dm.dc->debug.disable_stutter = true;
1752 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1753 adev->dm.dc->debug.disable_dsc = true;
1755 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1756 adev->dm.dc->debug.disable_clock_gate = true;
1758 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1759 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1761 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1763 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1764 adev->dm.dc->debug.ignore_cable_id = true;
1766 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1767 DRM_INFO("DP-HDMI FRL PCON supported\n");
1769 r = dm_dmub_hw_init(adev);
1771 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1775 dc_hardware_init(adev->dm.dc);
1777 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1778 if (!adev->dm.hpd_rx_offload_wq) {
1779 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1783 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1784 struct dc_phy_addr_space_config pa_config;
1786 mmhub_read_system_context(adev, &pa_config);
1788 // Call the DC init_memory func
1789 dc_setup_system_context(adev->dm.dc, &pa_config);
1792 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1793 if (!adev->dm.freesync_module) {
1795 "amdgpu: failed to initialize freesync_module.\n");
1797 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1798 adev->dm.freesync_module);
1800 amdgpu_dm_init_color_mod();
1802 if (adev->dm.dc->caps.max_links > 0) {
1803 adev->dm.vblank_control_workqueue =
1804 create_singlethread_workqueue("dm_vblank_control_workqueue");
1805 if (!adev->dm.vblank_control_workqueue)
1806 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1809 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1810 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1812 if (!adev->dm.hdcp_workqueue)
1813 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1815 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1817 dc_init_callbacks(adev->dm.dc, &init_params);
1819 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1820 init_completion(&adev->dm.dmub_aux_transfer_done);
1821 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1822 if (!adev->dm.dmub_notify) {
1823 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1827 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1828 if (!adev->dm.delayed_hpd_wq) {
1829 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1833 amdgpu_dm_outbox_init(adev);
1834 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1835 dmub_aux_setconfig_callback, false)) {
1836 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1839 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1840 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1843 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1844 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1849 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1850 * It is expected that DMUB will resend any pending notifications at this point, for
1851 * example HPD from DPIA.
1853 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1854 dc_enable_dmub_outbox(adev->dm.dc);
1856 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1857 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1858 dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1861 if (amdgpu_dm_initialize_drm_device(adev)) {
1863 "amdgpu: failed to initialize sw for display support.\n");
1867 /* create fake encoders for MST */
1868 dm_dp_create_fake_mst_encoders(adev);
1870 /* TODO: Add_display_info? */
1872 /* TODO use dynamic cursor width */
1873 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1874 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1876 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1878 "amdgpu: failed to initialize sw for display support.\n");
1882 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1883 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1884 if (!adev->dm.secure_display_ctxs)
1885 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1888 DRM_DEBUG_DRIVER("KMS initialized.\n");
1892 amdgpu_dm_fini(adev);
1897 static int amdgpu_dm_early_fini(void *handle)
1899 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1901 amdgpu_dm_audio_fini(adev);
1906 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1910 if (adev->dm.vblank_control_workqueue) {
1911 destroy_workqueue(adev->dm.vblank_control_workqueue);
1912 adev->dm.vblank_control_workqueue = NULL;
1915 amdgpu_dm_destroy_drm_device(&adev->dm);
1917 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1918 if (adev->dm.secure_display_ctxs) {
1919 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1920 if (adev->dm.secure_display_ctxs[i].crtc) {
1921 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1922 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1925 kfree(adev->dm.secure_display_ctxs);
1926 adev->dm.secure_display_ctxs = NULL;
1929 if (adev->dm.hdcp_workqueue) {
1930 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1931 adev->dm.hdcp_workqueue = NULL;
1935 dc_deinit_callbacks(adev->dm.dc);
1938 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1940 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1941 kfree(adev->dm.dmub_notify);
1942 adev->dm.dmub_notify = NULL;
1943 destroy_workqueue(adev->dm.delayed_hpd_wq);
1944 adev->dm.delayed_hpd_wq = NULL;
1947 if (adev->dm.dmub_bo)
1948 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1949 &adev->dm.dmub_bo_gpu_addr,
1950 &adev->dm.dmub_bo_cpu_addr);
1952 if (adev->dm.hpd_rx_offload_wq) {
1953 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1954 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1955 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1956 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1960 kfree(adev->dm.hpd_rx_offload_wq);
1961 adev->dm.hpd_rx_offload_wq = NULL;
1964 /* DC Destroy TODO: Replace destroy DAL */
1966 dc_destroy(&adev->dm.dc);
1968 * TODO: pageflip, vlank interrupt
1970 * amdgpu_dm_irq_fini(adev);
1973 if (adev->dm.cgs_device) {
1974 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1975 adev->dm.cgs_device = NULL;
1977 if (adev->dm.freesync_module) {
1978 mod_freesync_destroy(adev->dm.freesync_module);
1979 adev->dm.freesync_module = NULL;
1982 mutex_destroy(&adev->dm.audio_lock);
1983 mutex_destroy(&adev->dm.dc_lock);
1984 mutex_destroy(&adev->dm.dpia_aux_lock);
1987 static int load_dmcu_fw(struct amdgpu_device *adev)
1989 const char *fw_name_dmcu = NULL;
1991 const struct dmcu_firmware_header_v1_0 *hdr;
1993 switch (adev->asic_type) {
1994 #if defined(CONFIG_DRM_AMD_DC_SI)
2009 case CHIP_POLARIS11:
2010 case CHIP_POLARIS10:
2011 case CHIP_POLARIS12:
2018 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
2021 if (ASICREV_IS_PICASSO(adev->external_rev_id))
2022 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2023 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
2024 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2029 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2030 case IP_VERSION(2, 0, 2):
2031 case IP_VERSION(2, 0, 3):
2032 case IP_VERSION(2, 0, 0):
2033 case IP_VERSION(2, 1, 0):
2034 case IP_VERSION(3, 0, 0):
2035 case IP_VERSION(3, 0, 2):
2036 case IP_VERSION(3, 0, 3):
2037 case IP_VERSION(3, 0, 1):
2038 case IP_VERSION(3, 1, 2):
2039 case IP_VERSION(3, 1, 3):
2040 case IP_VERSION(3, 1, 4):
2041 case IP_VERSION(3, 1, 5):
2042 case IP_VERSION(3, 1, 6):
2043 case IP_VERSION(3, 2, 0):
2044 case IP_VERSION(3, 2, 1):
2045 case IP_VERSION(3, 5, 0):
2050 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2054 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2055 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2059 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2061 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2062 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2063 adev->dm.fw_dmcu = NULL;
2067 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2069 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2073 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2074 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2075 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2076 adev->firmware.fw_size +=
2077 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2079 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2080 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2081 adev->firmware.fw_size +=
2082 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2084 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2086 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2091 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2093 struct amdgpu_device *adev = ctx;
2095 return dm_read_reg(adev->dm.dc->ctx, address);
2098 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2101 struct amdgpu_device *adev = ctx;
2103 return dm_write_reg(adev->dm.dc->ctx, address, value);
2106 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2108 struct dmub_srv_create_params create_params;
2109 struct dmub_srv_region_params region_params;
2110 struct dmub_srv_region_info region_info;
2111 struct dmub_srv_memory_params memory_params;
2112 struct dmub_srv_fb_info *fb_info;
2113 struct dmub_srv *dmub_srv;
2114 const struct dmcub_firmware_header_v1_0 *hdr;
2115 enum dmub_asic dmub_asic;
2116 enum dmub_status status;
2119 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2120 case IP_VERSION(2, 1, 0):
2121 dmub_asic = DMUB_ASIC_DCN21;
2123 case IP_VERSION(3, 0, 0):
2124 dmub_asic = DMUB_ASIC_DCN30;
2126 case IP_VERSION(3, 0, 1):
2127 dmub_asic = DMUB_ASIC_DCN301;
2129 case IP_VERSION(3, 0, 2):
2130 dmub_asic = DMUB_ASIC_DCN302;
2132 case IP_VERSION(3, 0, 3):
2133 dmub_asic = DMUB_ASIC_DCN303;
2135 case IP_VERSION(3, 1, 2):
2136 case IP_VERSION(3, 1, 3):
2137 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2139 case IP_VERSION(3, 1, 4):
2140 dmub_asic = DMUB_ASIC_DCN314;
2142 case IP_VERSION(3, 1, 5):
2143 dmub_asic = DMUB_ASIC_DCN315;
2145 case IP_VERSION(3, 1, 6):
2146 dmub_asic = DMUB_ASIC_DCN316;
2148 case IP_VERSION(3, 2, 0):
2149 dmub_asic = DMUB_ASIC_DCN32;
2151 case IP_VERSION(3, 2, 1):
2152 dmub_asic = DMUB_ASIC_DCN321;
2154 case IP_VERSION(3, 5, 0):
2155 dmub_asic = DMUB_ASIC_DCN35;
2158 /* ASIC doesn't support DMUB. */
2162 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2163 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2165 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2166 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2167 AMDGPU_UCODE_ID_DMCUB;
2168 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2170 adev->firmware.fw_size +=
2171 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2173 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2174 adev->dm.dmcub_fw_version);
2178 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2179 dmub_srv = adev->dm.dmub_srv;
2182 DRM_ERROR("Failed to allocate DMUB service!\n");
2186 memset(&create_params, 0, sizeof(create_params));
2187 create_params.user_ctx = adev;
2188 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2189 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2190 create_params.asic = dmub_asic;
2192 /* Create the DMUB service. */
2193 status = dmub_srv_create(dmub_srv, &create_params);
2194 if (status != DMUB_STATUS_OK) {
2195 DRM_ERROR("Error creating DMUB service: %d\n", status);
2199 /* Calculate the size of all the regions for the DMUB service. */
2200 memset(®ion_params, 0, sizeof(region_params));
2202 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2203 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2204 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2205 region_params.vbios_size = adev->bios_size;
2206 region_params.fw_bss_data = region_params.bss_data_size ?
2207 adev->dm.dmub_fw->data +
2208 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2209 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2210 region_params.fw_inst_const =
2211 adev->dm.dmub_fw->data +
2212 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2214 region_params.is_mailbox_in_inbox = false;
2216 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
2219 if (status != DMUB_STATUS_OK) {
2220 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2225 * Allocate a framebuffer based on the total size of all the regions.
2226 * TODO: Move this into GART.
2228 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2229 AMDGPU_GEM_DOMAIN_VRAM |
2230 AMDGPU_GEM_DOMAIN_GTT,
2232 &adev->dm.dmub_bo_gpu_addr,
2233 &adev->dm.dmub_bo_cpu_addr);
2237 /* Rebase the regions on the framebuffer address. */
2238 memset(&memory_params, 0, sizeof(memory_params));
2239 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2240 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2241 memory_params.region_info = ®ion_info;
2243 adev->dm.dmub_fb_info =
2244 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2245 fb_info = adev->dm.dmub_fb_info;
2249 "Failed to allocate framebuffer info for DMUB service!\n");
2253 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2254 if (status != DMUB_STATUS_OK) {
2255 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2262 static int dm_sw_init(void *handle)
2264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2267 r = dm_dmub_sw_init(adev);
2271 return load_dmcu_fw(adev);
2274 static int dm_sw_fini(void *handle)
2276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2278 kfree(adev->dm.dmub_fb_info);
2279 adev->dm.dmub_fb_info = NULL;
2281 if (adev->dm.dmub_srv) {
2282 dmub_srv_destroy(adev->dm.dmub_srv);
2283 adev->dm.dmub_srv = NULL;
2286 amdgpu_ucode_release(&adev->dm.dmub_fw);
2287 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2292 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2294 struct amdgpu_dm_connector *aconnector;
2295 struct drm_connector *connector;
2296 struct drm_connector_list_iter iter;
2299 drm_connector_list_iter_begin(dev, &iter);
2300 drm_for_each_connector_iter(connector, &iter) {
2302 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2305 aconnector = to_amdgpu_dm_connector(connector);
2306 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2307 aconnector->mst_mgr.aux) {
2308 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2310 aconnector->base.base.id);
2312 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2314 DRM_ERROR("DM_MST: Failed to start MST\n");
2315 aconnector->dc_link->type =
2316 dc_connection_single;
2317 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2318 aconnector->dc_link);
2323 drm_connector_list_iter_end(&iter);
2328 static int dm_late_init(void *handle)
2330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2332 struct dmcu_iram_parameters params;
2333 unsigned int linear_lut[16];
2335 struct dmcu *dmcu = NULL;
2337 dmcu = adev->dm.dc->res_pool->dmcu;
2339 for (i = 0; i < 16; i++)
2340 linear_lut[i] = 0xFFFF * i / 15;
2343 params.backlight_ramping_override = false;
2344 params.backlight_ramping_start = 0xCCCC;
2345 params.backlight_ramping_reduction = 0xCCCCCCCC;
2346 params.backlight_lut_array_size = 16;
2347 params.backlight_lut_array = linear_lut;
2349 /* Min backlight level after ABM reduction, Don't allow below 1%
2350 * 0xFFFF x 0.01 = 0x28F
2352 params.min_abm_backlight = 0x28F;
2353 /* In the case where abm is implemented on dmcub,
2354 * dmcu object will be null.
2355 * ABM 2.4 and up are implemented on dmcub.
2358 if (!dmcu_load_iram(dmcu, params))
2360 } else if (adev->dm.dc->ctx->dmub_srv) {
2361 struct dc_link *edp_links[MAX_NUM_EDP];
2364 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2365 for (i = 0; i < edp_num; i++) {
2366 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2371 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2374 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2380 mutex_lock(&mgr->lock);
2381 if (!mgr->mst_primary)
2384 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2385 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2389 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2392 DP_UPSTREAM_IS_SRC);
2394 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2398 /* Some hubs forget their guids after they resume */
2399 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2401 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2405 if (memchr_inv(guid, 0, 16) == NULL) {
2406 tmp64 = get_jiffies_64();
2407 memcpy(&guid[0], &tmp64, sizeof(u64));
2408 memcpy(&guid[8], &tmp64, sizeof(u64));
2410 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2413 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2418 memcpy(mgr->mst_primary->guid, guid, 16);
2421 mutex_unlock(&mgr->lock);
2424 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2426 struct amdgpu_dm_connector *aconnector;
2427 struct drm_connector *connector;
2428 struct drm_connector_list_iter iter;
2429 struct drm_dp_mst_topology_mgr *mgr;
2431 drm_connector_list_iter_begin(dev, &iter);
2432 drm_for_each_connector_iter(connector, &iter) {
2434 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2437 aconnector = to_amdgpu_dm_connector(connector);
2438 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2439 aconnector->mst_root)
2442 mgr = &aconnector->mst_mgr;
2445 drm_dp_mst_topology_mgr_suspend(mgr);
2447 /* if extended timeout is supported in hardware,
2448 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2449 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2451 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2452 if (!dp_is_lttpr_present(aconnector->dc_link))
2453 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2455 /* TODO: move resume_mst_branch_status() into drm mst resume again
2456 * once topology probing work is pulled out from mst resume into mst
2457 * resume 2nd step. mst resume 2nd step should be called after old
2458 * state getting restored (i.e. drm_atomic_helper_resume()).
2460 resume_mst_branch_status(mgr);
2463 drm_connector_list_iter_end(&iter);
2466 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2470 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2471 * on window driver dc implementation.
2472 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2473 * should be passed to smu during boot up and resume from s3.
2474 * boot up: dc calculate dcn watermark clock settings within dc_create,
2475 * dcn20_resource_construct
2476 * then call pplib functions below to pass the settings to smu:
2477 * smu_set_watermarks_for_clock_ranges
2478 * smu_set_watermarks_table
2479 * navi10_set_watermarks_table
2480 * smu_write_watermarks_table
2482 * For Renoir, clock settings of dcn watermark are also fixed values.
2483 * dc has implemented different flow for window driver:
2484 * dc_hardware_init / dc_set_power_state
2489 * smu_set_watermarks_for_clock_ranges
2490 * renoir_set_watermarks_table
2491 * smu_write_watermarks_table
2494 * dc_hardware_init -> amdgpu_dm_init
2495 * dc_set_power_state --> dm_resume
2497 * therefore, this function apply to navi10/12/14 but not Renoir
2500 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2501 case IP_VERSION(2, 0, 2):
2502 case IP_VERSION(2, 0, 0):
2508 ret = amdgpu_dpm_write_watermarks_table(adev);
2510 DRM_ERROR("Failed to update WMTABLE!\n");
2518 * dm_hw_init() - Initialize DC device
2519 * @handle: The base driver device containing the amdgpu_dm device.
2521 * Initialize the &struct amdgpu_display_manager device. This involves calling
2522 * the initializers of each DM component, then populating the struct with them.
2524 * Although the function implies hardware initialization, both hardware and
2525 * software are initialized here. Splitting them out to their relevant init
2526 * hooks is a future TODO item.
2528 * Some notable things that are initialized here:
2530 * - Display Core, both software and hardware
2531 * - DC modules that we need (freesync and color management)
2532 * - DRM software states
2533 * - Interrupt sources and handlers
2535 * - Debug FS entries, if enabled
2537 static int dm_hw_init(void *handle)
2539 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2540 /* Create DAL display manager */
2541 amdgpu_dm_init(adev);
2542 amdgpu_dm_hpd_init(adev);
2548 * dm_hw_fini() - Teardown DC device
2549 * @handle: The base driver device containing the amdgpu_dm device.
2551 * Teardown components within &struct amdgpu_display_manager that require
2552 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2553 * were loaded. Also flush IRQ workqueues and disable them.
2555 static int dm_hw_fini(void *handle)
2557 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2559 amdgpu_dm_hpd_fini(adev);
2561 amdgpu_dm_irq_fini(adev);
2562 amdgpu_dm_fini(adev);
2567 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2568 struct dc_state *state, bool enable)
2570 enum dc_irq_source irq_source;
2571 struct amdgpu_crtc *acrtc;
2575 for (i = 0; i < state->stream_count; i++) {
2576 acrtc = get_crtc_by_otg_inst(
2577 adev, state->stream_status[i].primary_otg_inst);
2579 if (acrtc && state->stream_status[i].plane_count != 0) {
2580 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2581 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2583 DRM_WARN("Failed to %s pflip interrupts\n",
2584 enable ? "enable" : "disable");
2587 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2588 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2590 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2593 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2595 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2596 /* During gpu-reset we disable and then enable vblank irq, so
2597 * don't use amdgpu_irq_get/put() to avoid refcount change.
2599 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2600 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2606 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2608 struct dc_state *context = NULL;
2609 enum dc_status res = DC_ERROR_UNEXPECTED;
2611 struct dc_stream_state *del_streams[MAX_PIPES];
2612 int del_streams_count = 0;
2614 memset(del_streams, 0, sizeof(del_streams));
2616 context = dc_state_create_current_copy(dc);
2617 if (context == NULL)
2618 goto context_alloc_fail;
2620 /* First remove from context all streams */
2621 for (i = 0; i < context->stream_count; i++) {
2622 struct dc_stream_state *stream = context->streams[i];
2624 del_streams[del_streams_count++] = stream;
2627 /* Remove all planes for removed streams and then remove the streams */
2628 for (i = 0; i < del_streams_count; i++) {
2629 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2630 res = DC_FAIL_DETACH_SURFACES;
2634 res = dc_state_remove_stream(dc, context, del_streams[i]);
2639 res = dc_commit_streams(dc, context->streams, context->stream_count);
2642 dc_state_release(context);
2648 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2652 if (dm->hpd_rx_offload_wq) {
2653 for (i = 0; i < dm->dc->caps.max_links; i++)
2654 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2658 static int dm_suspend(void *handle)
2660 struct amdgpu_device *adev = handle;
2661 struct amdgpu_display_manager *dm = &adev->dm;
2664 if (amdgpu_in_reset(adev)) {
2665 mutex_lock(&dm->dc_lock);
2667 dc_allow_idle_optimizations(adev->dm.dc, false);
2669 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);
2671 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2673 amdgpu_dm_commit_zero_streams(dm->dc);
2675 amdgpu_dm_irq_suspend(adev);
2677 hpd_rx_irq_work_suspend(dm);
2682 WARN_ON(adev->dm.cached_state);
2683 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2684 if (IS_ERR(adev->dm.cached_state))
2685 return PTR_ERR(adev->dm.cached_state);
2687 s3_handle_mst(adev_to_drm(adev), true);
2689 amdgpu_dm_irq_suspend(adev);
2691 hpd_rx_irq_work_suspend(dm);
2693 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2694 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
2699 struct drm_connector *
2700 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2701 struct drm_crtc *crtc)
2704 struct drm_connector_state *new_con_state;
2705 struct drm_connector *connector;
2706 struct drm_crtc *crtc_from_state;
2708 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2709 crtc_from_state = new_con_state->crtc;
2711 if (crtc_from_state == crtc)
2718 static void emulated_link_detect(struct dc_link *link)
2720 struct dc_sink_init_data sink_init_data = { 0 };
2721 struct display_sink_capability sink_caps = { 0 };
2722 enum dc_edid_status edid_status;
2723 struct dc_context *dc_ctx = link->ctx;
2724 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2725 struct dc_sink *sink = NULL;
2726 struct dc_sink *prev_sink = NULL;
2728 link->type = dc_connection_none;
2729 prev_sink = link->local_sink;
2732 dc_sink_release(prev_sink);
2734 switch (link->connector_signal) {
2735 case SIGNAL_TYPE_HDMI_TYPE_A: {
2736 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2737 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2741 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2742 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2743 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2747 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2748 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2749 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2753 case SIGNAL_TYPE_LVDS: {
2754 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2755 sink_caps.signal = SIGNAL_TYPE_LVDS;
2759 case SIGNAL_TYPE_EDP: {
2760 sink_caps.transaction_type =
2761 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2762 sink_caps.signal = SIGNAL_TYPE_EDP;
2766 case SIGNAL_TYPE_DISPLAY_PORT: {
2767 sink_caps.transaction_type =
2768 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2769 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2774 drm_err(dev, "Invalid connector type! signal:%d\n",
2775 link->connector_signal);
2779 sink_init_data.link = link;
2780 sink_init_data.sink_signal = sink_caps.signal;
2782 sink = dc_sink_create(&sink_init_data);
2784 drm_err(dev, "Failed to create sink!\n");
2788 /* dc_sink_create returns a new reference */
2789 link->local_sink = sink;
2791 edid_status = dm_helpers_read_local_edid(
2796 if (edid_status != EDID_OK)
2797 drm_err(dev, "Failed to read EDID\n");
2801 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2802 struct amdgpu_display_manager *dm)
2805 struct dc_surface_update surface_updates[MAX_SURFACES];
2806 struct dc_plane_info plane_infos[MAX_SURFACES];
2807 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2808 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2809 struct dc_stream_update stream_update;
2813 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2816 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2820 for (k = 0; k < dc_state->stream_count; k++) {
2821 bundle->stream_update.stream = dc_state->streams[k];
2823 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2824 bundle->surface_updates[m].surface =
2825 dc_state->stream_status->plane_states[m];
2826 bundle->surface_updates[m].surface->force_full_update =
2830 update_planes_and_stream_adapter(dm->dc,
2832 dc_state->stream_status->plane_count,
2833 dc_state->streams[k],
2834 &bundle->stream_update,
2835 bundle->surface_updates);
2842 static int dm_resume(void *handle)
2844 struct amdgpu_device *adev = handle;
2845 struct drm_device *ddev = adev_to_drm(adev);
2846 struct amdgpu_display_manager *dm = &adev->dm;
2847 struct amdgpu_dm_connector *aconnector;
2848 struct drm_connector *connector;
2849 struct drm_connector_list_iter iter;
2850 struct drm_crtc *crtc;
2851 struct drm_crtc_state *new_crtc_state;
2852 struct dm_crtc_state *dm_new_crtc_state;
2853 struct drm_plane *plane;
2854 struct drm_plane_state *new_plane_state;
2855 struct dm_plane_state *dm_new_plane_state;
2856 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2857 enum dc_connection_type new_connection_type = dc_connection_none;
2858 struct dc_state *dc_state;
2860 bool need_hotplug = false;
2862 if (dm->dc->caps.ips_support) {
2863 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
2866 if (amdgpu_in_reset(adev)) {
2867 dc_state = dm->cached_dc_state;
2870 * The dc->current_state is backed up into dm->cached_dc_state
2871 * before we commit 0 streams.
2873 * DC will clear link encoder assignments on the real state
2874 * but the changes won't propagate over to the copy we made
2875 * before the 0 streams commit.
2877 * DC expects that link encoder assignments are *not* valid
2878 * when committing a state, so as a workaround we can copy
2879 * off of the current state.
2881 * We lose the previous assignments, but we had already
2882 * commit 0 streams anyway.
2884 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2886 r = dm_dmub_hw_init(adev);
2888 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2890 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
2891 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2895 amdgpu_dm_irq_resume_early(adev);
2897 for (i = 0; i < dc_state->stream_count; i++) {
2898 dc_state->streams[i]->mode_changed = true;
2899 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2900 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2905 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2906 amdgpu_dm_outbox_init(adev);
2907 dc_enable_dmub_outbox(adev->dm.dc);
2910 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2912 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2914 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2916 dc_state_release(dm->cached_dc_state);
2917 dm->cached_dc_state = NULL;
2919 amdgpu_dm_irq_resume_late(adev);
2921 mutex_unlock(&dm->dc_lock);
2925 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2926 dc_state_release(dm_state->context);
2927 dm_state->context = dc_state_create(dm->dc);
2928 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2930 /* Before powering on DC we need to re-initialize DMUB. */
2931 dm_dmub_hw_resume(adev);
2933 /* Re-enable outbox interrupts for DPIA. */
2934 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2935 amdgpu_dm_outbox_init(adev);
2936 dc_enable_dmub_outbox(adev->dm.dc);
2939 /* power on hardware */
2940 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
2941 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2943 /* program HPD filter */
2947 * early enable HPD Rx IRQ, should be done before set mode as short
2948 * pulse interrupts are used for MST
2950 amdgpu_dm_irq_resume_early(adev);
2952 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2953 s3_handle_mst(ddev, false);
2956 drm_connector_list_iter_begin(ddev, &iter);
2957 drm_for_each_connector_iter(connector, &iter) {
2959 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2962 aconnector = to_amdgpu_dm_connector(connector);
2964 if (!aconnector->dc_link)
2968 * this is the case when traversing through already created end sink
2969 * MST connectors, should be skipped
2971 if (aconnector && aconnector->mst_root)
2974 mutex_lock(&aconnector->hpd_lock);
2975 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2976 DRM_ERROR("KMS: Failed to detect connector\n");
2978 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2979 emulated_link_detect(aconnector->dc_link);
2981 mutex_lock(&dm->dc_lock);
2982 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2983 mutex_unlock(&dm->dc_lock);
2986 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2987 aconnector->fake_enable = false;
2989 if (aconnector->dc_sink)
2990 dc_sink_release(aconnector->dc_sink);
2991 aconnector->dc_sink = NULL;
2992 amdgpu_dm_update_connector_after_detect(aconnector);
2993 mutex_unlock(&aconnector->hpd_lock);
2995 drm_connector_list_iter_end(&iter);
2997 /* Force mode set in atomic commit */
2998 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2999 new_crtc_state->active_changed = true;
3002 * atomic_check is expected to create the dc states. We need to release
3003 * them here, since they were duplicated as part of the suspend
3006 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
3007 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3008 if (dm_new_crtc_state->stream) {
3009 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
3010 dc_stream_release(dm_new_crtc_state->stream);
3011 dm_new_crtc_state->stream = NULL;
3015 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
3016 dm_new_plane_state = to_dm_plane_state(new_plane_state);
3017 if (dm_new_plane_state->dc_state) {
3018 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
3019 dc_plane_state_release(dm_new_plane_state->dc_state);
3020 dm_new_plane_state->dc_state = NULL;
3024 drm_atomic_helper_resume(ddev, dm->cached_state);
3026 dm->cached_state = NULL;
3028 /* Do mst topology probing after resuming cached state*/
3029 drm_connector_list_iter_begin(ddev, &iter);
3030 drm_for_each_connector_iter(connector, &iter) {
3031 aconnector = to_amdgpu_dm_connector(connector);
3032 if (aconnector->dc_link->type != dc_connection_mst_branch ||
3033 aconnector->mst_root)
3036 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
3039 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
3040 aconnector->dc_link);
3041 need_hotplug = true;
3044 drm_connector_list_iter_end(&iter);
3047 drm_kms_helper_hotplug_event(ddev);
3049 amdgpu_dm_irq_resume_late(adev);
3051 amdgpu_dm_smu_write_watermarks_table(adev);
3059 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3060 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3061 * the base driver's device list to be initialized and torn down accordingly.
3063 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3066 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3068 .early_init = dm_early_init,
3069 .late_init = dm_late_init,
3070 .sw_init = dm_sw_init,
3071 .sw_fini = dm_sw_fini,
3072 .early_fini = amdgpu_dm_early_fini,
3073 .hw_init = dm_hw_init,
3074 .hw_fini = dm_hw_fini,
3075 .suspend = dm_suspend,
3076 .resume = dm_resume,
3077 .is_idle = dm_is_idle,
3078 .wait_for_idle = dm_wait_for_idle,
3079 .check_soft_reset = dm_check_soft_reset,
3080 .soft_reset = dm_soft_reset,
3081 .set_clockgating_state = dm_set_clockgating_state,
3082 .set_powergating_state = dm_set_powergating_state,
3085 const struct amdgpu_ip_block_version dm_ip_block = {
3086 .type = AMD_IP_BLOCK_TYPE_DCE,
3090 .funcs = &amdgpu_dm_funcs,
3100 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3101 .fb_create = amdgpu_display_user_framebuffer_create,
3102 .get_format_info = amdgpu_dm_plane_get_format_info,
3103 .atomic_check = amdgpu_dm_atomic_check,
3104 .atomic_commit = drm_atomic_helper_commit,
3107 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3108 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3109 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3112 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3114 struct amdgpu_dm_backlight_caps *caps;
3115 struct drm_connector *conn_base;
3116 struct amdgpu_device *adev;
3117 struct drm_luminance_range_info *luminance_range;
3119 if (aconnector->bl_idx == -1 ||
3120 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3123 conn_base = &aconnector->base;
3124 adev = drm_to_adev(conn_base->dev);
3126 caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3127 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3128 caps->aux_support = false;
3130 if (caps->ext_caps->bits.oled == 1
3133 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3134 * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3136 caps->aux_support = true;
3138 if (amdgpu_backlight == 0)
3139 caps->aux_support = false;
3140 else if (amdgpu_backlight == 1)
3141 caps->aux_support = true;
3143 luminance_range = &conn_base->display_info.luminance_range;
3145 if (luminance_range->max_luminance) {
3146 caps->aux_min_input_signal = luminance_range->min_luminance;
3147 caps->aux_max_input_signal = luminance_range->max_luminance;
3149 caps->aux_min_input_signal = 0;
3150 caps->aux_max_input_signal = 512;
3154 void amdgpu_dm_update_connector_after_detect(
3155 struct amdgpu_dm_connector *aconnector)
3157 struct drm_connector *connector = &aconnector->base;
3158 struct drm_device *dev = connector->dev;
3159 struct dc_sink *sink;
3161 /* MST handled by drm_mst framework */
3162 if (aconnector->mst_mgr.mst_state == true)
3165 sink = aconnector->dc_link->local_sink;
3167 dc_sink_retain(sink);
3170 * Edid mgmt connector gets first update only in mode_valid hook and then
3171 * the connector sink is set to either fake or physical sink depends on link status.
3172 * Skip if already done during boot.
3174 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3175 && aconnector->dc_em_sink) {
3178 * For S3 resume with headless use eml_sink to fake stream
3179 * because on resume connector->sink is set to NULL
3181 mutex_lock(&dev->mode_config.mutex);
3184 if (aconnector->dc_sink) {
3185 amdgpu_dm_update_freesync_caps(connector, NULL);
3187 * retain and release below are used to
3188 * bump up refcount for sink because the link doesn't point
3189 * to it anymore after disconnect, so on next crtc to connector
3190 * reshuffle by UMD we will get into unwanted dc_sink release
3192 dc_sink_release(aconnector->dc_sink);
3194 aconnector->dc_sink = sink;
3195 dc_sink_retain(aconnector->dc_sink);
3196 amdgpu_dm_update_freesync_caps(connector,
3199 amdgpu_dm_update_freesync_caps(connector, NULL);
3200 if (!aconnector->dc_sink) {
3201 aconnector->dc_sink = aconnector->dc_em_sink;
3202 dc_sink_retain(aconnector->dc_sink);
3206 mutex_unlock(&dev->mode_config.mutex);
3209 dc_sink_release(sink);
3214 * TODO: temporary guard to look for proper fix
3215 * if this sink is MST sink, we should not do anything
3217 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3218 dc_sink_release(sink);
3222 if (aconnector->dc_sink == sink) {
3224 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3227 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3228 aconnector->connector_id);
3230 dc_sink_release(sink);
3234 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3235 aconnector->connector_id, aconnector->dc_sink, sink);
3237 mutex_lock(&dev->mode_config.mutex);
3240 * 1. Update status of the drm connector
3241 * 2. Send an event and let userspace tell us what to do
3245 * TODO: check if we still need the S3 mode update workaround.
3246 * If yes, put it here.
3248 if (aconnector->dc_sink) {
3249 amdgpu_dm_update_freesync_caps(connector, NULL);
3250 dc_sink_release(aconnector->dc_sink);
3253 aconnector->dc_sink = sink;
3254 dc_sink_retain(aconnector->dc_sink);
3255 if (sink->dc_edid.length == 0) {
3256 aconnector->edid = NULL;
3257 if (aconnector->dc_link->aux_mode) {
3258 drm_dp_cec_unset_edid(
3259 &aconnector->dm_dp_aux.aux);
3263 (struct edid *)sink->dc_edid.raw_edid;
3265 if (aconnector->dc_link->aux_mode)
3266 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3270 if (!aconnector->timing_requested) {
3271 aconnector->timing_requested =
3272 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3273 if (!aconnector->timing_requested)
3275 "failed to create aconnector->requested_timing\n");
3278 drm_connector_update_edid_property(connector, aconnector->edid);
3279 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3280 update_connector_ext_caps(aconnector);
3282 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3283 amdgpu_dm_update_freesync_caps(connector, NULL);
3284 drm_connector_update_edid_property(connector, NULL);
3285 aconnector->num_modes = 0;
3286 dc_sink_release(aconnector->dc_sink);
3287 aconnector->dc_sink = NULL;
3288 aconnector->edid = NULL;
3289 kfree(aconnector->timing_requested);
3290 aconnector->timing_requested = NULL;
3291 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3292 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3293 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3296 mutex_unlock(&dev->mode_config.mutex);
3298 update_subconnector_property(aconnector);
3301 dc_sink_release(sink);
3304 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3306 struct drm_connector *connector = &aconnector->base;
3307 struct drm_device *dev = connector->dev;
3308 enum dc_connection_type new_connection_type = dc_connection_none;
3309 struct amdgpu_device *adev = drm_to_adev(dev);
3310 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3313 if (adev->dm.disable_hpd_irq)
3317 * In case of failure or MST no need to update connector status or notify the OS
3318 * since (for MST case) MST does this in its own context.
3320 mutex_lock(&aconnector->hpd_lock);
3322 if (adev->dm.hdcp_workqueue) {
3323 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3324 dm_con_state->update_hdcp = true;
3326 if (aconnector->fake_enable)
3327 aconnector->fake_enable = false;
3329 aconnector->timing_changed = false;
3331 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3332 DRM_ERROR("KMS: Failed to detect connector\n");
3334 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3335 emulated_link_detect(aconnector->dc_link);
3337 drm_modeset_lock_all(dev);
3338 dm_restore_drm_connector_state(dev, connector);
3339 drm_modeset_unlock_all(dev);
3341 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3342 drm_kms_helper_connector_hotplug_event(connector);
3344 mutex_lock(&adev->dm.dc_lock);
3345 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3346 mutex_unlock(&adev->dm.dc_lock);
3348 amdgpu_dm_update_connector_after_detect(aconnector);
3350 drm_modeset_lock_all(dev);
3351 dm_restore_drm_connector_state(dev, connector);
3352 drm_modeset_unlock_all(dev);
3354 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3355 drm_kms_helper_connector_hotplug_event(connector);
3358 mutex_unlock(&aconnector->hpd_lock);
3362 static void handle_hpd_irq(void *param)
3364 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3366 handle_hpd_irq_helper(aconnector);
3370 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3371 union hpd_irq_data hpd_irq_data)
3373 struct hpd_rx_irq_offload_work *offload_work =
3374 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3376 if (!offload_work) {
3377 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3381 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3382 offload_work->data = hpd_irq_data;
3383 offload_work->offload_wq = offload_wq;
3385 queue_work(offload_wq->wq, &offload_work->work);
3386 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3389 static void handle_hpd_rx_irq(void *param)
3391 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3392 struct drm_connector *connector = &aconnector->base;
3393 struct drm_device *dev = connector->dev;
3394 struct dc_link *dc_link = aconnector->dc_link;
3395 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3396 bool result = false;
3397 enum dc_connection_type new_connection_type = dc_connection_none;
3398 struct amdgpu_device *adev = drm_to_adev(dev);
3399 union hpd_irq_data hpd_irq_data;
3400 bool link_loss = false;
3401 bool has_left_work = false;
3402 int idx = dc_link->link_index;
3403 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3405 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3407 if (adev->dm.disable_hpd_irq)
3411 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3412 * conflict, after implement i2c helper, this mutex should be
3415 mutex_lock(&aconnector->hpd_lock);
3417 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3418 &link_loss, true, &has_left_work);
3423 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3424 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3428 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3429 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3430 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3434 * DOWN_REP_MSG_RDY is also handled by polling method
3435 * mgr->cbs->poll_hpd_irq()
3437 spin_lock(&offload_wq->offload_lock);
3438 skip = offload_wq->is_handling_mst_msg_rdy_event;
3441 offload_wq->is_handling_mst_msg_rdy_event = true;
3443 spin_unlock(&offload_wq->offload_lock);
3446 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3454 spin_lock(&offload_wq->offload_lock);
3455 skip = offload_wq->is_handling_link_loss;
3458 offload_wq->is_handling_link_loss = true;
3460 spin_unlock(&offload_wq->offload_lock);
3463 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3470 if (result && !is_mst_root_connector) {
3471 /* Downstream Port status changed. */
3472 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3473 DRM_ERROR("KMS: Failed to detect connector\n");
3475 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3476 emulated_link_detect(dc_link);
3478 if (aconnector->fake_enable)
3479 aconnector->fake_enable = false;
3481 amdgpu_dm_update_connector_after_detect(aconnector);
3484 drm_modeset_lock_all(dev);
3485 dm_restore_drm_connector_state(dev, connector);
3486 drm_modeset_unlock_all(dev);
3488 drm_kms_helper_connector_hotplug_event(connector);
3492 mutex_lock(&adev->dm.dc_lock);
3493 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3494 mutex_unlock(&adev->dm.dc_lock);
3497 if (aconnector->fake_enable)
3498 aconnector->fake_enable = false;
3500 amdgpu_dm_update_connector_after_detect(aconnector);
3502 drm_modeset_lock_all(dev);
3503 dm_restore_drm_connector_state(dev, connector);
3504 drm_modeset_unlock_all(dev);
3506 drm_kms_helper_connector_hotplug_event(connector);
3510 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3511 if (adev->dm.hdcp_workqueue)
3512 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3515 if (dc_link->type != dc_connection_mst_branch)
3516 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3518 mutex_unlock(&aconnector->hpd_lock);
3521 static void register_hpd_handlers(struct amdgpu_device *adev)
3523 struct drm_device *dev = adev_to_drm(adev);
3524 struct drm_connector *connector;
3525 struct amdgpu_dm_connector *aconnector;
3526 const struct dc_link *dc_link;
3527 struct dc_interrupt_params int_params = {0};
3529 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3530 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3532 list_for_each_entry(connector,
3533 &dev->mode_config.connector_list, head) {
3535 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
3538 aconnector = to_amdgpu_dm_connector(connector);
3539 dc_link = aconnector->dc_link;
3541 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3542 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3543 int_params.irq_source = dc_link->irq_source_hpd;
3545 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3547 (void *) aconnector);
3550 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3552 /* Also register for DP short pulse (hpd_rx). */
3553 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3554 int_params.irq_source = dc_link->irq_source_hpd_rx;
3556 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3558 (void *) aconnector);
3561 if (adev->dm.hpd_rx_offload_wq)
3562 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3567 #if defined(CONFIG_DRM_AMD_DC_SI)
3568 /* Register IRQ sources and initialize IRQ callbacks */
3569 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3571 struct dc *dc = adev->dm.dc;
3572 struct common_irq_params *c_irq_params;
3573 struct dc_interrupt_params int_params = {0};
3576 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3578 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3579 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3582 * Actions of amdgpu_irq_add_id():
3583 * 1. Register a set() function with base driver.
3584 * Base driver will call set() function to enable/disable an
3585 * interrupt in DC hardware.
3586 * 2. Register amdgpu_dm_irq_handler().
3587 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3588 * coming from DC hardware.
3589 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3590 * for acknowledging and handling.
3593 /* Use VBLANK interrupt */
3594 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3595 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3597 DRM_ERROR("Failed to add crtc irq id!\n");
3601 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3602 int_params.irq_source =
3603 dc_interrupt_to_irq_source(dc, i + 1, 0);
3605 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3607 c_irq_params->adev = adev;
3608 c_irq_params->irq_src = int_params.irq_source;
3610 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3611 dm_crtc_high_irq, c_irq_params);
3614 /* Use GRPH_PFLIP interrupt */
3615 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3616 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3617 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3619 DRM_ERROR("Failed to add page flip irq id!\n");
3623 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3624 int_params.irq_source =
3625 dc_interrupt_to_irq_source(dc, i, 0);
3627 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3629 c_irq_params->adev = adev;
3630 c_irq_params->irq_src = int_params.irq_source;
3632 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3633 dm_pflip_high_irq, c_irq_params);
3638 r = amdgpu_irq_add_id(adev, client_id,
3639 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3641 DRM_ERROR("Failed to add hpd irq id!\n");
3645 register_hpd_handlers(adev);
3651 /* Register IRQ sources and initialize IRQ callbacks */
3652 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3654 struct dc *dc = adev->dm.dc;
3655 struct common_irq_params *c_irq_params;
3656 struct dc_interrupt_params int_params = {0};
3659 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3661 if (adev->family >= AMDGPU_FAMILY_AI)
3662 client_id = SOC15_IH_CLIENTID_DCE;
3664 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3665 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3668 * Actions of amdgpu_irq_add_id():
3669 * 1. Register a set() function with base driver.
3670 * Base driver will call set() function to enable/disable an
3671 * interrupt in DC hardware.
3672 * 2. Register amdgpu_dm_irq_handler().
3673 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3674 * coming from DC hardware.
3675 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3676 * for acknowledging and handling.
3679 /* Use VBLANK interrupt */
3680 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3681 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3683 DRM_ERROR("Failed to add crtc irq id!\n");
3687 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3688 int_params.irq_source =
3689 dc_interrupt_to_irq_source(dc, i, 0);
3691 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3693 c_irq_params->adev = adev;
3694 c_irq_params->irq_src = int_params.irq_source;
3696 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3697 dm_crtc_high_irq, c_irq_params);
3700 /* Use VUPDATE interrupt */
3701 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3702 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3704 DRM_ERROR("Failed to add vupdate irq id!\n");
3708 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3709 int_params.irq_source =
3710 dc_interrupt_to_irq_source(dc, i, 0);
3712 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3714 c_irq_params->adev = adev;
3715 c_irq_params->irq_src = int_params.irq_source;
3717 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3718 dm_vupdate_high_irq, c_irq_params);
3721 /* Use GRPH_PFLIP interrupt */
3722 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3723 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3724 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3726 DRM_ERROR("Failed to add page flip irq id!\n");
3730 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3731 int_params.irq_source =
3732 dc_interrupt_to_irq_source(dc, i, 0);
3734 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3736 c_irq_params->adev = adev;
3737 c_irq_params->irq_src = int_params.irq_source;
3739 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3740 dm_pflip_high_irq, c_irq_params);
3745 r = amdgpu_irq_add_id(adev, client_id,
3746 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3748 DRM_ERROR("Failed to add hpd irq id!\n");
3752 register_hpd_handlers(adev);
3757 /* Register IRQ sources and initialize IRQ callbacks */
3758 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3760 struct dc *dc = adev->dm.dc;
3761 struct common_irq_params *c_irq_params;
3762 struct dc_interrupt_params int_params = {0};
3765 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3766 static const unsigned int vrtl_int_srcid[] = {
3767 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3768 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3769 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3770 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3771 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3772 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3776 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3777 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3780 * Actions of amdgpu_irq_add_id():
3781 * 1. Register a set() function with base driver.
3782 * Base driver will call set() function to enable/disable an
3783 * interrupt in DC hardware.
3784 * 2. Register amdgpu_dm_irq_handler().
3785 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3786 * coming from DC hardware.
3787 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3788 * for acknowledging and handling.
3791 /* Use VSTARTUP interrupt */
3792 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3793 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3795 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3798 DRM_ERROR("Failed to add crtc irq id!\n");
3802 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3803 int_params.irq_source =
3804 dc_interrupt_to_irq_source(dc, i, 0);
3806 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3808 c_irq_params->adev = adev;
3809 c_irq_params->irq_src = int_params.irq_source;
3811 amdgpu_dm_irq_register_interrupt(
3812 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3815 /* Use otg vertical line interrupt */
3816 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3817 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3818 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3819 vrtl_int_srcid[i], &adev->vline0_irq);
3822 DRM_ERROR("Failed to add vline0 irq id!\n");
3826 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3827 int_params.irq_source =
3828 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3830 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3831 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3835 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3836 - DC_IRQ_SOURCE_DC1_VLINE0];
3838 c_irq_params->adev = adev;
3839 c_irq_params->irq_src = int_params.irq_source;
3841 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3842 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3846 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3847 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3848 * to trigger at end of each vblank, regardless of state of the lock,
3849 * matching DCE behaviour.
3851 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3852 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3854 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3857 DRM_ERROR("Failed to add vupdate irq id!\n");
3861 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3862 int_params.irq_source =
3863 dc_interrupt_to_irq_source(dc, i, 0);
3865 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3867 c_irq_params->adev = adev;
3868 c_irq_params->irq_src = int_params.irq_source;
3870 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3871 dm_vupdate_high_irq, c_irq_params);
3874 /* Use GRPH_PFLIP interrupt */
3875 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3876 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3878 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3880 DRM_ERROR("Failed to add page flip irq id!\n");
3884 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3885 int_params.irq_source =
3886 dc_interrupt_to_irq_source(dc, i, 0);
3888 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3890 c_irq_params->adev = adev;
3891 c_irq_params->irq_src = int_params.irq_source;
3893 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3894 dm_pflip_high_irq, c_irq_params);
3899 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3902 DRM_ERROR("Failed to add hpd irq id!\n");
3906 register_hpd_handlers(adev);
3910 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3911 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3913 struct dc *dc = adev->dm.dc;
3914 struct common_irq_params *c_irq_params;
3915 struct dc_interrupt_params int_params = {0};
3918 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3919 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3921 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3922 &adev->dmub_outbox_irq);
3924 DRM_ERROR("Failed to add outbox irq id!\n");
3928 if (dc->ctx->dmub_srv) {
3929 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3930 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3931 int_params.irq_source =
3932 dc_interrupt_to_irq_source(dc, i, 0);
3934 c_irq_params = &adev->dm.dmub_outbox_params[0];
3936 c_irq_params->adev = adev;
3937 c_irq_params->irq_src = int_params.irq_source;
3939 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3940 dm_dmub_outbox1_low_irq, c_irq_params);
3947 * Acquires the lock for the atomic state object and returns
3948 * the new atomic state.
3950 * This should only be called during atomic check.
3952 int dm_atomic_get_state(struct drm_atomic_state *state,
3953 struct dm_atomic_state **dm_state)
3955 struct drm_device *dev = state->dev;
3956 struct amdgpu_device *adev = drm_to_adev(dev);
3957 struct amdgpu_display_manager *dm = &adev->dm;
3958 struct drm_private_state *priv_state;
3963 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3964 if (IS_ERR(priv_state))
3965 return PTR_ERR(priv_state);
3967 *dm_state = to_dm_atomic_state(priv_state);
3972 static struct dm_atomic_state *
3973 dm_atomic_get_new_state(struct drm_atomic_state *state)
3975 struct drm_device *dev = state->dev;
3976 struct amdgpu_device *adev = drm_to_adev(dev);
3977 struct amdgpu_display_manager *dm = &adev->dm;
3978 struct drm_private_obj *obj;
3979 struct drm_private_state *new_obj_state;
3982 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3983 if (obj->funcs == dm->atomic_obj.funcs)
3984 return to_dm_atomic_state(new_obj_state);
3990 static struct drm_private_state *
3991 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3993 struct dm_atomic_state *old_state, *new_state;
3995 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3999 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
4001 old_state = to_dm_atomic_state(obj->state);
4003 if (old_state && old_state->context)
4004 new_state->context = dc_state_create_copy(old_state->context);
4006 if (!new_state->context) {
4011 return &new_state->base;
4014 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
4015 struct drm_private_state *state)
4017 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4019 if (dm_state && dm_state->context)
4020 dc_state_release(dm_state->context);
4025 static struct drm_private_state_funcs dm_atomic_state_funcs = {
4026 .atomic_duplicate_state = dm_atomic_duplicate_state,
4027 .atomic_destroy_state = dm_atomic_destroy_state,
4030 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
4032 struct dm_atomic_state *state;
4035 adev->mode_info.mode_config_initialized = true;
4037 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
4038 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4040 adev_to_drm(adev)->mode_config.max_width = 16384;
4041 adev_to_drm(adev)->mode_config.max_height = 16384;
4043 adev_to_drm(adev)->mode_config.preferred_depth = 24;
4044 if (adev->asic_type == CHIP_HAWAII)
4045 /* disable prefer shadow for now due to hibernation issues */
4046 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4048 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4049 /* indicates support for immediate flip */
4050 adev_to_drm(adev)->mode_config.async_page_flip = true;
4052 state = kzalloc(sizeof(*state), GFP_KERNEL);
4056 state->context = dc_state_create_current_copy(adev->dm.dc);
4057 if (!state->context) {
4062 drm_atomic_private_obj_init(adev_to_drm(adev),
4063 &adev->dm.atomic_obj,
4065 &dm_atomic_state_funcs);
4067 r = amdgpu_display_modeset_create_props(adev);
4069 dc_state_release(state->context);
4074 #ifdef AMD_PRIVATE_COLOR
4075 if (amdgpu_dm_create_color_properties(adev))
4079 r = amdgpu_dm_audio_init(adev);
4081 dc_state_release(state->context);
4089 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4090 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4091 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4093 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4096 #if defined(CONFIG_ACPI)
4097 struct amdgpu_dm_backlight_caps caps;
4099 memset(&caps, 0, sizeof(caps));
4101 if (dm->backlight_caps[bl_idx].caps_valid)
4104 amdgpu_acpi_get_backlight_caps(&caps);
4105 if (caps.caps_valid) {
4106 dm->backlight_caps[bl_idx].caps_valid = true;
4107 if (caps.aux_support)
4109 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4110 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4112 dm->backlight_caps[bl_idx].min_input_signal =
4113 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4114 dm->backlight_caps[bl_idx].max_input_signal =
4115 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4118 if (dm->backlight_caps[bl_idx].aux_support)
4121 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4122 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4126 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4127 unsigned int *min, unsigned int *max)
4132 if (caps->aux_support) {
4133 // Firmware limits are in nits, DC API wants millinits.
4134 *max = 1000 * caps->aux_max_input_signal;
4135 *min = 1000 * caps->aux_min_input_signal;
4137 // Firmware limits are 8-bit, PWM control is 16-bit.
4138 *max = 0x101 * caps->max_input_signal;
4139 *min = 0x101 * caps->min_input_signal;
4144 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4145 uint32_t brightness)
4147 unsigned int min, max;
4149 if (!get_brightness_range(caps, &min, &max))
4152 // Rescale 0..255 to min..max
4153 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4154 AMDGPU_MAX_BL_LEVEL);
4157 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4158 uint32_t brightness)
4160 unsigned int min, max;
4162 if (!get_brightness_range(caps, &min, &max))
4165 if (brightness < min)
4167 // Rescale min..max to 0..255
4168 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4172 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4174 u32 user_brightness)
4176 struct amdgpu_dm_backlight_caps caps;
4177 struct dc_link *link;
4181 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4182 caps = dm->backlight_caps[bl_idx];
4184 dm->brightness[bl_idx] = user_brightness;
4185 /* update scratch register */
4187 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4188 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4189 link = (struct dc_link *)dm->backlight_link[bl_idx];
4191 /* Change brightness based on AUX property */
4192 if (caps.aux_support) {
4193 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4194 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4196 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4198 rc = dc_link_set_backlight_level(link, brightness, 0);
4200 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4204 dm->actual_brightness[bl_idx] = user_brightness;
4207 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4209 struct amdgpu_display_manager *dm = bl_get_data(bd);
4212 for (i = 0; i < dm->num_of_edps; i++) {
4213 if (bd == dm->backlight_dev[i])
4216 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4218 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4223 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4227 struct amdgpu_dm_backlight_caps caps;
4228 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4230 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4231 caps = dm->backlight_caps[bl_idx];
4233 if (caps.aux_support) {
4237 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4239 return dm->brightness[bl_idx];
4240 return convert_brightness_to_user(&caps, avg);
4243 ret = dc_link_get_backlight_level(link);
4245 if (ret == DC_ERROR_UNEXPECTED)
4246 return dm->brightness[bl_idx];
4248 return convert_brightness_to_user(&caps, ret);
4251 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4253 struct amdgpu_display_manager *dm = bl_get_data(bd);
4256 for (i = 0; i < dm->num_of_edps; i++) {
4257 if (bd == dm->backlight_dev[i])
4260 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4262 return amdgpu_dm_backlight_get_level(dm, i);
4265 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4266 .options = BL_CORE_SUSPENDRESUME,
4267 .get_brightness = amdgpu_dm_backlight_get_brightness,
4268 .update_status = amdgpu_dm_backlight_update_status,
4272 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4274 struct drm_device *drm = aconnector->base.dev;
4275 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4276 struct backlight_properties props = { 0 };
4279 if (aconnector->bl_idx == -1)
4282 if (!acpi_video_backlight_use_native()) {
4283 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4284 /* Try registering an ACPI video backlight device instead. */
4285 acpi_video_register_backlight();
4289 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4290 props.brightness = AMDGPU_MAX_BL_LEVEL;
4291 props.type = BACKLIGHT_RAW;
4293 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4294 drm->primary->index + aconnector->bl_idx);
4296 dm->backlight_dev[aconnector->bl_idx] =
4297 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4298 &amdgpu_dm_backlight_ops, &props);
4300 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4301 DRM_ERROR("DM: Backlight registration failed!\n");
4302 dm->backlight_dev[aconnector->bl_idx] = NULL;
4304 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4307 static int initialize_plane(struct amdgpu_display_manager *dm,
4308 struct amdgpu_mode_info *mode_info, int plane_id,
4309 enum drm_plane_type plane_type,
4310 const struct dc_plane_cap *plane_cap)
4312 struct drm_plane *plane;
4313 unsigned long possible_crtcs;
4316 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4318 DRM_ERROR("KMS: Failed to allocate plane\n");
4321 plane->type = plane_type;
4324 * HACK: IGT tests expect that the primary plane for a CRTC
4325 * can only have one possible CRTC. Only expose support for
4326 * any CRTC if they're not going to be used as a primary plane
4327 * for a CRTC - like overlay or underlay planes.
4329 possible_crtcs = 1 << plane_id;
4330 if (plane_id >= dm->dc->caps.max_streams)
4331 possible_crtcs = 0xff;
4333 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4336 DRM_ERROR("KMS: Failed to initialize plane\n");
4342 mode_info->planes[plane_id] = plane;
4348 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4349 struct amdgpu_dm_connector *aconnector)
4351 struct dc_link *link = aconnector->dc_link;
4352 int bl_idx = dm->num_of_edps;
4354 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4355 link->type == dc_connection_none)
4358 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4359 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4363 aconnector->bl_idx = bl_idx;
4365 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4366 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4367 dm->backlight_link[bl_idx] = link;
4370 update_connector_ext_caps(aconnector);
4373 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4376 * In this architecture, the association
4377 * connector -> encoder -> crtc
4378 * id not really requried. The crtc and connector will hold the
4379 * display_index as an abstraction to use with DAL component
4381 * Returns 0 on success
4383 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4385 struct amdgpu_display_manager *dm = &adev->dm;
4387 struct amdgpu_dm_connector *aconnector = NULL;
4388 struct amdgpu_encoder *aencoder = NULL;
4389 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4392 enum dc_connection_type new_connection_type = dc_connection_none;
4393 const struct dc_plane_cap *plane;
4394 bool psr_feature_enabled = false;
4395 int max_overlay = dm->dc->caps.max_slave_planes;
4397 dm->display_indexes_num = dm->dc->caps.max_streams;
4398 /* Update the actual used number of crtc */
4399 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4401 amdgpu_dm_set_irq_funcs(adev);
4403 link_cnt = dm->dc->caps.max_links;
4404 if (amdgpu_dm_mode_config_init(dm->adev)) {
4405 DRM_ERROR("DM: Failed to initialize mode config\n");
4409 /* There is one primary plane per CRTC */
4410 primary_planes = dm->dc->caps.max_streams;
4411 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4414 * Initialize primary planes, implicit planes for legacy IOCTLS.
4415 * Order is reversed to match iteration order in atomic check.
4417 for (i = (primary_planes - 1); i >= 0; i--) {
4418 plane = &dm->dc->caps.planes[i];
4420 if (initialize_plane(dm, mode_info, i,
4421 DRM_PLANE_TYPE_PRIMARY, plane)) {
4422 DRM_ERROR("KMS: Failed to initialize primary plane\n");
4428 * Initialize overlay planes, index starting after primary planes.
4429 * These planes have a higher DRM index than the primary planes since
4430 * they should be considered as having a higher z-order.
4431 * Order is reversed to match iteration order in atomic check.
4433 * Only support DCN for now, and only expose one so we don't encourage
4434 * userspace to use up all the pipes.
4436 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4437 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4439 /* Do not create overlay if MPO disabled */
4440 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4443 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4446 if (!plane->pixel_format_support.argb8888)
4449 if (max_overlay-- == 0)
4452 if (initialize_plane(dm, NULL, primary_planes + i,
4453 DRM_PLANE_TYPE_OVERLAY, plane)) {
4454 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4459 for (i = 0; i < dm->dc->caps.max_streams; i++)
4460 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4461 DRM_ERROR("KMS: Failed to initialize crtc\n");
4465 /* Use Outbox interrupt */
4466 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4467 case IP_VERSION(3, 0, 0):
4468 case IP_VERSION(3, 1, 2):
4469 case IP_VERSION(3, 1, 3):
4470 case IP_VERSION(3, 1, 4):
4471 case IP_VERSION(3, 1, 5):
4472 case IP_VERSION(3, 1, 6):
4473 case IP_VERSION(3, 2, 0):
4474 case IP_VERSION(3, 2, 1):
4475 case IP_VERSION(2, 1, 0):
4476 case IP_VERSION(3, 5, 0):
4477 if (register_outbox_irq_handlers(dm->adev)) {
4478 DRM_ERROR("DM: Failed to initialize IRQ\n");
4483 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4484 amdgpu_ip_version(adev, DCE_HWIP, 0));
4487 /* Determine whether to enable PSR support by default. */
4488 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4489 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4490 case IP_VERSION(3, 1, 2):
4491 case IP_VERSION(3, 1, 3):
4492 case IP_VERSION(3, 1, 4):
4493 case IP_VERSION(3, 1, 5):
4494 case IP_VERSION(3, 1, 6):
4495 case IP_VERSION(3, 2, 0):
4496 case IP_VERSION(3, 2, 1):
4497 case IP_VERSION(3, 5, 0):
4498 psr_feature_enabled = true;
4501 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4506 /* loops over all connectors on the board */
4507 for (i = 0; i < link_cnt; i++) {
4508 struct dc_link *link = NULL;
4510 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4512 "KMS: Cannot support more than %d display indexes\n",
4513 AMDGPU_DM_MAX_DISPLAY_INDEX);
4517 link = dc_get_link_at_index(dm->dc, i);
4519 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) {
4520 struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);
4523 DRM_ERROR("KMS: Failed to allocate writeback connector\n");
4527 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) {
4528 DRM_ERROR("KMS: Failed to initialize writeback connector\n");
4533 link->psr_settings.psr_feature_enabled = false;
4534 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
4539 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4543 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4547 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4548 DRM_ERROR("KMS: Failed to initialize encoder\n");
4552 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4553 DRM_ERROR("KMS: Failed to initialize connector\n");
4557 if (!dc_link_detect_connection_type(link, &new_connection_type))
4558 DRM_ERROR("KMS: Failed to detect connector\n");
4560 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4561 emulated_link_detect(link);
4562 amdgpu_dm_update_connector_after_detect(aconnector);
4566 mutex_lock(&dm->dc_lock);
4567 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4568 mutex_unlock(&dm->dc_lock);
4571 amdgpu_dm_update_connector_after_detect(aconnector);
4572 setup_backlight_device(dm, aconnector);
4574 if (psr_feature_enabled)
4575 amdgpu_dm_set_psr_caps(link);
4577 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4578 * PSR is also supported.
4580 if (link->psr_settings.psr_feature_enabled)
4581 adev_to_drm(adev)->vblank_disable_immediate = false;
4584 amdgpu_set_panel_orientation(&aconnector->base);
4587 /* Software is initialized. Now we can register interrupt handlers. */
4588 switch (adev->asic_type) {
4589 #if defined(CONFIG_DRM_AMD_DC_SI)
4594 if (dce60_register_irq_handlers(dm->adev)) {
4595 DRM_ERROR("DM: Failed to initialize IRQ\n");
4609 case CHIP_POLARIS11:
4610 case CHIP_POLARIS10:
4611 case CHIP_POLARIS12:
4616 if (dce110_register_irq_handlers(dm->adev)) {
4617 DRM_ERROR("DM: Failed to initialize IRQ\n");
4622 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4623 case IP_VERSION(1, 0, 0):
4624 case IP_VERSION(1, 0, 1):
4625 case IP_VERSION(2, 0, 2):
4626 case IP_VERSION(2, 0, 3):
4627 case IP_VERSION(2, 0, 0):
4628 case IP_VERSION(2, 1, 0):
4629 case IP_VERSION(3, 0, 0):
4630 case IP_VERSION(3, 0, 2):
4631 case IP_VERSION(3, 0, 3):
4632 case IP_VERSION(3, 0, 1):
4633 case IP_VERSION(3, 1, 2):
4634 case IP_VERSION(3, 1, 3):
4635 case IP_VERSION(3, 1, 4):
4636 case IP_VERSION(3, 1, 5):
4637 case IP_VERSION(3, 1, 6):
4638 case IP_VERSION(3, 2, 0):
4639 case IP_VERSION(3, 2, 1):
4640 case IP_VERSION(3, 5, 0):
4641 if (dcn10_register_irq_handlers(dm->adev)) {
4642 DRM_ERROR("DM: Failed to initialize IRQ\n");
4647 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4648 amdgpu_ip_version(adev, DCE_HWIP, 0));
4662 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4664 drm_atomic_private_obj_fini(&dm->atomic_obj);
4667 /******************************************************************************
4668 * amdgpu_display_funcs functions
4669 *****************************************************************************/
4672 * dm_bandwidth_update - program display watermarks
4674 * @adev: amdgpu_device pointer
4676 * Calculate and program the display watermarks and line buffer allocation.
4678 static void dm_bandwidth_update(struct amdgpu_device *adev)
4680 /* TODO: implement later */
4683 static const struct amdgpu_display_funcs dm_display_funcs = {
4684 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4685 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4686 .backlight_set_level = NULL, /* never called for DC */
4687 .backlight_get_level = NULL, /* never called for DC */
4688 .hpd_sense = NULL,/* called unconditionally */
4689 .hpd_set_polarity = NULL, /* called unconditionally */
4690 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4691 .page_flip_get_scanoutpos =
4692 dm_crtc_get_scanoutpos,/* called unconditionally */
4693 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4694 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4697 #if defined(CONFIG_DEBUG_KERNEL_DC)
4699 static ssize_t s3_debug_store(struct device *device,
4700 struct device_attribute *attr,
4706 struct drm_device *drm_dev = dev_get_drvdata(device);
4707 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4709 ret = kstrtoint(buf, 0, &s3_state);
4714 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4719 return ret == 0 ? count : 0;
4722 DEVICE_ATTR_WO(s3_debug);
4726 static int dm_init_microcode(struct amdgpu_device *adev)
4731 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4732 case IP_VERSION(2, 1, 0):
4733 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4734 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4735 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4737 case IP_VERSION(3, 0, 0):
4738 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4739 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4741 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4743 case IP_VERSION(3, 0, 1):
4744 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4746 case IP_VERSION(3, 0, 2):
4747 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4749 case IP_VERSION(3, 0, 3):
4750 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4752 case IP_VERSION(3, 1, 2):
4753 case IP_VERSION(3, 1, 3):
4754 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4756 case IP_VERSION(3, 1, 4):
4757 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4759 case IP_VERSION(3, 1, 5):
4760 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4762 case IP_VERSION(3, 1, 6):
4763 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4765 case IP_VERSION(3, 2, 0):
4766 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4768 case IP_VERSION(3, 2, 1):
4769 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4771 case IP_VERSION(3, 5, 0):
4772 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4775 /* ASIC doesn't support DMUB. */
4778 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4782 static int dm_early_init(void *handle)
4784 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4785 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4786 struct atom_context *ctx = mode_info->atom_context;
4787 int index = GetIndexIntoMasterTable(DATA, Object_Header);
4790 /* if there is no object header, skip DM */
4791 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4792 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4793 dev_info(adev->dev, "No object header, skipping DM\n");
4797 switch (adev->asic_type) {
4798 #if defined(CONFIG_DRM_AMD_DC_SI)
4802 adev->mode_info.num_crtc = 6;
4803 adev->mode_info.num_hpd = 6;
4804 adev->mode_info.num_dig = 6;
4807 adev->mode_info.num_crtc = 2;
4808 adev->mode_info.num_hpd = 2;
4809 adev->mode_info.num_dig = 2;
4814 adev->mode_info.num_crtc = 6;
4815 adev->mode_info.num_hpd = 6;
4816 adev->mode_info.num_dig = 6;
4819 adev->mode_info.num_crtc = 4;
4820 adev->mode_info.num_hpd = 6;
4821 adev->mode_info.num_dig = 7;
4825 adev->mode_info.num_crtc = 2;
4826 adev->mode_info.num_hpd = 6;
4827 adev->mode_info.num_dig = 6;
4831 adev->mode_info.num_crtc = 6;
4832 adev->mode_info.num_hpd = 6;
4833 adev->mode_info.num_dig = 7;
4836 adev->mode_info.num_crtc = 3;
4837 adev->mode_info.num_hpd = 6;
4838 adev->mode_info.num_dig = 9;
4841 adev->mode_info.num_crtc = 2;
4842 adev->mode_info.num_hpd = 6;
4843 adev->mode_info.num_dig = 9;
4845 case CHIP_POLARIS11:
4846 case CHIP_POLARIS12:
4847 adev->mode_info.num_crtc = 5;
4848 adev->mode_info.num_hpd = 5;
4849 adev->mode_info.num_dig = 5;
4851 case CHIP_POLARIS10:
4853 adev->mode_info.num_crtc = 6;
4854 adev->mode_info.num_hpd = 6;
4855 adev->mode_info.num_dig = 6;
4860 adev->mode_info.num_crtc = 6;
4861 adev->mode_info.num_hpd = 6;
4862 adev->mode_info.num_dig = 6;
4866 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4867 case IP_VERSION(2, 0, 2):
4868 case IP_VERSION(3, 0, 0):
4869 adev->mode_info.num_crtc = 6;
4870 adev->mode_info.num_hpd = 6;
4871 adev->mode_info.num_dig = 6;
4873 case IP_VERSION(2, 0, 0):
4874 case IP_VERSION(3, 0, 2):
4875 adev->mode_info.num_crtc = 5;
4876 adev->mode_info.num_hpd = 5;
4877 adev->mode_info.num_dig = 5;
4879 case IP_VERSION(2, 0, 3):
4880 case IP_VERSION(3, 0, 3):
4881 adev->mode_info.num_crtc = 2;
4882 adev->mode_info.num_hpd = 2;
4883 adev->mode_info.num_dig = 2;
4885 case IP_VERSION(1, 0, 0):
4886 case IP_VERSION(1, 0, 1):
4887 case IP_VERSION(3, 0, 1):
4888 case IP_VERSION(2, 1, 0):
4889 case IP_VERSION(3, 1, 2):
4890 case IP_VERSION(3, 1, 3):
4891 case IP_VERSION(3, 1, 4):
4892 case IP_VERSION(3, 1, 5):
4893 case IP_VERSION(3, 1, 6):
4894 case IP_VERSION(3, 2, 0):
4895 case IP_VERSION(3, 2, 1):
4896 case IP_VERSION(3, 5, 0):
4897 adev->mode_info.num_crtc = 4;
4898 adev->mode_info.num_hpd = 4;
4899 adev->mode_info.num_dig = 4;
4902 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4903 amdgpu_ip_version(adev, DCE_HWIP, 0));
4909 if (adev->mode_info.funcs == NULL)
4910 adev->mode_info.funcs = &dm_display_funcs;
4913 * Note: Do NOT change adev->audio_endpt_rreg and
4914 * adev->audio_endpt_wreg because they are initialised in
4915 * amdgpu_device_init()
4917 #if defined(CONFIG_DEBUG_KERNEL_DC)
4919 adev_to_drm(adev)->dev,
4920 &dev_attr_s3_debug);
4922 adev->dc_enabled = true;
4924 return dm_init_microcode(adev);
4927 static bool modereset_required(struct drm_crtc_state *crtc_state)
4929 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4932 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4934 drm_encoder_cleanup(encoder);
4938 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4939 .destroy = amdgpu_dm_encoder_destroy,
4943 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4944 const enum surface_pixel_format format,
4945 enum dc_color_space *color_space)
4949 *color_space = COLOR_SPACE_SRGB;
4951 /* DRM color properties only affect non-RGB formats. */
4952 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4955 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4957 switch (plane_state->color_encoding) {
4958 case DRM_COLOR_YCBCR_BT601:
4960 *color_space = COLOR_SPACE_YCBCR601;
4962 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4965 case DRM_COLOR_YCBCR_BT709:
4967 *color_space = COLOR_SPACE_YCBCR709;
4969 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4972 case DRM_COLOR_YCBCR_BT2020:
4974 *color_space = COLOR_SPACE_2020_YCBCR;
4987 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4988 const struct drm_plane_state *plane_state,
4989 const u64 tiling_flags,
4990 struct dc_plane_info *plane_info,
4991 struct dc_plane_address *address,
4993 bool force_disable_dcc)
4995 const struct drm_framebuffer *fb = plane_state->fb;
4996 const struct amdgpu_framebuffer *afb =
4997 to_amdgpu_framebuffer(plane_state->fb);
5000 memset(plane_info, 0, sizeof(*plane_info));
5002 switch (fb->format->format) {
5004 plane_info->format =
5005 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
5007 case DRM_FORMAT_RGB565:
5008 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
5010 case DRM_FORMAT_XRGB8888:
5011 case DRM_FORMAT_ARGB8888:
5012 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
5014 case DRM_FORMAT_XRGB2101010:
5015 case DRM_FORMAT_ARGB2101010:
5016 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
5018 case DRM_FORMAT_XBGR2101010:
5019 case DRM_FORMAT_ABGR2101010:
5020 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
5022 case DRM_FORMAT_XBGR8888:
5023 case DRM_FORMAT_ABGR8888:
5024 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
5026 case DRM_FORMAT_NV21:
5027 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
5029 case DRM_FORMAT_NV12:
5030 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
5032 case DRM_FORMAT_P010:
5033 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
5035 case DRM_FORMAT_XRGB16161616F:
5036 case DRM_FORMAT_ARGB16161616F:
5037 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
5039 case DRM_FORMAT_XBGR16161616F:
5040 case DRM_FORMAT_ABGR16161616F:
5041 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
5043 case DRM_FORMAT_XRGB16161616:
5044 case DRM_FORMAT_ARGB16161616:
5045 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5047 case DRM_FORMAT_XBGR16161616:
5048 case DRM_FORMAT_ABGR16161616:
5049 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5053 "Unsupported screen format %p4cc\n",
5054 &fb->format->format);
5058 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5059 case DRM_MODE_ROTATE_0:
5060 plane_info->rotation = ROTATION_ANGLE_0;
5062 case DRM_MODE_ROTATE_90:
5063 plane_info->rotation = ROTATION_ANGLE_90;
5065 case DRM_MODE_ROTATE_180:
5066 plane_info->rotation = ROTATION_ANGLE_180;
5068 case DRM_MODE_ROTATE_270:
5069 plane_info->rotation = ROTATION_ANGLE_270;
5072 plane_info->rotation = ROTATION_ANGLE_0;
5077 plane_info->visible = true;
5078 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5080 plane_info->layer_index = plane_state->normalized_zpos;
5082 ret = fill_plane_color_attributes(plane_state, plane_info->format,
5083 &plane_info->color_space);
5087 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5088 plane_info->rotation, tiling_flags,
5089 &plane_info->tiling_info,
5090 &plane_info->plane_size,
5091 &plane_info->dcc, address,
5092 tmz_surface, force_disable_dcc);
5096 amdgpu_dm_plane_fill_blending_from_plane_state(
5097 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5098 &plane_info->global_alpha, &plane_info->global_alpha_value);
5103 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5104 struct dc_plane_state *dc_plane_state,
5105 struct drm_plane_state *plane_state,
5106 struct drm_crtc_state *crtc_state)
5108 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5109 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5110 struct dc_scaling_info scaling_info;
5111 struct dc_plane_info plane_info;
5113 bool force_disable_dcc = false;
5115 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5119 dc_plane_state->src_rect = scaling_info.src_rect;
5120 dc_plane_state->dst_rect = scaling_info.dst_rect;
5121 dc_plane_state->clip_rect = scaling_info.clip_rect;
5122 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5124 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5125 ret = fill_dc_plane_info_and_addr(adev, plane_state,
5128 &dc_plane_state->address,
5134 dc_plane_state->format = plane_info.format;
5135 dc_plane_state->color_space = plane_info.color_space;
5136 dc_plane_state->format = plane_info.format;
5137 dc_plane_state->plane_size = plane_info.plane_size;
5138 dc_plane_state->rotation = plane_info.rotation;
5139 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5140 dc_plane_state->stereo_format = plane_info.stereo_format;
5141 dc_plane_state->tiling_info = plane_info.tiling_info;
5142 dc_plane_state->visible = plane_info.visible;
5143 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5144 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5145 dc_plane_state->global_alpha = plane_info.global_alpha;
5146 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5147 dc_plane_state->dcc = plane_info.dcc;
5148 dc_plane_state->layer_index = plane_info.layer_index;
5149 dc_plane_state->flip_int_enabled = true;
5152 * Always set input transfer function, since plane state is refreshed
5155 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state,
5164 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5165 struct rect *dirty_rect, int32_t x,
5166 s32 y, s32 width, s32 height,
5169 WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5173 dirty_rect->width = width;
5174 dirty_rect->height = height;
5178 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5179 plane->base.id, width, height);
5182 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5183 plane->base.id, x, y, width, height);
5189 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5191 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5193 * @old_plane_state: Old state of @plane
5194 * @new_plane_state: New state of @plane
5195 * @crtc_state: New state of CRTC connected to the @plane
5196 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5197 * @dirty_regions_changed: dirty regions changed
5199 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5200 * (referred to as "damage clips" in DRM nomenclature) that require updating on
5201 * the eDP remote buffer. The responsibility of specifying the dirty regions is
5204 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5205 * plane with regions that require flushing to the eDP remote buffer. In
5206 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5207 * implicitly provide damage clips without any client support via the plane
5210 static void fill_dc_dirty_rects(struct drm_plane *plane,
5211 struct drm_plane_state *old_plane_state,
5212 struct drm_plane_state *new_plane_state,
5213 struct drm_crtc_state *crtc_state,
5214 struct dc_flip_addrs *flip_addrs,
5215 bool *dirty_regions_changed)
5217 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5218 struct rect *dirty_rects = flip_addrs->dirty_rects;
5220 struct drm_mode_rect *clips;
5224 *dirty_regions_changed = false;
5227 * Cursor plane has it's own dirty rect update interface. See
5228 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5230 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5233 if (new_plane_state->rotation != DRM_MODE_ROTATE_0)
5236 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5237 clips = drm_plane_get_damage_clips(new_plane_state);
5239 if (!dm_crtc_state->mpo_requested) {
5240 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5243 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5244 fill_dc_dirty_rect(new_plane_state->plane,
5245 &dirty_rects[flip_addrs->dirty_rect_count],
5246 clips->x1, clips->y1,
5247 clips->x2 - clips->x1, clips->y2 - clips->y1,
5248 &flip_addrs->dirty_rect_count,
5254 * MPO is requested. Add entire plane bounding box to dirty rects if
5255 * flipped to or damaged.
5257 * If plane is moved or resized, also add old bounding box to dirty
5260 fb_changed = old_plane_state->fb->base.id !=
5261 new_plane_state->fb->base.id;
5262 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5263 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5264 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5265 old_plane_state->crtc_h != new_plane_state->crtc_h);
5268 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5269 new_plane_state->plane->base.id,
5270 bb_changed, fb_changed, num_clips);
5272 *dirty_regions_changed = bb_changed;
5274 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5278 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5279 new_plane_state->crtc_x,
5280 new_plane_state->crtc_y,
5281 new_plane_state->crtc_w,
5282 new_plane_state->crtc_h, &i, false);
5284 /* Add old plane bounding-box if plane is moved or resized */
5285 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5286 old_plane_state->crtc_x,
5287 old_plane_state->crtc_y,
5288 old_plane_state->crtc_w,
5289 old_plane_state->crtc_h, &i, false);
5293 for (; i < num_clips; clips++)
5294 fill_dc_dirty_rect(new_plane_state->plane,
5295 &dirty_rects[i], clips->x1,
5296 clips->y1, clips->x2 - clips->x1,
5297 clips->y2 - clips->y1, &i, false);
5298 } else if (fb_changed && !bb_changed) {
5299 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5300 new_plane_state->crtc_x,
5301 new_plane_state->crtc_y,
5302 new_plane_state->crtc_w,
5303 new_plane_state->crtc_h, &i, false);
5306 flip_addrs->dirty_rect_count = i;
5310 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5311 dm_crtc_state->base.mode.crtc_hdisplay,
5312 dm_crtc_state->base.mode.crtc_vdisplay,
5313 &flip_addrs->dirty_rect_count, true);
5316 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5317 const struct dm_connector_state *dm_state,
5318 struct dc_stream_state *stream)
5320 enum amdgpu_rmx_type rmx_type;
5322 struct rect src = { 0 }; /* viewport in composition space*/
5323 struct rect dst = { 0 }; /* stream addressable area */
5325 /* no mode. nothing to be done */
5329 /* Full screen scaling by default */
5330 src.width = mode->hdisplay;
5331 src.height = mode->vdisplay;
5332 dst.width = stream->timing.h_addressable;
5333 dst.height = stream->timing.v_addressable;
5336 rmx_type = dm_state->scaling;
5337 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5338 if (src.width * dst.height <
5339 src.height * dst.width) {
5340 /* height needs less upscaling/more downscaling */
5341 dst.width = src.width *
5342 dst.height / src.height;
5344 /* width needs less upscaling/more downscaling */
5345 dst.height = src.height *
5346 dst.width / src.width;
5348 } else if (rmx_type == RMX_CENTER) {
5352 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5353 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5355 if (dm_state->underscan_enable) {
5356 dst.x += dm_state->underscan_hborder / 2;
5357 dst.y += dm_state->underscan_vborder / 2;
5358 dst.width -= dm_state->underscan_hborder;
5359 dst.height -= dm_state->underscan_vborder;
5366 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5367 dst.x, dst.y, dst.width, dst.height);
5371 static enum dc_color_depth
5372 convert_color_depth_from_display_info(const struct drm_connector *connector,
5373 bool is_y420, int requested_bpc)
5380 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5381 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5383 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5385 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5388 bpc = (uint8_t)connector->display_info.bpc;
5389 /* Assume 8 bpc by default if no bpc is specified. */
5390 bpc = bpc ? bpc : 8;
5393 if (requested_bpc > 0) {
5395 * Cap display bpc based on the user requested value.
5397 * The value for state->max_bpc may not correctly updated
5398 * depending on when the connector gets added to the state
5399 * or if this was called outside of atomic check, so it
5400 * can't be used directly.
5402 bpc = min_t(u8, bpc, requested_bpc);
5404 /* Round down to the nearest even number. */
5405 bpc = bpc - (bpc & 1);
5411 * Temporary Work around, DRM doesn't parse color depth for
5412 * EDID revision before 1.4
5413 * TODO: Fix edid parsing
5415 return COLOR_DEPTH_888;
5417 return COLOR_DEPTH_666;
5419 return COLOR_DEPTH_888;
5421 return COLOR_DEPTH_101010;
5423 return COLOR_DEPTH_121212;
5425 return COLOR_DEPTH_141414;
5427 return COLOR_DEPTH_161616;
5429 return COLOR_DEPTH_UNDEFINED;
5433 static enum dc_aspect_ratio
5434 get_aspect_ratio(const struct drm_display_mode *mode_in)
5436 /* 1-1 mapping, since both enums follow the HDMI spec. */
5437 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5440 static enum dc_color_space
5441 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5442 const struct drm_connector_state *connector_state)
5444 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5446 switch (connector_state->colorspace) {
5447 case DRM_MODE_COLORIMETRY_BT601_YCC:
5448 if (dc_crtc_timing->flags.Y_ONLY)
5449 color_space = COLOR_SPACE_YCBCR601_LIMITED;
5451 color_space = COLOR_SPACE_YCBCR601;
5453 case DRM_MODE_COLORIMETRY_BT709_YCC:
5454 if (dc_crtc_timing->flags.Y_ONLY)
5455 color_space = COLOR_SPACE_YCBCR709_LIMITED;
5457 color_space = COLOR_SPACE_YCBCR709;
5459 case DRM_MODE_COLORIMETRY_OPRGB:
5460 color_space = COLOR_SPACE_ADOBERGB;
5462 case DRM_MODE_COLORIMETRY_BT2020_RGB:
5463 case DRM_MODE_COLORIMETRY_BT2020_YCC:
5464 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5465 color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5467 color_space = COLOR_SPACE_2020_YCBCR;
5469 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5471 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5472 color_space = COLOR_SPACE_SRGB;
5474 * 27030khz is the separation point between HDTV and SDTV
5475 * according to HDMI spec, we use YCbCr709 and YCbCr601
5478 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5479 if (dc_crtc_timing->flags.Y_ONLY)
5481 COLOR_SPACE_YCBCR709_LIMITED;
5483 color_space = COLOR_SPACE_YCBCR709;
5485 if (dc_crtc_timing->flags.Y_ONLY)
5487 COLOR_SPACE_YCBCR601_LIMITED;
5489 color_space = COLOR_SPACE_YCBCR601;
5497 static enum display_content_type
5498 get_output_content_type(const struct drm_connector_state *connector_state)
5500 switch (connector_state->content_type) {
5502 case DRM_MODE_CONTENT_TYPE_NO_DATA:
5503 return DISPLAY_CONTENT_TYPE_NO_DATA;
5504 case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5505 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5506 case DRM_MODE_CONTENT_TYPE_PHOTO:
5507 return DISPLAY_CONTENT_TYPE_PHOTO;
5508 case DRM_MODE_CONTENT_TYPE_CINEMA:
5509 return DISPLAY_CONTENT_TYPE_CINEMA;
5510 case DRM_MODE_CONTENT_TYPE_GAME:
5511 return DISPLAY_CONTENT_TYPE_GAME;
5515 static bool adjust_colour_depth_from_display_info(
5516 struct dc_crtc_timing *timing_out,
5517 const struct drm_display_info *info)
5519 enum dc_color_depth depth = timing_out->display_color_depth;
5523 normalized_clk = timing_out->pix_clk_100hz / 10;
5524 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5525 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5526 normalized_clk /= 2;
5527 /* Adjusting pix clock following on HDMI spec based on colour depth */
5529 case COLOR_DEPTH_888:
5531 case COLOR_DEPTH_101010:
5532 normalized_clk = (normalized_clk * 30) / 24;
5534 case COLOR_DEPTH_121212:
5535 normalized_clk = (normalized_clk * 36) / 24;
5537 case COLOR_DEPTH_161616:
5538 normalized_clk = (normalized_clk * 48) / 24;
5541 /* The above depths are the only ones valid for HDMI. */
5544 if (normalized_clk <= info->max_tmds_clock) {
5545 timing_out->display_color_depth = depth;
5548 } while (--depth > COLOR_DEPTH_666);
5552 static void fill_stream_properties_from_drm_display_mode(
5553 struct dc_stream_state *stream,
5554 const struct drm_display_mode *mode_in,
5555 const struct drm_connector *connector,
5556 const struct drm_connector_state *connector_state,
5557 const struct dc_stream_state *old_stream,
5560 struct dc_crtc_timing *timing_out = &stream->timing;
5561 const struct drm_display_info *info = &connector->display_info;
5562 struct amdgpu_dm_connector *aconnector = NULL;
5563 struct hdmi_vendor_infoframe hv_frame;
5564 struct hdmi_avi_infoframe avi_frame;
5566 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
5567 aconnector = to_amdgpu_dm_connector(connector);
5569 memset(&hv_frame, 0, sizeof(hv_frame));
5570 memset(&avi_frame, 0, sizeof(avi_frame));
5572 timing_out->h_border_left = 0;
5573 timing_out->h_border_right = 0;
5574 timing_out->v_border_top = 0;
5575 timing_out->v_border_bottom = 0;
5576 /* TODO: un-hardcode */
5577 if (drm_mode_is_420_only(info, mode_in)
5578 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5579 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5580 else if (drm_mode_is_420_also(info, mode_in)
5582 && aconnector->force_yuv420_output)
5583 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5584 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5585 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5586 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5588 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5590 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5591 timing_out->display_color_depth = convert_color_depth_from_display_info(
5593 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5595 timing_out->scan_type = SCANNING_TYPE_NODATA;
5596 timing_out->hdmi_vic = 0;
5599 timing_out->vic = old_stream->timing.vic;
5600 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5601 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5603 timing_out->vic = drm_match_cea_mode(mode_in);
5604 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5605 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5606 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5607 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5610 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5611 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5612 timing_out->vic = avi_frame.video_code;
5613 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5614 timing_out->hdmi_vic = hv_frame.vic;
5617 if (aconnector && is_freesync_video_mode(mode_in, aconnector)) {
5618 timing_out->h_addressable = mode_in->hdisplay;
5619 timing_out->h_total = mode_in->htotal;
5620 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5621 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5622 timing_out->v_total = mode_in->vtotal;
5623 timing_out->v_addressable = mode_in->vdisplay;
5624 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5625 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5626 timing_out->pix_clk_100hz = mode_in->clock * 10;
5628 timing_out->h_addressable = mode_in->crtc_hdisplay;
5629 timing_out->h_total = mode_in->crtc_htotal;
5630 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5631 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5632 timing_out->v_total = mode_in->crtc_vtotal;
5633 timing_out->v_addressable = mode_in->crtc_vdisplay;
5634 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5635 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5636 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5639 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5641 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5642 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5643 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5644 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5645 drm_mode_is_420_also(info, mode_in) &&
5646 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5647 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5648 adjust_colour_depth_from_display_info(timing_out, info);
5652 stream->output_color_space = get_output_color_space(timing_out, connector_state);
5653 stream->content_type = get_output_content_type(connector_state);
5656 static void fill_audio_info(struct audio_info *audio_info,
5657 const struct drm_connector *drm_connector,
5658 const struct dc_sink *dc_sink)
5661 int cea_revision = 0;
5662 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5664 audio_info->manufacture_id = edid_caps->manufacturer_id;
5665 audio_info->product_id = edid_caps->product_id;
5667 cea_revision = drm_connector->display_info.cea_rev;
5669 strscpy(audio_info->display_name,
5670 edid_caps->display_name,
5671 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5673 if (cea_revision >= 3) {
5674 audio_info->mode_count = edid_caps->audio_mode_count;
5676 for (i = 0; i < audio_info->mode_count; ++i) {
5677 audio_info->modes[i].format_code =
5678 (enum audio_format_code)
5679 (edid_caps->audio_modes[i].format_code);
5680 audio_info->modes[i].channel_count =
5681 edid_caps->audio_modes[i].channel_count;
5682 audio_info->modes[i].sample_rates.all =
5683 edid_caps->audio_modes[i].sample_rate;
5684 audio_info->modes[i].sample_size =
5685 edid_caps->audio_modes[i].sample_size;
5689 audio_info->flags.all = edid_caps->speaker_flags;
5691 /* TODO: We only check for the progressive mode, check for interlace mode too */
5692 if (drm_connector->latency_present[0]) {
5693 audio_info->video_latency = drm_connector->video_latency[0];
5694 audio_info->audio_latency = drm_connector->audio_latency[0];
5697 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5702 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5703 struct drm_display_mode *dst_mode)
5705 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5706 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5707 dst_mode->crtc_clock = src_mode->crtc_clock;
5708 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5709 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5710 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5711 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5712 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5713 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5714 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5715 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5716 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5717 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5718 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5722 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5723 const struct drm_display_mode *native_mode,
5726 if (scale_enabled) {
5727 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5728 } else if (native_mode->clock == drm_mode->clock &&
5729 native_mode->htotal == drm_mode->htotal &&
5730 native_mode->vtotal == drm_mode->vtotal) {
5731 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5733 /* no scaling nor amdgpu inserted, no need to patch */
5737 static struct dc_sink *
5738 create_fake_sink(struct dc_link *link)
5740 struct dc_sink_init_data sink_init_data = { 0 };
5741 struct dc_sink *sink = NULL;
5743 sink_init_data.link = link;
5744 sink_init_data.sink_signal = link->connector_signal;
5746 sink = dc_sink_create(&sink_init_data);
5748 DRM_ERROR("Failed to create sink!\n");
5751 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5756 static void set_multisync_trigger_params(
5757 struct dc_stream_state *stream)
5759 struct dc_stream_state *master = NULL;
5761 if (stream->triggered_crtc_reset.enabled) {
5762 master = stream->triggered_crtc_reset.event_source;
5763 stream->triggered_crtc_reset.event =
5764 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5765 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5766 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5770 static void set_master_stream(struct dc_stream_state *stream_set[],
5773 int j, highest_rfr = 0, master_stream = 0;
5775 for (j = 0; j < stream_count; j++) {
5776 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5777 int refresh_rate = 0;
5779 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5780 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5781 if (refresh_rate > highest_rfr) {
5782 highest_rfr = refresh_rate;
5787 for (j = 0; j < stream_count; j++) {
5789 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5793 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5796 struct dc_stream_state *stream;
5798 if (context->stream_count < 2)
5800 for (i = 0; i < context->stream_count ; i++) {
5801 if (!context->streams[i])
5804 * TODO: add a function to read AMD VSDB bits and set
5805 * crtc_sync_master.multi_sync_enabled flag
5806 * For now it's set to false
5810 set_master_stream(context->streams, context->stream_count);
5812 for (i = 0; i < context->stream_count ; i++) {
5813 stream = context->streams[i];
5818 set_multisync_trigger_params(stream);
5823 * DOC: FreeSync Video
5825 * When a userspace application wants to play a video, the content follows a
5826 * standard format definition that usually specifies the FPS for that format.
5827 * The below list illustrates some video format and the expected FPS,
5830 * - TV/NTSC (23.976 FPS)
5833 * - TV/NTSC (29.97 FPS)
5834 * - TV/NTSC (30 FPS)
5835 * - Cinema HFR (48 FPS)
5837 * - Commonly used (60 FPS)
5838 * - Multiples of 24 (48,72,96 FPS)
5840 * The list of standards video format is not huge and can be added to the
5841 * connector modeset list beforehand. With that, userspace can leverage
5842 * FreeSync to extends the front porch in order to attain the target refresh
5843 * rate. Such a switch will happen seamlessly, without screen blanking or
5844 * reprogramming of the output in any other way. If the userspace requests a
5845 * modesetting change compatible with FreeSync modes that only differ in the
5846 * refresh rate, DC will skip the full update and avoid blink during the
5847 * transition. For example, the video player can change the modesetting from
5848 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5849 * causing any display blink. This same concept can be applied to a mode
5852 static struct drm_display_mode *
5853 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5854 bool use_probed_modes)
5856 struct drm_display_mode *m, *m_pref = NULL;
5857 u16 current_refresh, highest_refresh;
5858 struct list_head *list_head = use_probed_modes ?
5859 &aconnector->base.probed_modes :
5860 &aconnector->base.modes;
5862 if (aconnector->freesync_vid_base.clock != 0)
5863 return &aconnector->freesync_vid_base;
5865 /* Find the preferred mode */
5866 list_for_each_entry(m, list_head, head) {
5867 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5874 /* Probably an EDID with no preferred mode. Fallback to first entry */
5875 m_pref = list_first_entry_or_null(
5876 &aconnector->base.modes, struct drm_display_mode, head);
5878 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5883 highest_refresh = drm_mode_vrefresh(m_pref);
5886 * Find the mode with highest refresh rate with same resolution.
5887 * For some monitors, preferred mode is not the mode with highest
5888 * supported refresh rate.
5890 list_for_each_entry(m, list_head, head) {
5891 current_refresh = drm_mode_vrefresh(m);
5893 if (m->hdisplay == m_pref->hdisplay &&
5894 m->vdisplay == m_pref->vdisplay &&
5895 highest_refresh < current_refresh) {
5896 highest_refresh = current_refresh;
5901 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5905 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5906 struct amdgpu_dm_connector *aconnector)
5908 struct drm_display_mode *high_mode;
5911 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5912 if (!high_mode || !mode)
5915 timing_diff = high_mode->vtotal - mode->vtotal;
5917 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5918 high_mode->hdisplay != mode->hdisplay ||
5919 high_mode->vdisplay != mode->vdisplay ||
5920 high_mode->hsync_start != mode->hsync_start ||
5921 high_mode->hsync_end != mode->hsync_end ||
5922 high_mode->htotal != mode->htotal ||
5923 high_mode->hskew != mode->hskew ||
5924 high_mode->vscan != mode->vscan ||
5925 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5926 high_mode->vsync_end - mode->vsync_end != timing_diff)
5932 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5933 struct dc_sink *sink, struct dc_stream_state *stream,
5934 struct dsc_dec_dpcd_caps *dsc_caps)
5936 stream->timing.flags.DSC = 0;
5937 dsc_caps->is_dsc_supported = false;
5939 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5940 sink->sink_signal == SIGNAL_TYPE_EDP)) {
5941 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5942 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5943 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5944 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5945 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5951 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5952 struct dc_sink *sink, struct dc_stream_state *stream,
5953 struct dsc_dec_dpcd_caps *dsc_caps,
5954 uint32_t max_dsc_target_bpp_limit_override)
5956 const struct dc_link_settings *verified_link_cap = NULL;
5957 u32 link_bw_in_kbps;
5958 u32 edp_min_bpp_x16, edp_max_bpp_x16;
5959 struct dc *dc = sink->ctx->dc;
5960 struct dc_dsc_bw_range bw_range = {0};
5961 struct dc_dsc_config dsc_cfg = {0};
5962 struct dc_dsc_config_options dsc_options = {0};
5964 dc_dsc_get_default_config_option(dc, &dsc_options);
5965 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5967 verified_link_cap = dc_link_get_link_cap(stream->link);
5968 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5969 edp_min_bpp_x16 = 8 * 16;
5970 edp_max_bpp_x16 = 8 * 16;
5972 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5973 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5975 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5976 edp_min_bpp_x16 = edp_max_bpp_x16;
5978 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5979 dc->debug.dsc_min_slice_height_override,
5980 edp_min_bpp_x16, edp_max_bpp_x16,
5983 dc_link_get_highest_encoding_format(aconnector->dc_link),
5986 if (bw_range.max_kbps < link_bw_in_kbps) {
5987 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5992 dc_link_get_highest_encoding_format(aconnector->dc_link),
5994 stream->timing.dsc_cfg = dsc_cfg;
5995 stream->timing.flags.DSC = 1;
5996 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
6002 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
6007 dc_link_get_highest_encoding_format(aconnector->dc_link),
6009 stream->timing.dsc_cfg = dsc_cfg;
6010 stream->timing.flags.DSC = 1;
6015 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
6016 struct dc_sink *sink, struct dc_stream_state *stream,
6017 struct dsc_dec_dpcd_caps *dsc_caps)
6019 struct drm_connector *drm_connector = &aconnector->base;
6020 u32 link_bandwidth_kbps;
6021 struct dc *dc = sink->ctx->dc;
6022 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
6023 u32 dsc_max_supported_bw_in_kbps;
6024 u32 max_dsc_target_bpp_limit_override =
6025 drm_connector->display_info.max_dsc_bpp;
6026 struct dc_dsc_config_options dsc_options = {0};
6028 dc_dsc_get_default_config_option(dc, &dsc_options);
6029 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
6031 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
6032 dc_link_get_link_cap(aconnector->dc_link));
6034 /* Set DSC policy according to dsc_clock_en */
6035 dc_dsc_policy_set_enable_dsc_when_not_needed(
6036 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
6038 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
6039 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
6040 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
6042 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
6044 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6045 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
6046 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6049 link_bandwidth_kbps,
6051 dc_link_get_highest_encoding_format(aconnector->dc_link),
6052 &stream->timing.dsc_cfg)) {
6053 stream->timing.flags.DSC = 1;
6054 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
6056 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6057 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6058 dc_link_get_highest_encoding_format(aconnector->dc_link));
6059 max_supported_bw_in_kbps = link_bandwidth_kbps;
6060 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6062 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6063 max_supported_bw_in_kbps > 0 &&
6064 dsc_max_supported_bw_in_kbps > 0)
6065 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6068 dsc_max_supported_bw_in_kbps,
6070 dc_link_get_highest_encoding_format(aconnector->dc_link),
6071 &stream->timing.dsc_cfg)) {
6072 stream->timing.flags.DSC = 1;
6073 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6074 __func__, drm_connector->name);
6079 /* Overwrite the stream flag if DSC is enabled through debugfs */
6080 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6081 stream->timing.flags.DSC = 1;
6083 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6084 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6086 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6087 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6089 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6090 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6093 static struct dc_stream_state *
6094 create_stream_for_sink(struct drm_connector *connector,
6095 const struct drm_display_mode *drm_mode,
6096 const struct dm_connector_state *dm_state,
6097 const struct dc_stream_state *old_stream,
6100 struct amdgpu_dm_connector *aconnector = NULL;
6101 struct drm_display_mode *preferred_mode = NULL;
6102 const struct drm_connector_state *con_state = &dm_state->base;
6103 struct dc_stream_state *stream = NULL;
6104 struct drm_display_mode mode;
6105 struct drm_display_mode saved_mode;
6106 struct drm_display_mode *freesync_mode = NULL;
6107 bool native_mode_found = false;
6108 bool recalculate_timing = false;
6109 bool scale = dm_state->scaling != RMX_OFF;
6111 int preferred_refresh = 0;
6112 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6113 struct dsc_dec_dpcd_caps dsc_caps;
6115 struct dc_link *link = NULL;
6116 struct dc_sink *sink = NULL;
6118 drm_mode_init(&mode, drm_mode);
6119 memset(&saved_mode, 0, sizeof(saved_mode));
6121 if (connector == NULL) {
6122 DRM_ERROR("connector is NULL!\n");
6126 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) {
6128 aconnector = to_amdgpu_dm_connector(connector);
6129 link = aconnector->dc_link;
6131 struct drm_writeback_connector *wbcon = NULL;
6132 struct amdgpu_dm_wb_connector *dm_wbcon = NULL;
6134 wbcon = drm_connector_to_writeback(connector);
6135 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon);
6136 link = dm_wbcon->link;
6139 if (!aconnector || !aconnector->dc_sink) {
6140 sink = create_fake_sink(link);
6145 sink = aconnector->dc_sink;
6146 dc_sink_retain(sink);
6149 stream = dc_create_stream_for_sink(sink);
6151 if (stream == NULL) {
6152 DRM_ERROR("Failed to create stream for sink!\n");
6156 /* We leave this NULL for writeback connectors */
6157 stream->dm_stream_context = aconnector;
6159 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6160 connector->display_info.hdmi.scdc.scrambling.low_rates;
6162 list_for_each_entry(preferred_mode, &connector->modes, head) {
6163 /* Search for preferred mode */
6164 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6165 native_mode_found = true;
6169 if (!native_mode_found)
6170 preferred_mode = list_first_entry_or_null(
6172 struct drm_display_mode,
6175 mode_refresh = drm_mode_vrefresh(&mode);
6177 if (preferred_mode == NULL) {
6179 * This may not be an error, the use case is when we have no
6180 * usermode calls to reset and set mode upon hotplug. In this
6181 * case, we call set mode ourselves to restore the previous mode
6182 * and the modelist may not be filled in time.
6184 DRM_DEBUG_DRIVER("No preferred mode found\n");
6185 } else if (aconnector) {
6186 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6187 if (recalculate_timing) {
6188 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6189 drm_mode_copy(&saved_mode, &mode);
6190 drm_mode_copy(&mode, freesync_mode);
6192 decide_crtc_timing_for_drm_display_mode(
6193 &mode, preferred_mode, scale);
6195 preferred_refresh = drm_mode_vrefresh(preferred_mode);
6199 if (recalculate_timing)
6200 drm_mode_set_crtcinfo(&saved_mode, 0);
6203 * If scaling is enabled and refresh rate didn't change
6204 * we copy the vic and polarities of the old timings
6206 if (!scale || mode_refresh != preferred_refresh)
6207 fill_stream_properties_from_drm_display_mode(
6208 stream, &mode, connector, con_state, NULL,
6211 fill_stream_properties_from_drm_display_mode(
6212 stream, &mode, connector, con_state, old_stream,
6215 /* The rest isn't needed for writeback connectors */
6219 if (aconnector->timing_changed) {
6220 drm_dbg(aconnector->base.dev,
6221 "overriding timing for automated test, bpc %d, changing to %d\n",
6222 stream->timing.display_color_depth,
6223 aconnector->timing_requested->display_color_depth);
6224 stream->timing = *aconnector->timing_requested;
6227 /* SST DSC determination policy */
6228 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6229 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6230 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6232 update_stream_scaling_settings(&mode, dm_state, stream);
6235 &stream->audio_info,
6239 update_stream_signal(stream, sink);
6241 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6242 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6243 else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
6244 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
6245 stream->signal == SIGNAL_TYPE_EDP) {
6247 // should decide stream support vsc sdp colorimetry capability
6248 // before building vsc info packet
6250 stream->use_vsc_sdp_for_colorimetry = false;
6251 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6252 stream->use_vsc_sdp_for_colorimetry =
6253 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6255 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6256 stream->use_vsc_sdp_for_colorimetry = true;
6258 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6259 tf = TRANSFER_FUNC_GAMMA_22;
6260 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6262 if (stream->link->psr_settings.psr_feature_enabled)
6263 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6266 dc_sink_release(sink);
6271 static enum drm_connector_status
6272 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6275 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6279 * 1. This interface is NOT called in context of HPD irq.
6280 * 2. This interface *is called* in context of user-mode ioctl. Which
6281 * makes it a bad place for *any* MST-related activity.
6284 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6285 !aconnector->fake_enable)
6286 connected = (aconnector->dc_sink != NULL);
6288 connected = (aconnector->base.force == DRM_FORCE_ON ||
6289 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6291 update_subconnector_property(aconnector);
6293 return (connected ? connector_status_connected :
6294 connector_status_disconnected);
6297 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6298 struct drm_connector_state *connector_state,
6299 struct drm_property *property,
6302 struct drm_device *dev = connector->dev;
6303 struct amdgpu_device *adev = drm_to_adev(dev);
6304 struct dm_connector_state *dm_old_state =
6305 to_dm_connector_state(connector->state);
6306 struct dm_connector_state *dm_new_state =
6307 to_dm_connector_state(connector_state);
6311 if (property == dev->mode_config.scaling_mode_property) {
6312 enum amdgpu_rmx_type rmx_type;
6315 case DRM_MODE_SCALE_CENTER:
6316 rmx_type = RMX_CENTER;
6318 case DRM_MODE_SCALE_ASPECT:
6319 rmx_type = RMX_ASPECT;
6321 case DRM_MODE_SCALE_FULLSCREEN:
6322 rmx_type = RMX_FULL;
6324 case DRM_MODE_SCALE_NONE:
6330 if (dm_old_state->scaling == rmx_type)
6333 dm_new_state->scaling = rmx_type;
6335 } else if (property == adev->mode_info.underscan_hborder_property) {
6336 dm_new_state->underscan_hborder = val;
6338 } else if (property == adev->mode_info.underscan_vborder_property) {
6339 dm_new_state->underscan_vborder = val;
6341 } else if (property == adev->mode_info.underscan_property) {
6342 dm_new_state->underscan_enable = val;
6344 } else if (property == adev->mode_info.abm_level_property) {
6345 dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;
6352 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6353 const struct drm_connector_state *state,
6354 struct drm_property *property,
6357 struct drm_device *dev = connector->dev;
6358 struct amdgpu_device *adev = drm_to_adev(dev);
6359 struct dm_connector_state *dm_state =
6360 to_dm_connector_state(state);
6363 if (property == dev->mode_config.scaling_mode_property) {
6364 switch (dm_state->scaling) {
6366 *val = DRM_MODE_SCALE_CENTER;
6369 *val = DRM_MODE_SCALE_ASPECT;
6372 *val = DRM_MODE_SCALE_FULLSCREEN;
6376 *val = DRM_MODE_SCALE_NONE;
6380 } else if (property == adev->mode_info.underscan_hborder_property) {
6381 *val = dm_state->underscan_hborder;
6383 } else if (property == adev->mode_info.underscan_vborder_property) {
6384 *val = dm_state->underscan_vborder;
6386 } else if (property == adev->mode_info.underscan_property) {
6387 *val = dm_state->underscan_enable;
6389 } else if (property == adev->mode_info.abm_level_property) {
6390 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?
6391 dm_state->abm_level : 0;
6398 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6400 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6402 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6405 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6407 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6408 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6409 struct amdgpu_display_manager *dm = &adev->dm;
6412 * Call only if mst_mgr was initialized before since it's not done
6413 * for all connector types.
6415 if (aconnector->mst_mgr.dev)
6416 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6418 if (aconnector->bl_idx != -1) {
6419 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6420 dm->backlight_dev[aconnector->bl_idx] = NULL;
6423 if (aconnector->dc_em_sink)
6424 dc_sink_release(aconnector->dc_em_sink);
6425 aconnector->dc_em_sink = NULL;
6426 if (aconnector->dc_sink)
6427 dc_sink_release(aconnector->dc_sink);
6428 aconnector->dc_sink = NULL;
6430 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6431 drm_connector_unregister(connector);
6432 drm_connector_cleanup(connector);
6433 if (aconnector->i2c) {
6434 i2c_del_adapter(&aconnector->i2c->base);
6435 kfree(aconnector->i2c);
6437 kfree(aconnector->dm_dp_aux.aux.name);
6442 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6444 struct dm_connector_state *state =
6445 to_dm_connector_state(connector->state);
6447 if (connector->state)
6448 __drm_atomic_helper_connector_destroy_state(connector->state);
6452 state = kzalloc(sizeof(*state), GFP_KERNEL);
6455 state->scaling = RMX_OFF;
6456 state->underscan_enable = false;
6457 state->underscan_hborder = 0;
6458 state->underscan_vborder = 0;
6459 state->base.max_requested_bpc = 8;
6460 state->vcpi_slots = 0;
6463 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6464 state->abm_level = amdgpu_dm_abm_level ?:
6465 ABM_LEVEL_IMMEDIATE_DISABLE;
6467 __drm_atomic_helper_connector_reset(connector, &state->base);
6471 struct drm_connector_state *
6472 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6474 struct dm_connector_state *state =
6475 to_dm_connector_state(connector->state);
6477 struct dm_connector_state *new_state =
6478 kmemdup(state, sizeof(*state), GFP_KERNEL);
6483 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6485 new_state->freesync_capable = state->freesync_capable;
6486 new_state->abm_level = state->abm_level;
6487 new_state->scaling = state->scaling;
6488 new_state->underscan_enable = state->underscan_enable;
6489 new_state->underscan_hborder = state->underscan_hborder;
6490 new_state->underscan_vborder = state->underscan_vborder;
6491 new_state->vcpi_slots = state->vcpi_slots;
6492 new_state->pbn = state->pbn;
6493 return &new_state->base;
6497 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6499 struct amdgpu_dm_connector *amdgpu_dm_connector =
6500 to_amdgpu_dm_connector(connector);
6503 amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6505 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6506 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6507 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6508 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6513 #if defined(CONFIG_DEBUG_FS)
6514 connector_debugfs_init(amdgpu_dm_connector);
6520 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6522 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6523 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6524 struct dc_link *dc_link = aconnector->dc_link;
6525 struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6529 * Note: drm_get_edid gets edid in the following order:
6530 * 1) override EDID if set via edid_override debugfs,
6531 * 2) firmware EDID if set via edid_firmware module parameter
6532 * 3) regular DDC read.
6534 edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6536 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6540 aconnector->edid = edid;
6542 /* Update emulated (virtual) sink's EDID */
6543 if (dc_em_sink && dc_link) {
6544 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6545 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6546 dm_helpers_parse_edid_caps(
6548 &dc_em_sink->dc_edid,
6549 &dc_em_sink->edid_caps);
6553 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6554 .reset = amdgpu_dm_connector_funcs_reset,
6555 .detect = amdgpu_dm_connector_detect,
6556 .fill_modes = drm_helper_probe_single_connector_modes,
6557 .destroy = amdgpu_dm_connector_destroy,
6558 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6559 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6560 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6561 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6562 .late_register = amdgpu_dm_connector_late_register,
6563 .early_unregister = amdgpu_dm_connector_unregister,
6564 .force = amdgpu_dm_connector_funcs_force
6567 static int get_modes(struct drm_connector *connector)
6569 return amdgpu_dm_connector_get_modes(connector);
6572 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6574 struct drm_connector *connector = &aconnector->base;
6575 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base);
6576 struct dc_sink_init_data init_params = {
6577 .link = aconnector->dc_link,
6578 .sink_signal = SIGNAL_TYPE_VIRTUAL
6583 * Note: drm_get_edid gets edid in the following order:
6584 * 1) override EDID if set via edid_override debugfs,
6585 * 2) firmware EDID if set via edid_firmware module parameter
6586 * 3) regular DDC read.
6588 edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6590 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6594 if (drm_detect_hdmi_monitor(edid))
6595 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
6597 aconnector->edid = edid;
6599 aconnector->dc_em_sink = dc_link_add_remote_sink(
6600 aconnector->dc_link,
6602 (edid->extensions + 1) * EDID_LENGTH,
6605 if (aconnector->base.force == DRM_FORCE_ON) {
6606 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6607 aconnector->dc_link->local_sink :
6608 aconnector->dc_em_sink;
6609 dc_sink_retain(aconnector->dc_sink);
6613 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6615 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6618 * In case of headless boot with force on for DP managed connector
6619 * Those settings have to be != 0 to get initial modeset
6621 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6622 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6623 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6626 create_eml_sink(aconnector);
6629 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6630 struct dc_stream_state *stream)
6632 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6633 struct dc_plane_state *dc_plane_state = NULL;
6634 struct dc_state *dc_state = NULL;
6639 dc_plane_state = dc_create_plane_state(dc);
6640 if (!dc_plane_state)
6643 dc_state = dc_state_create(dc);
6647 /* populate stream to plane */
6648 dc_plane_state->src_rect.height = stream->src.height;
6649 dc_plane_state->src_rect.width = stream->src.width;
6650 dc_plane_state->dst_rect.height = stream->src.height;
6651 dc_plane_state->dst_rect.width = stream->src.width;
6652 dc_plane_state->clip_rect.height = stream->src.height;
6653 dc_plane_state->clip_rect.width = stream->src.width;
6654 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6655 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6656 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6657 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6658 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6659 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6660 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6661 dc_plane_state->rotation = ROTATION_ANGLE_0;
6662 dc_plane_state->is_tiling_rotated = false;
6663 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6665 dc_result = dc_validate_stream(dc, stream);
6666 if (dc_result == DC_OK)
6667 dc_result = dc_validate_plane(dc, dc_plane_state);
6669 if (dc_result == DC_OK)
6670 dc_result = dc_state_add_stream(dc, dc_state, stream);
6672 if (dc_result == DC_OK && !dc_state_add_plane(
6677 dc_result = DC_FAIL_ATTACH_SURFACES;
6679 if (dc_result == DC_OK)
6680 dc_result = dc_validate_global_state(dc, dc_state, true);
6684 dc_state_release(dc_state);
6687 dc_plane_state_release(dc_plane_state);
6692 struct dc_stream_state *
6693 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6694 const struct drm_display_mode *drm_mode,
6695 const struct dm_connector_state *dm_state,
6696 const struct dc_stream_state *old_stream)
6698 struct drm_connector *connector = &aconnector->base;
6699 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6700 struct dc_stream_state *stream;
6701 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6702 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6703 enum dc_status dc_result = DC_OK;
6706 stream = create_stream_for_sink(connector, drm_mode,
6707 dm_state, old_stream,
6709 if (stream == NULL) {
6710 DRM_ERROR("Failed to create stream for sink!\n");
6714 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
6717 dc_result = dc_validate_stream(adev->dm.dc, stream);
6718 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6719 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6721 if (dc_result == DC_OK)
6722 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6724 if (dc_result != DC_OK) {
6725 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6730 dc_status_to_str(dc_result));
6732 dc_stream_release(stream);
6734 requested_bpc -= 2; /* lower bpc to retry validation */
6737 } while (stream == NULL && requested_bpc >= 6);
6739 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6740 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6742 aconnector->force_yuv420_output = true;
6743 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6744 dm_state, old_stream);
6745 aconnector->force_yuv420_output = false;
6751 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6752 struct drm_display_mode *mode)
6754 int result = MODE_ERROR;
6755 struct dc_sink *dc_sink;
6756 /* TODO: Unhardcode stream count */
6757 struct dc_stream_state *stream;
6758 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6760 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6761 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6765 * Only run this the first time mode_valid is called to initilialize
6768 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6769 !aconnector->dc_em_sink)
6770 handle_edid_mgmt(aconnector);
6772 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6774 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6775 aconnector->base.force != DRM_FORCE_ON) {
6776 DRM_ERROR("dc_sink is NULL!\n");
6780 drm_mode_set_crtcinfo(mode, 0);
6782 stream = create_validate_stream_for_sink(aconnector, mode,
6783 to_dm_connector_state(connector->state),
6786 dc_stream_release(stream);
6791 /* TODO: error handling*/
6795 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6796 struct dc_info_packet *out)
6798 struct hdmi_drm_infoframe frame;
6799 unsigned char buf[30]; /* 26 + 4 */
6803 memset(out, 0, sizeof(*out));
6805 if (!state->hdr_output_metadata)
6808 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6812 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6816 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6820 /* Prepare the infopacket for DC. */
6821 switch (state->connector->connector_type) {
6822 case DRM_MODE_CONNECTOR_HDMIA:
6823 out->hb0 = 0x87; /* type */
6824 out->hb1 = 0x01; /* version */
6825 out->hb2 = 0x1A; /* length */
6826 out->sb[0] = buf[3]; /* checksum */
6830 case DRM_MODE_CONNECTOR_DisplayPort:
6831 case DRM_MODE_CONNECTOR_eDP:
6832 out->hb0 = 0x00; /* sdp id, zero */
6833 out->hb1 = 0x87; /* type */
6834 out->hb2 = 0x1D; /* payload len - 1 */
6835 out->hb3 = (0x13 << 2); /* sdp version */
6836 out->sb[0] = 0x01; /* version */
6837 out->sb[1] = 0x1A; /* length */
6845 memcpy(&out->sb[i], &buf[4], 26);
6848 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6849 sizeof(out->sb), false);
6855 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6856 struct drm_atomic_state *state)
6858 struct drm_connector_state *new_con_state =
6859 drm_atomic_get_new_connector_state(state, conn);
6860 struct drm_connector_state *old_con_state =
6861 drm_atomic_get_old_connector_state(state, conn);
6862 struct drm_crtc *crtc = new_con_state->crtc;
6863 struct drm_crtc_state *new_crtc_state;
6864 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6867 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6869 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6870 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6878 if (new_con_state->colorspace != old_con_state->colorspace) {
6879 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6880 if (IS_ERR(new_crtc_state))
6881 return PTR_ERR(new_crtc_state);
6883 new_crtc_state->mode_changed = true;
6886 if (new_con_state->content_type != old_con_state->content_type) {
6887 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6888 if (IS_ERR(new_crtc_state))
6889 return PTR_ERR(new_crtc_state);
6891 new_crtc_state->mode_changed = true;
6894 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6895 struct dc_info_packet hdr_infopacket;
6897 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6901 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6902 if (IS_ERR(new_crtc_state))
6903 return PTR_ERR(new_crtc_state);
6906 * DC considers the stream backends changed if the
6907 * static metadata changes. Forcing the modeset also
6908 * gives a simple way for userspace to switch from
6909 * 8bpc to 10bpc when setting the metadata to enter
6912 * Changing the static metadata after it's been
6913 * set is permissible, however. So only force a
6914 * modeset if we're entering or exiting HDR.
6916 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6917 !old_con_state->hdr_output_metadata ||
6918 !new_con_state->hdr_output_metadata;
6924 static const struct drm_connector_helper_funcs
6925 amdgpu_dm_connector_helper_funcs = {
6927 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6928 * modes will be filtered by drm_mode_validate_size(), and those modes
6929 * are missing after user start lightdm. So we need to renew modes list.
6930 * in get_modes call back, not just return the modes count
6932 .get_modes = get_modes,
6933 .mode_valid = amdgpu_dm_connector_mode_valid,
6934 .atomic_check = amdgpu_dm_connector_atomic_check,
6937 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6942 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6944 switch (display_color_depth) {
6945 case COLOR_DEPTH_666:
6947 case COLOR_DEPTH_888:
6949 case COLOR_DEPTH_101010:
6951 case COLOR_DEPTH_121212:
6953 case COLOR_DEPTH_141414:
6955 case COLOR_DEPTH_161616:
6963 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6964 struct drm_crtc_state *crtc_state,
6965 struct drm_connector_state *conn_state)
6967 struct drm_atomic_state *state = crtc_state->state;
6968 struct drm_connector *connector = conn_state->connector;
6969 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6970 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6971 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6972 struct drm_dp_mst_topology_mgr *mst_mgr;
6973 struct drm_dp_mst_port *mst_port;
6974 struct drm_dp_mst_topology_state *mst_state;
6975 enum dc_color_depth color_depth;
6977 bool is_y420 = false;
6979 if (!aconnector->mst_output_port)
6982 mst_port = aconnector->mst_output_port;
6983 mst_mgr = &aconnector->mst_root->mst_mgr;
6985 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6988 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6989 if (IS_ERR(mst_state))
6990 return PTR_ERR(mst_state);
6992 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
6994 if (!state->duplicated) {
6995 int max_bpc = conn_state->max_requested_bpc;
6997 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6998 aconnector->force_yuv420_output;
6999 color_depth = convert_color_depth_from_display_info(connector,
7002 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
7003 clock = adjusted_mode->clock;
7004 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
7007 dm_new_connector_state->vcpi_slots =
7008 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
7009 dm_new_connector_state->pbn);
7010 if (dm_new_connector_state->vcpi_slots < 0) {
7011 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
7012 return dm_new_connector_state->vcpi_slots;
7017 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
7018 .disable = dm_encoder_helper_disable,
7019 .atomic_check = dm_encoder_helper_atomic_check
7022 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
7023 struct dc_state *dc_state,
7024 struct dsc_mst_fairness_vars *vars)
7026 struct dc_stream_state *stream = NULL;
7027 struct drm_connector *connector;
7028 struct drm_connector_state *new_con_state;
7029 struct amdgpu_dm_connector *aconnector;
7030 struct dm_connector_state *dm_conn_state;
7032 int vcpi, pbn_div, pbn, slot_num = 0;
7034 for_each_new_connector_in_state(state, connector, new_con_state, i) {
7036 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
7039 aconnector = to_amdgpu_dm_connector(connector);
7041 if (!aconnector->mst_output_port)
7044 if (!new_con_state || !new_con_state->crtc)
7047 dm_conn_state = to_dm_connector_state(new_con_state);
7049 for (j = 0; j < dc_state->stream_count; j++) {
7050 stream = dc_state->streams[j];
7054 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
7063 pbn_div = dm_mst_get_pbn_divider(stream->link);
7064 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
7065 for (j = 0; j < dc_state->stream_count; j++) {
7066 if (vars[j].aconnector == aconnector) {
7072 if (j == dc_state->stream_count)
7075 slot_num = DIV_ROUND_UP(pbn, pbn_div);
7077 if (stream->timing.flags.DSC != 1) {
7078 dm_conn_state->pbn = pbn;
7079 dm_conn_state->vcpi_slots = slot_num;
7081 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7082 dm_conn_state->pbn, false);
7089 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7093 dm_conn_state->pbn = pbn;
7094 dm_conn_state->vcpi_slots = vcpi;
7099 static int to_drm_connector_type(enum signal_type st)
7102 case SIGNAL_TYPE_HDMI_TYPE_A:
7103 return DRM_MODE_CONNECTOR_HDMIA;
7104 case SIGNAL_TYPE_EDP:
7105 return DRM_MODE_CONNECTOR_eDP;
7106 case SIGNAL_TYPE_LVDS:
7107 return DRM_MODE_CONNECTOR_LVDS;
7108 case SIGNAL_TYPE_RGB:
7109 return DRM_MODE_CONNECTOR_VGA;
7110 case SIGNAL_TYPE_DISPLAY_PORT:
7111 case SIGNAL_TYPE_DISPLAY_PORT_MST:
7112 return DRM_MODE_CONNECTOR_DisplayPort;
7113 case SIGNAL_TYPE_DVI_DUAL_LINK:
7114 case SIGNAL_TYPE_DVI_SINGLE_LINK:
7115 return DRM_MODE_CONNECTOR_DVID;
7116 case SIGNAL_TYPE_VIRTUAL:
7117 return DRM_MODE_CONNECTOR_VIRTUAL;
7120 return DRM_MODE_CONNECTOR_Unknown;
7124 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7126 struct drm_encoder *encoder;
7128 /* There is only one encoder per connector */
7129 drm_connector_for_each_possible_encoder(connector, encoder)
7135 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7137 struct drm_encoder *encoder;
7138 struct amdgpu_encoder *amdgpu_encoder;
7140 encoder = amdgpu_dm_connector_to_encoder(connector);
7142 if (encoder == NULL)
7145 amdgpu_encoder = to_amdgpu_encoder(encoder);
7147 amdgpu_encoder->native_mode.clock = 0;
7149 if (!list_empty(&connector->probed_modes)) {
7150 struct drm_display_mode *preferred_mode = NULL;
7152 list_for_each_entry(preferred_mode,
7153 &connector->probed_modes,
7155 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7156 amdgpu_encoder->native_mode = *preferred_mode;
7164 static struct drm_display_mode *
7165 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7167 int hdisplay, int vdisplay)
7169 struct drm_device *dev = encoder->dev;
7170 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7171 struct drm_display_mode *mode = NULL;
7172 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7174 mode = drm_mode_duplicate(dev, native_mode);
7179 mode->hdisplay = hdisplay;
7180 mode->vdisplay = vdisplay;
7181 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7182 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7188 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7189 struct drm_connector *connector)
7191 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7192 struct drm_display_mode *mode = NULL;
7193 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7194 struct amdgpu_dm_connector *amdgpu_dm_connector =
7195 to_amdgpu_dm_connector(connector);
7199 char name[DRM_DISPLAY_MODE_LEN];
7202 } common_modes[] = {
7203 { "640x480", 640, 480},
7204 { "800x600", 800, 600},
7205 { "1024x768", 1024, 768},
7206 { "1280x720", 1280, 720},
7207 { "1280x800", 1280, 800},
7208 {"1280x1024", 1280, 1024},
7209 { "1440x900", 1440, 900},
7210 {"1680x1050", 1680, 1050},
7211 {"1600x1200", 1600, 1200},
7212 {"1920x1080", 1920, 1080},
7213 {"1920x1200", 1920, 1200}
7216 n = ARRAY_SIZE(common_modes);
7218 for (i = 0; i < n; i++) {
7219 struct drm_display_mode *curmode = NULL;
7220 bool mode_existed = false;
7222 if (common_modes[i].w > native_mode->hdisplay ||
7223 common_modes[i].h > native_mode->vdisplay ||
7224 (common_modes[i].w == native_mode->hdisplay &&
7225 common_modes[i].h == native_mode->vdisplay))
7228 list_for_each_entry(curmode, &connector->probed_modes, head) {
7229 if (common_modes[i].w == curmode->hdisplay &&
7230 common_modes[i].h == curmode->vdisplay) {
7231 mode_existed = true;
7239 mode = amdgpu_dm_create_common_mode(encoder,
7240 common_modes[i].name, common_modes[i].w,
7245 drm_mode_probed_add(connector, mode);
7246 amdgpu_dm_connector->num_modes++;
7250 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7252 struct drm_encoder *encoder;
7253 struct amdgpu_encoder *amdgpu_encoder;
7254 const struct drm_display_mode *native_mode;
7256 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7257 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7260 mutex_lock(&connector->dev->mode_config.mutex);
7261 amdgpu_dm_connector_get_modes(connector);
7262 mutex_unlock(&connector->dev->mode_config.mutex);
7264 encoder = amdgpu_dm_connector_to_encoder(connector);
7268 amdgpu_encoder = to_amdgpu_encoder(encoder);
7270 native_mode = &amdgpu_encoder->native_mode;
7271 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7274 drm_connector_set_panel_orientation_with_quirk(connector,
7275 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7276 native_mode->hdisplay,
7277 native_mode->vdisplay);
7280 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7283 struct amdgpu_dm_connector *amdgpu_dm_connector =
7284 to_amdgpu_dm_connector(connector);
7287 /* empty probed_modes */
7288 INIT_LIST_HEAD(&connector->probed_modes);
7289 amdgpu_dm_connector->num_modes =
7290 drm_add_edid_modes(connector, edid);
7292 /* sorting the probed modes before calling function
7293 * amdgpu_dm_get_native_mode() since EDID can have
7294 * more than one preferred mode. The modes that are
7295 * later in the probed mode list could be of higher
7296 * and preferred resolution. For example, 3840x2160
7297 * resolution in base EDID preferred timing and 4096x2160
7298 * preferred resolution in DID extension block later.
7300 drm_mode_sort(&connector->probed_modes);
7301 amdgpu_dm_get_native_mode(connector);
7303 /* Freesync capabilities are reset by calling
7304 * drm_add_edid_modes() and need to be
7307 amdgpu_dm_update_freesync_caps(connector, edid);
7309 amdgpu_dm_connector->num_modes = 0;
7313 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7314 struct drm_display_mode *mode)
7316 struct drm_display_mode *m;
7318 list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7319 if (drm_mode_equal(m, mode))
7326 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7328 const struct drm_display_mode *m;
7329 struct drm_display_mode *new_mode;
7331 u32 new_modes_count = 0;
7333 /* Standard FPS values
7342 * 60 - Commonly used
7343 * 48,72,96,120 - Multiples of 24
7345 static const u32 common_rates[] = {
7346 23976, 24000, 25000, 29970, 30000,
7347 48000, 50000, 60000, 72000, 96000, 120000
7351 * Find mode with highest refresh rate with the same resolution
7352 * as the preferred mode. Some monitors report a preferred mode
7353 * with lower resolution than the highest refresh rate supported.
7356 m = get_highest_refresh_rate_mode(aconnector, true);
7360 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7361 u64 target_vtotal, target_vtotal_diff;
7364 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7367 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7368 common_rates[i] > aconnector->max_vfreq * 1000)
7371 num = (unsigned long long)m->clock * 1000 * 1000;
7372 den = common_rates[i] * (unsigned long long)m->htotal;
7373 target_vtotal = div_u64(num, den);
7374 target_vtotal_diff = target_vtotal - m->vtotal;
7376 /* Check for illegal modes */
7377 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7378 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7379 m->vtotal + target_vtotal_diff < m->vsync_end)
7382 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7386 new_mode->vtotal += (u16)target_vtotal_diff;
7387 new_mode->vsync_start += (u16)target_vtotal_diff;
7388 new_mode->vsync_end += (u16)target_vtotal_diff;
7389 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7390 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7392 if (!is_duplicate_mode(aconnector, new_mode)) {
7393 drm_mode_probed_add(&aconnector->base, new_mode);
7394 new_modes_count += 1;
7396 drm_mode_destroy(aconnector->base.dev, new_mode);
7399 return new_modes_count;
7402 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7405 struct amdgpu_dm_connector *amdgpu_dm_connector =
7406 to_amdgpu_dm_connector(connector);
7411 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7412 amdgpu_dm_connector->num_modes +=
7413 add_fs_modes(amdgpu_dm_connector);
7416 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7418 struct amdgpu_dm_connector *amdgpu_dm_connector =
7419 to_amdgpu_dm_connector(connector);
7420 struct drm_encoder *encoder;
7421 struct edid *edid = amdgpu_dm_connector->edid;
7422 struct dc_link_settings *verified_link_cap =
7423 &amdgpu_dm_connector->dc_link->verified_link_cap;
7424 const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7426 encoder = amdgpu_dm_connector_to_encoder(connector);
7428 if (!drm_edid_is_valid(edid)) {
7429 amdgpu_dm_connector->num_modes =
7430 drm_add_modes_noedid(connector, 640, 480);
7431 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7432 amdgpu_dm_connector->num_modes +=
7433 drm_add_modes_noedid(connector, 1920, 1080);
7435 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7436 amdgpu_dm_connector_add_common_modes(encoder, connector);
7437 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7439 amdgpu_dm_fbc_init(connector);
7441 return amdgpu_dm_connector->num_modes;
7444 static const u32 supported_colorspaces =
7445 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7446 BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7447 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7448 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7450 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7451 struct amdgpu_dm_connector *aconnector,
7453 struct dc_link *link,
7456 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7459 * Some of the properties below require access to state, like bpc.
7460 * Allocate some default initial connector state with our reset helper.
7462 if (aconnector->base.funcs->reset)
7463 aconnector->base.funcs->reset(&aconnector->base);
7465 aconnector->connector_id = link_index;
7466 aconnector->bl_idx = -1;
7467 aconnector->dc_link = link;
7468 aconnector->base.interlace_allowed = false;
7469 aconnector->base.doublescan_allowed = false;
7470 aconnector->base.stereo_allowed = false;
7471 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7472 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7473 aconnector->audio_inst = -1;
7474 aconnector->pack_sdp_v1_3 = false;
7475 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7476 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7477 mutex_init(&aconnector->hpd_lock);
7478 mutex_init(&aconnector->handle_mst_msg_ready);
7481 * configure support HPD hot plug connector_>polled default value is 0
7482 * which means HPD hot plug not supported
7484 switch (connector_type) {
7485 case DRM_MODE_CONNECTOR_HDMIA:
7486 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7487 aconnector->base.ycbcr_420_allowed =
7488 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7490 case DRM_MODE_CONNECTOR_DisplayPort:
7491 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7492 link->link_enc = link_enc_cfg_get_link_enc(link);
7493 ASSERT(link->link_enc);
7495 aconnector->base.ycbcr_420_allowed =
7496 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7498 case DRM_MODE_CONNECTOR_DVID:
7499 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7505 drm_object_attach_property(&aconnector->base.base,
7506 dm->ddev->mode_config.scaling_mode_property,
7507 DRM_MODE_SCALE_NONE);
7509 drm_object_attach_property(&aconnector->base.base,
7510 adev->mode_info.underscan_property,
7512 drm_object_attach_property(&aconnector->base.base,
7513 adev->mode_info.underscan_hborder_property,
7515 drm_object_attach_property(&aconnector->base.base,
7516 adev->mode_info.underscan_vborder_property,
7519 if (!aconnector->mst_root)
7520 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7522 aconnector->base.state->max_bpc = 16;
7523 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7525 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7526 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7527 drm_object_attach_property(&aconnector->base.base,
7528 adev->mode_info.abm_level_property, 0);
7531 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7532 /* Content Type is currently only implemented for HDMI. */
7533 drm_connector_attach_content_type_property(&aconnector->base);
7536 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7537 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7538 drm_connector_attach_colorspace_property(&aconnector->base);
7539 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7540 connector_type == DRM_MODE_CONNECTOR_eDP) {
7541 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7542 drm_connector_attach_colorspace_property(&aconnector->base);
7545 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7546 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7547 connector_type == DRM_MODE_CONNECTOR_eDP) {
7548 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7550 if (!aconnector->mst_root)
7551 drm_connector_attach_vrr_capable_property(&aconnector->base);
7553 if (adev->dm.hdcp_workqueue)
7554 drm_connector_attach_content_protection_property(&aconnector->base, true);
7558 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7559 struct i2c_msg *msgs, int num)
7561 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7562 struct ddc_service *ddc_service = i2c->ddc_service;
7563 struct i2c_command cmd;
7567 if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
7570 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7575 cmd.number_of_payloads = num;
7576 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7579 for (i = 0; i < num; i++) {
7580 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7581 cmd.payloads[i].address = msgs[i].addr;
7582 cmd.payloads[i].length = msgs[i].len;
7583 cmd.payloads[i].data = msgs[i].buf;
7587 ddc_service->ctx->dc,
7588 ddc_service->link->link_index,
7592 kfree(cmd.payloads);
7596 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7598 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7601 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7602 .master_xfer = amdgpu_dm_i2c_xfer,
7603 .functionality = amdgpu_dm_i2c_func,
7606 static struct amdgpu_i2c_adapter *
7607 create_i2c(struct ddc_service *ddc_service,
7611 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7612 struct amdgpu_i2c_adapter *i2c;
7614 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7617 i2c->base.owner = THIS_MODULE;
7618 i2c->base.dev.parent = &adev->pdev->dev;
7619 i2c->base.algo = &amdgpu_dm_i2c_algo;
7620 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7621 i2c_set_adapdata(&i2c->base, i2c);
7622 i2c->ddc_service = ddc_service;
7629 * Note: this function assumes that dc_link_detect() was called for the
7630 * dc_link which will be represented by this aconnector.
7632 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7633 struct amdgpu_dm_connector *aconnector,
7635 struct amdgpu_encoder *aencoder)
7639 struct dc *dc = dm->dc;
7640 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7641 struct amdgpu_i2c_adapter *i2c;
7643 /* Not needed for writeback connector */
7644 link->priv = aconnector;
7647 i2c = create_i2c(link->ddc, link->link_index, &res);
7649 DRM_ERROR("Failed to create i2c adapter data\n");
7653 aconnector->i2c = i2c;
7654 res = i2c_add_adapter(&i2c->base);
7657 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7661 connector_type = to_drm_connector_type(link->connector_signal);
7663 res = drm_connector_init_with_ddc(
7666 &amdgpu_dm_connector_funcs,
7671 DRM_ERROR("connector_init failed\n");
7672 aconnector->connector_id = -1;
7676 drm_connector_helper_add(
7678 &amdgpu_dm_connector_helper_funcs);
7680 amdgpu_dm_connector_init_helper(
7687 drm_connector_attach_encoder(
7688 &aconnector->base, &aencoder->base);
7690 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7691 || connector_type == DRM_MODE_CONNECTOR_eDP)
7692 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7697 aconnector->i2c = NULL;
7702 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7704 switch (adev->mode_info.num_crtc) {
7721 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7722 struct amdgpu_encoder *aencoder,
7723 uint32_t link_index)
7725 struct amdgpu_device *adev = drm_to_adev(dev);
7727 int res = drm_encoder_init(dev,
7729 &amdgpu_dm_encoder_funcs,
7730 DRM_MODE_ENCODER_TMDS,
7733 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7736 aencoder->encoder_id = link_index;
7738 aencoder->encoder_id = -1;
7740 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7745 static void manage_dm_interrupts(struct amdgpu_device *adev,
7746 struct amdgpu_crtc *acrtc,
7750 * We have no guarantee that the frontend index maps to the same
7751 * backend index - some even map to more than one.
7753 * TODO: Use a different interrupt or check DC itself for the mapping.
7756 amdgpu_display_crtc_idx_to_irq_type(
7761 drm_crtc_vblank_on(&acrtc->base);
7764 &adev->pageflip_irq,
7766 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7773 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7781 &adev->pageflip_irq,
7783 drm_crtc_vblank_off(&acrtc->base);
7787 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7788 struct amdgpu_crtc *acrtc)
7791 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7794 * This reads the current state for the IRQ and force reapplies
7795 * the setting to hardware.
7797 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7801 is_scaling_state_different(const struct dm_connector_state *dm_state,
7802 const struct dm_connector_state *old_dm_state)
7804 if (dm_state->scaling != old_dm_state->scaling)
7806 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7807 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7809 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7810 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7812 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7813 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7818 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7819 struct drm_crtc_state *old_crtc_state,
7820 struct drm_connector_state *new_conn_state,
7821 struct drm_connector_state *old_conn_state,
7822 const struct drm_connector *connector,
7823 struct hdcp_workqueue *hdcp_w)
7825 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7826 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7828 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7829 connector->index, connector->status, connector->dpms);
7830 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7831 old_conn_state->content_protection, new_conn_state->content_protection);
7834 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7835 old_crtc_state->enable,
7836 old_crtc_state->active,
7837 old_crtc_state->mode_changed,
7838 old_crtc_state->active_changed,
7839 old_crtc_state->connectors_changed);
7842 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7843 new_crtc_state->enable,
7844 new_crtc_state->active,
7845 new_crtc_state->mode_changed,
7846 new_crtc_state->active_changed,
7847 new_crtc_state->connectors_changed);
7849 /* hdcp content type change */
7850 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7851 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7852 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7853 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7857 /* CP is being re enabled, ignore this */
7858 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7859 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7860 if (new_crtc_state && new_crtc_state->mode_changed) {
7861 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7862 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7865 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7866 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7870 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7872 * Handles: UNDESIRED -> ENABLED
7874 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7875 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7876 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7878 /* Stream removed and re-enabled
7880 * Can sometimes overlap with the HPD case,
7881 * thus set update_hdcp to false to avoid
7882 * setting HDCP multiple times.
7884 * Handles: DESIRED -> DESIRED (Special case)
7886 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7887 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7888 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7889 dm_con_state->update_hdcp = false;
7890 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7895 /* Hot-plug, headless s3, dpms
7897 * Only start HDCP if the display is connected/enabled.
7898 * update_hdcp flag will be set to false until the next
7901 * Handles: DESIRED -> DESIRED (Special case)
7903 if (dm_con_state->update_hdcp &&
7904 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7905 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7906 dm_con_state->update_hdcp = false;
7907 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7912 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7913 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7914 if (new_crtc_state && new_crtc_state->mode_changed) {
7915 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7919 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7924 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7928 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7929 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7934 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7938 static void remove_stream(struct amdgpu_device *adev,
7939 struct amdgpu_crtc *acrtc,
7940 struct dc_stream_state *stream)
7942 /* this is the update mode case */
7944 acrtc->otg_inst = -1;
7945 acrtc->enabled = false;
7948 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7951 assert_spin_locked(&acrtc->base.dev->event_lock);
7952 WARN_ON(acrtc->event);
7954 acrtc->event = acrtc->base.state->event;
7956 /* Set the flip status */
7957 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7959 /* Mark this event as consumed */
7960 acrtc->base.state->event = NULL;
7962 drm_dbg_state(acrtc->base.dev,
7963 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7967 static void update_freesync_state_on_stream(
7968 struct amdgpu_display_manager *dm,
7969 struct dm_crtc_state *new_crtc_state,
7970 struct dc_stream_state *new_stream,
7971 struct dc_plane_state *surface,
7972 u32 flip_timestamp_in_us)
7974 struct mod_vrr_params vrr_params;
7975 struct dc_info_packet vrr_infopacket = {0};
7976 struct amdgpu_device *adev = dm->adev;
7977 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7978 unsigned long flags;
7979 bool pack_sdp_v1_3 = false;
7980 struct amdgpu_dm_connector *aconn;
7981 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7987 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7988 * For now it's sufficient to just guard against these conditions.
7991 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7994 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7995 vrr_params = acrtc->dm_irq_params.vrr_params;
7998 mod_freesync_handle_preflip(
7999 dm->freesync_module,
8002 flip_timestamp_in_us,
8005 if (adev->family < AMDGPU_FAMILY_AI &&
8006 amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
8007 mod_freesync_handle_v_update(dm->freesync_module,
8008 new_stream, &vrr_params);
8010 /* Need to call this before the frame ends. */
8011 dc_stream_adjust_vmin_vmax(dm->dc,
8012 new_crtc_state->stream,
8013 &vrr_params.adjust);
8017 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
8019 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
8020 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
8022 if (aconn->vsdb_info.amd_vsdb_version == 1)
8023 packet_type = PACKET_TYPE_FS_V1;
8024 else if (aconn->vsdb_info.amd_vsdb_version == 2)
8025 packet_type = PACKET_TYPE_FS_V2;
8026 else if (aconn->vsdb_info.amd_vsdb_version == 3)
8027 packet_type = PACKET_TYPE_FS_V3;
8029 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
8030 &new_stream->adaptive_sync_infopacket);
8033 mod_freesync_build_vrr_infopacket(
8034 dm->freesync_module,
8038 TRANSFER_FUNC_UNKNOWN,
8042 new_crtc_state->freesync_vrr_info_changed |=
8043 (memcmp(&new_crtc_state->vrr_infopacket,
8045 sizeof(vrr_infopacket)) != 0);
8047 acrtc->dm_irq_params.vrr_params = vrr_params;
8048 new_crtc_state->vrr_infopacket = vrr_infopacket;
8050 new_stream->vrr_infopacket = vrr_infopacket;
8051 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
8053 if (new_crtc_state->freesync_vrr_info_changed)
8054 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
8055 new_crtc_state->base.crtc->base.id,
8056 (int)new_crtc_state->base.vrr_enabled,
8057 (int)vrr_params.state);
8059 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8062 static void update_stream_irq_parameters(
8063 struct amdgpu_display_manager *dm,
8064 struct dm_crtc_state *new_crtc_state)
8066 struct dc_stream_state *new_stream = new_crtc_state->stream;
8067 struct mod_vrr_params vrr_params;
8068 struct mod_freesync_config config = new_crtc_state->freesync_config;
8069 struct amdgpu_device *adev = dm->adev;
8070 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8071 unsigned long flags;
8077 * TODO: Determine why min/max totals and vrefresh can be 0 here.
8078 * For now it's sufficient to just guard against these conditions.
8080 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8083 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8084 vrr_params = acrtc->dm_irq_params.vrr_params;
8086 if (new_crtc_state->vrr_supported &&
8087 config.min_refresh_in_uhz &&
8088 config.max_refresh_in_uhz) {
8090 * if freesync compatible mode was set, config.state will be set
8093 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8094 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8095 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8096 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8097 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8098 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8099 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8101 config.state = new_crtc_state->base.vrr_enabled ?
8102 VRR_STATE_ACTIVE_VARIABLE :
8106 config.state = VRR_STATE_UNSUPPORTED;
8109 mod_freesync_build_vrr_params(dm->freesync_module,
8111 &config, &vrr_params);
8113 new_crtc_state->freesync_config = config;
8114 /* Copy state for access from DM IRQ handler */
8115 acrtc->dm_irq_params.freesync_config = config;
8116 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8117 acrtc->dm_irq_params.vrr_params = vrr_params;
8118 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8121 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8122 struct dm_crtc_state *new_state)
8124 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8125 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8127 if (!old_vrr_active && new_vrr_active) {
8128 /* Transition VRR inactive -> active:
8129 * While VRR is active, we must not disable vblank irq, as a
8130 * reenable after disable would compute bogus vblank/pflip
8131 * timestamps if it likely happened inside display front-porch.
8133 * We also need vupdate irq for the actual core vblank handling
8136 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8137 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8138 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8139 __func__, new_state->base.crtc->base.id);
8140 } else if (old_vrr_active && !new_vrr_active) {
8141 /* Transition VRR active -> inactive:
8142 * Allow vblank irq disable again for fixed refresh rate.
8144 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8145 drm_crtc_vblank_put(new_state->base.crtc);
8146 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8147 __func__, new_state->base.crtc->base.id);
8151 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8153 struct drm_plane *plane;
8154 struct drm_plane_state *old_plane_state;
8158 * TODO: Make this per-stream so we don't issue redundant updates for
8159 * commits with multiple streams.
8161 for_each_old_plane_in_state(state, plane, old_plane_state, i)
8162 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8163 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8166 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8168 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8170 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8173 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8174 struct drm_device *dev,
8175 struct amdgpu_display_manager *dm,
8176 struct drm_crtc *pcrtc,
8177 bool wait_for_vblank)
8180 u64 timestamp_ns = ktime_get_ns();
8181 struct drm_plane *plane;
8182 struct drm_plane_state *old_plane_state, *new_plane_state;
8183 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8184 struct drm_crtc_state *new_pcrtc_state =
8185 drm_atomic_get_new_crtc_state(state, pcrtc);
8186 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8187 struct dm_crtc_state *dm_old_crtc_state =
8188 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8189 int planes_count = 0, vpos, hpos;
8190 unsigned long flags;
8191 u32 target_vblank, last_flip_vblank;
8192 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8193 bool cursor_update = false;
8194 bool pflip_present = false;
8195 bool dirty_rects_changed = false;
8197 struct dc_surface_update surface_updates[MAX_SURFACES];
8198 struct dc_plane_info plane_infos[MAX_SURFACES];
8199 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8200 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8201 struct dc_stream_update stream_update;
8204 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8207 drm_err(dev, "Failed to allocate update bundle\n");
8212 * Disable the cursor first if we're disabling all the planes.
8213 * It'll remain on the screen after the planes are re-enabled
8216 if (acrtc_state->active_planes == 0)
8217 amdgpu_dm_commit_cursors(state);
8219 /* update planes when needed */
8220 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8221 struct drm_crtc *crtc = new_plane_state->crtc;
8222 struct drm_crtc_state *new_crtc_state;
8223 struct drm_framebuffer *fb = new_plane_state->fb;
8224 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8225 bool plane_needs_flip;
8226 struct dc_plane_state *dc_plane;
8227 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8229 /* Cursor plane is handled after stream updates */
8230 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8231 if ((fb && crtc == pcrtc) ||
8232 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8233 cursor_update = true;
8238 if (!fb || !crtc || pcrtc != crtc)
8241 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8242 if (!new_crtc_state->active)
8245 dc_plane = dm_new_plane_state->dc_state;
8249 bundle->surface_updates[planes_count].surface = dc_plane;
8250 if (new_pcrtc_state->color_mgmt_changed) {
8251 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8252 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8253 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8254 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult;
8255 bundle->surface_updates[planes_count].func_shaper = dc_plane->in_shaper_func;
8256 bundle->surface_updates[planes_count].lut3d_func = dc_plane->lut3d_func;
8257 bundle->surface_updates[planes_count].blend_tf = dc_plane->blend_tf;
8260 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8261 &bundle->scaling_infos[planes_count]);
8263 bundle->surface_updates[planes_count].scaling_info =
8264 &bundle->scaling_infos[planes_count];
8266 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8268 pflip_present = pflip_present || plane_needs_flip;
8270 if (!plane_needs_flip) {
8275 fill_dc_plane_info_and_addr(
8276 dm->adev, new_plane_state,
8278 &bundle->plane_infos[planes_count],
8279 &bundle->flip_addrs[planes_count].address,
8280 afb->tmz_surface, false);
8282 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8283 new_plane_state->plane->index,
8284 bundle->plane_infos[planes_count].dcc.enable);
8286 bundle->surface_updates[planes_count].plane_info =
8287 &bundle->plane_infos[planes_count];
8289 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8290 acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8291 fill_dc_dirty_rects(plane, old_plane_state,
8292 new_plane_state, new_crtc_state,
8293 &bundle->flip_addrs[planes_count],
8294 &dirty_rects_changed);
8297 * If the dirty regions changed, PSR-SU need to be disabled temporarily
8298 * and enabled it again after dirty regions are stable to avoid video glitch.
8299 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8300 * during the PSR-SU was disabled.
8302 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8303 acrtc_attach->dm_irq_params.allow_psr_entry &&
8304 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8305 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8307 dirty_rects_changed) {
8308 mutex_lock(&dm->dc_lock);
8309 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8311 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8312 amdgpu_dm_psr_disable(acrtc_state->stream);
8313 mutex_unlock(&dm->dc_lock);
8318 * Only allow immediate flips for fast updates that don't
8319 * change memory domain, FB pitch, DCC state, rotation or
8322 * dm_crtc_helper_atomic_check() only accepts async flips with
8325 if (crtc->state->async_flip &&
8326 (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8327 get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8328 drm_warn_once(state->dev,
8329 "[PLANE:%d:%s] async flip with non-fast update\n",
8330 plane->base.id, plane->name);
8332 bundle->flip_addrs[planes_count].flip_immediate =
8333 crtc->state->async_flip &&
8334 acrtc_state->update_type == UPDATE_TYPE_FAST &&
8335 get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8337 timestamp_ns = ktime_get_ns();
8338 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8339 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8340 bundle->surface_updates[planes_count].surface = dc_plane;
8342 if (!bundle->surface_updates[planes_count].surface) {
8343 DRM_ERROR("No surface for CRTC: id=%d\n",
8344 acrtc_attach->crtc_id);
8348 if (plane == pcrtc->primary)
8349 update_freesync_state_on_stream(
8352 acrtc_state->stream,
8354 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8356 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8358 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8359 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8365 if (pflip_present) {
8367 /* Use old throttling in non-vrr fixed refresh rate mode
8368 * to keep flip scheduling based on target vblank counts
8369 * working in a backwards compatible way, e.g., for
8370 * clients using the GLX_OML_sync_control extension or
8371 * DRI3/Present extension with defined target_msc.
8373 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8375 /* For variable refresh rate mode only:
8376 * Get vblank of last completed flip to avoid > 1 vrr
8377 * flips per video frame by use of throttling, but allow
8378 * flip programming anywhere in the possibly large
8379 * variable vrr vblank interval for fine-grained flip
8380 * timing control and more opportunity to avoid stutter
8381 * on late submission of flips.
8383 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8384 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8385 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8388 target_vblank = last_flip_vblank + wait_for_vblank;
8391 * Wait until we're out of the vertical blank period before the one
8392 * targeted by the flip
8394 while ((acrtc_attach->enabled &&
8395 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8396 0, &vpos, &hpos, NULL,
8397 NULL, &pcrtc->hwmode)
8398 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8399 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8400 (int)(target_vblank -
8401 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8402 usleep_range(1000, 1100);
8406 * Prepare the flip event for the pageflip interrupt to handle.
8408 * This only works in the case where we've already turned on the
8409 * appropriate hardware blocks (eg. HUBP) so in the transition case
8410 * from 0 -> n planes we have to skip a hardware generated event
8411 * and rely on sending it from software.
8413 if (acrtc_attach->base.state->event &&
8414 acrtc_state->active_planes > 0) {
8415 drm_crtc_vblank_get(pcrtc);
8417 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8419 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8420 prepare_flip_isr(acrtc_attach);
8422 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8425 if (acrtc_state->stream) {
8426 if (acrtc_state->freesync_vrr_info_changed)
8427 bundle->stream_update.vrr_infopacket =
8428 &acrtc_state->stream->vrr_infopacket;
8430 } else if (cursor_update && acrtc_state->active_planes > 0 &&
8431 acrtc_attach->base.state->event) {
8432 drm_crtc_vblank_get(pcrtc);
8434 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8436 acrtc_attach->event = acrtc_attach->base.state->event;
8437 acrtc_attach->base.state->event = NULL;
8439 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8442 /* Update the planes if changed or disable if we don't have any. */
8443 if ((planes_count || acrtc_state->active_planes == 0) &&
8444 acrtc_state->stream) {
8446 * If PSR or idle optimizations are enabled then flush out
8447 * any pending work before hardware programming.
8449 if (dm->vblank_control_workqueue)
8450 flush_workqueue(dm->vblank_control_workqueue);
8452 bundle->stream_update.stream = acrtc_state->stream;
8453 if (new_pcrtc_state->mode_changed) {
8454 bundle->stream_update.src = acrtc_state->stream->src;
8455 bundle->stream_update.dst = acrtc_state->stream->dst;
8458 if (new_pcrtc_state->color_mgmt_changed) {
8460 * TODO: This isn't fully correct since we've actually
8461 * already modified the stream in place.
8463 bundle->stream_update.gamut_remap =
8464 &acrtc_state->stream->gamut_remap_matrix;
8465 bundle->stream_update.output_csc_transform =
8466 &acrtc_state->stream->csc_color_matrix;
8467 bundle->stream_update.out_transfer_func =
8468 acrtc_state->stream->out_transfer_func;
8469 bundle->stream_update.lut3d_func =
8470 (struct dc_3dlut *) acrtc_state->stream->lut3d_func;
8471 bundle->stream_update.func_shaper =
8472 (struct dc_transfer_func *) acrtc_state->stream->func_shaper;
8475 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8476 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8477 bundle->stream_update.abm_level = &acrtc_state->abm_level;
8479 mutex_lock(&dm->dc_lock);
8480 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8481 acrtc_state->stream->link->psr_settings.psr_allow_active)
8482 amdgpu_dm_psr_disable(acrtc_state->stream);
8483 mutex_unlock(&dm->dc_lock);
8486 * If FreeSync state on the stream has changed then we need to
8487 * re-adjust the min/max bounds now that DC doesn't handle this
8488 * as part of commit.
8490 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8491 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8492 dc_stream_adjust_vmin_vmax(
8493 dm->dc, acrtc_state->stream,
8494 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8495 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8497 mutex_lock(&dm->dc_lock);
8498 update_planes_and_stream_adapter(dm->dc,
8499 acrtc_state->update_type,
8501 acrtc_state->stream,
8502 &bundle->stream_update,
8503 bundle->surface_updates);
8506 * Enable or disable the interrupts on the backend.
8508 * Most pipes are put into power gating when unused.
8510 * When power gating is enabled on a pipe we lose the
8511 * interrupt enablement state when power gating is disabled.
8513 * So we need to update the IRQ control state in hardware
8514 * whenever the pipe turns on (since it could be previously
8515 * power gated) or off (since some pipes can't be power gated
8518 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8519 dm_update_pflip_irq_state(drm_to_adev(dev),
8522 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8523 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8524 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8525 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8527 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8528 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8529 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8530 struct amdgpu_dm_connector *aconn =
8531 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8533 if (aconn->psr_skip_count > 0)
8534 aconn->psr_skip_count--;
8536 /* Allow PSR when skip count is 0. */
8537 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8540 * If sink supports PSR SU, there is no need to rely on
8541 * a vblank event disable request to enable PSR. PSR SU
8542 * can be enabled immediately once OS demonstrates an
8543 * adequate number of fast atomic commits to notify KMD
8544 * of update events. See `vblank_control_worker()`.
8546 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8547 acrtc_attach->dm_irq_params.allow_psr_entry &&
8548 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8549 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8551 !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8553 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8555 amdgpu_dm_psr_enable(acrtc_state->stream);
8557 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8560 mutex_unlock(&dm->dc_lock);
8564 * Update cursor state *after* programming all the planes.
8565 * This avoids redundant programming in the case where we're going
8566 * to be disabling a single plane - those pipes are being disabled.
8568 if (acrtc_state->active_planes)
8569 amdgpu_dm_commit_cursors(state);
8575 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8576 struct drm_atomic_state *state)
8578 struct amdgpu_device *adev = drm_to_adev(dev);
8579 struct amdgpu_dm_connector *aconnector;
8580 struct drm_connector *connector;
8581 struct drm_connector_state *old_con_state, *new_con_state;
8582 struct drm_crtc_state *new_crtc_state;
8583 struct dm_crtc_state *new_dm_crtc_state;
8584 const struct dc_stream_status *status;
8587 /* Notify device removals. */
8588 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8589 if (old_con_state->crtc != new_con_state->crtc) {
8590 /* CRTC changes require notification. */
8594 if (!new_con_state->crtc)
8597 new_crtc_state = drm_atomic_get_new_crtc_state(
8598 state, new_con_state->crtc);
8600 if (!new_crtc_state)
8603 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8606 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
8610 aconnector = to_amdgpu_dm_connector(connector);
8612 mutex_lock(&adev->dm.audio_lock);
8613 inst = aconnector->audio_inst;
8614 aconnector->audio_inst = -1;
8615 mutex_unlock(&adev->dm.audio_lock);
8617 amdgpu_dm_audio_eld_notify(adev, inst);
8620 /* Notify audio device additions. */
8621 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8622 if (!new_con_state->crtc)
8625 new_crtc_state = drm_atomic_get_new_crtc_state(
8626 state, new_con_state->crtc);
8628 if (!new_crtc_state)
8631 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8634 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8635 if (!new_dm_crtc_state->stream)
8638 status = dc_stream_get_status(new_dm_crtc_state->stream);
8642 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
8645 aconnector = to_amdgpu_dm_connector(connector);
8647 mutex_lock(&adev->dm.audio_lock);
8648 inst = status->audio_inst;
8649 aconnector->audio_inst = inst;
8650 mutex_unlock(&adev->dm.audio_lock);
8652 amdgpu_dm_audio_eld_notify(adev, inst);
8657 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8658 * @crtc_state: the DRM CRTC state
8659 * @stream_state: the DC stream state.
8661 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8662 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8664 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8665 struct dc_stream_state *stream_state)
8667 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8670 static void dm_clear_writeback(struct amdgpu_display_manager *dm,
8671 struct dm_crtc_state *crtc_state)
8673 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
8676 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8677 struct dc_state *dc_state)
8679 struct drm_device *dev = state->dev;
8680 struct amdgpu_device *adev = drm_to_adev(dev);
8681 struct amdgpu_display_manager *dm = &adev->dm;
8682 struct drm_crtc *crtc;
8683 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8684 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8685 struct drm_connector_state *old_con_state;
8686 struct drm_connector *connector;
8687 bool mode_set_reset_required = false;
8690 /* Disable writeback */
8691 for_each_old_connector_in_state(state, connector, old_con_state, i) {
8692 struct dm_connector_state *dm_old_con_state;
8693 struct amdgpu_crtc *acrtc;
8695 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
8698 old_crtc_state = NULL;
8700 dm_old_con_state = to_dm_connector_state(old_con_state);
8701 if (!dm_old_con_state->base.crtc)
8704 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc);
8706 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8708 if (!acrtc->wb_enabled)
8711 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8713 dm_clear_writeback(dm, dm_old_crtc_state);
8714 acrtc->wb_enabled = false;
8717 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8718 new_crtc_state, i) {
8719 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8721 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8723 if (old_crtc_state->active &&
8724 (!new_crtc_state->active ||
8725 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8726 manage_dm_interrupts(adev, acrtc, false);
8727 dc_stream_release(dm_old_crtc_state->stream);
8731 drm_atomic_helper_calc_timestamping_constants(state);
8733 /* update changed items */
8734 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8735 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8737 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8738 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8740 drm_dbg_state(state->dev,
8741 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8743 new_crtc_state->enable,
8744 new_crtc_state->active,
8745 new_crtc_state->planes_changed,
8746 new_crtc_state->mode_changed,
8747 new_crtc_state->active_changed,
8748 new_crtc_state->connectors_changed);
8750 /* Disable cursor if disabling crtc */
8751 if (old_crtc_state->active && !new_crtc_state->active) {
8752 struct dc_cursor_position position;
8754 memset(&position, 0, sizeof(position));
8755 mutex_lock(&dm->dc_lock);
8756 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8757 mutex_unlock(&dm->dc_lock);
8760 /* Copy all transient state flags into dc state */
8761 if (dm_new_crtc_state->stream) {
8762 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8763 dm_new_crtc_state->stream);
8766 /* handles headless hotplug case, updating new_state and
8767 * aconnector as needed
8770 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8772 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8774 if (!dm_new_crtc_state->stream) {
8776 * this could happen because of issues with
8777 * userspace notifications delivery.
8778 * In this case userspace tries to set mode on
8779 * display which is disconnected in fact.
8780 * dc_sink is NULL in this case on aconnector.
8781 * We expect reset mode will come soon.
8783 * This can also happen when unplug is done
8784 * during resume sequence ended
8786 * In this case, we want to pretend we still
8787 * have a sink to keep the pipe running so that
8788 * hw state is consistent with the sw state
8790 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8791 __func__, acrtc->base.base.id);
8795 if (dm_old_crtc_state->stream)
8796 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8798 pm_runtime_get_noresume(dev->dev);
8800 acrtc->enabled = true;
8801 acrtc->hw_mode = new_crtc_state->mode;
8802 crtc->hwmode = new_crtc_state->mode;
8803 mode_set_reset_required = true;
8804 } else if (modereset_required(new_crtc_state)) {
8805 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8806 /* i.e. reset mode */
8807 if (dm_old_crtc_state->stream)
8808 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8810 mode_set_reset_required = true;
8812 } /* for_each_crtc_in_state() */
8814 /* if there mode set or reset, disable eDP PSR */
8815 if (mode_set_reset_required) {
8816 if (dm->vblank_control_workqueue)
8817 flush_workqueue(dm->vblank_control_workqueue);
8819 amdgpu_dm_psr_disable_all(dm);
8822 dm_enable_per_frame_crtc_master_sync(dc_state);
8823 mutex_lock(&dm->dc_lock);
8824 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8826 /* Allow idle optimization when vblank count is 0 for display off */
8827 if (dm->active_vblank_irq_count == 0)
8828 dc_allow_idle_optimizations(dm->dc, true);
8829 mutex_unlock(&dm->dc_lock);
8831 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8832 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8834 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8836 if (dm_new_crtc_state->stream != NULL) {
8837 const struct dc_stream_status *status =
8838 dc_stream_get_status(dm_new_crtc_state->stream);
8841 status = dc_state_get_stream_status(dc_state,
8842 dm_new_crtc_state->stream);
8845 "got no status for stream %p on acrtc%p\n",
8846 dm_new_crtc_state->stream, acrtc);
8848 acrtc->otg_inst = status->primary_otg_inst;
8853 static void dm_set_writeback(struct amdgpu_display_manager *dm,
8854 struct dm_crtc_state *crtc_state,
8855 struct drm_connector *connector,
8856 struct drm_connector_state *new_con_state)
8858 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);
8859 struct amdgpu_device *adev = dm->adev;
8860 struct amdgpu_crtc *acrtc;
8861 struct dc_writeback_info *wb_info;
8862 struct pipe_ctx *pipe = NULL;
8863 struct amdgpu_framebuffer *afb;
8866 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);
8868 DRM_ERROR("Failed to allocate wb_info\n");
8872 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc);
8874 DRM_ERROR("no amdgpu_crtc found\n");
8879 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb);
8881 DRM_ERROR("No amdgpu_framebuffer found\n");
8886 for (i = 0; i < MAX_PIPES; i++) {
8887 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
8888 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];
8893 /* fill in wb_info */
8894 wb_info->wb_enabled = true;
8896 wb_info->dwb_pipe_inst = 0;
8897 wb_info->dwb_params.dwbscl_black_color = 0;
8898 wb_info->dwb_params.hdr_mult = 0x1F000;
8899 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS;
8900 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
8901 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC;
8902 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC;
8904 /* width & height from crtc */
8905 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay;
8906 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay;
8907 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay;
8908 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay;
8910 wb_info->dwb_params.cnv_params.crop_en = false;
8911 wb_info->dwb_params.stereo_params.stereo_enabled = false;
8913 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits
8914 wb_info->dwb_params.cnv_params.out_min_pix_val = 0;
8915 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB;
8916 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS;
8918 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444;
8920 wb_info->dwb_params.capture_rate = dwb_capture_rate_0;
8922 wb_info->dwb_params.scaler_taps.h_taps = 4;
8923 wb_info->dwb_params.scaler_taps.v_taps = 4;
8924 wb_info->dwb_params.scaler_taps.h_taps_c = 2;
8925 wb_info->dwb_params.scaler_taps.v_taps_c = 2;
8926 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING;
8928 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0];
8929 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1];
8931 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) {
8932 wb_info->mcif_buf_params.luma_address[i] = afb->address;
8933 wb_info->mcif_buf_params.chroma_address[i] = 0;
8936 wb_info->mcif_buf_params.p_vmid = 1;
8937 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) {
8938 wb_info->mcif_warmup_params.start_address.quad_part = afb->address;
8939 wb_info->mcif_warmup_params.region_size =
8940 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height;
8942 wb_info->mcif_warmup_params.p_vmid = 1;
8943 wb_info->writeback_source_plane = pipe->plane_state;
8945 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);
8947 acrtc->wb_pending = true;
8948 acrtc->wb_conn = wb_conn;
8949 drm_writeback_queue_job(wb_conn, new_con_state);
8953 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8954 * @state: The atomic state to commit
8956 * This will tell DC to commit the constructed DC state from atomic_check,
8957 * programming the hardware. Any failures here implies a hardware failure, since
8958 * atomic check should have filtered anything non-kosher.
8960 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8962 struct drm_device *dev = state->dev;
8963 struct amdgpu_device *adev = drm_to_adev(dev);
8964 struct amdgpu_display_manager *dm = &adev->dm;
8965 struct dm_atomic_state *dm_state;
8966 struct dc_state *dc_state = NULL;
8968 struct drm_crtc *crtc;
8969 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8970 unsigned long flags;
8971 bool wait_for_vblank = true;
8972 struct drm_connector *connector;
8973 struct drm_connector_state *old_con_state, *new_con_state;
8974 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8975 int crtc_disable_count = 0;
8977 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8979 if (dm->dc->caps.ips_support) {
8980 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8981 if (new_con_state->crtc &&
8982 new_con_state->crtc->state->active &&
8983 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8984 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
8990 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8991 drm_dp_mst_atomic_wait_for_dependencies(state);
8993 dm_state = dm_atomic_get_new_state(state);
8994 if (dm_state && dm_state->context) {
8995 dc_state = dm_state->context;
8996 amdgpu_dm_commit_streams(state, dc_state);
8999 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9000 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9001 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9002 struct amdgpu_dm_connector *aconnector;
9004 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9007 aconnector = to_amdgpu_dm_connector(connector);
9009 if (!adev->dm.hdcp_workqueue)
9012 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
9017 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
9018 connector->index, connector->status, connector->dpms);
9019 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
9020 old_con_state->content_protection, new_con_state->content_protection);
9022 if (aconnector->dc_sink) {
9023 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
9024 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
9025 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
9026 aconnector->dc_sink->edid_caps.display_name);
9030 new_crtc_state = NULL;
9031 old_crtc_state = NULL;
9034 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9035 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9039 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
9040 old_crtc_state->enable,
9041 old_crtc_state->active,
9042 old_crtc_state->mode_changed,
9043 old_crtc_state->active_changed,
9044 old_crtc_state->connectors_changed);
9047 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
9048 new_crtc_state->enable,
9049 new_crtc_state->active,
9050 new_crtc_state->mode_changed,
9051 new_crtc_state->active_changed,
9052 new_crtc_state->connectors_changed);
9055 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9056 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9057 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9058 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9060 if (!adev->dm.hdcp_workqueue)
9063 new_crtc_state = NULL;
9064 old_crtc_state = NULL;
9067 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9068 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9071 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9073 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
9074 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
9075 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
9076 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
9077 dm_new_con_state->update_hdcp = true;
9081 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
9082 old_con_state, connector, adev->dm.hdcp_workqueue)) {
9083 /* when display is unplugged from mst hub, connctor will
9084 * be destroyed within dm_dp_mst_connector_destroy. connector
9085 * hdcp perperties, like type, undesired, desired, enabled,
9086 * will be lost. So, save hdcp properties into hdcp_work within
9087 * amdgpu_dm_atomic_commit_tail. if the same display is
9088 * plugged back with same display index, its hdcp properties
9089 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
9092 bool enable_encryption = false;
9094 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
9095 enable_encryption = true;
9097 if (aconnector->dc_link && aconnector->dc_sink &&
9098 aconnector->dc_link->type == dc_connection_mst_branch) {
9099 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
9100 struct hdcp_workqueue *hdcp_w =
9101 &hdcp_work[aconnector->dc_link->link_index];
9103 hdcp_w->hdcp_content_type[connector->index] =
9104 new_con_state->hdcp_content_type;
9105 hdcp_w->content_protection[connector->index] =
9106 new_con_state->content_protection;
9109 if (new_crtc_state && new_crtc_state->mode_changed &&
9110 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
9111 enable_encryption = true;
9113 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
9115 hdcp_update_display(
9116 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
9117 new_con_state->hdcp_content_type, enable_encryption);
9121 /* Handle connector state changes */
9122 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9123 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9124 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9125 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9126 struct dc_surface_update *dummy_updates;
9127 struct dc_stream_update stream_update;
9128 struct dc_info_packet hdr_packet;
9129 struct dc_stream_status *status = NULL;
9130 bool abm_changed, hdr_changed, scaling_changed;
9132 memset(&stream_update, 0, sizeof(stream_update));
9135 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9136 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
9139 /* Skip any modesets/resets */
9140 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
9143 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9144 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9146 scaling_changed = is_scaling_state_different(dm_new_con_state,
9149 abm_changed = dm_new_crtc_state->abm_level !=
9150 dm_old_crtc_state->abm_level;
9153 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
9155 if (!scaling_changed && !abm_changed && !hdr_changed)
9158 stream_update.stream = dm_new_crtc_state->stream;
9159 if (scaling_changed) {
9160 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
9161 dm_new_con_state, dm_new_crtc_state->stream);
9163 stream_update.src = dm_new_crtc_state->stream->src;
9164 stream_update.dst = dm_new_crtc_state->stream->dst;
9168 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
9170 stream_update.abm_level = &dm_new_crtc_state->abm_level;
9174 fill_hdr_info_packet(new_con_state, &hdr_packet);
9175 stream_update.hdr_static_metadata = &hdr_packet;
9178 status = dc_stream_get_status(dm_new_crtc_state->stream);
9180 if (WARN_ON(!status))
9183 WARN_ON(!status->plane_count);
9186 * TODO: DC refuses to perform stream updates without a dc_surface_update.
9187 * Here we create an empty update on each plane.
9188 * To fix this, DC should permit updating only stream properties.
9190 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
9191 for (j = 0; j < status->plane_count; j++)
9192 dummy_updates[j].surface = status->plane_states[0];
9195 mutex_lock(&dm->dc_lock);
9196 dc_update_planes_and_stream(dm->dc,
9198 status->plane_count,
9199 dm_new_crtc_state->stream,
9201 mutex_unlock(&dm->dc_lock);
9202 kfree(dummy_updates);
9206 * Enable interrupts for CRTCs that are newly enabled or went through
9207 * a modeset. It was intentionally deferred until after the front end
9208 * state was modified to wait until the OTG was on and so the IRQ
9209 * handlers didn't access stale or invalid state.
9211 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9212 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
9213 #ifdef CONFIG_DEBUG_FS
9214 enum amdgpu_dm_pipe_crc_source cur_crc_src;
9216 /* Count number of newly disabled CRTCs for dropping PM refs later. */
9217 if (old_crtc_state->active && !new_crtc_state->active)
9218 crtc_disable_count++;
9220 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9221 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9223 /* For freesync config update on crtc state and params for irq */
9224 update_stream_irq_parameters(dm, dm_new_crtc_state);
9226 #ifdef CONFIG_DEBUG_FS
9227 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9228 cur_crc_src = acrtc->dm_irq_params.crc_src;
9229 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9232 if (new_crtc_state->active &&
9233 (!old_crtc_state->active ||
9234 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9235 dc_stream_retain(dm_new_crtc_state->stream);
9236 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
9237 manage_dm_interrupts(adev, acrtc, true);
9239 /* Handle vrr on->off / off->on transitions */
9240 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
9242 #ifdef CONFIG_DEBUG_FS
9243 if (new_crtc_state->active &&
9244 (!old_crtc_state->active ||
9245 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9247 * Frontend may have changed so reapply the CRC capture
9248 * settings for the stream.
9250 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9251 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9252 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9253 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9254 acrtc->dm_irq_params.window_param.update_win = true;
9257 * It takes 2 frames for HW to stably generate CRC when
9258 * resuming from suspend, so we set skip_frame_cnt 2.
9260 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9261 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9264 if (amdgpu_dm_crtc_configure_crc_source(
9265 crtc, dm_new_crtc_state, cur_crc_src))
9266 DRM_DEBUG_DRIVER("Failed to configure crc source");
9272 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9273 if (new_crtc_state->async_flip)
9274 wait_for_vblank = false;
9276 /* update planes when needed per crtc*/
9277 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9278 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9280 if (dm_new_crtc_state->stream)
9281 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9284 /* Enable writeback */
9285 for_each_new_connector_in_state(state, connector, new_con_state, i) {
9286 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9287 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9289 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
9292 if (!new_con_state->writeback_job)
9295 new_crtc_state = NULL;
9298 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
9300 if (acrtc->wb_enabled)
9303 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9305 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);
9306 acrtc->wb_enabled = true;
9309 /* Update audio instances for each connector. */
9310 amdgpu_dm_commit_audio(dev, state);
9312 /* restore the backlight level */
9313 for (i = 0; i < dm->num_of_edps; i++) {
9314 if (dm->backlight_dev[i] &&
9315 (dm->actual_brightness[i] != dm->brightness[i]))
9316 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9320 * send vblank event on all events not handled in flip and
9321 * mark consumed event for drm_atomic_helper_commit_hw_done
9323 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9324 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9326 if (new_crtc_state->event)
9327 drm_send_event_locked(dev, &new_crtc_state->event->base);
9329 new_crtc_state->event = NULL;
9331 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9333 /* Signal HW programming completion */
9334 drm_atomic_helper_commit_hw_done(state);
9336 if (wait_for_vblank)
9337 drm_atomic_helper_wait_for_flip_done(dev, state);
9339 drm_atomic_helper_cleanup_planes(dev, state);
9341 /* Don't free the memory if we are hitting this as part of suspend.
9342 * This way we don't free any memory during suspend; see
9343 * amdgpu_bo_free_kernel(). The memory will be freed in the first
9344 * non-suspend modeset or when the driver is torn down.
9346 if (!adev->in_suspend) {
9347 /* return the stolen vga memory back to VRAM */
9348 if (!adev->mman.keep_stolen_vga_memory)
9349 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9350 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9354 * Finally, drop a runtime PM reference for each newly disabled CRTC,
9355 * so we can put the GPU into runtime suspend if we're not driving any
9358 for (i = 0; i < crtc_disable_count; i++)
9359 pm_runtime_put_autosuspend(dev->dev);
9360 pm_runtime_mark_last_busy(dev->dev);
9363 static int dm_force_atomic_commit(struct drm_connector *connector)
9366 struct drm_device *ddev = connector->dev;
9367 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9368 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9369 struct drm_plane *plane = disconnected_acrtc->base.primary;
9370 struct drm_connector_state *conn_state;
9371 struct drm_crtc_state *crtc_state;
9372 struct drm_plane_state *plane_state;
9377 state->acquire_ctx = ddev->mode_config.acquire_ctx;
9379 /* Construct an atomic state to restore previous display setting */
9382 * Attach connectors to drm_atomic_state
9384 conn_state = drm_atomic_get_connector_state(state, connector);
9386 ret = PTR_ERR_OR_ZERO(conn_state);
9390 /* Attach crtc to drm_atomic_state*/
9391 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9393 ret = PTR_ERR_OR_ZERO(crtc_state);
9397 /* force a restore */
9398 crtc_state->mode_changed = true;
9400 /* Attach plane to drm_atomic_state */
9401 plane_state = drm_atomic_get_plane_state(state, plane);
9403 ret = PTR_ERR_OR_ZERO(plane_state);
9407 /* Call commit internally with the state we just constructed */
9408 ret = drm_atomic_commit(state);
9411 drm_atomic_state_put(state);
9413 DRM_ERROR("Restoring old state failed with %i\n", ret);
9419 * This function handles all cases when set mode does not come upon hotplug.
9420 * This includes when a display is unplugged then plugged back into the
9421 * same port and when running without usermode desktop manager supprot
9423 void dm_restore_drm_connector_state(struct drm_device *dev,
9424 struct drm_connector *connector)
9426 struct amdgpu_dm_connector *aconnector;
9427 struct amdgpu_crtc *disconnected_acrtc;
9428 struct dm_crtc_state *acrtc_state;
9430 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9433 aconnector = to_amdgpu_dm_connector(connector);
9435 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9438 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9439 if (!disconnected_acrtc)
9442 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9443 if (!acrtc_state->stream)
9447 * If the previous sink is not released and different from the current,
9448 * we deduce we are in a state where we can not rely on usermode call
9449 * to turn on the display, so we do it here
9451 if (acrtc_state->stream->sink != aconnector->dc_sink)
9452 dm_force_atomic_commit(&aconnector->base);
9456 * Grabs all modesetting locks to serialize against any blocking commits,
9457 * Waits for completion of all non blocking commits.
9459 static int do_aquire_global_lock(struct drm_device *dev,
9460 struct drm_atomic_state *state)
9462 struct drm_crtc *crtc;
9463 struct drm_crtc_commit *commit;
9467 * Adding all modeset locks to aquire_ctx will
9468 * ensure that when the framework release it the
9469 * extra locks we are locking here will get released to
9471 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9475 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9476 spin_lock(&crtc->commit_lock);
9477 commit = list_first_entry_or_null(&crtc->commit_list,
9478 struct drm_crtc_commit, commit_entry);
9480 drm_crtc_commit_get(commit);
9481 spin_unlock(&crtc->commit_lock);
9487 * Make sure all pending HW programming completed and
9490 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9493 ret = wait_for_completion_interruptible_timeout(
9494 &commit->flip_done, 10*HZ);
9497 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9498 crtc->base.id, crtc->name);
9500 drm_crtc_commit_put(commit);
9503 return ret < 0 ? ret : 0;
9506 static void get_freesync_config_for_crtc(
9507 struct dm_crtc_state *new_crtc_state,
9508 struct dm_connector_state *new_con_state)
9510 struct mod_freesync_config config = {0};
9511 struct amdgpu_dm_connector *aconnector;
9512 struct drm_display_mode *mode = &new_crtc_state->base.mode;
9513 int vrefresh = drm_mode_vrefresh(mode);
9514 bool fs_vid_mode = false;
9516 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
9519 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector);
9521 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9522 vrefresh >= aconnector->min_vfreq &&
9523 vrefresh <= aconnector->max_vfreq;
9525 if (new_crtc_state->vrr_supported) {
9526 new_crtc_state->stream->ignore_msa_timing_param = true;
9527 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9529 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9530 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9531 config.vsif_supported = true;
9535 config.state = VRR_STATE_ACTIVE_FIXED;
9536 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9538 } else if (new_crtc_state->base.vrr_enabled) {
9539 config.state = VRR_STATE_ACTIVE_VARIABLE;
9541 config.state = VRR_STATE_INACTIVE;
9545 new_crtc_state->freesync_config = config;
9548 static void reset_freesync_config_for_crtc(
9549 struct dm_crtc_state *new_crtc_state)
9551 new_crtc_state->vrr_supported = false;
9553 memset(&new_crtc_state->vrr_infopacket, 0,
9554 sizeof(new_crtc_state->vrr_infopacket));
9558 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9559 struct drm_crtc_state *new_crtc_state)
9561 const struct drm_display_mode *old_mode, *new_mode;
9563 if (!old_crtc_state || !new_crtc_state)
9566 old_mode = &old_crtc_state->mode;
9567 new_mode = &new_crtc_state->mode;
9569 if (old_mode->clock == new_mode->clock &&
9570 old_mode->hdisplay == new_mode->hdisplay &&
9571 old_mode->vdisplay == new_mode->vdisplay &&
9572 old_mode->htotal == new_mode->htotal &&
9573 old_mode->vtotal != new_mode->vtotal &&
9574 old_mode->hsync_start == new_mode->hsync_start &&
9575 old_mode->vsync_start != new_mode->vsync_start &&
9576 old_mode->hsync_end == new_mode->hsync_end &&
9577 old_mode->vsync_end != new_mode->vsync_end &&
9578 old_mode->hskew == new_mode->hskew &&
9579 old_mode->vscan == new_mode->vscan &&
9580 (old_mode->vsync_end - old_mode->vsync_start) ==
9581 (new_mode->vsync_end - new_mode->vsync_start))
9587 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9590 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9592 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9594 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9595 den = (unsigned long long)new_crtc_state->mode.htotal *
9596 (unsigned long long)new_crtc_state->mode.vtotal;
9598 res = div_u64(num, den);
9599 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9602 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9603 struct drm_atomic_state *state,
9604 struct drm_crtc *crtc,
9605 struct drm_crtc_state *old_crtc_state,
9606 struct drm_crtc_state *new_crtc_state,
9608 bool *lock_and_validation_needed)
9610 struct dm_atomic_state *dm_state = NULL;
9611 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9612 struct dc_stream_state *new_stream;
9616 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9617 * update changed items
9619 struct amdgpu_crtc *acrtc = NULL;
9620 struct drm_connector *connector = NULL;
9621 struct amdgpu_dm_connector *aconnector = NULL;
9622 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9623 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9627 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9628 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9629 acrtc = to_amdgpu_crtc(crtc);
9630 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9632 aconnector = to_amdgpu_dm_connector(connector);
9634 /* TODO This hack should go away */
9635 if (connector && enable) {
9636 /* Make sure fake sink is created in plug-in scenario */
9637 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9639 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9642 if (IS_ERR(drm_new_conn_state)) {
9643 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9647 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9648 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9650 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9653 new_stream = create_validate_stream_for_sink(aconnector,
9654 &new_crtc_state->mode,
9656 dm_old_crtc_state->stream);
9659 * we can have no stream on ACTION_SET if a display
9660 * was disconnected during S3, in this case it is not an
9661 * error, the OS will be updated after detection, and
9662 * will do the right thing on next atomic commit
9666 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9667 __func__, acrtc->base.base.id);
9673 * TODO: Check VSDB bits to decide whether this should
9674 * be enabled or not.
9676 new_stream->triggered_crtc_reset.enabled =
9677 dm->force_timing_sync;
9679 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9681 ret = fill_hdr_info_packet(drm_new_conn_state,
9682 &new_stream->hdr_static_metadata);
9687 * If we already removed the old stream from the context
9688 * (and set the new stream to NULL) then we can't reuse
9689 * the old stream even if the stream and scaling are unchanged.
9690 * We'll hit the BUG_ON and black screen.
9692 * TODO: Refactor this function to allow this check to work
9693 * in all conditions.
9695 if (dm_new_crtc_state->stream &&
9696 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9699 if (dm_new_crtc_state->stream &&
9700 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9701 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9702 new_crtc_state->mode_changed = false;
9703 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9704 new_crtc_state->mode_changed);
9708 /* mode_changed flag may get updated above, need to check again */
9709 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9712 drm_dbg_state(state->dev,
9713 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9715 new_crtc_state->enable,
9716 new_crtc_state->active,
9717 new_crtc_state->planes_changed,
9718 new_crtc_state->mode_changed,
9719 new_crtc_state->active_changed,
9720 new_crtc_state->connectors_changed);
9722 /* Remove stream for any changed/disabled CRTC */
9725 if (!dm_old_crtc_state->stream)
9728 /* Unset freesync video if it was active before */
9729 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9730 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9731 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9734 /* Now check if we should set freesync video mode */
9735 if (dm_new_crtc_state->stream &&
9736 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9737 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9738 is_timing_unchanged_for_freesync(new_crtc_state,
9740 new_crtc_state->mode_changed = false;
9742 "Mode change not required for front porch change, setting mode_changed to %d",
9743 new_crtc_state->mode_changed);
9745 set_freesync_fixed_config(dm_new_crtc_state);
9748 } else if (aconnector &&
9749 is_freesync_video_mode(&new_crtc_state->mode,
9751 struct drm_display_mode *high_mode;
9753 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9754 if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9755 set_freesync_fixed_config(dm_new_crtc_state);
9758 ret = dm_atomic_get_state(state, &dm_state);
9762 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9765 /* i.e. reset mode */
9766 if (dc_state_remove_stream(
9769 dm_old_crtc_state->stream) != DC_OK) {
9774 dc_stream_release(dm_old_crtc_state->stream);
9775 dm_new_crtc_state->stream = NULL;
9777 reset_freesync_config_for_crtc(dm_new_crtc_state);
9779 *lock_and_validation_needed = true;
9781 } else {/* Add stream for any updated/enabled CRTC */
9783 * Quick fix to prevent NULL pointer on new_stream when
9784 * added MST connectors not found in existing crtc_state in the chained mode
9785 * TODO: need to dig out the root cause of that
9790 if (modereset_required(new_crtc_state))
9793 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9794 dm_old_crtc_state->stream)) {
9796 WARN_ON(dm_new_crtc_state->stream);
9798 ret = dm_atomic_get_state(state, &dm_state);
9802 dm_new_crtc_state->stream = new_stream;
9804 dc_stream_retain(new_stream);
9806 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9809 if (dc_state_add_stream(
9812 dm_new_crtc_state->stream) != DC_OK) {
9817 *lock_and_validation_needed = true;
9822 /* Release extra reference */
9824 dc_stream_release(new_stream);
9827 * We want to do dc stream updates that do not require a
9828 * full modeset below.
9830 if (!(enable && connector && new_crtc_state->active))
9833 * Given above conditions, the dc state cannot be NULL because:
9834 * 1. We're in the process of enabling CRTCs (just been added
9835 * to the dc context, or already is on the context)
9836 * 2. Has a valid connector attached, and
9837 * 3. Is currently active and enabled.
9838 * => The dc stream state currently exists.
9840 BUG_ON(dm_new_crtc_state->stream == NULL);
9842 /* Scaling or underscan settings */
9843 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9844 drm_atomic_crtc_needs_modeset(new_crtc_state))
9845 update_stream_scaling_settings(
9846 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9849 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9852 * Color management settings. We also update color properties
9853 * when a modeset is needed, to ensure it gets reprogrammed.
9855 if (dm_new_crtc_state->base.color_mgmt_changed ||
9856 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf ||
9857 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9858 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9863 /* Update Freesync settings. */
9864 get_freesync_config_for_crtc(dm_new_crtc_state,
9871 dc_stream_release(new_stream);
9875 static bool should_reset_plane(struct drm_atomic_state *state,
9876 struct drm_plane *plane,
9877 struct drm_plane_state *old_plane_state,
9878 struct drm_plane_state *new_plane_state)
9880 struct drm_plane *other;
9881 struct drm_plane_state *old_other_state, *new_other_state;
9882 struct drm_crtc_state *new_crtc_state;
9883 struct amdgpu_device *adev = drm_to_adev(plane->dev);
9887 * TODO: Remove this hack for all asics once it proves that the
9888 * fast updates works fine on DCN3.2+.
9890 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) &&
9891 state->allow_modeset)
9894 /* Exit early if we know that we're adding or removing the plane. */
9895 if (old_plane_state->crtc != new_plane_state->crtc)
9898 /* old crtc == new_crtc == NULL, plane not in context. */
9899 if (!new_plane_state->crtc)
9903 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9905 if (!new_crtc_state)
9908 /* CRTC Degamma changes currently require us to recreate planes. */
9909 if (new_crtc_state->color_mgmt_changed)
9912 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9916 * If there are any new primary or overlay planes being added or
9917 * removed then the z-order can potentially change. To ensure
9918 * correct z-order and pipe acquisition the current DC architecture
9919 * requires us to remove and recreate all existing planes.
9921 * TODO: Come up with a more elegant solution for this.
9923 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9924 struct amdgpu_framebuffer *old_afb, *new_afb;
9925 struct dm_plane_state *dm_new_other_state, *dm_old_other_state;
9927 dm_new_other_state = to_dm_plane_state(new_other_state);
9928 dm_old_other_state = to_dm_plane_state(old_other_state);
9930 if (other->type == DRM_PLANE_TYPE_CURSOR)
9933 if (old_other_state->crtc != new_plane_state->crtc &&
9934 new_other_state->crtc != new_plane_state->crtc)
9937 if (old_other_state->crtc != new_other_state->crtc)
9940 /* Src/dst size and scaling updates. */
9941 if (old_other_state->src_w != new_other_state->src_w ||
9942 old_other_state->src_h != new_other_state->src_h ||
9943 old_other_state->crtc_w != new_other_state->crtc_w ||
9944 old_other_state->crtc_h != new_other_state->crtc_h)
9947 /* Rotation / mirroring updates. */
9948 if (old_other_state->rotation != new_other_state->rotation)
9951 /* Blending updates. */
9952 if (old_other_state->pixel_blend_mode !=
9953 new_other_state->pixel_blend_mode)
9956 /* Alpha updates. */
9957 if (old_other_state->alpha != new_other_state->alpha)
9960 /* Colorspace changes. */
9961 if (old_other_state->color_range != new_other_state->color_range ||
9962 old_other_state->color_encoding != new_other_state->color_encoding)
9965 /* HDR/Transfer Function changes. */
9966 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf ||
9967 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut ||
9968 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult ||
9969 dm_old_other_state->ctm != dm_new_other_state->ctm ||
9970 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut ||
9971 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf ||
9972 dm_old_other_state->lut3d != dm_new_other_state->lut3d ||
9973 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut ||
9974 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf)
9977 /* Framebuffer checks fall at the end. */
9978 if (!old_other_state->fb || !new_other_state->fb)
9981 /* Pixel format changes can require bandwidth updates. */
9982 if (old_other_state->fb->format != new_other_state->fb->format)
9985 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9986 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9988 /* Tiling and DCC changes also require bandwidth updates. */
9989 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9990 old_afb->base.modifier != new_afb->base.modifier)
9997 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9998 struct drm_plane_state *new_plane_state,
9999 struct drm_framebuffer *fb)
10001 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
10002 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
10003 unsigned int pitch;
10006 if (fb->width > new_acrtc->max_cursor_width ||
10007 fb->height > new_acrtc->max_cursor_height) {
10008 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
10009 new_plane_state->fb->width,
10010 new_plane_state->fb->height);
10013 if (new_plane_state->src_w != fb->width << 16 ||
10014 new_plane_state->src_h != fb->height << 16) {
10015 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
10019 /* Pitch in pixels */
10020 pitch = fb->pitches[0] / fb->format->cpp[0];
10022 if (fb->width != pitch) {
10023 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
10032 /* FB pitch is supported by cursor plane */
10035 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
10039 /* Core DRM takes care of checking FB modifiers, so we only need to
10040 * check tiling flags when the FB doesn't have a modifier.
10042 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
10043 if (adev->family < AMDGPU_FAMILY_AI) {
10044 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
10045 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
10046 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
10048 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
10051 DRM_DEBUG_ATOMIC("Cursor FB not linear");
10059 static int dm_update_plane_state(struct dc *dc,
10060 struct drm_atomic_state *state,
10061 struct drm_plane *plane,
10062 struct drm_plane_state *old_plane_state,
10063 struct drm_plane_state *new_plane_state,
10065 bool *lock_and_validation_needed,
10066 bool *is_top_most_overlay)
10069 struct dm_atomic_state *dm_state = NULL;
10070 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
10071 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10072 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
10073 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
10074 struct amdgpu_crtc *new_acrtc;
10079 new_plane_crtc = new_plane_state->crtc;
10080 old_plane_crtc = old_plane_state->crtc;
10081 dm_new_plane_state = to_dm_plane_state(new_plane_state);
10082 dm_old_plane_state = to_dm_plane_state(old_plane_state);
10084 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
10085 if (!enable || !new_plane_crtc ||
10086 drm_atomic_plane_disabling(plane->state, new_plane_state))
10089 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
10091 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
10092 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
10096 if (new_plane_state->fb) {
10097 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
10098 new_plane_state->fb);
10106 needs_reset = should_reset_plane(state, plane, old_plane_state,
10109 /* Remove any changed/removed planes */
10114 if (!old_plane_crtc)
10117 old_crtc_state = drm_atomic_get_old_crtc_state(
10118 state, old_plane_crtc);
10119 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10121 if (!dm_old_crtc_state->stream)
10124 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
10125 plane->base.id, old_plane_crtc->base.id);
10127 ret = dm_atomic_get_state(state, &dm_state);
10131 if (!dc_state_remove_plane(
10133 dm_old_crtc_state->stream,
10134 dm_old_plane_state->dc_state,
10135 dm_state->context)) {
10140 if (dm_old_plane_state->dc_state)
10141 dc_plane_state_release(dm_old_plane_state->dc_state);
10143 dm_new_plane_state->dc_state = NULL;
10145 *lock_and_validation_needed = true;
10147 } else { /* Add new planes */
10148 struct dc_plane_state *dc_new_plane_state;
10150 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
10153 if (!new_plane_crtc)
10156 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
10157 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10159 if (!dm_new_crtc_state->stream)
10165 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
10169 WARN_ON(dm_new_plane_state->dc_state);
10171 dc_new_plane_state = dc_create_plane_state(dc);
10172 if (!dc_new_plane_state)
10175 /* Block top most plane from being a video plane */
10176 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
10177 if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
10180 *is_top_most_overlay = false;
10183 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
10184 plane->base.id, new_plane_crtc->base.id);
10186 ret = fill_dc_plane_attributes(
10187 drm_to_adev(new_plane_crtc->dev),
10188 dc_new_plane_state,
10192 dc_plane_state_release(dc_new_plane_state);
10196 ret = dm_atomic_get_state(state, &dm_state);
10198 dc_plane_state_release(dc_new_plane_state);
10203 * Any atomic check errors that occur after this will
10204 * not need a release. The plane state will be attached
10205 * to the stream, and therefore part of the atomic
10206 * state. It'll be released when the atomic state is
10209 if (!dc_state_add_plane(
10211 dm_new_crtc_state->stream,
10212 dc_new_plane_state,
10213 dm_state->context)) {
10215 dc_plane_state_release(dc_new_plane_state);
10219 dm_new_plane_state->dc_state = dc_new_plane_state;
10221 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
10223 /* Tell DC to do a full surface update every time there
10224 * is a plane change. Inefficient, but works for now.
10226 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
10228 *lock_and_validation_needed = true;
10235 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
10236 int *src_w, int *src_h)
10238 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
10239 case DRM_MODE_ROTATE_90:
10240 case DRM_MODE_ROTATE_270:
10241 *src_w = plane_state->src_h >> 16;
10242 *src_h = plane_state->src_w >> 16;
10244 case DRM_MODE_ROTATE_0:
10245 case DRM_MODE_ROTATE_180:
10247 *src_w = plane_state->src_w >> 16;
10248 *src_h = plane_state->src_h >> 16;
10254 dm_get_plane_scale(struct drm_plane_state *plane_state,
10255 int *out_plane_scale_w, int *out_plane_scale_h)
10257 int plane_src_w, plane_src_h;
10259 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
10260 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
10261 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
10264 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
10265 struct drm_crtc *crtc,
10266 struct drm_crtc_state *new_crtc_state)
10268 struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
10269 struct drm_plane_state *old_plane_state, *new_plane_state;
10270 struct drm_plane_state *new_cursor_state, *new_underlying_state;
10272 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
10273 bool any_relevant_change = false;
10275 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
10276 * cursor per pipe but it's going to inherit the scaling and
10277 * positioning from the underlying pipe. Check the cursor plane's
10278 * blending properties match the underlying planes'.
10281 /* If no plane was enabled or changed scaling, no need to check again */
10282 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10283 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
10285 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
10288 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
10289 any_relevant_change = true;
10293 if (new_plane_state->fb == old_plane_state->fb &&
10294 new_plane_state->crtc_w == old_plane_state->crtc_w &&
10295 new_plane_state->crtc_h == old_plane_state->crtc_h)
10298 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10299 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10301 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10302 any_relevant_change = true;
10307 if (!any_relevant_change)
10310 new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10311 if (IS_ERR(new_cursor_state))
10312 return PTR_ERR(new_cursor_state);
10314 if (!new_cursor_state->fb)
10317 dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10319 /* Need to check all enabled planes, even if this commit doesn't change
10322 i = drm_atomic_add_affected_planes(state, crtc);
10326 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10327 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10328 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10331 /* Ignore disabled planes */
10332 if (!new_underlying_state->fb)
10335 dm_get_plane_scale(new_underlying_state,
10336 &underlying_scale_w, &underlying_scale_h);
10338 if (cursor_scale_w != underlying_scale_w ||
10339 cursor_scale_h != underlying_scale_h) {
10340 drm_dbg_atomic(crtc->dev,
10341 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10342 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10346 /* If this plane covers the whole CRTC, no need to check planes underneath */
10347 if (new_underlying_state->crtc_x <= 0 &&
10348 new_underlying_state->crtc_y <= 0 &&
10349 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10350 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10357 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10359 struct drm_connector *connector;
10360 struct drm_connector_state *conn_state, *old_conn_state;
10361 struct amdgpu_dm_connector *aconnector = NULL;
10364 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10365 if (!conn_state->crtc)
10366 conn_state = old_conn_state;
10368 if (conn_state->crtc != crtc)
10371 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
10374 aconnector = to_amdgpu_dm_connector(connector);
10375 if (!aconnector->mst_output_port || !aconnector->mst_root)
10384 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10388 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10390 * @dev: The DRM device
10391 * @state: The atomic state to commit
10393 * Validate that the given atomic state is programmable by DC into hardware.
10394 * This involves constructing a &struct dc_state reflecting the new hardware
10395 * state we wish to commit, then querying DC to see if it is programmable. It's
10396 * important not to modify the existing DC state. Otherwise, atomic_check
10397 * may unexpectedly commit hardware changes.
10399 * When validating the DC state, it's important that the right locks are
10400 * acquired. For full updates case which removes/adds/updates streams on one
10401 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10402 * that any such full update commit will wait for completion of any outstanding
10403 * flip using DRMs synchronization events.
10405 * Note that DM adds the affected connectors for all CRTCs in state, when that
10406 * might not seem necessary. This is because DC stream creation requires the
10407 * DC sink, which is tied to the DRM connector state. Cleaning this up should
10408 * be possible but non-trivial - a possible TODO item.
10410 * Return: -Error code if validation failed.
10412 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10413 struct drm_atomic_state *state)
10415 struct amdgpu_device *adev = drm_to_adev(dev);
10416 struct dm_atomic_state *dm_state = NULL;
10417 struct dc *dc = adev->dm.dc;
10418 struct drm_connector *connector;
10419 struct drm_connector_state *old_con_state, *new_con_state;
10420 struct drm_crtc *crtc;
10421 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10422 struct drm_plane *plane;
10423 struct drm_plane_state *old_plane_state, *new_plane_state;
10424 enum dc_status status;
10426 bool lock_and_validation_needed = false;
10427 bool is_top_most_overlay = true;
10428 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10429 struct drm_dp_mst_topology_mgr *mgr;
10430 struct drm_dp_mst_topology_state *mst_state;
10431 struct dsc_mst_fairness_vars vars[MAX_PIPES];
10433 trace_amdgpu_dm_atomic_check_begin(state);
10435 ret = drm_atomic_helper_check_modeset(dev, state);
10437 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10441 /* Check connector changes */
10442 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10443 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10444 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10446 /* Skip connectors that are disabled or part of modeset already. */
10447 if (!new_con_state->crtc)
10450 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10451 if (IS_ERR(new_crtc_state)) {
10452 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10453 ret = PTR_ERR(new_crtc_state);
10457 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10458 dm_old_con_state->scaling != dm_new_con_state->scaling)
10459 new_crtc_state->connectors_changed = true;
10462 if (dc_resource_is_dsc_encoding_supported(dc)) {
10463 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10464 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10465 ret = add_affected_mst_dsc_crtcs(state, crtc);
10467 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10473 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10474 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10476 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10477 !new_crtc_state->color_mgmt_changed &&
10478 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10479 dm_old_crtc_state->dsc_force_changed == false)
10482 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10484 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10488 if (!new_crtc_state->enable)
10491 ret = drm_atomic_add_affected_connectors(state, crtc);
10493 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10497 ret = drm_atomic_add_affected_planes(state, crtc);
10499 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10503 if (dm_old_crtc_state->dsc_force_changed)
10504 new_crtc_state->mode_changed = true;
10508 * Add all primary and overlay planes on the CRTC to the state
10509 * whenever a plane is enabled to maintain correct z-ordering
10510 * and to enable fast surface updates.
10512 drm_for_each_crtc(crtc, dev) {
10513 bool modified = false;
10515 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10516 if (plane->type == DRM_PLANE_TYPE_CURSOR)
10519 if (new_plane_state->crtc == crtc ||
10520 old_plane_state->crtc == crtc) {
10529 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10530 if (plane->type == DRM_PLANE_TYPE_CURSOR)
10534 drm_atomic_get_plane_state(state, plane);
10536 if (IS_ERR(new_plane_state)) {
10537 ret = PTR_ERR(new_plane_state);
10538 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10545 * DC consults the zpos (layer_index in DC terminology) to determine the
10546 * hw plane on which to enable the hw cursor (see
10547 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10548 * atomic state, so call drm helper to normalize zpos.
10550 ret = drm_atomic_normalize_zpos(dev, state);
10552 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10556 /* Remove exiting planes if they are modified */
10557 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10558 if (old_plane_state->fb && new_plane_state->fb &&
10559 get_mem_type(old_plane_state->fb) !=
10560 get_mem_type(new_plane_state->fb))
10561 lock_and_validation_needed = true;
10563 ret = dm_update_plane_state(dc, state, plane,
10567 &lock_and_validation_needed,
10568 &is_top_most_overlay);
10570 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10575 /* Disable all crtcs which require disable */
10576 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10577 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10581 &lock_and_validation_needed);
10583 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10588 /* Enable all crtcs which require enable */
10589 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10590 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10594 &lock_and_validation_needed);
10596 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10601 /* Add new/modified planes */
10602 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10603 ret = dm_update_plane_state(dc, state, plane,
10607 &lock_and_validation_needed,
10608 &is_top_most_overlay);
10610 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10615 if (dc_resource_is_dsc_encoding_supported(dc)) {
10616 ret = pre_validate_dsc(state, &dm_state, vars);
10621 /* Run this here since we want to validate the streams we created */
10622 ret = drm_atomic_helper_check_planes(dev, state);
10624 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10628 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10629 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10630 if (dm_new_crtc_state->mpo_requested)
10631 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10634 /* Check cursor planes scaling */
10635 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10636 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10638 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10643 if (state->legacy_cursor_update) {
10645 * This is a fast cursor update coming from the plane update
10646 * helper, check if it can be done asynchronously for better
10649 state->async_update =
10650 !drm_atomic_helper_async_check(dev, state);
10653 * Skip the remaining global validation if this is an async
10654 * update. Cursor updates can be done without affecting
10655 * state or bandwidth calcs and this avoids the performance
10656 * penalty of locking the private state object and
10657 * allocating a new dc_state.
10659 if (state->async_update)
10663 /* Check scaling and underscan changes*/
10664 /* TODO Removed scaling changes validation due to inability to commit
10665 * new stream into context w\o causing full reset. Need to
10666 * decide how to handle.
10668 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10669 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10670 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10671 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10673 /* Skip any modesets/resets */
10674 if (!acrtc || drm_atomic_crtc_needs_modeset(
10675 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10678 /* Skip any thing not scale or underscan changes */
10679 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10682 lock_and_validation_needed = true;
10685 /* set the slot info for each mst_state based on the link encoding format */
10686 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10687 struct amdgpu_dm_connector *aconnector;
10688 struct drm_connector *connector;
10689 struct drm_connector_list_iter iter;
10690 u8 link_coding_cap;
10692 drm_connector_list_iter_begin(dev, &iter);
10693 drm_for_each_connector_iter(connector, &iter) {
10694 if (connector->index == mst_state->mgr->conn_base_id) {
10695 aconnector = to_amdgpu_dm_connector(connector);
10696 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10697 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10702 drm_connector_list_iter_end(&iter);
10706 * Streams and planes are reset when there are changes that affect
10707 * bandwidth. Anything that affects bandwidth needs to go through
10708 * DC global validation to ensure that the configuration can be applied
10711 * We have to currently stall out here in atomic_check for outstanding
10712 * commits to finish in this case because our IRQ handlers reference
10713 * DRM state directly - we can end up disabling interrupts too early
10716 * TODO: Remove this stall and drop DM state private objects.
10718 if (lock_and_validation_needed) {
10719 ret = dm_atomic_get_state(state, &dm_state);
10721 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10725 ret = do_aquire_global_lock(dev, state);
10727 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10731 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10733 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10738 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10740 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10745 * Perform validation of MST topology in the state:
10746 * We need to perform MST atomic check before calling
10747 * dc_validate_global_state(), or there is a chance
10748 * to get stuck in an infinite loop and hang eventually.
10750 ret = drm_dp_mst_atomic_check(state);
10752 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10755 status = dc_validate_global_state(dc, dm_state->context, false);
10756 if (status != DC_OK) {
10757 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10758 dc_status_to_str(status), status);
10764 * The commit is a fast update. Fast updates shouldn't change
10765 * the DC context, affect global validation, and can have their
10766 * commit work done in parallel with other commits not touching
10767 * the same resource. If we have a new DC context as part of
10768 * the DM atomic state from validation we need to free it and
10769 * retain the existing one instead.
10771 * Furthermore, since the DM atomic state only contains the DC
10772 * context and can safely be annulled, we can free the state
10773 * and clear the associated private object now to free
10774 * some memory and avoid a possible use-after-free later.
10777 for (i = 0; i < state->num_private_objs; i++) {
10778 struct drm_private_obj *obj = state->private_objs[i].ptr;
10780 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10781 int j = state->num_private_objs-1;
10783 dm_atomic_destroy_state(obj,
10784 state->private_objs[i].state);
10786 /* If i is not at the end of the array then the
10787 * last element needs to be moved to where i was
10788 * before the array can safely be truncated.
10791 state->private_objs[i] =
10792 state->private_objs[j];
10794 state->private_objs[j].ptr = NULL;
10795 state->private_objs[j].state = NULL;
10796 state->private_objs[j].old_state = NULL;
10797 state->private_objs[j].new_state = NULL;
10799 state->num_private_objs = j;
10805 /* Store the overall update type for use later in atomic check. */
10806 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10807 struct dm_crtc_state *dm_new_crtc_state =
10808 to_dm_crtc_state(new_crtc_state);
10811 * Only allow async flips for fast updates that don't change
10812 * the FB pitch, the DCC state, rotation, etc.
10814 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10815 drm_dbg_atomic(crtc->dev,
10816 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10817 crtc->base.id, crtc->name);
10822 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10823 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10826 /* Must be success */
10829 trace_amdgpu_dm_atomic_check_finish(state, ret);
10834 if (ret == -EDEADLK)
10835 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10836 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10837 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10839 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10841 trace_amdgpu_dm_atomic_check_finish(state, ret);
10846 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10847 struct amdgpu_dm_connector *amdgpu_dm_connector)
10850 bool capable = false;
10852 if (amdgpu_dm_connector->dc_link &&
10853 dm_helpers_dp_read_dpcd(
10855 amdgpu_dm_connector->dc_link,
10856 DP_DOWN_STREAM_PORT_COUNT,
10858 sizeof(dpcd_data))) {
10859 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10865 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10866 unsigned int offset,
10867 unsigned int total_length,
10869 unsigned int length,
10870 struct amdgpu_hdmi_vsdb_info *vsdb)
10873 union dmub_rb_cmd cmd;
10874 struct dmub_cmd_send_edid_cea *input;
10875 struct dmub_cmd_edid_cea_output *output;
10877 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10880 memset(&cmd, 0, sizeof(cmd));
10882 input = &cmd.edid_cea.data.input;
10884 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10885 cmd.edid_cea.header.sub_type = 0;
10886 cmd.edid_cea.header.payload_bytes =
10887 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10888 input->offset = offset;
10889 input->length = length;
10890 input->cea_total_length = total_length;
10891 memcpy(input->payload, data, length);
10893 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10895 DRM_ERROR("EDID CEA parser failed\n");
10899 output = &cmd.edid_cea.data.output;
10901 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10902 if (!output->ack.success) {
10903 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10904 output->ack.offset);
10906 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10907 if (!output->amd_vsdb.vsdb_found)
10910 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10911 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10912 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10913 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10915 DRM_WARN("Unknown EDID CEA parser results\n");
10922 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10923 u8 *edid_ext, int len,
10924 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10928 /* send extension block to DMCU for parsing */
10929 for (i = 0; i < len; i += 8) {
10933 /* send 8 bytes a time */
10934 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10938 /* EDID block sent completed, expect result */
10939 int version, min_rate, max_rate;
10941 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10943 /* amd vsdb found */
10944 vsdb_info->freesync_supported = 1;
10945 vsdb_info->amd_vsdb_version = version;
10946 vsdb_info->min_refresh_rate_hz = min_rate;
10947 vsdb_info->max_refresh_rate_hz = max_rate;
10955 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10963 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10964 u8 *edid_ext, int len,
10965 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10969 /* send extension block to DMCU for parsing */
10970 for (i = 0; i < len; i += 8) {
10971 /* send 8 bytes a time */
10972 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10976 return vsdb_info->freesync_supported;
10979 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10980 u8 *edid_ext, int len,
10981 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10983 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10986 mutex_lock(&adev->dm.dc_lock);
10987 if (adev->dm.dmub_srv)
10988 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10990 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10991 mutex_unlock(&adev->dm.dc_lock);
10995 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10996 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10998 u8 *edid_ext = NULL;
11002 if (edid == NULL || edid->extensions == 0)
11005 /* Find DisplayID extension */
11006 for (i = 0; i < edid->extensions; i++) {
11007 edid_ext = (void *)(edid + (i + 1));
11008 if (edid_ext[0] == DISPLAYID_EXT)
11012 while (j < EDID_LENGTH) {
11013 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
11014 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
11016 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
11017 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
11018 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
11019 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
11020 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
11030 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
11031 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
11033 u8 *edid_ext = NULL;
11035 bool valid_vsdb_found = false;
11037 /*----- drm_find_cea_extension() -----*/
11038 /* No EDID or EDID extensions */
11039 if (edid == NULL || edid->extensions == 0)
11042 /* Find CEA extension */
11043 for (i = 0; i < edid->extensions; i++) {
11044 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
11045 if (edid_ext[0] == CEA_EXT)
11049 if (i == edid->extensions)
11052 /*----- cea_db_offsets() -----*/
11053 if (edid_ext[0] != CEA_EXT)
11056 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
11058 return valid_vsdb_found ? i : -ENODEV;
11062 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
11064 * @connector: Connector to query.
11065 * @edid: EDID from monitor
11067 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
11068 * track of some of the display information in the internal data struct used by
11069 * amdgpu_dm. This function checks which type of connector we need to set the
11070 * FreeSync parameters.
11072 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
11076 struct detailed_timing *timing;
11077 struct detailed_non_pixel *data;
11078 struct detailed_data_monitor_range *range;
11079 struct amdgpu_dm_connector *amdgpu_dm_connector =
11080 to_amdgpu_dm_connector(connector);
11081 struct dm_connector_state *dm_con_state = NULL;
11082 struct dc_sink *sink;
11084 struct amdgpu_device *adev = drm_to_adev(connector->dev);
11085 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
11086 bool freesync_capable = false;
11087 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
11089 if (!connector->state) {
11090 DRM_ERROR("%s - Connector has no state", __func__);
11094 sink = amdgpu_dm_connector->dc_sink ?
11095 amdgpu_dm_connector->dc_sink :
11096 amdgpu_dm_connector->dc_em_sink;
11098 if (!edid || !sink) {
11099 dm_con_state = to_dm_connector_state(connector->state);
11101 amdgpu_dm_connector->min_vfreq = 0;
11102 amdgpu_dm_connector->max_vfreq = 0;
11103 amdgpu_dm_connector->pixel_clock_mhz = 0;
11104 connector->display_info.monitor_range.min_vfreq = 0;
11105 connector->display_info.monitor_range.max_vfreq = 0;
11106 freesync_capable = false;
11111 dm_con_state = to_dm_connector_state(connector->state);
11113 if (!adev->dm.freesync_module)
11116 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
11117 || sink->sink_signal == SIGNAL_TYPE_EDP) {
11118 bool edid_check_required = false;
11121 edid_check_required = is_dp_capable_without_timing_msa(
11123 amdgpu_dm_connector);
11126 if (edid_check_required == true && (edid->version > 1 ||
11127 (edid->version == 1 && edid->revision > 1))) {
11128 for (i = 0; i < 4; i++) {
11130 timing = &edid->detailed_timings[i];
11131 data = &timing->data.other_data;
11132 range = &data->data.range;
11134 * Check if monitor has continuous frequency mode
11136 if (data->type != EDID_DETAIL_MONITOR_RANGE)
11139 * Check for flag range limits only. If flag == 1 then
11140 * no additional timing information provided.
11141 * Default GTF, GTF Secondary curve and CVT are not
11144 if (range->flags != 1)
11147 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
11148 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
11149 amdgpu_dm_connector->pixel_clock_mhz =
11150 range->pixel_clock_mhz * 10;
11152 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
11153 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
11158 if (amdgpu_dm_connector->max_vfreq -
11159 amdgpu_dm_connector->min_vfreq > 10) {
11161 freesync_capable = true;
11164 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11166 if (vsdb_info.replay_mode) {
11167 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
11168 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
11169 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
11172 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
11173 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11174 if (i >= 0 && vsdb_info.freesync_supported) {
11175 timing = &edid->detailed_timings[i];
11176 data = &timing->data.other_data;
11178 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
11179 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
11180 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
11181 freesync_capable = true;
11183 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
11184 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
11188 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
11190 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
11191 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
11192 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
11194 amdgpu_dm_connector->pack_sdp_v1_3 = true;
11195 amdgpu_dm_connector->as_type = as_type;
11196 amdgpu_dm_connector->vsdb_info = vsdb_info;
11198 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
11199 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
11200 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
11201 freesync_capable = true;
11203 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
11204 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
11210 dm_con_state->freesync_capable = freesync_capable;
11212 if (connector->vrr_capable_property)
11213 drm_connector_set_vrr_capable_property(connector,
11217 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
11219 struct amdgpu_device *adev = drm_to_adev(dev);
11220 struct dc *dc = adev->dm.dc;
11223 mutex_lock(&adev->dm.dc_lock);
11224 if (dc->current_state) {
11225 for (i = 0; i < dc->current_state->stream_count; ++i)
11226 dc->current_state->streams[i]
11227 ->triggered_crtc_reset.enabled =
11228 adev->dm.force_timing_sync;
11230 dm_enable_per_frame_crtc_master_sync(dc->current_state);
11231 dc_trigger_sync(dc, dc->current_state);
11233 mutex_unlock(&adev->dm.dc_lock);
11236 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
11237 u32 value, const char *func_name)
11239 #ifdef DM_CHECK_ADDR_0
11240 if (address == 0) {
11241 drm_err(adev_to_drm(ctx->driver_context),
11242 "invalid register write. address = 0");
11246 cgs_write_register(ctx->cgs_device, address, value);
11247 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
11250 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
11251 const char *func_name)
11254 #ifdef DM_CHECK_ADDR_0
11255 if (address == 0) {
11256 drm_err(adev_to_drm(ctx->driver_context),
11257 "invalid register read; address = 0\n");
11262 if (ctx->dmub_srv &&
11263 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
11264 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
11269 value = cgs_read_register(ctx->cgs_device, address);
11271 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
11276 int amdgpu_dm_process_dmub_aux_transfer_sync(
11277 struct dc_context *ctx,
11278 unsigned int link_index,
11279 struct aux_payload *payload,
11280 enum aux_return_code_type *operation_result)
11282 struct amdgpu_device *adev = ctx->driver_context;
11283 struct dmub_notification *p_notify = adev->dm.dmub_notify;
11286 mutex_lock(&adev->dm.dpia_aux_lock);
11287 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
11288 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
11292 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11293 DRM_ERROR("wait_for_completion_timeout timeout!");
11294 *operation_result = AUX_RET_ERROR_TIMEOUT;
11298 if (p_notify->result != AUX_RET_SUCCESS) {
11300 * Transient states before tunneling is enabled could
11301 * lead to this error. We can ignore this for now.
11303 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11304 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11305 payload->address, payload->length,
11308 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11313 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11314 if (!payload->write && p_notify->aux_reply.length &&
11315 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11317 if (payload->length != p_notify->aux_reply.length) {
11318 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11319 p_notify->aux_reply.length,
11320 payload->address, payload->length);
11321 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11325 memcpy(payload->data, p_notify->aux_reply.data,
11326 p_notify->aux_reply.length);
11330 ret = p_notify->aux_reply.length;
11331 *operation_result = p_notify->result;
11333 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11334 mutex_unlock(&adev->dm.dpia_aux_lock);
11338 int amdgpu_dm_process_dmub_set_config_sync(
11339 struct dc_context *ctx,
11340 unsigned int link_index,
11341 struct set_config_cmd_payload *payload,
11342 enum set_config_status *operation_result)
11344 struct amdgpu_device *adev = ctx->driver_context;
11345 bool is_cmd_complete;
11348 mutex_lock(&adev->dm.dpia_aux_lock);
11349 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11350 link_index, payload, adev->dm.dmub_notify);
11352 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11354 *operation_result = adev->dm.dmub_notify->sc_status;
11356 DRM_ERROR("wait_for_completion_timeout timeout!");
11358 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11361 if (!is_cmd_complete)
11362 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11363 mutex_unlock(&adev->dm.dpia_aux_lock);
11367 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11369 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11372 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11374 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);