drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 /*--------------------MES_MAP_PROCESS (PER DEBUG VMID)--------------------*/
  25
  26 #ifndef PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
  27 #define PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
  28
  29 struct pm4_mes_map_process_aldebaran {
  30         union {
  31                 union PM4_MES_TYPE_3_HEADER header;     /* header */
  32                 uint32_t ordinal1;
  33         };
  34
  35         union {
  36                 struct {
  37                         uint32_t pasid:16;          /* 0 - 15  */
  38                         uint32_t single_memops:1;   /* 16      */
  39                         uint32_t reserved1:1;       /* 17      */
  40                         uint32_t debug_vmid:4;      /* 18 - 21 */
  41                         uint32_t new_debug:1;       /* 22      */
  42                         uint32_t tmz:1;             /* 23      */
  43                         uint32_t diq_enable:1;      /* 24      */
  44                         uint32_t process_quantum:7; /* 25 - 31 */
  45                 } bitfields2;
  46                 uint32_t ordinal2;
  47         };
  48
  49         uint32_t vm_context_page_table_base_addr_lo32;
  50
  51         uint32_t vm_context_page_table_base_addr_hi32;
  52
  53         uint32_t sh_mem_bases;
  54
  55         uint32_t sh_mem_config;
  56
  57         uint32_t sq_shader_tba_lo;
  58
  59         uint32_t sq_shader_tba_hi;
  60
  61         uint32_t sq_shader_tma_lo;
  62
  63         uint32_t sq_shader_tma_hi;
  64
  65         uint32_t reserved6;
  66
  67         uint32_t gds_addr_lo;
  68
  69         uint32_t gds_addr_hi;
  70
  71         union {
  72                 struct {
  73                         uint32_t num_gws:7;
  74                         uint32_t sdma_enable:1;
  75                         uint32_t num_oac:4;
  76                         uint32_t gds_size_hi:4;
  77                         uint32_t gds_size:6;
  78                         uint32_t num_queues:10;
  79                 } bitfields14;
  80                 uint32_t ordinal14;
  81         };
  82
  83         uint32_t spi_gdbg_per_vmid_cntl;
  84
  85         uint32_t tcp_watch_cntl[4];
  86
  87         uint32_t completion_signal_lo;
  88
  89         uint32_t completion_signal_hi;
  90
  91 };
  92
  93 #endif