2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_vcn.h"
28 #include "amdgpu_pm.h"
31 #include "soc15_common.h"
33 #include "vcn/vcn_1_0_offset.h"
34 #include "vcn/vcn_1_0_sh_mask.h"
35 #include "mmhub/mmhub_9_1_offset.h"
36 #include "mmhub/mmhub_9_1_sh_mask.h"
38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
39 #include "jpeg_v1_0.h"
42 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab
43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1
44 #define mmUVD_REG_XX_MASK_1_0 0x05ac
45 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1
47 static int vcn_v1_0_stop(struct amdgpu_device *adev);
48 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
49 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
50 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
53 int inst_idx, struct dpg_pause_state *new_state);
55 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
56 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
59 * vcn_v1_0_early_init - set function pointers
61 * @handle: amdgpu_device pointer
63 * Set ring and irq function pointers
65 static int vcn_v1_0_early_init(void *handle)
67 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
69 adev->vcn.num_vcn_inst = 1;
70 adev->vcn.num_enc_rings = 2;
72 vcn_v1_0_set_dec_ring_funcs(adev);
73 vcn_v1_0_set_enc_ring_funcs(adev);
74 vcn_v1_0_set_irq_funcs(adev);
76 jpeg_v1_0_early_init(handle);
82 * vcn_v1_0_sw_init - sw init for VCN block
84 * @handle: amdgpu_device pointer
86 * Load firmware and sw initialization
88 static int vcn_v1_0_sw_init(void *handle)
90 struct amdgpu_ring *ring;
92 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
95 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
96 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
101 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
102 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
103 &adev->vcn.inst->irq);
108 r = amdgpu_vcn_sw_init(adev);
112 /* Override the work func */
113 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
115 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
116 const struct common_firmware_header *hdr;
117 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
118 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
119 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
120 adev->firmware.fw_size +=
121 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
122 DRM_INFO("PSP loading VCN firmware\n");
125 r = amdgpu_vcn_resume(adev);
129 ring = &adev->vcn.inst->ring_dec;
130 sprintf(ring->name, "vcn_dec");
131 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
132 AMDGPU_RING_PRIO_DEFAULT, NULL);
136 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
137 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
138 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
139 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
140 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
141 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
142 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
143 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
144 adev->vcn.internal.nop = adev->vcn.inst->external.nop =
145 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
147 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
148 ring = &adev->vcn.inst->ring_enc[i];
149 sprintf(ring->name, "vcn_enc%d", i);
150 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
151 AMDGPU_RING_PRIO_DEFAULT, NULL);
156 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
158 r = jpeg_v1_0_sw_init(handle);
164 * vcn_v1_0_sw_fini - sw fini for VCN block
166 * @handle: amdgpu_device pointer
168 * VCN suspend and free up sw allocation
170 static int vcn_v1_0_sw_fini(void *handle)
173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
175 r = amdgpu_vcn_suspend(adev);
179 jpeg_v1_0_sw_fini(handle);
181 r = amdgpu_vcn_sw_fini(adev);
187 * vcn_v1_0_hw_init - start and test VCN block
189 * @handle: amdgpu_device pointer
191 * Initialize the hardware, boot up the VCPU and do some testing
193 static int vcn_v1_0_hw_init(void *handle)
195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
196 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
199 r = amdgpu_ring_test_helper(ring);
203 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
204 ring = &adev->vcn.inst->ring_enc[i];
205 r = amdgpu_ring_test_helper(ring);
210 ring = &adev->jpeg.inst->ring_dec;
211 r = amdgpu_ring_test_helper(ring);
217 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
218 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
224 * vcn_v1_0_hw_fini - stop the hardware block
226 * @handle: amdgpu_device pointer
228 * Stop the VCN block, mark ring as not ready any more
230 static int vcn_v1_0_hw_fini(void *handle)
232 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234 cancel_delayed_work_sync(&adev->vcn.idle_work);
236 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
237 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
238 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
239 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
246 * vcn_v1_0_suspend - suspend VCN block
248 * @handle: amdgpu_device pointer
250 * HW fini and suspend VCN block
252 static int vcn_v1_0_suspend(void *handle)
255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
257 r = vcn_v1_0_hw_fini(adev);
261 r = amdgpu_vcn_suspend(adev);
267 * vcn_v1_0_resume - resume VCN block
269 * @handle: amdgpu_device pointer
271 * Resume firmware and hw init VCN block
273 static int vcn_v1_0_resume(void *handle)
276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
278 r = amdgpu_vcn_resume(adev);
282 r = vcn_v1_0_hw_init(adev);
288 * vcn_v1_0_mc_resume_spg_mode - memory controller programming
290 * @adev: amdgpu_device pointer
292 * Let the VCN memory controller know it's offsets
294 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
296 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
299 /* cache window 0: fw */
300 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
301 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
302 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
303 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
304 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
305 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
308 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
309 lower_32_bits(adev->vcn.inst->gpu_addr));
310 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
311 upper_32_bits(adev->vcn.inst->gpu_addr));
313 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
314 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
317 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
319 /* cache window 1: stack */
320 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
321 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
322 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
323 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
324 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
325 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
327 /* cache window 2: context */
328 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
329 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
330 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
331 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
332 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
333 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
335 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
336 adev->gfx.config.gb_addr_config);
337 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
338 adev->gfx.config.gb_addr_config);
339 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
340 adev->gfx.config.gb_addr_config);
341 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
342 adev->gfx.config.gb_addr_config);
343 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
344 adev->gfx.config.gb_addr_config);
345 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
346 adev->gfx.config.gb_addr_config);
347 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
348 adev->gfx.config.gb_addr_config);
349 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
350 adev->gfx.config.gb_addr_config);
351 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
352 adev->gfx.config.gb_addr_config);
353 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
354 adev->gfx.config.gb_addr_config);
355 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
356 adev->gfx.config.gb_addr_config);
357 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
358 adev->gfx.config.gb_addr_config);
361 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
363 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
366 /* cache window 0: fw */
367 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
368 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
369 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
371 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
372 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
374 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
378 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
379 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
380 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
381 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
383 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
384 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
387 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
389 /* cache window 1: stack */
390 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
391 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
392 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
393 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
394 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
396 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
399 /* cache window 2: context */
400 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
401 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
403 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
404 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
406 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
407 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
410 /* VCN global tiling registers */
411 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
412 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
413 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
414 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
415 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
416 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
417 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
418 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
419 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
420 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
421 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
422 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
423 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
424 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
425 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
426 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
427 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
428 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
429 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
430 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
434 * vcn_v1_0_disable_clock_gating - disable VCN clock gating
436 * @adev: amdgpu_device pointer
438 * Disable clock gating for VCN block
440 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
444 /* JPEG disable CGC */
445 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
447 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
448 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
450 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
452 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
453 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
454 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
456 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
457 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
458 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
460 /* UVD disable CGC */
461 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
462 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
463 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
465 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
467 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
468 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
469 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
471 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
472 data &= ~(UVD_CGC_GATE__SYS_MASK
473 | UVD_CGC_GATE__UDEC_MASK
474 | UVD_CGC_GATE__MPEG2_MASK
475 | UVD_CGC_GATE__REGS_MASK
476 | UVD_CGC_GATE__RBC_MASK
477 | UVD_CGC_GATE__LMI_MC_MASK
478 | UVD_CGC_GATE__LMI_UMC_MASK
479 | UVD_CGC_GATE__IDCT_MASK
480 | UVD_CGC_GATE__MPRD_MASK
481 | UVD_CGC_GATE__MPC_MASK
482 | UVD_CGC_GATE__LBSI_MASK
483 | UVD_CGC_GATE__LRBBM_MASK
484 | UVD_CGC_GATE__UDEC_RE_MASK
485 | UVD_CGC_GATE__UDEC_CM_MASK
486 | UVD_CGC_GATE__UDEC_IT_MASK
487 | UVD_CGC_GATE__UDEC_DB_MASK
488 | UVD_CGC_GATE__UDEC_MP_MASK
489 | UVD_CGC_GATE__WCB_MASK
490 | UVD_CGC_GATE__VCPU_MASK
491 | UVD_CGC_GATE__SCPU_MASK);
492 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
494 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
495 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
496 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
497 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
498 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
499 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
500 | UVD_CGC_CTRL__SYS_MODE_MASK
501 | UVD_CGC_CTRL__UDEC_MODE_MASK
502 | UVD_CGC_CTRL__MPEG2_MODE_MASK
503 | UVD_CGC_CTRL__REGS_MODE_MASK
504 | UVD_CGC_CTRL__RBC_MODE_MASK
505 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
506 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
507 | UVD_CGC_CTRL__IDCT_MODE_MASK
508 | UVD_CGC_CTRL__MPRD_MODE_MASK
509 | UVD_CGC_CTRL__MPC_MODE_MASK
510 | UVD_CGC_CTRL__LBSI_MODE_MASK
511 | UVD_CGC_CTRL__LRBBM_MODE_MASK
512 | UVD_CGC_CTRL__WCB_MODE_MASK
513 | UVD_CGC_CTRL__VCPU_MODE_MASK
514 | UVD_CGC_CTRL__SCPU_MODE_MASK);
515 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
518 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
519 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
520 | UVD_SUVD_CGC_GATE__SIT_MASK
521 | UVD_SUVD_CGC_GATE__SMP_MASK
522 | UVD_SUVD_CGC_GATE__SCM_MASK
523 | UVD_SUVD_CGC_GATE__SDB_MASK
524 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
525 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
526 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
527 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
528 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
529 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
530 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
531 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
532 | UVD_SUVD_CGC_GATE__SCLR_MASK
533 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
534 | UVD_SUVD_CGC_GATE__ENT_MASK
535 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
536 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
537 | UVD_SUVD_CGC_GATE__SITE_MASK
538 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
539 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
540 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
541 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
542 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
543 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
545 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
546 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
547 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
548 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
549 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
550 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
551 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
552 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
553 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
554 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
555 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
556 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
560 * vcn_v1_0_enable_clock_gating - enable VCN clock gating
562 * @adev: amdgpu_device pointer
564 * Enable clock gating for VCN block
566 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
570 /* enable JPEG CGC */
571 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
572 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
573 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
575 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
576 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
577 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
578 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
580 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
581 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
582 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
585 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
586 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
587 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
589 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
590 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
591 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
592 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
594 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
595 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
596 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
597 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
598 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
599 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
600 | UVD_CGC_CTRL__SYS_MODE_MASK
601 | UVD_CGC_CTRL__UDEC_MODE_MASK
602 | UVD_CGC_CTRL__MPEG2_MODE_MASK
603 | UVD_CGC_CTRL__REGS_MODE_MASK
604 | UVD_CGC_CTRL__RBC_MODE_MASK
605 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
606 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
607 | UVD_CGC_CTRL__IDCT_MODE_MASK
608 | UVD_CGC_CTRL__MPRD_MODE_MASK
609 | UVD_CGC_CTRL__MPC_MODE_MASK
610 | UVD_CGC_CTRL__LBSI_MODE_MASK
611 | UVD_CGC_CTRL__LRBBM_MODE_MASK
612 | UVD_CGC_CTRL__WCB_MODE_MASK
613 | UVD_CGC_CTRL__VCPU_MODE_MASK
614 | UVD_CGC_CTRL__SCPU_MODE_MASK);
615 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
617 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
618 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
619 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
620 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
621 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
622 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
623 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
624 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
625 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
626 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
627 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
628 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
631 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
633 uint32_t reg_data = 0;
635 /* disable JPEG CGC */
636 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
637 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
639 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
640 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
641 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
642 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
644 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
646 /* enable sw clock gating control */
647 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
648 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
650 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
651 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
652 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
653 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
654 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
655 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
656 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
657 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
658 UVD_CGC_CTRL__SYS_MODE_MASK |
659 UVD_CGC_CTRL__UDEC_MODE_MASK |
660 UVD_CGC_CTRL__MPEG2_MODE_MASK |
661 UVD_CGC_CTRL__REGS_MODE_MASK |
662 UVD_CGC_CTRL__RBC_MODE_MASK |
663 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
664 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
665 UVD_CGC_CTRL__IDCT_MODE_MASK |
666 UVD_CGC_CTRL__MPRD_MODE_MASK |
667 UVD_CGC_CTRL__MPC_MODE_MASK |
668 UVD_CGC_CTRL__LBSI_MODE_MASK |
669 UVD_CGC_CTRL__LRBBM_MODE_MASK |
670 UVD_CGC_CTRL__WCB_MODE_MASK |
671 UVD_CGC_CTRL__VCPU_MODE_MASK |
672 UVD_CGC_CTRL__SCPU_MODE_MASK);
673 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
675 /* turn off clock gating */
676 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
678 /* turn on SUVD clock gating */
679 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
681 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
682 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
685 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
689 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
690 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
691 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
692 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
693 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
694 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
695 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
696 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
697 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
698 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
699 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
700 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
702 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
703 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
705 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
706 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
707 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
708 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
709 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
710 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
711 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
712 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
713 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
714 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
715 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
716 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
717 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF);
720 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
722 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
724 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
725 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
727 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
730 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
734 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
735 /* Before power off, this indicator has to be turned on */
736 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
737 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
738 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
739 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
742 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
743 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
744 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
745 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
746 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
747 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
748 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
749 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
750 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
751 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
752 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
754 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
756 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
757 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
758 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
759 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
760 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
761 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
762 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
763 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
764 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
765 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
766 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
767 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
772 * vcn_v1_0_start - start VCN block
774 * @adev: amdgpu_device pointer
776 * Setup and start the VCN block
778 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
780 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
781 uint32_t rb_bufsz, tmp;
782 uint32_t lmi_swap_cntl;
785 /* disable byte swapping */
788 vcn_1_0_disable_static_power_gating(adev);
790 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
791 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
793 /* disable clock gating */
794 vcn_v1_0_disable_clock_gating(adev);
796 /* disable interupt */
797 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
798 ~UVD_MASTINT_EN__VCPU_EN_MASK);
800 /* initialize VCN memory controller */
801 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
802 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
803 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
804 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
805 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
806 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
809 /* swap (8 in 32) RB and IB */
812 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
814 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
815 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
816 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
817 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
819 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
820 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
821 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
822 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
823 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
825 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
826 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
827 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
828 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
829 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
831 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
832 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
833 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
834 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
836 vcn_v1_0_mc_resume_spg_mode(adev);
838 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
839 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
840 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
842 /* enable VCPU clock */
843 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
845 /* boot up the VCPU */
846 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
847 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
850 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
851 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
853 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
854 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
855 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
856 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
858 for (i = 0; i < 10; ++i) {
861 for (j = 0; j < 100; ++j) {
862 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
863 if (status & UVD_STATUS__IDLE)
868 if (status & UVD_STATUS__IDLE)
871 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
872 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
873 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
874 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
876 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
877 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
883 DRM_ERROR("VCN decode not responding, giving up!!!\n");
886 /* enable master interrupt */
887 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
888 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
890 /* enable system interrupt for JRBC, TODO: move to set interrupt*/
891 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
892 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
893 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
895 /* clear the busy bit of UVD_STATUS */
896 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
897 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
899 /* force RBC into idle state */
900 rb_bufsz = order_base_2(ring->ring_size);
901 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
902 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
903 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
904 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
905 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
906 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
908 /* set the write pointer delay */
909 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
911 /* set the wb address */
912 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
913 (upper_32_bits(ring->gpu_addr) >> 2));
915 /* program the RB_BASE for ring buffer */
916 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
917 lower_32_bits(ring->gpu_addr));
918 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
919 upper_32_bits(ring->gpu_addr));
921 /* Initialize the ring buffer's read and write pointers */
922 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
924 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
926 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
927 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
928 lower_32_bits(ring->wptr));
930 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
931 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
933 ring = &adev->vcn.inst->ring_enc[0];
934 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
935 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
936 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
937 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
938 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
940 ring = &adev->vcn.inst->ring_enc[1];
941 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
942 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
943 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
944 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
945 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
947 jpeg_v1_0_start(adev, 0);
952 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
954 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
955 uint32_t rb_bufsz, tmp;
956 uint32_t lmi_swap_cntl;
958 /* disable byte swapping */
961 vcn_1_0_enable_static_power_gating(adev);
963 /* enable dynamic power gating mode */
964 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
965 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
966 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
967 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
969 /* enable clock gating */
970 vcn_v1_0_clock_gating_dpg_mode(adev, 0);
972 /* enable VCPU clock */
973 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
974 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
975 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
976 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
978 /* disable interupt */
979 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
980 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
982 /* initialize VCN memory controller */
983 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
984 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
985 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
986 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
987 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
988 UVD_LMI_CTRL__REQ_MODE_MASK |
989 UVD_LMI_CTRL__CRC_RESET_MASK |
990 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
991 0x00100000L, 0xFFFFFFFF, 0);
994 /* swap (8 in 32) RB and IB */
997 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
999 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
1000 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1002 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
1003 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1004 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1005 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1006 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1008 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1009 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1010 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1011 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1012 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1014 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1015 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1016 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1017 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1019 vcn_v1_0_mc_resume_dpg_mode(adev);
1021 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1022 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1024 /* boot up the VCPU */
1025 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1028 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1029 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1032 /* enable master interrupt */
1033 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1034 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1036 vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1037 /* setup mmUVD_LMI_CTRL */
1038 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1039 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1040 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1041 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1042 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1043 UVD_LMI_CTRL__REQ_MODE_MASK |
1044 UVD_LMI_CTRL__CRC_RESET_MASK |
1045 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1046 0x00100000L, 0xFFFFFFFF, 1);
1048 tmp = adev->gfx.config.gb_addr_config;
1049 /* setup VCN global tiling registers */
1050 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1051 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1053 /* enable System Interrupt for JRBC */
1054 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1055 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1057 /* force RBC into idle state */
1058 rb_bufsz = order_base_2(ring->ring_size);
1059 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1064 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1066 /* set the write pointer delay */
1067 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1069 /* set the wb address */
1070 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1071 (upper_32_bits(ring->gpu_addr) >> 2));
1073 /* program the RB_BASE for ring buffer */
1074 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1075 lower_32_bits(ring->gpu_addr));
1076 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1077 upper_32_bits(ring->gpu_addr));
1079 /* Initialize the ring buffer's read and write pointers */
1080 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1082 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1084 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1085 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1086 lower_32_bits(ring->wptr));
1088 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1089 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1091 jpeg_v1_0_start(adev, 1);
1096 static int vcn_v1_0_start(struct amdgpu_device *adev)
1100 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1101 r = vcn_v1_0_start_dpg_mode(adev);
1103 r = vcn_v1_0_start_spg_mode(adev);
1108 * vcn_v1_0_stop - stop VCN block
1110 * @adev: amdgpu_device pointer
1112 * stop the VCN block
1114 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1118 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1120 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1121 UVD_LMI_STATUS__READ_CLEAN_MASK |
1122 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1123 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1124 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1126 /* stall UMC channel */
1127 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1128 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1129 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1131 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1132 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1133 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1135 /* disable VCPU clock */
1136 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1137 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1139 /* reset LMI UMC/LMI */
1140 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1141 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1142 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1144 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1145 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1146 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1148 /* put VCPU into reset */
1149 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1150 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1151 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1153 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1155 vcn_v1_0_enable_clock_gating(adev);
1156 vcn_1_0_enable_static_power_gating(adev);
1160 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1164 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1166 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1167 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1169 /* wait for read ptr to be equal to write ptr */
1170 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1171 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1173 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1174 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1176 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1179 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1180 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1182 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1183 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1184 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1186 /* disable dynamic power gating mode */
1187 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1188 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1193 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1197 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1198 r = vcn_v1_0_stop_dpg_mode(adev);
1200 r = vcn_v1_0_stop_spg_mode(adev);
1205 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
1206 int inst_idx, struct dpg_pause_state *new_state)
1209 uint32_t reg_data = 0;
1210 uint32_t reg_data2 = 0;
1211 struct amdgpu_ring *ring;
1213 /* pause/unpause if state is changed */
1214 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1215 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1216 adev->vcn.inst[inst_idx].pause_state.fw_based,
1217 adev->vcn.inst[inst_idx].pause_state.jpeg,
1218 new_state->fw_based, new_state->jpeg);
1220 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1221 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1223 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1226 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1227 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1228 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1229 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1232 /* pause DPG non-jpeg */
1233 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1234 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1235 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1236 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1237 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1240 ring = &adev->vcn.inst->ring_enc[0];
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1242 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1243 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1244 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1245 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1247 ring = &adev->vcn.inst->ring_enc[1];
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1249 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1251 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1252 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1254 ring = &adev->vcn.inst->ring_dec;
1255 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1256 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1257 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1258 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1259 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1262 /* unpause dpg non-jpeg, no need to wait */
1263 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1264 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1266 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1269 /* pause/unpause if state is changed */
1270 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1271 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1272 adev->vcn.inst[inst_idx].pause_state.fw_based,
1273 adev->vcn.inst[inst_idx].pause_state.jpeg,
1274 new_state->fw_based, new_state->jpeg);
1276 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1277 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1279 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1282 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1283 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1284 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1285 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1288 /* Make sure JPRG Snoop is disabled before sending the pause */
1289 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1290 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1291 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1293 /* pause DPG jpeg */
1294 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1295 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1296 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1297 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1298 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1301 ring = &adev->jpeg.inst->ring_dec;
1302 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1303 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1304 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1305 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1306 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1307 lower_32_bits(ring->gpu_addr));
1308 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1309 upper_32_bits(ring->gpu_addr));
1310 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1311 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1312 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1313 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1315 ring = &adev->vcn.inst->ring_dec;
1316 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1317 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1318 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1319 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1320 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1323 /* unpause dpg jpeg, no need to wait */
1324 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1325 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1327 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1333 static bool vcn_v1_0_is_idle(void *handle)
1335 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1337 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1340 static int vcn_v1_0_wait_for_idle(void *handle)
1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1351 static int vcn_v1_0_set_clockgating_state(void *handle,
1352 enum amd_clockgating_state state)
1354 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1355 bool enable = (state == AMD_CG_STATE_GATE);
1358 /* wait for STATUS to clear */
1359 if (!vcn_v1_0_is_idle(handle))
1361 vcn_v1_0_enable_clock_gating(adev);
1363 /* disable HW gating and enable Sw gating */
1364 vcn_v1_0_disable_clock_gating(adev);
1370 * vcn_v1_0_dec_ring_get_rptr - get read pointer
1372 * @ring: amdgpu_ring pointer
1374 * Returns the current hardware read pointer
1376 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1378 struct amdgpu_device *adev = ring->adev;
1380 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1384 * vcn_v1_0_dec_ring_get_wptr - get write pointer
1386 * @ring: amdgpu_ring pointer
1388 * Returns the current hardware write pointer
1390 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1392 struct amdgpu_device *adev = ring->adev;
1394 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1398 * vcn_v1_0_dec_ring_set_wptr - set write pointer
1400 * @ring: amdgpu_ring pointer
1402 * Commits the write pointer to the hardware
1404 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1406 struct amdgpu_device *adev = ring->adev;
1408 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1409 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1410 lower_32_bits(ring->wptr) | 0x80000000);
1412 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1416 * vcn_v1_0_dec_ring_insert_start - insert a start command
1418 * @ring: amdgpu_ring pointer
1420 * Write a start command to the ring.
1422 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1424 struct amdgpu_device *adev = ring->adev;
1426 amdgpu_ring_write(ring,
1427 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1428 amdgpu_ring_write(ring, 0);
1429 amdgpu_ring_write(ring,
1430 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1431 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1435 * vcn_v1_0_dec_ring_insert_end - insert a end command
1437 * @ring: amdgpu_ring pointer
1439 * Write a end command to the ring.
1441 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1443 struct amdgpu_device *adev = ring->adev;
1445 amdgpu_ring_write(ring,
1446 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1447 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1451 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1453 * @ring: amdgpu_ring pointer
1455 * @seq: sequence number
1456 * @flags: fence related flags
1458 * Write a fence and a trap command to the ring.
1460 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1463 struct amdgpu_device *adev = ring->adev;
1465 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1467 amdgpu_ring_write(ring,
1468 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1469 amdgpu_ring_write(ring, seq);
1470 amdgpu_ring_write(ring,
1471 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1472 amdgpu_ring_write(ring, addr & 0xffffffff);
1473 amdgpu_ring_write(ring,
1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1475 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1476 amdgpu_ring_write(ring,
1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1478 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1480 amdgpu_ring_write(ring,
1481 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1482 amdgpu_ring_write(ring, 0);
1483 amdgpu_ring_write(ring,
1484 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1485 amdgpu_ring_write(ring, 0);
1486 amdgpu_ring_write(ring,
1487 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1488 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1492 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1494 * @ring: amdgpu_ring pointer
1495 * @job: job to retrieve vmid from
1496 * @ib: indirect buffer to execute
1499 * Write ring commands to execute the indirect buffer
1501 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1502 struct amdgpu_job *job,
1503 struct amdgpu_ib *ib,
1506 struct amdgpu_device *adev = ring->adev;
1507 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1509 amdgpu_ring_write(ring,
1510 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1511 amdgpu_ring_write(ring, vmid);
1513 amdgpu_ring_write(ring,
1514 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1515 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1516 amdgpu_ring_write(ring,
1517 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1518 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1519 amdgpu_ring_write(ring,
1520 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1521 amdgpu_ring_write(ring, ib->length_dw);
1524 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1525 uint32_t reg, uint32_t val,
1528 struct amdgpu_device *adev = ring->adev;
1530 amdgpu_ring_write(ring,
1531 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1532 amdgpu_ring_write(ring, reg << 2);
1533 amdgpu_ring_write(ring,
1534 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1535 amdgpu_ring_write(ring, val);
1536 amdgpu_ring_write(ring,
1537 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1538 amdgpu_ring_write(ring, mask);
1539 amdgpu_ring_write(ring,
1540 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1541 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1544 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1545 unsigned vmid, uint64_t pd_addr)
1547 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1548 uint32_t data0, data1, mask;
1550 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1552 /* wait for register write */
1553 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1554 data1 = lower_32_bits(pd_addr);
1556 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1559 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1560 uint32_t reg, uint32_t val)
1562 struct amdgpu_device *adev = ring->adev;
1564 amdgpu_ring_write(ring,
1565 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1566 amdgpu_ring_write(ring, reg << 2);
1567 amdgpu_ring_write(ring,
1568 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1569 amdgpu_ring_write(ring, val);
1570 amdgpu_ring_write(ring,
1571 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1572 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1576 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1578 * @ring: amdgpu_ring pointer
1580 * Returns the current hardware enc read pointer
1582 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1584 struct amdgpu_device *adev = ring->adev;
1586 if (ring == &adev->vcn.inst->ring_enc[0])
1587 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1589 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1593 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1595 * @ring: amdgpu_ring pointer
1597 * Returns the current hardware enc write pointer
1599 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1601 struct amdgpu_device *adev = ring->adev;
1603 if (ring == &adev->vcn.inst->ring_enc[0])
1604 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1606 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1610 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1612 * @ring: amdgpu_ring pointer
1614 * Commits the enc write pointer to the hardware
1616 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1618 struct amdgpu_device *adev = ring->adev;
1620 if (ring == &adev->vcn.inst->ring_enc[0])
1621 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1622 lower_32_bits(ring->wptr));
1624 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1625 lower_32_bits(ring->wptr));
1629 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1631 * @ring: amdgpu_ring pointer
1633 * @seq: sequence number
1634 * @flags: fence related flags
1636 * Write enc a fence and a trap command to the ring.
1638 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1639 u64 seq, unsigned flags)
1641 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1643 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1644 amdgpu_ring_write(ring, addr);
1645 amdgpu_ring_write(ring, upper_32_bits(addr));
1646 amdgpu_ring_write(ring, seq);
1647 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1650 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1652 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1656 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1658 * @ring: amdgpu_ring pointer
1659 * @job: job to retrive vmid from
1660 * @ib: indirect buffer to execute
1663 * Write enc ring commands to execute the indirect buffer
1665 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1666 struct amdgpu_job *job,
1667 struct amdgpu_ib *ib,
1670 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1672 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1673 amdgpu_ring_write(ring, vmid);
1674 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1675 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1676 amdgpu_ring_write(ring, ib->length_dw);
1679 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1680 uint32_t reg, uint32_t val,
1683 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1684 amdgpu_ring_write(ring, reg << 2);
1685 amdgpu_ring_write(ring, mask);
1686 amdgpu_ring_write(ring, val);
1689 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1690 unsigned int vmid, uint64_t pd_addr)
1692 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1694 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1696 /* wait for reg writes */
1697 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1698 vmid * hub->ctx_addr_distance,
1699 lower_32_bits(pd_addr), 0xffffffff);
1702 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1703 uint32_t reg, uint32_t val)
1705 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1706 amdgpu_ring_write(ring, reg << 2);
1707 amdgpu_ring_write(ring, val);
1710 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1711 struct amdgpu_irq_src *source,
1713 enum amdgpu_interrupt_state state)
1718 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1719 struct amdgpu_irq_src *source,
1720 struct amdgpu_iv_entry *entry)
1722 DRM_DEBUG("IH: VCN TRAP\n");
1724 switch (entry->src_id) {
1726 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1729 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1732 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1735 DRM_ERROR("Unhandled interrupt: %d %d\n",
1736 entry->src_id, entry->src_data[0]);
1743 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1745 struct amdgpu_device *adev = ring->adev;
1748 WARN_ON(ring->wptr % 2 || count % 2);
1750 for (i = 0; i < count / 2; i++) {
1751 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1752 amdgpu_ring_write(ring, 0);
1756 static int vcn_v1_0_set_powergating_state(void *handle,
1757 enum amd_powergating_state state)
1759 /* This doesn't actually powergate the VCN block.
1760 * That's done in the dpm code via the SMC. This
1761 * just re-inits the block as necessary. The actual
1762 * gating still happens in the dpm code. We should
1763 * revisit this when there is a cleaner line between
1764 * the smc and the hw blocks
1767 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1769 if(state == adev->vcn.cur_state)
1772 if (state == AMD_PG_STATE_GATE)
1773 ret = vcn_v1_0_stop(adev);
1775 ret = vcn_v1_0_start(adev);
1778 adev->vcn.cur_state = state;
1782 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1784 struct amdgpu_device *adev =
1785 container_of(work, struct amdgpu_device, vcn.idle_work.work);
1786 unsigned int fences = 0, i;
1788 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1789 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1791 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1792 struct dpg_pause_state new_state;
1795 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1797 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1799 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1800 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1802 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1804 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1807 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec);
1808 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1811 amdgpu_gfx_off_ctrl(adev, true);
1812 if (adev->pm.dpm_enabled)
1813 amdgpu_dpm_enable_uvd(adev, false);
1815 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1818 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1822 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1824 struct amdgpu_device *adev = ring->adev;
1825 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
1827 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
1829 if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
1830 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1832 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1836 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1838 struct amdgpu_device *adev = ring->adev;
1841 amdgpu_gfx_off_ctrl(adev, false);
1842 if (adev->pm.dpm_enabled)
1843 amdgpu_dpm_enable_uvd(adev, true);
1845 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1846 AMD_PG_STATE_UNGATE);
1849 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1850 struct dpg_pause_state new_state;
1851 unsigned int fences = 0, i;
1853 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1854 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1857 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1859 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1861 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1862 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1864 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1866 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1867 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1868 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1869 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1871 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1875 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1877 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1878 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1881 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1883 .early_init = vcn_v1_0_early_init,
1885 .sw_init = vcn_v1_0_sw_init,
1886 .sw_fini = vcn_v1_0_sw_fini,
1887 .hw_init = vcn_v1_0_hw_init,
1888 .hw_fini = vcn_v1_0_hw_fini,
1889 .suspend = vcn_v1_0_suspend,
1890 .resume = vcn_v1_0_resume,
1891 .is_idle = vcn_v1_0_is_idle,
1892 .wait_for_idle = vcn_v1_0_wait_for_idle,
1893 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
1894 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
1895 .soft_reset = NULL /* vcn_v1_0_soft_reset */,
1896 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
1897 .set_clockgating_state = vcn_v1_0_set_clockgating_state,
1898 .set_powergating_state = vcn_v1_0_set_powergating_state,
1901 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
1902 .type = AMDGPU_RING_TYPE_VCN_DEC,
1904 .support_64bit_ptrs = false,
1905 .no_user_fence = true,
1906 .vmhub = AMDGPU_MMHUB_0,
1907 .get_rptr = vcn_v1_0_dec_ring_get_rptr,
1908 .get_wptr = vcn_v1_0_dec_ring_get_wptr,
1909 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1911 6 + 6 + /* hdp invalidate / flush */
1912 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1913 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1914 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1915 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1917 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
1918 .emit_ib = vcn_v1_0_dec_ring_emit_ib,
1919 .emit_fence = vcn_v1_0_dec_ring_emit_fence,
1920 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
1921 .test_ring = amdgpu_vcn_dec_ring_test_ring,
1922 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1923 .insert_nop = vcn_v1_0_dec_ring_insert_nop,
1924 .insert_start = vcn_v1_0_dec_ring_insert_start,
1925 .insert_end = vcn_v1_0_dec_ring_insert_end,
1926 .pad_ib = amdgpu_ring_generic_pad_ib,
1927 .begin_use = vcn_v1_0_ring_begin_use,
1928 .end_use = vcn_v1_0_ring_end_use,
1929 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
1930 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1931 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1934 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
1935 .type = AMDGPU_RING_TYPE_VCN_ENC,
1937 .nop = VCN_ENC_CMD_NO_OP,
1938 .support_64bit_ptrs = false,
1939 .no_user_fence = true,
1940 .vmhub = AMDGPU_MMHUB_0,
1941 .get_rptr = vcn_v1_0_enc_ring_get_rptr,
1942 .get_wptr = vcn_v1_0_enc_ring_get_wptr,
1943 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
1945 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1946 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1947 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
1948 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1949 1, /* vcn_v1_0_enc_ring_insert_end */
1950 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
1951 .emit_ib = vcn_v1_0_enc_ring_emit_ib,
1952 .emit_fence = vcn_v1_0_enc_ring_emit_fence,
1953 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
1954 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1955 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1956 .insert_nop = amdgpu_ring_insert_nop,
1957 .insert_end = vcn_v1_0_enc_ring_insert_end,
1958 .pad_ib = amdgpu_ring_generic_pad_ib,
1959 .begin_use = vcn_v1_0_ring_begin_use,
1960 .end_use = vcn_v1_0_ring_end_use,
1961 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
1962 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1963 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1966 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1968 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
1969 DRM_INFO("VCN decode is enabled in VM mode\n");
1972 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1976 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1977 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
1979 DRM_INFO("VCN encode is enabled in VM mode\n");
1982 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
1983 .set = vcn_v1_0_set_interrupt_state,
1984 .process = vcn_v1_0_process_interrupt,
1987 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
1989 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
1990 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
1993 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
1995 .type = AMD_IP_BLOCK_TYPE_VCN,
1999 .funcs = &vcn_v1_0_ip_funcs,