drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "atom.h"
  36 #include "amd_pcie.h"
  37
  38 #include "uvd/uvd_7_0_offset.h"
  39 #include "gc/gc_9_0_offset.h"
  40 #include "gc/gc_9_0_sh_mask.h"
  41 #include "sdma0/sdma0_4_0_offset.h"
  42 #include "sdma1/sdma1_4_0_offset.h"
  43 #include "hdp/hdp_4_0_offset.h"
  44 #include "hdp/hdp_4_0_sh_mask.h"
  45 #include "smuio/smuio_9_0_offset.h"
  46 #include "smuio/smuio_9_0_sh_mask.h"
  47 #include "nbio/nbio_7_0_default.h"
  48 #include "nbio/nbio_7_0_offset.h"
  49 #include "nbio/nbio_7_0_sh_mask.h"
  50 #include "nbio/nbio_7_0_smn.h"
  51 #include "mp/mp_9_0_offset.h"
  52
  53 #include "soc15.h"
  54 #include "soc15_common.h"
  55 #include "gfx_v9_0.h"
  56 #include "gmc_v9_0.h"
  57 #include "gfxhub_v1_0.h"
  58 #include "mmhub_v1_0.h"
  59 #include "df_v1_7.h"
  60 #include "df_v3_6.h"
  61 #include "vega10_ih.h"
  62 #include "sdma_v4_0.h"
  63 #include "uvd_v7_0.h"
  64 #include "vce_v4_0.h"
  65 #include "vcn_v1_0.h"
  66 #include "dce_virtual.h"
  67 #include "mxgpu_ai.h"
  68 #include "amdgpu_smu.h"
  69 #include "amdgpu_ras.h"
  70 #include "amdgpu_xgmi.h"
  71 #include <uapi/linux/kfd_ioctl.h>
  72
  73 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  74 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  75 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  76 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  77
  78 /* for Vega20 register name change */
  79 #define mmHDP_MEM_POWER_CTRL    0x00d4
  80 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  81 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  82 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  83 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  84 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  85 /*
  86  * Indirect registers accessor
  87  */
  88 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  89 {
  90         unsigned long flags, address, data;
  91         u32 r;
  92         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  93         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  94
  95         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  96         WREG32(address, reg);
  97         (void)RREG32(address);
  98         r = RREG32(data);
  99         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 100         return r;
 101 }
 102
 103 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 104 {
 105         unsigned long flags, address, data;
 106
 107         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 108         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 109
 110         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 111         WREG32(address, reg);
 112         (void)RREG32(address);
 113         WREG32(data, v);
 114         (void)RREG32(data);
 115         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 116 }
 117
 118 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 119 {
 120         unsigned long flags, address, data;
 121         u32 r;
 122
 123         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 124         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 125
 126         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 127         WREG32(address, ((reg) & 0x1ff));
 128         r = RREG32(data);
 129         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 130         return r;
 131 }
 132
 133 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 134 {
 135         unsigned long flags, address, data;
 136
 137         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 138         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 139
 140         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 141         WREG32(address, ((reg) & 0x1ff));
 142         WREG32(data, (v));
 143         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 144 }
 145
 146 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 147 {
 148         unsigned long flags, address, data;
 149         u32 r;
 150
 151         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 152         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 153
 154         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 155         WREG32(address, (reg));
 156         r = RREG32(data);
 157         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 158         return r;
 159 }
 160
 161 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 162 {
 163         unsigned long flags, address, data;
 164
 165         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 166         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 167
 168         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 169         WREG32(address, (reg));
 170         WREG32(data, (v));
 171         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 172 }
 173
 174 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 175 {
 176         unsigned long flags;
 177         u32 r;
 178
 179         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 180         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 181         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 182         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 183         return r;
 184 }
 185
 186 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 187 {
 188         unsigned long flags;
 189
 190         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 191         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 192         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 193         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 194 }
 195
 196 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 197 {
 198         unsigned long flags;
 199         u32 r;
 200
 201         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 202         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 203         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 204         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 205         return r;
 206 }
 207
 208 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 209 {
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 213         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 214         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 215         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 216 }
 217
 218 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 219 {
 220         return adev->nbio_funcs->get_memsize(adev);
 221 }
 222
 223 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 224 {
 225         return adev->clock.spll.reference_freq;
 226 }
 227
 228
 229 void soc15_grbm_select(struct amdgpu_device *adev,
 230                      u32 me, u32 pipe, u32 queue, u32 vmid)
 231 {
 232         u32 grbm_gfx_cntl = 0;
 233         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 234         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 235         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 236         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 237
 238         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 239 }
 240
 241 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 242 {
 243         /* todo */
 244 }
 245
 246 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 247 {
 248         /* todo */
 249         return false;
 250 }
 251
 252 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 253                                      u8 *bios, u32 length_bytes)
 254 {
 255         u32 *dw_ptr;
 256         u32 i, length_dw;
 257
 258         if (bios == NULL)
 259                 return false;
 260         if (length_bytes == 0)
 261                 return false;
 262         /* APU vbios image is part of sbios image */
 263         if (adev->flags & AMD_IS_APU)
 264                 return false;
 265
 266         dw_ptr = (u32 *)bios;
 267         length_dw = ALIGN(length_bytes, 4) / 4;
 268
 269         /* set rom index to 0 */
 270         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 271         /* read out the rom data */
 272         for (i = 0; i < length_dw; i++)
 273                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 274
 275         return true;
 276 }
 277
 278 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 279         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 280         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 281         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 282         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 283         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 284         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 285         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 286         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 287         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 288         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 289         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 290         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 291         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 292         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 293         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 294         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 295         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 296         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 297         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 298 };
 299
 300 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 301                                          u32 sh_num, u32 reg_offset)
 302 {
 303         uint32_t val;
 304
 305         mutex_lock(&adev->grbm_idx_mutex);
 306         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 307                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 308
 309         val = RREG32(reg_offset);
 310
 311         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 312                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 313         mutex_unlock(&adev->grbm_idx_mutex);
 314         return val;
 315 }
 316
 317 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 318                                          bool indexed, u32 se_num,
 319                                          u32 sh_num, u32 reg_offset)
 320 {
 321         if (indexed) {
 322                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 323         } else {
 324                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 325                         return adev->gfx.config.gb_addr_config;
 326                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 327                         return adev->gfx.config.db_debug2;
 328                 return RREG32(reg_offset);
 329         }
 330 }
 331
 332 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 333                             u32 sh_num, u32 reg_offset, u32 *value)
 334 {
 335         uint32_t i;
 336         struct soc15_allowed_register_entry  *en;
 337
 338         *value = 0;
 339         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 340                 en = &soc15_allowed_read_registers[i];
 341                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 342                                         + en->reg_offset))
 343                         continue;
 344
 345                 *value = soc15_get_register_value(adev,
 346                                                   soc15_allowed_read_registers[i].grbm_indexed,
 347                                                   se_num, sh_num, reg_offset);
 348                 return 0;
 349         }
 350         return -EINVAL;
 351 }
 352
 353
 354 /**
 355  * soc15_program_register_sequence - program an array of registers.
 356  *
 357  * @adev: amdgpu_device pointer
 358  * @regs: pointer to the register array
 359  * @array_size: size of the register array
 360  *
 361  * Programs an array or registers with and and or masks.
 362  * This is a helper for setting golden registers.
 363  */
 364
 365 void soc15_program_register_sequence(struct amdgpu_device *adev,
 366                                              const struct soc15_reg_golden *regs,
 367                                              const u32 array_size)
 368 {
 369         const struct soc15_reg_golden *entry;
 370         u32 tmp, reg;
 371         int i;
 372
 373         for (i = 0; i < array_size; ++i) {
 374                 entry = &regs[i];
 375                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 376
 377                 if (entry->and_mask == 0xffffffff) {
 378                         tmp = entry->or_mask;
 379                 } else {
 380                         tmp = RREG32(reg);
 381                         tmp &= ~(entry->and_mask);
 382                         tmp |= (entry->or_mask & entry->and_mask);
 383                 }
 384
 385                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 386                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 387                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 388                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 389                         WREG32_RLC(reg, tmp);
 390                 else
 391                         WREG32(reg, tmp);
 392
 393         }
 394
 395 }
 396
 397 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 398 {
 399         u32 i;
 400         int ret = 0;
 401
 402         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 403
 404         dev_info(adev->dev, "GPU mode1 reset\n");
 405
 406         /* disable BM */
 407         pci_clear_master(adev->pdev);
 408
 409         pci_save_state(adev->pdev);
 410
 411         ret = psp_gpu_reset(adev);
 412         if (ret)
 413                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 414
 415         pci_restore_state(adev->pdev);
 416
 417         /* wait for asic to come out of reset */
 418         for (i = 0; i < adev->usec_timeout; i++) {
 419                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 420
 421                 if (memsize != 0xffffffff)
 422                         break;
 423                 udelay(1);
 424         }
 425
 426         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 427
 428         return ret;
 429 }
 430
 431 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
 432 {
 433         void *pp_handle = adev->powerplay.pp_handle;
 434         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 435
 436         if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
 437                 *cap = false;
 438                 return -ENOENT;
 439         }
 440
 441         return pp_funcs->get_asic_baco_capability(pp_handle, cap);
 442 }
 443
 444 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 445 {
 446         void *pp_handle = adev->powerplay.pp_handle;
 447         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 448
 449         if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
 450                 return -ENOENT;
 451
 452         /* enter BACO state */
 453         if (pp_funcs->set_asic_baco_state(pp_handle, 1))
 454                 return -EIO;
 455
 456         /* exit BACO state */
 457         if (pp_funcs->set_asic_baco_state(pp_handle, 0))
 458                 return -EIO;
 459
 460         dev_info(adev->dev, "GPU BACO reset\n");
 461
 462         adev->in_baco_reset = 1;
 463
 464         return 0;
 465 }
 466
 467 static int soc15_asic_reset(struct amdgpu_device *adev)
 468 {
 469         int ret;
 470         bool baco_reset;
 471
 472         switch (adev->asic_type) {
 473         case CHIP_VEGA10:
 474         case CHIP_VEGA12:
 475                 soc15_asic_get_baco_capability(adev, &baco_reset);
 476                 break;
 477         case CHIP_VEGA20:
 478                 if (adev->psp.sos_fw_version >= 0x80067)
 479                         soc15_asic_get_baco_capability(adev, &baco_reset);
 480                 else
 481                         baco_reset = false;
 482                 if (baco_reset) {
 483                         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
 484                         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 485
 486                         if (hive || (ras && ras->supported))
 487                                 baco_reset = false;
 488                 }
 489                 break;
 490         default:
 491                 baco_reset = false;
 492                 break;
 493         }
 494
 495         if (baco_reset)
 496                 ret = soc15_asic_baco_reset(adev);
 497         else
 498                 ret = soc15_asic_mode1_reset(adev);
 499
 500         return ret;
 501 }
 502
 503 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 504                         u32 cntl_reg, u32 status_reg)
 505 {
 506         return 0;
 507 }*/
 508
 509 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 510 {
 511         /*int r;
 512
 513         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 514         if (r)
 515                 return r;
 516
 517         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 518         */
 519         return 0;
 520 }
 521
 522 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 523 {
 524         /* todo */
 525
 526         return 0;
 527 }
 528
 529 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 530 {
 531         if (pci_is_root_bus(adev->pdev->bus))
 532                 return;
 533
 534         if (amdgpu_pcie_gen2 == 0)
 535                 return;
 536
 537         if (adev->flags & AMD_IS_APU)
 538                 return;
 539
 540         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 541                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 542                 return;
 543
 544         /* todo */
 545 }
 546
 547 static void soc15_program_aspm(struct amdgpu_device *adev)
 548 {
 549
 550         if (amdgpu_aspm == 0)
 551                 return;
 552
 553         /* todo */
 554 }
 555
 556 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 557                                            bool enable)
 558 {
 559         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 560         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 561 }
 562
 563 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 564 {
 565         .type = AMD_IP_BLOCK_TYPE_COMMON,
 566         .major = 2,
 567         .minor = 0,
 568         .rev = 0,
 569         .funcs = &soc15_common_ip_funcs,
 570 };
 571
 572 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 573 {
 574         return adev->nbio_funcs->get_rev_id(adev);
 575 }
 576
 577 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 578 {
 579         /* Set IP register base before any HW register access */
 580         switch (adev->asic_type) {
 581         case CHIP_VEGA10:
 582         case CHIP_VEGA12:
 583         case CHIP_RAVEN:
 584                 vega10_reg_base_init(adev);
 585                 break;
 586         case CHIP_VEGA20:
 587                 vega20_reg_base_init(adev);
 588                 break;
 589         default:
 590                 return -EINVAL;
 591         }
 592
 593         if (adev->asic_type == CHIP_VEGA20)
 594                 adev->gmc.xgmi.supported = true;
 595
 596         if (adev->flags & AMD_IS_APU)
 597                 adev->nbio_funcs = &nbio_v7_0_funcs;
 598         else if (adev->asic_type == CHIP_VEGA20)
 599                 adev->nbio_funcs = &nbio_v7_4_funcs;
 600         else
 601                 adev->nbio_funcs = &nbio_v6_1_funcs;
 602
 603         if (adev->asic_type == CHIP_VEGA20)
 604                 adev->df_funcs = &df_v3_6_funcs;
 605         else
 606                 adev->df_funcs = &df_v1_7_funcs;
 607
 608         adev->rev_id = soc15_get_rev_id(adev);
 609         adev->nbio_funcs->detect_hw_virt(adev);
 610
 611         if (amdgpu_sriov_vf(adev))
 612                 adev->virt.ops = &xgpu_ai_virt_ops;
 613
 614         switch (adev->asic_type) {
 615         case CHIP_VEGA10:
 616         case CHIP_VEGA12:
 617         case CHIP_VEGA20:
 618                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 619                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 620
 621                 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
 622                 if (amdgpu_sriov_vf(adev)) {
 623                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 624                                 if (adev->asic_type == CHIP_VEGA20)
 625                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 626                                 else
 627                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 628                         }
 629                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 630                 } else {
 631                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 632                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 633                                 if (adev->asic_type == CHIP_VEGA20)
 634                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 635                                 else
 636                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 637                         }
 638                 }
 639                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 640                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 641                 if (!amdgpu_sriov_vf(adev)) {
 642                         if (is_support_sw_smu(adev))
 643                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 644                         else
 645                                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 646                 }
 647                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 648                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 649 #if defined(CONFIG_DRM_AMD_DC)
 650                 else if (amdgpu_device_has_dc_support(adev))
 651                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 652 #endif
 653                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 654                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 655                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 656                 }
 657                 break;
 658         case CHIP_RAVEN:
 659                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 660                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 661                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 662                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 663                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 664                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 665                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 666                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 667                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 668                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 669 #if defined(CONFIG_DRM_AMD_DC)
 670                 else if (amdgpu_device_has_dc_support(adev))
 671                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 672 #endif
 673                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 674                 break;
 675         default:
 676                 return -EINVAL;
 677         }
 678
 679         return 0;
 680 }
 681
 682 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 683 {
 684         adev->nbio_funcs->hdp_flush(adev, ring);
 685 }
 686
 687 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 688                                  struct amdgpu_ring *ring)
 689 {
 690         if (!ring || !ring->funcs->emit_wreg)
 691                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 692         else
 693                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 694                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 695 }
 696
 697 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 698 {
 699         /* change this when we implement soft reset */
 700         return true;
 701 }
 702 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 703                                  uint64_t *count1)
 704 {
 705         uint32_t perfctr = 0;
 706         uint64_t cnt0_of, cnt1_of;
 707         int tmp;
 708
 709         /* This reports 0 on APUs, so return to avoid writing/reading registers
 710          * that may or may not be different from their GPU counterparts
 711          */
 712         if (adev->flags & AMD_IS_APU)
 713                 return;
 714
 715         /* Set the 2 events that we wish to watch, defined above */
 716         /* Reg 40 is # received msgs */
 717         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 718         /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
 719         if (adev->asic_type == CHIP_VEGA20)
 720                 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
 721                                         EVENT1_SEL, 108);
 722         else
 723                 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
 724                                         EVENT1_SEL, 104);
 725
 726         /* Write to enable desired perf counters */
 727         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 728         /* Zero out and enable the perf counters
 729          * Write 0x5:
 730          * Bit 0 = Start all counters(1)
 731          * Bit 2 = Global counter reset enable(1)
 732          */
 733         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 734
 735         msleep(1000);
 736
 737         /* Load the shadow and disable the perf counters
 738          * Write 0x2:
 739          * Bit 0 = Stop counters(0)
 740          * Bit 1 = Load the shadow counters(1)
 741          */
 742         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 743
 744         /* Read register values to get any >32bit overflow */
 745         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 746         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 747         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 748
 749         /* Get the values and add the overflow */
 750         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 751         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 752 }
 753
 754 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 755 {
 756         u32 sol_reg;
 757
 758         /* Just return false for soc15 GPUs.  Reset does not seem to
 759          * be necessary.
 760          */
 761         if (!amdgpu_passthrough(adev))
 762                 return false;
 763
 764         if (adev->flags & AMD_IS_APU)
 765                 return false;
 766
 767         /* Check sOS sign of life register to confirm sys driver and sOS
 768          * are already been loaded.
 769          */
 770         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 771         if (sol_reg)
 772                 return true;
 773
 774         return false;
 775 }
 776
 777 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 778 {
 779         uint64_t nak_r, nak_g;
 780
 781         /* Get the number of NAKs received and generated */
 782         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 783         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 784
 785         /* Add the total number of NAKs, i.e the number of replays */
 786         return (nak_r + nak_g);
 787 }
 788
 789 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 790 {
 791         .read_disabled_bios = &soc15_read_disabled_bios,
 792         .read_bios_from_rom = &soc15_read_bios_from_rom,
 793         .read_register = &soc15_read_register,
 794         .reset = &soc15_asic_reset,
 795         .set_vga_state = &soc15_vga_set_state,
 796         .get_xclk = &soc15_get_xclk,
 797         .set_uvd_clocks = &soc15_set_uvd_clocks,
 798         .set_vce_clocks = &soc15_set_vce_clocks,
 799         .get_config_memsize = &soc15_get_config_memsize,
 800         .flush_hdp = &soc15_flush_hdp,
 801         .invalidate_hdp = &soc15_invalidate_hdp,
 802         .need_full_reset = &soc15_need_full_reset,
 803         .init_doorbell_index = &vega10_doorbell_index_init,
 804         .get_pcie_usage = &soc15_get_pcie_usage,
 805         .need_reset_on_init = &soc15_need_reset_on_init,
 806         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 807 };
 808
 809 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 810 {
 811         .read_disabled_bios = &soc15_read_disabled_bios,
 812         .read_bios_from_rom = &soc15_read_bios_from_rom,
 813         .read_register = &soc15_read_register,
 814         .reset = &soc15_asic_reset,
 815         .set_vga_state = &soc15_vga_set_state,
 816         .get_xclk = &soc15_get_xclk,
 817         .set_uvd_clocks = &soc15_set_uvd_clocks,
 818         .set_vce_clocks = &soc15_set_vce_clocks,
 819         .get_config_memsize = &soc15_get_config_memsize,
 820         .flush_hdp = &soc15_flush_hdp,
 821         .invalidate_hdp = &soc15_invalidate_hdp,
 822         .need_full_reset = &soc15_need_full_reset,
 823         .init_doorbell_index = &vega20_doorbell_index_init,
 824         .get_pcie_usage = &soc15_get_pcie_usage,
 825         .need_reset_on_init = &soc15_need_reset_on_init,
 826         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 827 };
 828
 829 static int soc15_common_early_init(void *handle)
 830 {
 831 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 832         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 833
 834         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 835         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 836         adev->smc_rreg = NULL;
 837         adev->smc_wreg = NULL;
 838         adev->pcie_rreg = &soc15_pcie_rreg;
 839         adev->pcie_wreg = &soc15_pcie_wreg;
 840         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 841         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 842         adev->didt_rreg = &soc15_didt_rreg;
 843         adev->didt_wreg = &soc15_didt_wreg;
 844         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 845         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 846         adev->se_cac_rreg = &soc15_se_cac_rreg;
 847         adev->se_cac_wreg = &soc15_se_cac_wreg;
 848
 849
 850         adev->external_rev_id = 0xFF;
 851         switch (adev->asic_type) {
 852         case CHIP_VEGA10:
 853                 adev->asic_funcs = &soc15_asic_funcs;
 854                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 855                         AMD_CG_SUPPORT_GFX_MGLS |
 856                         AMD_CG_SUPPORT_GFX_RLC_LS |
 857                         AMD_CG_SUPPORT_GFX_CP_LS |
 858                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 859                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 860                         AMD_CG_SUPPORT_GFX_CGCG |
 861                         AMD_CG_SUPPORT_GFX_CGLS |
 862                         AMD_CG_SUPPORT_BIF_MGCG |
 863                         AMD_CG_SUPPORT_BIF_LS |
 864                         AMD_CG_SUPPORT_HDP_LS |
 865                         AMD_CG_SUPPORT_DRM_MGCG |
 866                         AMD_CG_SUPPORT_DRM_LS |
 867                         AMD_CG_SUPPORT_ROM_MGCG |
 868                         AMD_CG_SUPPORT_DF_MGCG |
 869                         AMD_CG_SUPPORT_SDMA_MGCG |
 870                         AMD_CG_SUPPORT_SDMA_LS |
 871                         AMD_CG_SUPPORT_MC_MGCG |
 872                         AMD_CG_SUPPORT_MC_LS;
 873                 adev->pg_flags = 0;
 874                 adev->external_rev_id = 0x1;
 875                 break;
 876         case CHIP_VEGA12:
 877                 adev->asic_funcs = &soc15_asic_funcs;
 878                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 879                         AMD_CG_SUPPORT_GFX_MGLS |
 880                         AMD_CG_SUPPORT_GFX_CGCG |
 881                         AMD_CG_SUPPORT_GFX_CGLS |
 882                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 883                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 884                         AMD_CG_SUPPORT_GFX_CP_LS |
 885                         AMD_CG_SUPPORT_MC_LS |
 886                         AMD_CG_SUPPORT_MC_MGCG |
 887                         AMD_CG_SUPPORT_SDMA_MGCG |
 888                         AMD_CG_SUPPORT_SDMA_LS |
 889                         AMD_CG_SUPPORT_BIF_MGCG |
 890                         AMD_CG_SUPPORT_BIF_LS |
 891                         AMD_CG_SUPPORT_HDP_MGCG |
 892                         AMD_CG_SUPPORT_HDP_LS |
 893                         AMD_CG_SUPPORT_ROM_MGCG |
 894                         AMD_CG_SUPPORT_VCE_MGCG |
 895                         AMD_CG_SUPPORT_UVD_MGCG;
 896                 adev->pg_flags = 0;
 897                 adev->external_rev_id = adev->rev_id + 0x14;
 898                 break;
 899         case CHIP_VEGA20:
 900                 adev->asic_funcs = &vega20_asic_funcs;
 901                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 902                         AMD_CG_SUPPORT_GFX_MGLS |
 903                         AMD_CG_SUPPORT_GFX_CGCG |
 904                         AMD_CG_SUPPORT_GFX_CGLS |
 905                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 906                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 907                         AMD_CG_SUPPORT_GFX_CP_LS |
 908                         AMD_CG_SUPPORT_MC_LS |
 909                         AMD_CG_SUPPORT_MC_MGCG |
 910                         AMD_CG_SUPPORT_SDMA_MGCG |
 911                         AMD_CG_SUPPORT_SDMA_LS |
 912                         AMD_CG_SUPPORT_BIF_MGCG |
 913                         AMD_CG_SUPPORT_BIF_LS |
 914                         AMD_CG_SUPPORT_HDP_MGCG |
 915                         AMD_CG_SUPPORT_HDP_LS |
 916                         AMD_CG_SUPPORT_ROM_MGCG |
 917                         AMD_CG_SUPPORT_VCE_MGCG |
 918                         AMD_CG_SUPPORT_UVD_MGCG;
 919                 adev->pg_flags = 0;
 920                 adev->external_rev_id = adev->rev_id + 0x28;
 921                 break;
 922         case CHIP_RAVEN:
 923                 adev->asic_funcs = &soc15_asic_funcs;
 924                 if (adev->rev_id >= 0x8)
 925                         adev->external_rev_id = adev->rev_id + 0x79;
 926                 else if (adev->pdev->device == 0x15d8)
 927                         adev->external_rev_id = adev->rev_id + 0x41;
 928                 else if (adev->rev_id == 1)
 929                         adev->external_rev_id = adev->rev_id + 0x20;
 930                 else
 931                         adev->external_rev_id = adev->rev_id + 0x01;
 932
 933                 if (adev->rev_id >= 0x8) {
 934                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 935                                 AMD_CG_SUPPORT_GFX_MGLS |
 936                                 AMD_CG_SUPPORT_GFX_CP_LS |
 937                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 938                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 939                                 AMD_CG_SUPPORT_GFX_CGCG |
 940                                 AMD_CG_SUPPORT_GFX_CGLS |
 941                                 AMD_CG_SUPPORT_BIF_LS |
 942                                 AMD_CG_SUPPORT_HDP_LS |
 943                                 AMD_CG_SUPPORT_ROM_MGCG |
 944                                 AMD_CG_SUPPORT_MC_MGCG |
 945                                 AMD_CG_SUPPORT_MC_LS |
 946                                 AMD_CG_SUPPORT_SDMA_MGCG |
 947                                 AMD_CG_SUPPORT_SDMA_LS |
 948                                 AMD_CG_SUPPORT_VCN_MGCG;
 949
 950                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 951                 } else if (adev->pdev->device == 0x15d8) {
 952                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 953                                 AMD_CG_SUPPORT_GFX_MGLS |
 954                                 AMD_CG_SUPPORT_GFX_CP_LS |
 955                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 956                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 957                                 AMD_CG_SUPPORT_GFX_CGCG |
 958                                 AMD_CG_SUPPORT_GFX_CGLS |
 959                                 AMD_CG_SUPPORT_BIF_LS |
 960                                 AMD_CG_SUPPORT_HDP_LS |
 961                                 AMD_CG_SUPPORT_ROM_MGCG |
 962                                 AMD_CG_SUPPORT_MC_MGCG |
 963                                 AMD_CG_SUPPORT_MC_LS |
 964                                 AMD_CG_SUPPORT_SDMA_MGCG |
 965                                 AMD_CG_SUPPORT_SDMA_LS;
 966
 967                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
 968                                 AMD_PG_SUPPORT_MMHUB |
 969                                 AMD_PG_SUPPORT_VCN |
 970                                 AMD_PG_SUPPORT_VCN_DPG;
 971                 } else {
 972                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 973                                 AMD_CG_SUPPORT_GFX_MGLS |
 974                                 AMD_CG_SUPPORT_GFX_RLC_LS |
 975                                 AMD_CG_SUPPORT_GFX_CP_LS |
 976                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 977                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 978                                 AMD_CG_SUPPORT_GFX_CGCG |
 979                                 AMD_CG_SUPPORT_GFX_CGLS |
 980                                 AMD_CG_SUPPORT_BIF_MGCG |
 981                                 AMD_CG_SUPPORT_BIF_LS |
 982                                 AMD_CG_SUPPORT_HDP_MGCG |
 983                                 AMD_CG_SUPPORT_HDP_LS |
 984                                 AMD_CG_SUPPORT_DRM_MGCG |
 985                                 AMD_CG_SUPPORT_DRM_LS |
 986                                 AMD_CG_SUPPORT_ROM_MGCG |
 987                                 AMD_CG_SUPPORT_MC_MGCG |
 988                                 AMD_CG_SUPPORT_MC_LS |
 989                                 AMD_CG_SUPPORT_SDMA_MGCG |
 990                                 AMD_CG_SUPPORT_SDMA_LS |
 991                                 AMD_CG_SUPPORT_VCN_MGCG;
 992
 993                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 994                 }
 995
 996                 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 997                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 998                                 AMD_PG_SUPPORT_CP |
 999                                 AMD_PG_SUPPORT_RLC_SMU_HS;
1000                 break;
1001         default:
1002                 /* FIXME: not supported yet */
1003                 return -EINVAL;
1004         }
1005
1006         if (amdgpu_sriov_vf(adev)) {
1007                 amdgpu_virt_init_setting(adev);
1008                 xgpu_ai_mailbox_set_irq_funcs(adev);
1009         }
1010
1011         return 0;
1012 }
1013
1014 static int soc15_common_late_init(void *handle)
1015 {
1016         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017
1018         if (amdgpu_sriov_vf(adev))
1019                 xgpu_ai_mailbox_get_irq(adev);
1020
1021         return 0;
1022 }
1023
1024 static int soc15_common_sw_init(void *handle)
1025 {
1026         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028         if (amdgpu_sriov_vf(adev))
1029                 xgpu_ai_mailbox_add_irq_id(adev);
1030
1031         adev->df_funcs->sw_init(adev);
1032
1033         return 0;
1034 }
1035
1036 static int soc15_common_sw_fini(void *handle)
1037 {
1038         return 0;
1039 }
1040
1041 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1042 {
1043         int i;
1044         struct amdgpu_ring *ring;
1045
1046         /*  Two reasons to skip
1047         *               1, Host driver already programmed them
1048         *               2, To avoid registers program violations in SR-IOV
1049         */
1050         if (!amdgpu_virt_support_skip_setting(adev)) {
1051                 for (i = 0; i < adev->sdma.num_instances; i++) {
1052                         ring = &adev->sdma.instance[i].ring;
1053                         adev->nbio_funcs->sdma_doorbell_range(adev, i,
1054                                 ring->use_doorbell, ring->doorbell_index,
1055                                 adev->doorbell_index.sdma_doorbell_range);
1056                 }
1057         }
1058
1059         adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1060                                                 adev->irq.ih.doorbell_index);
1061 }
1062
1063 static int soc15_common_hw_init(void *handle)
1064 {
1065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1066
1067         /* enable pcie gen2/3 link */
1068         soc15_pcie_gen3_enable(adev);
1069         /* enable aspm */
1070         soc15_program_aspm(adev);
1071         /* setup nbio registers */
1072         adev->nbio_funcs->init_registers(adev);
1073         /* remap HDP registers to a hole in mmio space,
1074          * for the purpose of expose those registers
1075          * to process space
1076          */
1077         if (adev->nbio_funcs->remap_hdp_registers)
1078                 adev->nbio_funcs->remap_hdp_registers(adev);
1079
1080         /* enable the doorbell aperture */
1081         soc15_enable_doorbell_aperture(adev, true);
1082         /* HW doorbell routing policy: doorbell writing not
1083          * in SDMA/IH/MM/ACV range will be routed to CP. So
1084          * we need to init SDMA/IH/MM/ACV doorbell range prior
1085          * to CP ip block init and ring test.
1086          */
1087         soc15_doorbell_range_init(adev);
1088
1089         return 0;
1090 }
1091
1092 static int soc15_common_hw_fini(void *handle)
1093 {
1094         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1095
1096         /* disable the doorbell aperture */
1097         soc15_enable_doorbell_aperture(adev, false);
1098         if (amdgpu_sriov_vf(adev))
1099                 xgpu_ai_mailbox_put_irq(adev);
1100
1101         return 0;
1102 }
1103
1104 static int soc15_common_suspend(void *handle)
1105 {
1106         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1107
1108         return soc15_common_hw_fini(adev);
1109 }
1110
1111 static int soc15_common_resume(void *handle)
1112 {
1113         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114
1115         return soc15_common_hw_init(adev);
1116 }
1117
1118 static bool soc15_common_is_idle(void *handle)
1119 {
1120         return true;
1121 }
1122
1123 static int soc15_common_wait_for_idle(void *handle)
1124 {
1125         return 0;
1126 }
1127
1128 static int soc15_common_soft_reset(void *handle)
1129 {
1130         return 0;
1131 }
1132
1133 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1134 {
1135         uint32_t def, data;
1136
1137         if (adev->asic_type == CHIP_VEGA20) {
1138                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1139
1140                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1141                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1142                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1143                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1144                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1145                 else
1146                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1147                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1148                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1149                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1150
1151                 if (def != data)
1152                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1153         } else {
1154                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1155
1156                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1157                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1158                 else
1159                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1160
1161                 if (def != data)
1162                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1163         }
1164 }
1165
1166 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1167 {
1168         uint32_t def, data;
1169
1170         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1171
1172         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1173                 data &= ~(0x01000000 |
1174                           0x02000000 |
1175                           0x04000000 |
1176                           0x08000000 |
1177                           0x10000000 |
1178                           0x20000000 |
1179                           0x40000000 |
1180                           0x80000000);
1181         else
1182                 data |= (0x01000000 |
1183                          0x02000000 |
1184                          0x04000000 |
1185                          0x08000000 |
1186                          0x10000000 |
1187                          0x20000000 |
1188                          0x40000000 |
1189                          0x80000000);
1190
1191         if (def != data)
1192                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1193 }
1194
1195 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1196 {
1197         uint32_t def, data;
1198
1199         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1200
1201         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1202                 data |= 1;
1203         else
1204                 data &= ~1;
1205
1206         if (def != data)
1207                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1208 }
1209
1210 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1211                                                        bool enable)
1212 {
1213         uint32_t def, data;
1214
1215         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1216
1217         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1218                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1219                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1220         else
1221                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1222                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1223
1224         if (def != data)
1225                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1226 }
1227
1228 static int soc15_common_set_clockgating_state(void *handle,
1229                                             enum amd_clockgating_state state)
1230 {
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233         if (amdgpu_sriov_vf(adev))
1234                 return 0;
1235
1236         switch (adev->asic_type) {
1237         case CHIP_VEGA10:
1238         case CHIP_VEGA12:
1239         case CHIP_VEGA20:
1240                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1241                                 state == AMD_CG_STATE_GATE ? true : false);
1242                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1243                                 state == AMD_CG_STATE_GATE ? true : false);
1244                 soc15_update_hdp_light_sleep(adev,
1245                                 state == AMD_CG_STATE_GATE ? true : false);
1246                 soc15_update_drm_clock_gating(adev,
1247                                 state == AMD_CG_STATE_GATE ? true : false);
1248                 soc15_update_drm_light_sleep(adev,
1249                                 state == AMD_CG_STATE_GATE ? true : false);
1250                 soc15_update_rom_medium_grain_clock_gating(adev,
1251                                 state == AMD_CG_STATE_GATE ? true : false);
1252                 adev->df_funcs->update_medium_grain_clock_gating(adev,
1253                                 state == AMD_CG_STATE_GATE ? true : false);
1254                 break;
1255         case CHIP_RAVEN:
1256                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1257                                 state == AMD_CG_STATE_GATE ? true : false);
1258                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1259                                 state == AMD_CG_STATE_GATE ? true : false);
1260                 soc15_update_hdp_light_sleep(adev,
1261                                 state == AMD_CG_STATE_GATE ? true : false);
1262                 soc15_update_drm_clock_gating(adev,
1263                                 state == AMD_CG_STATE_GATE ? true : false);
1264                 soc15_update_drm_light_sleep(adev,
1265                                 state == AMD_CG_STATE_GATE ? true : false);
1266                 soc15_update_rom_medium_grain_clock_gating(adev,
1267                                 state == AMD_CG_STATE_GATE ? true : false);
1268                 break;
1269         default:
1270                 break;
1271         }
1272         return 0;
1273 }
1274
1275 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1276 {
1277         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278         int data;
1279
1280         if (amdgpu_sriov_vf(adev))
1281                 *flags = 0;
1282
1283         adev->nbio_funcs->get_clockgating_state(adev, flags);
1284
1285         /* AMD_CG_SUPPORT_HDP_LS */
1286         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1287         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1288                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1289
1290         /* AMD_CG_SUPPORT_DRM_MGCG */
1291         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1292         if (!(data & 0x01000000))
1293                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1294
1295         /* AMD_CG_SUPPORT_DRM_LS */
1296         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1297         if (data & 0x1)
1298                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1299
1300         /* AMD_CG_SUPPORT_ROM_MGCG */
1301         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1302         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1303                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1304
1305         adev->df_funcs->get_clockgating_state(adev, flags);
1306 }
1307
1308 static int soc15_common_set_powergating_state(void *handle,
1309                                             enum amd_powergating_state state)
1310 {
1311         /* todo */
1312         return 0;
1313 }
1314
1315 const struct amd_ip_funcs soc15_common_ip_funcs = {
1316         .name = "soc15_common",
1317         .early_init = soc15_common_early_init,
1318         .late_init = soc15_common_late_init,
1319         .sw_init = soc15_common_sw_init,
1320         .sw_fini = soc15_common_sw_fini,
1321         .hw_init = soc15_common_hw_init,
1322         .hw_fini = soc15_common_hw_fini,
1323         .suspend = soc15_common_suspend,
1324         .resume = soc15_common_resume,
1325         .is_idle = soc15_common_is_idle,
1326         .wait_for_idle = soc15_common_wait_for_idle,
1327         .soft_reset = soc15_common_soft_reset,
1328         .set_clockgating_state = soc15_common_set_clockgating_state,
1329         .set_powergating_state = soc15_common_set_powergating_state,
1330         .get_clockgating_state= soc15_common_get_clockgating_state,
1331 };