2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
38 #include "uvd/uvd_7_0_offset.h"
39 #include "gc/gc_9_0_offset.h"
40 #include "gc/gc_9_0_sh_mask.h"
41 #include "sdma0/sdma0_4_0_offset.h"
42 #include "sdma1/sdma1_4_0_offset.h"
43 #include "hdp/hdp_4_0_offset.h"
44 #include "hdp/hdp_4_0_sh_mask.h"
45 #include "smuio/smuio_9_0_offset.h"
46 #include "smuio/smuio_9_0_sh_mask.h"
47 #include "nbio/nbio_7_0_default.h"
48 #include "nbio/nbio_7_0_offset.h"
49 #include "nbio/nbio_7_0_sh_mask.h"
50 #include "nbio/nbio_7_0_smn.h"
51 #include "mp/mp_9_0_offset.h"
54 #include "soc15_common.h"
57 #include "gfxhub_v1_0.h"
58 #include "mmhub_v1_0.h"
61 #include "vega10_ih.h"
62 #include "sdma_v4_0.h"
66 #include "dce_virtual.h"
68 #include "amdgpu_smu.h"
69 #include "amdgpu_ras.h"
70 #include "amdgpu_xgmi.h"
71 #include <uapi/linux/kfd_ioctl.h>
73 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
74 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
75 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
76 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
78 /* for Vega20 register name change */
79 #define mmHDP_MEM_POWER_CTRL 0x00d4
80 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
81 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
82 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
83 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
84 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
86 * Indirect registers accessor
88 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
90 unsigned long flags, address, data;
92 address = adev->nbio_funcs->get_pcie_index_offset(adev);
93 data = adev->nbio_funcs->get_pcie_data_offset(adev);
95 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
97 (void)RREG32(address);
99 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
103 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
105 unsigned long flags, address, data;
107 address = adev->nbio_funcs->get_pcie_index_offset(adev);
108 data = adev->nbio_funcs->get_pcie_data_offset(adev);
110 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
111 WREG32(address, reg);
112 (void)RREG32(address);
115 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
118 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
120 unsigned long flags, address, data;
123 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
124 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
126 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
127 WREG32(address, ((reg) & 0x1ff));
129 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
133 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
135 unsigned long flags, address, data;
137 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
138 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
140 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
141 WREG32(address, ((reg) & 0x1ff));
143 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
146 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
148 unsigned long flags, address, data;
151 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
152 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
154 spin_lock_irqsave(&adev->didt_idx_lock, flags);
155 WREG32(address, (reg));
157 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
161 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
163 unsigned long flags, address, data;
165 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
166 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
168 spin_lock_irqsave(&adev->didt_idx_lock, flags);
169 WREG32(address, (reg));
171 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
174 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
179 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
180 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
181 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
182 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
186 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
190 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
191 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
192 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
193 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
196 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
201 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
202 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
203 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
204 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
208 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
212 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
213 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
214 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
215 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
218 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
220 return adev->nbio_funcs->get_memsize(adev);
223 static u32 soc15_get_xclk(struct amdgpu_device *adev)
225 return adev->clock.spll.reference_freq;
229 void soc15_grbm_select(struct amdgpu_device *adev,
230 u32 me, u32 pipe, u32 queue, u32 vmid)
232 u32 grbm_gfx_cntl = 0;
233 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
234 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
235 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
236 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
238 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
241 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
246 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
252 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
253 u8 *bios, u32 length_bytes)
260 if (length_bytes == 0)
262 /* APU vbios image is part of sbios image */
263 if (adev->flags & AMD_IS_APU)
266 dw_ptr = (u32 *)bios;
267 length_dw = ALIGN(length_bytes, 4) / 4;
269 /* set rom index to 0 */
270 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
271 /* read out the rom data */
272 for (i = 0; i < length_dw; i++)
273 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
278 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
279 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
280 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
281 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
282 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
283 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
284 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
285 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
286 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
287 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
288 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
289 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
290 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
291 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
292 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
293 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
294 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
295 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
296 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
297 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
300 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
301 u32 sh_num, u32 reg_offset)
305 mutex_lock(&adev->grbm_idx_mutex);
306 if (se_num != 0xffffffff || sh_num != 0xffffffff)
307 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
309 val = RREG32(reg_offset);
311 if (se_num != 0xffffffff || sh_num != 0xffffffff)
312 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
313 mutex_unlock(&adev->grbm_idx_mutex);
317 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
318 bool indexed, u32 se_num,
319 u32 sh_num, u32 reg_offset)
322 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
324 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
325 return adev->gfx.config.gb_addr_config;
326 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
327 return adev->gfx.config.db_debug2;
328 return RREG32(reg_offset);
332 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
333 u32 sh_num, u32 reg_offset, u32 *value)
336 struct soc15_allowed_register_entry *en;
339 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
340 en = &soc15_allowed_read_registers[i];
341 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
345 *value = soc15_get_register_value(adev,
346 soc15_allowed_read_registers[i].grbm_indexed,
347 se_num, sh_num, reg_offset);
355 * soc15_program_register_sequence - program an array of registers.
357 * @adev: amdgpu_device pointer
358 * @regs: pointer to the register array
359 * @array_size: size of the register array
361 * Programs an array or registers with and and or masks.
362 * This is a helper for setting golden registers.
365 void soc15_program_register_sequence(struct amdgpu_device *adev,
366 const struct soc15_reg_golden *regs,
367 const u32 array_size)
369 const struct soc15_reg_golden *entry;
373 for (i = 0; i < array_size; ++i) {
375 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
377 if (entry->and_mask == 0xffffffff) {
378 tmp = entry->or_mask;
381 tmp &= ~(entry->and_mask);
382 tmp |= (entry->or_mask & entry->and_mask);
385 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
386 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
387 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
388 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
389 WREG32_RLC(reg, tmp);
397 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
402 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
404 dev_info(adev->dev, "GPU mode1 reset\n");
407 pci_clear_master(adev->pdev);
409 pci_save_state(adev->pdev);
411 ret = psp_gpu_reset(adev);
413 dev_err(adev->dev, "GPU mode1 reset failed\n");
415 pci_restore_state(adev->pdev);
417 /* wait for asic to come out of reset */
418 for (i = 0; i < adev->usec_timeout; i++) {
419 u32 memsize = adev->nbio_funcs->get_memsize(adev);
421 if (memsize != 0xffffffff)
426 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
431 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
433 void *pp_handle = adev->powerplay.pp_handle;
434 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
436 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
441 return pp_funcs->get_asic_baco_capability(pp_handle, cap);
444 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
446 void *pp_handle = adev->powerplay.pp_handle;
447 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
449 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
452 /* enter BACO state */
453 if (pp_funcs->set_asic_baco_state(pp_handle, 1))
456 /* exit BACO state */
457 if (pp_funcs->set_asic_baco_state(pp_handle, 0))
460 dev_info(adev->dev, "GPU BACO reset\n");
462 adev->in_baco_reset = 1;
467 static int soc15_asic_reset(struct amdgpu_device *adev)
472 switch (adev->asic_type) {
475 soc15_asic_get_baco_capability(adev, &baco_reset);
478 if (adev->psp.sos_fw_version >= 0x80067)
479 soc15_asic_get_baco_capability(adev, &baco_reset);
483 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
484 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
486 if (hive || (ras && ras->supported))
496 ret = soc15_asic_baco_reset(adev);
498 ret = soc15_asic_mode1_reset(adev);
503 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
504 u32 cntl_reg, u32 status_reg)
509 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
513 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
517 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
522 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
529 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
531 if (pci_is_root_bus(adev->pdev->bus))
534 if (amdgpu_pcie_gen2 == 0)
537 if (adev->flags & AMD_IS_APU)
540 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
541 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
547 static void soc15_program_aspm(struct amdgpu_device *adev)
550 if (amdgpu_aspm == 0)
556 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
559 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
560 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
563 static const struct amdgpu_ip_block_version vega10_common_ip_block =
565 .type = AMD_IP_BLOCK_TYPE_COMMON,
569 .funcs = &soc15_common_ip_funcs,
572 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
574 return adev->nbio_funcs->get_rev_id(adev);
577 int soc15_set_ip_blocks(struct amdgpu_device *adev)
579 /* Set IP register base before any HW register access */
580 switch (adev->asic_type) {
584 vega10_reg_base_init(adev);
587 vega20_reg_base_init(adev);
593 if (adev->asic_type == CHIP_VEGA20)
594 adev->gmc.xgmi.supported = true;
596 if (adev->flags & AMD_IS_APU)
597 adev->nbio_funcs = &nbio_v7_0_funcs;
598 else if (adev->asic_type == CHIP_VEGA20)
599 adev->nbio_funcs = &nbio_v7_4_funcs;
601 adev->nbio_funcs = &nbio_v6_1_funcs;
603 if (adev->asic_type == CHIP_VEGA20)
604 adev->df_funcs = &df_v3_6_funcs;
606 adev->df_funcs = &df_v1_7_funcs;
608 adev->rev_id = soc15_get_rev_id(adev);
609 adev->nbio_funcs->detect_hw_virt(adev);
611 if (amdgpu_sriov_vf(adev))
612 adev->virt.ops = &xgpu_ai_virt_ops;
614 switch (adev->asic_type) {
618 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
619 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
621 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
622 if (amdgpu_sriov_vf(adev)) {
623 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
624 if (adev->asic_type == CHIP_VEGA20)
625 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
627 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
629 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
631 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
632 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
633 if (adev->asic_type == CHIP_VEGA20)
634 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
636 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
639 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
640 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
641 if (!amdgpu_sriov_vf(adev)) {
642 if (is_support_sw_smu(adev))
643 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
645 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
647 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
648 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
649 #if defined(CONFIG_DRM_AMD_DC)
650 else if (amdgpu_device_has_dc_support(adev))
651 amdgpu_device_ip_block_add(adev, &dm_ip_block);
653 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
655 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
656 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
657 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
661 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
662 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
663 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
664 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
665 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
666 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
667 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
668 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
669 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
670 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
671 #if defined(CONFIG_DRM_AMD_DC)
672 else if (amdgpu_device_has_dc_support(adev))
673 amdgpu_device_ip_block_add(adev, &dm_ip_block);
675 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
677 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
686 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
688 adev->nbio_funcs->hdp_flush(adev, ring);
691 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
692 struct amdgpu_ring *ring)
694 if (!ring || !ring->funcs->emit_wreg)
695 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
697 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
698 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
701 static bool soc15_need_full_reset(struct amdgpu_device *adev)
703 /* change this when we implement soft reset */
706 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
709 uint32_t perfctr = 0;
710 uint64_t cnt0_of, cnt1_of;
713 /* This reports 0 on APUs, so return to avoid writing/reading registers
714 * that may or may not be different from their GPU counterparts
716 if (adev->flags & AMD_IS_APU)
719 /* Set the 2 events that we wish to watch, defined above */
720 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
721 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
722 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
724 /* Write to enable desired perf counters */
725 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
726 /* Zero out and enable the perf counters
728 * Bit 0 = Start all counters(1)
729 * Bit 2 = Global counter reset enable(1)
731 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
735 /* Load the shadow and disable the perf counters
737 * Bit 0 = Stop counters(0)
738 * Bit 1 = Load the shadow counters(1)
740 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
742 /* Read register values to get any >32bit overflow */
743 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
744 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
745 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
747 /* Get the values and add the overflow */
748 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
749 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
752 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
756 /* Just return false for soc15 GPUs. Reset does not seem to
759 if (!amdgpu_passthrough(adev))
762 if (adev->flags & AMD_IS_APU)
765 /* Check sOS sign of life register to confirm sys driver and sOS
766 * are already been loaded.
768 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
775 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
777 uint64_t nak_r, nak_g;
779 /* Get the number of NAKs received and generated */
780 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
781 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
783 /* Add the total number of NAKs, i.e the number of replays */
784 return (nak_r + nak_g);
787 static const struct amdgpu_asic_funcs soc15_asic_funcs =
789 .read_disabled_bios = &soc15_read_disabled_bios,
790 .read_bios_from_rom = &soc15_read_bios_from_rom,
791 .read_register = &soc15_read_register,
792 .reset = &soc15_asic_reset,
793 .set_vga_state = &soc15_vga_set_state,
794 .get_xclk = &soc15_get_xclk,
795 .set_uvd_clocks = &soc15_set_uvd_clocks,
796 .set_vce_clocks = &soc15_set_vce_clocks,
797 .get_config_memsize = &soc15_get_config_memsize,
798 .flush_hdp = &soc15_flush_hdp,
799 .invalidate_hdp = &soc15_invalidate_hdp,
800 .need_full_reset = &soc15_need_full_reset,
801 .init_doorbell_index = &vega10_doorbell_index_init,
802 .get_pcie_usage = &soc15_get_pcie_usage,
803 .need_reset_on_init = &soc15_need_reset_on_init,
804 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
807 static const struct amdgpu_asic_funcs vega20_asic_funcs =
809 .read_disabled_bios = &soc15_read_disabled_bios,
810 .read_bios_from_rom = &soc15_read_bios_from_rom,
811 .read_register = &soc15_read_register,
812 .reset = &soc15_asic_reset,
813 .set_vga_state = &soc15_vga_set_state,
814 .get_xclk = &soc15_get_xclk,
815 .set_uvd_clocks = &soc15_set_uvd_clocks,
816 .set_vce_clocks = &soc15_set_vce_clocks,
817 .get_config_memsize = &soc15_get_config_memsize,
818 .flush_hdp = &soc15_flush_hdp,
819 .invalidate_hdp = &soc15_invalidate_hdp,
820 .need_full_reset = &soc15_need_full_reset,
821 .init_doorbell_index = &vega20_doorbell_index_init,
822 .get_pcie_usage = &soc15_get_pcie_usage,
823 .need_reset_on_init = &soc15_need_reset_on_init,
824 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
827 static int soc15_common_early_init(void *handle)
829 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
830 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
832 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
833 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
834 adev->smc_rreg = NULL;
835 adev->smc_wreg = NULL;
836 adev->pcie_rreg = &soc15_pcie_rreg;
837 adev->pcie_wreg = &soc15_pcie_wreg;
838 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
839 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
840 adev->didt_rreg = &soc15_didt_rreg;
841 adev->didt_wreg = &soc15_didt_wreg;
842 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
843 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
844 adev->se_cac_rreg = &soc15_se_cac_rreg;
845 adev->se_cac_wreg = &soc15_se_cac_wreg;
848 adev->external_rev_id = 0xFF;
849 switch (adev->asic_type) {
851 adev->asic_funcs = &soc15_asic_funcs;
852 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
853 AMD_CG_SUPPORT_GFX_MGLS |
854 AMD_CG_SUPPORT_GFX_RLC_LS |
855 AMD_CG_SUPPORT_GFX_CP_LS |
856 AMD_CG_SUPPORT_GFX_3D_CGCG |
857 AMD_CG_SUPPORT_GFX_3D_CGLS |
858 AMD_CG_SUPPORT_GFX_CGCG |
859 AMD_CG_SUPPORT_GFX_CGLS |
860 AMD_CG_SUPPORT_BIF_MGCG |
861 AMD_CG_SUPPORT_BIF_LS |
862 AMD_CG_SUPPORT_HDP_LS |
863 AMD_CG_SUPPORT_DRM_MGCG |
864 AMD_CG_SUPPORT_DRM_LS |
865 AMD_CG_SUPPORT_ROM_MGCG |
866 AMD_CG_SUPPORT_DF_MGCG |
867 AMD_CG_SUPPORT_SDMA_MGCG |
868 AMD_CG_SUPPORT_SDMA_LS |
869 AMD_CG_SUPPORT_MC_MGCG |
870 AMD_CG_SUPPORT_MC_LS;
872 adev->external_rev_id = 0x1;
875 adev->asic_funcs = &soc15_asic_funcs;
876 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
877 AMD_CG_SUPPORT_GFX_MGLS |
878 AMD_CG_SUPPORT_GFX_CGCG |
879 AMD_CG_SUPPORT_GFX_CGLS |
880 AMD_CG_SUPPORT_GFX_3D_CGCG |
881 AMD_CG_SUPPORT_GFX_3D_CGLS |
882 AMD_CG_SUPPORT_GFX_CP_LS |
883 AMD_CG_SUPPORT_MC_LS |
884 AMD_CG_SUPPORT_MC_MGCG |
885 AMD_CG_SUPPORT_SDMA_MGCG |
886 AMD_CG_SUPPORT_SDMA_LS |
887 AMD_CG_SUPPORT_BIF_MGCG |
888 AMD_CG_SUPPORT_BIF_LS |
889 AMD_CG_SUPPORT_HDP_MGCG |
890 AMD_CG_SUPPORT_HDP_LS |
891 AMD_CG_SUPPORT_ROM_MGCG |
892 AMD_CG_SUPPORT_VCE_MGCG |
893 AMD_CG_SUPPORT_UVD_MGCG;
895 adev->external_rev_id = adev->rev_id + 0x14;
898 adev->asic_funcs = &vega20_asic_funcs;
899 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
900 AMD_CG_SUPPORT_GFX_MGLS |
901 AMD_CG_SUPPORT_GFX_CGCG |
902 AMD_CG_SUPPORT_GFX_CGLS |
903 AMD_CG_SUPPORT_GFX_3D_CGCG |
904 AMD_CG_SUPPORT_GFX_3D_CGLS |
905 AMD_CG_SUPPORT_GFX_CP_LS |
906 AMD_CG_SUPPORT_MC_LS |
907 AMD_CG_SUPPORT_MC_MGCG |
908 AMD_CG_SUPPORT_SDMA_MGCG |
909 AMD_CG_SUPPORT_SDMA_LS |
910 AMD_CG_SUPPORT_BIF_MGCG |
911 AMD_CG_SUPPORT_BIF_LS |
912 AMD_CG_SUPPORT_HDP_MGCG |
913 AMD_CG_SUPPORT_HDP_LS |
914 AMD_CG_SUPPORT_ROM_MGCG |
915 AMD_CG_SUPPORT_VCE_MGCG |
916 AMD_CG_SUPPORT_UVD_MGCG;
918 adev->external_rev_id = adev->rev_id + 0x28;
921 adev->asic_funcs = &soc15_asic_funcs;
922 if (adev->rev_id >= 0x8)
923 adev->external_rev_id = adev->rev_id + 0x79;
924 else if (adev->pdev->device == 0x15d8)
925 adev->external_rev_id = adev->rev_id + 0x41;
926 else if (adev->rev_id == 1)
927 adev->external_rev_id = adev->rev_id + 0x20;
929 adev->external_rev_id = adev->rev_id + 0x01;
931 if (adev->rev_id >= 0x8) {
932 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
933 AMD_CG_SUPPORT_GFX_MGLS |
934 AMD_CG_SUPPORT_GFX_CP_LS |
935 AMD_CG_SUPPORT_GFX_3D_CGCG |
936 AMD_CG_SUPPORT_GFX_3D_CGLS |
937 AMD_CG_SUPPORT_GFX_CGCG |
938 AMD_CG_SUPPORT_GFX_CGLS |
939 AMD_CG_SUPPORT_BIF_LS |
940 AMD_CG_SUPPORT_HDP_LS |
941 AMD_CG_SUPPORT_ROM_MGCG |
942 AMD_CG_SUPPORT_MC_MGCG |
943 AMD_CG_SUPPORT_MC_LS |
944 AMD_CG_SUPPORT_SDMA_MGCG |
945 AMD_CG_SUPPORT_SDMA_LS |
946 AMD_CG_SUPPORT_VCN_MGCG;
948 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
949 } else if (adev->pdev->device == 0x15d8) {
950 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
951 AMD_CG_SUPPORT_GFX_MGLS |
952 AMD_CG_SUPPORT_GFX_CP_LS |
953 AMD_CG_SUPPORT_GFX_3D_CGCG |
954 AMD_CG_SUPPORT_GFX_3D_CGLS |
955 AMD_CG_SUPPORT_GFX_CGCG |
956 AMD_CG_SUPPORT_GFX_CGLS |
957 AMD_CG_SUPPORT_BIF_LS |
958 AMD_CG_SUPPORT_HDP_LS |
959 AMD_CG_SUPPORT_ROM_MGCG |
960 AMD_CG_SUPPORT_MC_MGCG |
961 AMD_CG_SUPPORT_MC_LS |
962 AMD_CG_SUPPORT_SDMA_MGCG |
963 AMD_CG_SUPPORT_SDMA_LS;
965 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
966 AMD_PG_SUPPORT_MMHUB |
968 AMD_PG_SUPPORT_VCN_DPG;
970 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
971 AMD_CG_SUPPORT_GFX_MGLS |
972 AMD_CG_SUPPORT_GFX_RLC_LS |
973 AMD_CG_SUPPORT_GFX_CP_LS |
974 AMD_CG_SUPPORT_GFX_3D_CGCG |
975 AMD_CG_SUPPORT_GFX_3D_CGLS |
976 AMD_CG_SUPPORT_GFX_CGCG |
977 AMD_CG_SUPPORT_GFX_CGLS |
978 AMD_CG_SUPPORT_BIF_MGCG |
979 AMD_CG_SUPPORT_BIF_LS |
980 AMD_CG_SUPPORT_HDP_MGCG |
981 AMD_CG_SUPPORT_HDP_LS |
982 AMD_CG_SUPPORT_DRM_MGCG |
983 AMD_CG_SUPPORT_DRM_LS |
984 AMD_CG_SUPPORT_ROM_MGCG |
985 AMD_CG_SUPPORT_MC_MGCG |
986 AMD_CG_SUPPORT_MC_LS |
987 AMD_CG_SUPPORT_SDMA_MGCG |
988 AMD_CG_SUPPORT_SDMA_LS |
989 AMD_CG_SUPPORT_VCN_MGCG;
991 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
994 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
995 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
997 AMD_PG_SUPPORT_RLC_SMU_HS;
1000 /* FIXME: not supported yet */
1004 if (amdgpu_sriov_vf(adev)) {
1005 amdgpu_virt_init_setting(adev);
1006 xgpu_ai_mailbox_set_irq_funcs(adev);
1012 static int soc15_common_late_init(void *handle)
1014 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1016 if (amdgpu_sriov_vf(adev))
1017 xgpu_ai_mailbox_get_irq(adev);
1022 static int soc15_common_sw_init(void *handle)
1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026 if (amdgpu_sriov_vf(adev))
1027 xgpu_ai_mailbox_add_irq_id(adev);
1029 adev->df_funcs->sw_init(adev);
1034 static int soc15_common_sw_fini(void *handle)
1039 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1042 struct amdgpu_ring *ring;
1044 /* Two reasons to skip
1045 * 1, Host driver already programmed them
1046 * 2, To avoid registers program violations in SR-IOV
1048 if (!amdgpu_virt_support_skip_setting(adev)) {
1049 for (i = 0; i < adev->sdma.num_instances; i++) {
1050 ring = &adev->sdma.instance[i].ring;
1051 adev->nbio_funcs->sdma_doorbell_range(adev, i,
1052 ring->use_doorbell, ring->doorbell_index,
1053 adev->doorbell_index.sdma_doorbell_range);
1057 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1058 adev->irq.ih.doorbell_index);
1061 static int soc15_common_hw_init(void *handle)
1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1065 /* enable pcie gen2/3 link */
1066 soc15_pcie_gen3_enable(adev);
1068 soc15_program_aspm(adev);
1069 /* setup nbio registers */
1070 adev->nbio_funcs->init_registers(adev);
1071 /* remap HDP registers to a hole in mmio space,
1072 * for the purpose of expose those registers
1075 if (adev->nbio_funcs->remap_hdp_registers)
1076 adev->nbio_funcs->remap_hdp_registers(adev);
1078 /* enable the doorbell aperture */
1079 soc15_enable_doorbell_aperture(adev, true);
1080 /* HW doorbell routing policy: doorbell writing not
1081 * in SDMA/IH/MM/ACV range will be routed to CP. So
1082 * we need to init SDMA/IH/MM/ACV doorbell range prior
1083 * to CP ip block init and ring test.
1085 soc15_doorbell_range_init(adev);
1090 static int soc15_common_hw_fini(void *handle)
1092 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1094 /* disable the doorbell aperture */
1095 soc15_enable_doorbell_aperture(adev, false);
1096 if (amdgpu_sriov_vf(adev))
1097 xgpu_ai_mailbox_put_irq(adev);
1102 static int soc15_common_suspend(void *handle)
1104 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1106 return soc15_common_hw_fini(adev);
1109 static int soc15_common_resume(void *handle)
1111 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113 return soc15_common_hw_init(adev);
1116 static bool soc15_common_is_idle(void *handle)
1121 static int soc15_common_wait_for_idle(void *handle)
1126 static int soc15_common_soft_reset(void *handle)
1131 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1135 if (adev->asic_type == CHIP_VEGA20) {
1136 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1138 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1139 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1140 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1141 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1142 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1144 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1145 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1146 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1147 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1150 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1152 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1154 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1155 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1157 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1160 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1164 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1168 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1170 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1171 data &= ~(0x01000000 |
1180 data |= (0x01000000 |
1190 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1193 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1197 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1199 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1205 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1208 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1213 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1215 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1216 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1217 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1219 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1220 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1223 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1226 static int soc15_common_set_clockgating_state(void *handle,
1227 enum amd_clockgating_state state)
1229 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1231 if (amdgpu_sriov_vf(adev))
1234 switch (adev->asic_type) {
1238 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1239 state == AMD_CG_STATE_GATE ? true : false);
1240 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1241 state == AMD_CG_STATE_GATE ? true : false);
1242 soc15_update_hdp_light_sleep(adev,
1243 state == AMD_CG_STATE_GATE ? true : false);
1244 soc15_update_drm_clock_gating(adev,
1245 state == AMD_CG_STATE_GATE ? true : false);
1246 soc15_update_drm_light_sleep(adev,
1247 state == AMD_CG_STATE_GATE ? true : false);
1248 soc15_update_rom_medium_grain_clock_gating(adev,
1249 state == AMD_CG_STATE_GATE ? true : false);
1250 adev->df_funcs->update_medium_grain_clock_gating(adev,
1251 state == AMD_CG_STATE_GATE ? true : false);
1254 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1255 state == AMD_CG_STATE_GATE ? true : false);
1256 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1257 state == AMD_CG_STATE_GATE ? true : false);
1258 soc15_update_hdp_light_sleep(adev,
1259 state == AMD_CG_STATE_GATE ? true : false);
1260 soc15_update_drm_clock_gating(adev,
1261 state == AMD_CG_STATE_GATE ? true : false);
1262 soc15_update_drm_light_sleep(adev,
1263 state == AMD_CG_STATE_GATE ? true : false);
1264 soc15_update_rom_medium_grain_clock_gating(adev,
1265 state == AMD_CG_STATE_GATE ? true : false);
1273 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278 if (amdgpu_sriov_vf(adev))
1281 adev->nbio_funcs->get_clockgating_state(adev, flags);
1283 /* AMD_CG_SUPPORT_HDP_LS */
1284 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1285 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1286 *flags |= AMD_CG_SUPPORT_HDP_LS;
1288 /* AMD_CG_SUPPORT_DRM_MGCG */
1289 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1290 if (!(data & 0x01000000))
1291 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1293 /* AMD_CG_SUPPORT_DRM_LS */
1294 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1296 *flags |= AMD_CG_SUPPORT_DRM_LS;
1298 /* AMD_CG_SUPPORT_ROM_MGCG */
1299 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1300 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1301 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1303 adev->df_funcs->get_clockgating_state(adev, flags);
1306 static int soc15_common_set_powergating_state(void *handle,
1307 enum amd_powergating_state state)
1313 const struct amd_ip_funcs soc15_common_ip_funcs = {
1314 .name = "soc15_common",
1315 .early_init = soc15_common_early_init,
1316 .late_init = soc15_common_late_init,
1317 .sw_init = soc15_common_sw_init,
1318 .sw_fini = soc15_common_sw_fini,
1319 .hw_init = soc15_common_hw_init,
1320 .hw_fini = soc15_common_hw_fini,
1321 .suspend = soc15_common_suspend,
1322 .resume = soc15_common_resume,
1323 .is_idle = soc15_common_is_idle,
1324 .wait_for_idle = soc15_common_wait_for_idle,
1325 .soft_reset = soc15_common_soft_reset,
1326 .set_clockgating_state = soc15_common_set_clockgating_state,
1327 .set_powergating_state = soc15_common_set_powergating_state,
1328 .get_clockgating_state= soc15_common_get_clockgating_state,