drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v13_0.h"
  30
  31 #include "mp/mp_13_0_2_offset.h"
  32 #include "mp/mp_13_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
  48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
  50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
  51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
  52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
  53 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
  54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
  55
  56 /* For large FW files the time to complete can be very long */
  57 #define USBC_PD_POLLING_LIMIT_S 240
  58
  59 /* Read USB-PD from LFB */
  60 #define GFX_CMD_USB_PD_USE_LFB 0x480
  61
  62 /* VBIOS gfl defines */
  63 #define MBOX_READY_MASK 0x80000000
  64 #define MBOX_STATUS_MASK 0x0000FFFF
  65 #define MBOX_COMMAND_MASK 0x00FF0000
  66 #define MBOX_READY_FLAG 0x80000000
  67 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  68 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  69 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  70
  71 /* memory training timeout define */
  72 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  73
  74 static int psp_v13_0_init_microcode(struct psp_context *psp)
  75 {
  76         struct amdgpu_device *adev = psp->adev;
  77         char ucode_prefix[30];
  78         int err = 0;
  79
  80         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  81
  82         switch (adev->ip_versions[MP0_HWIP][0]) {
  83         case IP_VERSION(13, 0, 2):
  84                 err = psp_init_sos_microcode(psp, ucode_prefix);
  85                 if (err)
  86                         return err;
  87                 /* It's not necessary to load ras ta on Guest side */
  88                 if (!amdgpu_sriov_vf(adev)) {
  89                         err = psp_init_ta_microcode(psp, ucode_prefix);
  90                         if (err)
  91                                 return err;
  92                 }
  93                 break;
  94         case IP_VERSION(13, 0, 1):
  95         case IP_VERSION(13, 0, 3):
  96         case IP_VERSION(13, 0, 5):
  97         case IP_VERSION(13, 0, 8):
  98         case IP_VERSION(13, 0, 11):
  99         case IP_VERSION(14, 0, 0):
 100                 err = psp_init_toc_microcode(psp, ucode_prefix);
 101                 if (err)
 102                         return err;
 103                 err = psp_init_ta_microcode(psp, ucode_prefix);
 104                 if (err)
 105                         return err;
 106                 break;
 107         case IP_VERSION(13, 0, 0):
 108         case IP_VERSION(13, 0, 6):
 109         case IP_VERSION(13, 0, 7):
 110         case IP_VERSION(13, 0, 10):
 111                 err = psp_init_sos_microcode(psp, ucode_prefix);
 112                 if (err)
 113                         return err;
 114                 /* It's not necessary to load ras ta on Guest side */
 115                 err = psp_init_ta_microcode(psp, ucode_prefix);
 116                 if (err)
 117                         return err;
 118                 break;
 119         default:
 120                 BUG();
 121         }
 122
 123         return 0;
 124 }
 125
 126 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         uint32_t sol_reg;
 130
 131         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 132
 133         return sol_reg != 0x0;
 134 }
 135
 136 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 137 {
 138         struct amdgpu_device *adev = psp->adev;
 139
 140         int ret;
 141         int retry_loop;
 142
 143         /* Wait for bootloader to signify that it is ready having bit 31 of
 144          * C2PMSG_35 set to 1. All other bits are expected to be cleared.
 145          * If there is an error in processing command, bits[7:0] will be set.
 146          * This is applicable for PSP v13.0.6 and newer.
 147          */
 148         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 149                 ret = psp_wait_for(
 150                         psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 151                         0x80000000, 0xffffffff, false);
 152
 153                 if (ret == 0)
 154                         return 0;
 155         }
 156
 157         return ret;
 158 }
 159
 160 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 161                                                struct psp_bin_desc      *bin_desc,
 162                                                enum psp_bootloader_cmd  bl_cmd)
 163 {
 164         int ret;
 165         uint32_t psp_gfxdrv_command_reg = 0;
 166         struct amdgpu_device *adev = psp->adev;
 167
 168         /* Check tOS sign of life register to confirm sys driver and sOS
 169          * are already been loaded.
 170          */
 171         if (psp_v13_0_is_sos_alive(psp))
 172                 return 0;
 173
 174         ret = psp_v13_0_wait_for_bootloader(psp);
 175         if (ret)
 176                 return ret;
 177
 178         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 179
 180         /* Copy PSP KDB binary to memory */
 181         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 182
 183         /* Provide the PSP KDB to bootloader */
 184         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 185                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 186         psp_gfxdrv_command_reg = bl_cmd;
 187         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 188                psp_gfxdrv_command_reg);
 189
 190         ret = psp_v13_0_wait_for_bootloader(psp);
 191
 192         return ret;
 193 }
 194
 195 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 196 {
 197         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 198 }
 199
 200 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 201 {
 202         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 203 }
 204
 205 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 206 {
 207         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 208 }
 209
 210 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 211 {
 212         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 213 }
 214
 215 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 216 {
 217         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 218 }
 219
 220 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 221 {
 222         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 223 }
 224
 225 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
 226 {
 227         return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 228 }
 229
 230
 231 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 232 {
 233         int ret;
 234         unsigned int psp_gfxdrv_command_reg = 0;
 235         struct amdgpu_device *adev = psp->adev;
 236
 237         /* Check sOS sign of life register to confirm sys driver and sOS
 238          * are already been loaded.
 239          */
 240         if (psp_v13_0_is_sos_alive(psp))
 241                 return 0;
 242
 243         ret = psp_v13_0_wait_for_bootloader(psp);
 244         if (ret)
 245                 return ret;
 246
 247         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 248
 249         /* Copy Secure OS binary to PSP memory */
 250         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 251
 252         /* Provide the PSP secure OS to bootloader */
 253         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 254                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 255         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 256         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 257                psp_gfxdrv_command_reg);
 258
 259         /* there might be handshake issue with hardware which needs delay */
 260         mdelay(20);
 261         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 262                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 263                            0, true);
 264
 265         return ret;
 266 }
 267
 268 static int psp_v13_0_ring_stop(struct psp_context *psp,
 269                                enum psp_ring_type ring_type)
 270 {
 271         int ret = 0;
 272         struct amdgpu_device *adev = psp->adev;
 273
 274         if (amdgpu_sriov_vf(adev)) {
 275                 /* Write the ring destroy command*/
 276                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 277                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 278                 /* there might be handshake issue with hardware which needs delay */
 279                 mdelay(20);
 280                 /* Wait for response flag (bit 31) */
 281                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 282                                    0x80000000, 0x80000000, false);
 283         } else {
 284                 /* Write the ring destroy command*/
 285                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 286                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 287                 /* there might be handshake issue with hardware which needs delay */
 288                 mdelay(20);
 289                 /* Wait for response flag (bit 31) */
 290                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 291                                    0x80000000, 0x80000000, false);
 292         }
 293
 294         return ret;
 295 }
 296
 297 static int psp_v13_0_ring_create(struct psp_context *psp,
 298                                  enum psp_ring_type ring_type)
 299 {
 300         int ret = 0;
 301         unsigned int psp_ring_reg = 0;
 302         struct psp_ring *ring = &psp->km_ring;
 303         struct amdgpu_device *adev = psp->adev;
 304
 305         if (amdgpu_sriov_vf(adev)) {
 306                 ret = psp_v13_0_ring_stop(psp, ring_type);
 307                 if (ret) {
 308                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 309                         return ret;
 310                 }
 311
 312                 /* Write low address of the ring to C2PMSG_102 */
 313                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 314                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 315                 /* Write high address of the ring to C2PMSG_103 */
 316                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 317                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 318
 319                 /* Write the ring initialization command to C2PMSG_101 */
 320                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 321                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 322
 323                 /* there might be handshake issue with hardware which needs delay */
 324                 mdelay(20);
 325
 326                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 327                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 328                                    0x80000000, 0x8000FFFF, false);
 329
 330         } else {
 331                 /* Wait for sOS ready for ring creation */
 332                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 333                                    0x80000000, 0x80000000, false);
 334                 if (ret) {
 335                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 336                         return ret;
 337                 }
 338
 339                 /* Write low address of the ring to C2PMSG_69 */
 340                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 341                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 342                 /* Write high address of the ring to C2PMSG_70 */
 343                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 344                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 345                 /* Write size of ring to C2PMSG_71 */
 346                 psp_ring_reg = ring->ring_size;
 347                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 348                 /* Write the ring initialization command to C2PMSG_64 */
 349                 psp_ring_reg = ring_type;
 350                 psp_ring_reg = psp_ring_reg << 16;
 351                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 352
 353                 /* there might be handshake issue with hardware which needs delay */
 354                 mdelay(20);
 355
 356                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 357                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 358                                    0x80000000, 0x8000FFFF, false);
 359         }
 360
 361         return ret;
 362 }
 363
 364 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 365                                   enum psp_ring_type ring_type)
 366 {
 367         int ret = 0;
 368         struct psp_ring *ring = &psp->km_ring;
 369         struct amdgpu_device *adev = psp->adev;
 370
 371         ret = psp_v13_0_ring_stop(psp, ring_type);
 372         if (ret)
 373                 DRM_ERROR("Fail to stop psp ring\n");
 374
 375         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 376                               &ring->ring_mem_mc_addr,
 377                               (void **)&ring->ring_mem);
 378
 379         return ret;
 380 }
 381
 382 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 383 {
 384         uint32_t data;
 385         struct amdgpu_device *adev = psp->adev;
 386
 387         if (amdgpu_sriov_vf(adev))
 388                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 389         else
 390                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 391
 392         return data;
 393 }
 394
 395 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 396 {
 397         struct amdgpu_device *adev = psp->adev;
 398
 399         if (amdgpu_sriov_vf(adev)) {
 400                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 401                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 402                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 403         } else
 404                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 405 }
 406
 407 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 408 {
 409         int ret;
 410         int i;
 411         uint32_t data_32;
 412         int max_wait;
 413         struct amdgpu_device *adev = psp->adev;
 414
 415         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 416         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 417         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 418
 419         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 420         for (i = 0; i < max_wait; i++) {
 421                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 422                                    0x80000000, 0x80000000, false);
 423                 if (ret == 0)
 424                         break;
 425         }
 426         if (i < max_wait)
 427                 ret = 0;
 428         else
 429                 ret = -ETIME;
 430
 431         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 432                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 433                   (ret == 0) ? "succeed" : "failed",
 434                   i, adev->usec_timeout/1000);
 435         return ret;
 436 }
 437
 438
 439 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 440 {
 441         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 442         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 443         struct amdgpu_device *adev = psp->adev;
 444         uint32_t p2c_header[4];
 445         uint32_t sz;
 446         void *buf;
 447         int ret, idx;
 448
 449         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 450                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 451                 return 0;
 452         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 453                 dev_err(adev->dev, "Memory training initialization failure.\n");
 454                 return -EINVAL;
 455         }
 456
 457         if (psp_v13_0_is_sos_alive(psp)) {
 458                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 459                 return 0;
 460         }
 461
 462         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 463         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 464                   pcache[0], pcache[1], pcache[2], pcache[3],
 465                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 466
 467         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 468                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 469                 ops |= PSP_MEM_TRAIN_RESTORE;
 470         }
 471
 472         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 473             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 474                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 475                 ops |= PSP_MEM_TRAIN_SAVE;
 476         }
 477
 478         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 479             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 480               pcache[3] == p2c_header[3])) {
 481                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 482                 ops |= PSP_MEM_TRAIN_SAVE;
 483         }
 484
 485         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 486             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 487                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 488                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 489         }
 490
 491         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 492                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 493                 ops |= PSP_MEM_TRAIN_SAVE;
 494         }
 495
 496         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 497
 498         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 499                 /*
 500                  * Long training will encroach a certain amount on the bottom of VRAM;
 501                  * save the content from the bottom of VRAM to system memory
 502                  * before training, and restore it after training to avoid
 503                  * VRAM corruption.
 504                  */
 505                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 506
 507                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 508                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 509                                   adev->gmc.visible_vram_size,
 510                                   adev->mman.aper_base_kaddr);
 511                         return -EINVAL;
 512                 }
 513
 514                 buf = vmalloc(sz);
 515                 if (!buf) {
 516                         dev_err(adev->dev, "failed to allocate system memory.\n");
 517                         return -ENOMEM;
 518                 }
 519
 520                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 521                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 522                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 523                         if (ret) {
 524                                 DRM_ERROR("Send long training msg failed.\n");
 525                                 vfree(buf);
 526                                 drm_dev_exit(idx);
 527                                 return ret;
 528                         }
 529
 530                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 531                         adev->hdp.funcs->flush_hdp(adev, NULL);
 532                         vfree(buf);
 533                         drm_dev_exit(idx);
 534                 } else {
 535                         vfree(buf);
 536                         return -ENODEV;
 537                 }
 538         }
 539
 540         if (ops & PSP_MEM_TRAIN_SAVE) {
 541                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 542         }
 543
 544         if (ops & PSP_MEM_TRAIN_RESTORE) {
 545                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 546         }
 547
 548         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 549                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 550                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 551                 if (ret) {
 552                         dev_err(adev->dev, "send training msg failed.\n");
 553                         return ret;
 554                 }
 555         }
 556         ctx->training_cnt++;
 557         return 0;
 558 }
 559
 560 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 561 {
 562         struct amdgpu_device *adev = psp->adev;
 563         uint32_t reg_status;
 564         int ret, i = 0;
 565
 566         /*
 567          * LFB address which is aligned to 1MB address and has to be
 568          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 569          * register
 570          */
 571         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 572
 573         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 574                              0x80000000, 0x80000000, false);
 575         if (ret)
 576                 return ret;
 577
 578         /* Fireup interrupt so PSP can pick up the address */
 579         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 580
 581         /* FW load takes very long time */
 582         do {
 583                 msleep(1000);
 584                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 585
 586                 if (reg_status & 0x80000000)
 587                         goto done;
 588
 589         } while (++i < USBC_PD_POLLING_LIMIT_S);
 590
 591         return -ETIME;
 592 done:
 593
 594         if ((reg_status & 0xFFFF) != 0) {
 595                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 596                                 reg_status & 0xFFFF);
 597                 return -EIO;
 598         }
 599
 600         return 0;
 601 }
 602
 603 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 604 {
 605         struct amdgpu_device *adev = psp->adev;
 606         int ret;
 607
 608         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 609
 610         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 611                                      0x80000000, 0x80000000, false);
 612         if (!ret)
 613                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 614
 615         return ret;
 616 }
 617
 618 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 619 {
 620         uint32_t reg_status = 0, reg_val = 0;
 621         struct amdgpu_device *adev = psp->adev;
 622         int ret;
 623
 624         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 625         reg_val |= (cmd << 16);
 626         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 627
 628         /* Ring the doorbell */
 629         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 630
 631         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 632                 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 633                                                  MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
 634         else
 635                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 636                                    MBOX_READY_FLAG, MBOX_READY_MASK, false);
 637         if (ret) {
 638                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 639                 return ret;
 640         }
 641
 642         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 643         if ((reg_status & 0xFFFF) != 0) {
 644                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 645                                 cmd, reg_status & 0xFFFF);
 646                 return -EIO;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static int psp_v13_0_update_spirom(struct psp_context *psp,
 653                                    uint64_t fw_pri_mc_addr)
 654 {
 655         struct amdgpu_device *adev = psp->adev;
 656         int ret;
 657
 658         /* Confirm PSP is ready to start */
 659         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 660                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 661         if (ret) {
 662                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 663                 return ret;
 664         }
 665
 666         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 667
 668         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 669         if (ret)
 670                 return ret;
 671
 672         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 673
 674         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 675         if (ret)
 676                 return ret;
 677
 678         psp->vbflash_done = true;
 679
 680         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 681         if (ret)
 682                 return ret;
 683
 684         return 0;
 685 }
 686
 687 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 688 {
 689         struct amdgpu_device *adev = psp->adev;
 690
 691         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 692 }
 693
 694 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
 695 {
 696         struct amdgpu_device *adev = psp->adev;
 697
 698         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) {
 699                 uint32_t  reg_data;
 700                 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
 701                  * during MP1 triggered sync flood.
 702                  */
 703                 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 704                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
 705
 706                 /* delay 1000ms for the mode1 reset for fatal error
 707                  * to be recovered back.
 708                  */
 709                 msleep(1000);
 710         }
 711
 712         return 0;
 713 }
 714
 715 static const struct psp_funcs psp_v13_0_funcs = {
 716         .init_microcode = psp_v13_0_init_microcode,
 717         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 718         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 719         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 720         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 721         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 722         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 723         .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
 724         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 725         .ring_create = psp_v13_0_ring_create,
 726         .ring_stop = psp_v13_0_ring_stop,
 727         .ring_destroy = psp_v13_0_ring_destroy,
 728         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 729         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 730         .mem_training = psp_v13_0_memory_training,
 731         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 732         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 733         .update_spirom = psp_v13_0_update_spirom,
 734         .vbflash_stat = psp_v13_0_vbflash_status,
 735         .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
 736 };
 737
 738 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 739 {
 740         psp->funcs = &psp_v13_0_funcs;
 741 }