drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_psp.h"
  26 #include "amdgpu_ucode.h"
  27 #include "soc15_common.h"
  28 #include "psp_v11_0.h"
  29
  30 #include "mp/mp_11_0_offset.h"
  31 #include "mp/mp_11_0_sh_mask.h"
  32 #include "gc/gc_9_0_offset.h"
  33 #include "sdma0/sdma0_4_0_offset.h"
  34 #include "nbio/nbio_7_4_offset.h"
  35
  36 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  37 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  38 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  39
  40 /* address block */
  41 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  42
  43 static int psp_v11_0_init_microcode(struct psp_context *psp)
  44 {
  45         struct amdgpu_device *adev = psp->adev;
  46         const char *chip_name;
  47         char fw_name[30];
  48         int err = 0;
  49         const struct psp_firmware_header_v1_0 *sos_hdr;
  50         const struct psp_firmware_header_v1_0 *asd_hdr;
  51         const struct ta_firmware_header_v1_0 *ta_hdr;
  52
  53         DRM_DEBUG("\n");
  54
  55         switch (adev->asic_type) {
  56         case CHIP_VEGA20:
  57                 chip_name = "vega20";
  58                 break;
  59         default:
  60                 BUG();
  61         }
  62
  63         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
  64         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
  65         if (err)
  66                 goto out;
  67
  68         err = amdgpu_ucode_validate(adev->psp.sos_fw);
  69         if (err)
  70                 goto out;
  71
  72         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
  73         adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
  74         adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
  75         adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
  76         adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->header.ucode_size_bytes) -
  77                                         le32_to_cpu(sos_hdr->sos_size_bytes);
  78         adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
  79                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
  80         adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
  81                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
  82
  83         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
  84         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
  85         if (err)
  86                 goto out1;
  87
  88         err = amdgpu_ucode_validate(adev->psp.asd_fw);
  89         if (err)
  90                 goto out1;
  91
  92         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
  93         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
  94         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
  95         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
  96         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
  97                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
  98
  99         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 100         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 101         if (err)
 102                 goto out2;
 103
 104         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 105         if (err)
 106                 goto out2;
 107
 108         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 109         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 110         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 111         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 112                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 113
 114         return 0;
 115
 116 out2:
 117         release_firmware(adev->psp.ta_fw);
 118         adev->psp.ta_fw = NULL;
 119 out1:
 120         release_firmware(adev->psp.asd_fw);
 121         adev->psp.asd_fw = NULL;
 122 out:
 123         dev_err(adev->dev,
 124                 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 125         release_firmware(adev->psp.sos_fw);
 126         adev->psp.sos_fw = NULL;
 127
 128         return err;
 129 }
 130
 131 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 132 {
 133         int ret;
 134         uint32_t psp_gfxdrv_command_reg = 0;
 135         struct amdgpu_device *adev = psp->adev;
 136         uint32_t sol_reg;
 137
 138         /* Check sOS sign of life register to confirm sys driver and sOS
 139          * are already been loaded.
 140          */
 141         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 142         if (sol_reg) {
 143                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 144                 printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
 145                 return 0;
 146         }
 147
 148         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 149         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 150                            0x80000000, 0x80000000, false);
 151         if (ret)
 152                 return ret;
 153
 154         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 155
 156         /* Copy PSP System Driver binary to memory */
 157         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 158
 159         /* Provide the sys driver to bootloader */
 160         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 161                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 162         psp_gfxdrv_command_reg = 1 << 16;
 163         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 164                psp_gfxdrv_command_reg);
 165
 166         /* there might be handshake issue with hardware which needs delay */
 167         mdelay(20);
 168
 169         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 170                            0x80000000, 0x80000000, false);
 171
 172         return ret;
 173 }
 174
 175 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 176 {
 177         int ret;
 178         unsigned int psp_gfxdrv_command_reg = 0;
 179         struct amdgpu_device *adev = psp->adev;
 180         uint32_t sol_reg;
 181
 182         /* Check sOS sign of life register to confirm sys driver and sOS
 183          * are already been loaded.
 184          */
 185         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 186         if (sol_reg)
 187                 return 0;
 188
 189         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 190         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 191                            0x80000000, 0x80000000, false);
 192         if (ret)
 193                 return ret;
 194
 195         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 196
 197         /* Copy Secure OS binary to PSP memory */
 198         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 199
 200         /* Provide the PSP secure OS to bootloader */
 201         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 202                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 203         psp_gfxdrv_command_reg = 2 << 16;
 204         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 205                psp_gfxdrv_command_reg);
 206
 207         /* there might be handshake issue with hardware which needs delay */
 208         mdelay(20);
 209         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 210                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 211                            0, true);
 212
 213         return ret;
 214 }
 215
 216 static int psp_v11_0_ring_init(struct psp_context *psp,
 217                               enum psp_ring_type ring_type)
 218 {
 219         int ret = 0;
 220         struct psp_ring *ring;
 221         struct amdgpu_device *adev = psp->adev;
 222
 223         ring = &psp->km_ring;
 224
 225         ring->ring_type = ring_type;
 226
 227         /* allocate 4k Page of Local Frame Buffer memory for ring */
 228         ring->ring_size = 0x1000;
 229         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 230                                       AMDGPU_GEM_DOMAIN_VRAM,
 231                                       &adev->firmware.rbuf,
 232                                       &ring->ring_mem_mc_addr,
 233                                       (void **)&ring->ring_mem);
 234         if (ret) {
 235                 ring->ring_size = 0;
 236                 return ret;
 237         }
 238
 239         return 0;
 240 }
 241
 242 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
 243 {
 244         if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
 245                 return true;
 246         return false;
 247 }
 248
 249 static int psp_v11_0_ring_create(struct psp_context *psp,
 250                                 enum psp_ring_type ring_type)
 251 {
 252         int ret = 0;
 253         unsigned int psp_ring_reg = 0;
 254         struct psp_ring *ring = &psp->km_ring;
 255         struct amdgpu_device *adev = psp->adev;
 256
 257         if (psp_v11_0_support_vmr_ring(psp)) {
 258                 /* Write low address of the ring to C2PMSG_102 */
 259                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 260                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 261                 /* Write high address of the ring to C2PMSG_103 */
 262                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 263                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 264
 265                 /* Write the ring initialization command to C2PMSG_101 */
 266                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 267                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 268
 269                 /* there might be handshake issue with hardware which needs delay */
 270                 mdelay(20);
 271
 272                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 273                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 274                                    0x80000000, 0x8000FFFF, false);
 275
 276         } else {
 277                 /* Write low address of the ring to C2PMSG_69 */
 278                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 279                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 280                 /* Write high address of the ring to C2PMSG_70 */
 281                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 282                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 283                 /* Write size of ring to C2PMSG_71 */
 284                 psp_ring_reg = ring->ring_size;
 285                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 286                 /* Write the ring initialization command to C2PMSG_64 */
 287                 psp_ring_reg = ring_type;
 288                 psp_ring_reg = psp_ring_reg << 16;
 289                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 290
 291                 /* there might be handshake issue with hardware which needs delay */
 292                 mdelay(20);
 293
 294                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 295                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 296                                    0x80000000, 0x8000FFFF, false);
 297         }
 298
 299         return ret;
 300 }
 301
 302 static int psp_v11_0_ring_stop(struct psp_context *psp,
 303                               enum psp_ring_type ring_type)
 304 {
 305         int ret = 0;
 306         struct amdgpu_device *adev = psp->adev;
 307
 308         /* Write the ring destroy command*/
 309         if (psp_v11_0_support_vmr_ring(psp))
 310                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 311                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 312         else
 313                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 314                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 315
 316         /* there might be handshake issue with hardware which needs delay */
 317         mdelay(20);
 318
 319         /* Wait for response flag (bit 31) */
 320         if (psp_v11_0_support_vmr_ring(psp))
 321                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 322                                    0x80000000, 0x80000000, false);
 323         else
 324                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 325                                    0x80000000, 0x80000000, false);
 326
 327         return ret;
 328 }
 329
 330 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 331                                  enum psp_ring_type ring_type)
 332 {
 333         int ret = 0;
 334         struct psp_ring *ring = &psp->km_ring;
 335         struct amdgpu_device *adev = psp->adev;
 336
 337         ret = psp_v11_0_ring_stop(psp, ring_type);
 338         if (ret)
 339                 DRM_ERROR("Fail to stop psp ring\n");
 340
 341         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 342                               &ring->ring_mem_mc_addr,
 343                               (void **)&ring->ring_mem);
 344
 345         return ret;
 346 }
 347
 348 static int psp_v11_0_cmd_submit(struct psp_context *psp,
 349                                struct amdgpu_firmware_info *ucode,
 350                                uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 351                                int index)
 352 {
 353         unsigned int psp_write_ptr_reg = 0;
 354         struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
 355         struct psp_ring *ring = &psp->km_ring;
 356         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 357         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 358                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 359         struct amdgpu_device *adev = psp->adev;
 360         uint32_t ring_size_dw = ring->ring_size / 4;
 361         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 362
 363         /* KM (GPCOM) prepare write pointer */
 364         if (psp_v11_0_support_vmr_ring(psp))
 365                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 366         else
 367                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 368
 369         /* Update KM RB frame pointer to new frame */
 370         /* write_frame ptr increments by size of rb_frame in bytes */
 371         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
 372         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 373                 write_frame = ring_buffer_start;
 374         else
 375                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 376         /* Check invalid write_frame ptr address */
 377         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 378                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 379                           ring_buffer_start, ring_buffer_end, write_frame);
 380                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 381                 return -EINVAL;
 382         }
 383
 384         /* Initialize KM RB frame */
 385         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 386
 387         /* Update KM RB frame */
 388         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 389         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 390         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 391         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 392         write_frame->fence_value = index;
 393
 394         /* Update the write Pointer in DWORDs */
 395         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 396         if (psp_v11_0_support_vmr_ring(psp)) {
 397                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
 398                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 399         } else
 400                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 401
 402         return 0;
 403 }
 404
 405 static int
 406 psp_v11_0_sram_map(struct amdgpu_device *adev,
 407                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 408                   unsigned int *sram_data_reg_offset,
 409                   enum AMDGPU_UCODE_ID ucode_id)
 410 {
 411         int ret = 0;
 412
 413         switch (ucode_id) {
 414 /* TODO: needs to confirm */
 415 #if 0
 416         case AMDGPU_UCODE_ID_SMC:
 417                 *sram_offset = 0;
 418                 *sram_addr_reg_offset = 0;
 419                 *sram_data_reg_offset = 0;
 420                 break;
 421 #endif
 422
 423         case AMDGPU_UCODE_ID_CP_CE:
 424                 *sram_offset = 0x0;
 425                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 426                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 427                 break;
 428
 429         case AMDGPU_UCODE_ID_CP_PFP:
 430                 *sram_offset = 0x0;
 431                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 432                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 433                 break;
 434
 435         case AMDGPU_UCODE_ID_CP_ME:
 436                 *sram_offset = 0x0;
 437                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 438                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 439                 break;
 440
 441         case AMDGPU_UCODE_ID_CP_MEC1:
 442                 *sram_offset = 0x10000;
 443                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 444                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 445                 break;
 446
 447         case AMDGPU_UCODE_ID_CP_MEC2:
 448                 *sram_offset = 0x10000;
 449                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 450                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 451                 break;
 452
 453         case AMDGPU_UCODE_ID_RLC_G:
 454                 *sram_offset = 0x2000;
 455                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 456                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 457                 break;
 458
 459         case AMDGPU_UCODE_ID_SDMA0:
 460                 *sram_offset = 0x0;
 461                 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 462                 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 463                 break;
 464
 465 /* TODO: needs to confirm */
 466 #if 0
 467         case AMDGPU_UCODE_ID_SDMA1:
 468                 *sram_offset = ;
 469                 *sram_addr_reg_offset = ;
 470                 break;
 471
 472         case AMDGPU_UCODE_ID_UVD:
 473                 *sram_offset = ;
 474                 *sram_addr_reg_offset = ;
 475                 break;
 476
 477         case AMDGPU_UCODE_ID_VCE:
 478                 *sram_offset = ;
 479                 *sram_addr_reg_offset = ;
 480                 break;
 481 #endif
 482
 483         case AMDGPU_UCODE_ID_MAXIMUM:
 484         default:
 485                 ret = -EINVAL;
 486                 break;
 487         }
 488
 489         return ret;
 490 }
 491
 492 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
 493                                        struct amdgpu_firmware_info *ucode,
 494                                        enum AMDGPU_UCODE_ID ucode_type)
 495 {
 496         int err = 0;
 497         unsigned int fw_sram_reg_val = 0;
 498         unsigned int fw_sram_addr_reg_offset = 0;
 499         unsigned int fw_sram_data_reg_offset = 0;
 500         unsigned int ucode_size;
 501         uint32_t *ucode_mem = NULL;
 502         struct amdgpu_device *adev = psp->adev;
 503
 504         err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 505                                 &fw_sram_data_reg_offset, ucode_type);
 506         if (err)
 507                 return false;
 508
 509         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 510
 511         ucode_size = ucode->ucode_size;
 512         ucode_mem = (uint32_t *)ucode->kaddr;
 513         while (ucode_size) {
 514                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 515
 516                 if (*ucode_mem != fw_sram_reg_val)
 517                         return false;
 518
 519                 ucode_mem++;
 520                 /* 4 bytes */
 521                 ucode_size -= 4;
 522         }
 523
 524         return true;
 525 }
 526
 527 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 528 {
 529         int ret;
 530         uint32_t offset;
 531         struct amdgpu_device *adev = psp->adev;
 532
 533         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 534
 535         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 536
 537         if (ret) {
 538                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 539                 return -EINVAL;
 540         }
 541
 542         /*send the mode 1 reset command*/
 543         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 544
 545         msleep(500);
 546
 547         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 548
 549         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 550
 551         if (ret) {
 552                 DRM_INFO("psp mode 1 reset failed!\n");
 553                 return -EINVAL;
 554         }
 555
 556         DRM_INFO("psp mode1 reset succeed \n");
 557
 558         return 0;
 559 }
 560
 561 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
 562  * For now, return success and hack the hive_id so high level code can
 563  * start testing
 564  */
 565 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
 566         int number_devices, struct psp_xgmi_topology_info *topology)
 567 {
 568         struct ta_xgmi_shared_memory *xgmi_cmd;
 569         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 570         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 571         int i;
 572         int ret;
 573
 574         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 575                 return -EINVAL;
 576
 577         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 578         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 579
 580         /* Fill in the shared memory with topology information as input */
 581         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 582         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 583         topology_info_input->num_nodes = number_devices;
 584
 585         for (i = 0; i < topology_info_input->num_nodes; i++) {
 586                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 587                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 588                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 589                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 590         }
 591
 592         /* Invoke xgmi ta to get the topology information */
 593         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 594         if (ret)
 595                 return ret;
 596
 597         /* Read the output topology information from the shared memory */
 598         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 599         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 600         for (i = 0; i < topology->num_nodes; i++) {
 601                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 602                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 603                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 604                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
 611         int number_devices, struct psp_xgmi_topology_info *topology)
 612 {
 613         struct ta_xgmi_shared_memory *xgmi_cmd;
 614         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 615         int i;
 616
 617         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 618                 return -EINVAL;
 619
 620         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 621         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 622
 623         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 624         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 625         topology_info_input->num_nodes = number_devices;
 626
 627         for (i = 0; i < topology_info_input->num_nodes; i++) {
 628                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 629                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 630                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 631                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 632         }
 633
 634         /* Invoke xgmi ta to set topology information */
 635         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 636 }
 637
 638 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 639 {
 640         struct ta_xgmi_shared_memory *xgmi_cmd;
 641         int ret;
 642
 643         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 644         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 645
 646         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 647
 648         /* Invoke xgmi ta to get hive id */
 649         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 650         if (ret)
 651                 return ret;
 652
 653         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 654
 655         return 0;
 656 }
 657
 658 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 659 {
 660         struct ta_xgmi_shared_memory *xgmi_cmd;
 661         int ret;
 662
 663         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 664         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 665
 666         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 667
 668         /* Invoke xgmi ta to get the node id */
 669         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 670         if (ret)
 671                 return ret;
 672
 673         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 674
 675         return 0;
 676 }
 677
 678 static const struct psp_funcs psp_v11_0_funcs = {
 679         .init_microcode = psp_v11_0_init_microcode,
 680         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 681         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 682         .ring_init = psp_v11_0_ring_init,
 683         .ring_create = psp_v11_0_ring_create,
 684         .ring_stop = psp_v11_0_ring_stop,
 685         .ring_destroy = psp_v11_0_ring_destroy,
 686         .cmd_submit = psp_v11_0_cmd_submit,
 687         .compare_sram_data = psp_v11_0_compare_sram_data,
 688         .mode1_reset = psp_v11_0_mode1_reset,
 689         .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
 690         .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
 691         .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
 692         .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
 693         .support_vmr_ring = psp_v11_0_support_vmr_ring,
 694 };
 695
 696 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 697 {
 698         psp->funcs = &psp_v11_0_funcs;
 699 }