drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "cikd.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34 #include "amdgpu_display.h"
  35 #include "dce_v8_0.h"
  36
  37 #include "dce/dce_8_0_d.h"
  38 #include "dce/dce_8_0_sh_mask.h"
  39
  40 #include "gca/gfx_7_2_enum.h"
  41
  42 #include "gmc/gmc_7_1_d.h"
  43 #include "gmc/gmc_7_1_sh_mask.h"
  44
  45 #include "oss/oss_2_0_d.h"
  46 #include "oss/oss_2_0_sh_mask.h"
  47
  48 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
  49 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  50
  51 static const u32 crtc_offsets[6] =
  52 {
  53         CRTC0_REGISTER_OFFSET,
  54         CRTC1_REGISTER_OFFSET,
  55         CRTC2_REGISTER_OFFSET,
  56         CRTC3_REGISTER_OFFSET,
  57         CRTC4_REGISTER_OFFSET,
  58         CRTC5_REGISTER_OFFSET
  59 };
  60
  61 static const u32 hpd_offsets[] =
  62 {
  63         HPD0_REGISTER_OFFSET,
  64         HPD1_REGISTER_OFFSET,
  65         HPD2_REGISTER_OFFSET,
  66         HPD3_REGISTER_OFFSET,
  67         HPD4_REGISTER_OFFSET,
  68         HPD5_REGISTER_OFFSET
  69 };
  70
  71 static const uint32_t dig_offsets[] = {
  72         CRTC0_REGISTER_OFFSET,
  73         CRTC1_REGISTER_OFFSET,
  74         CRTC2_REGISTER_OFFSET,
  75         CRTC3_REGISTER_OFFSET,
  76         CRTC4_REGISTER_OFFSET,
  77         CRTC5_REGISTER_OFFSET,
  78         (0x13830 - 0x7030) >> 2,
  79 };
  80
  81 static const struct {
  82         uint32_t        reg;
  83         uint32_t        vblank;
  84         uint32_t        vline;
  85         uint32_t        hpd;
  86
  87 } interrupt_status_offsets[6] = { {
  88         .reg = mmDISP_INTERRUPT_STATUS,
  89         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  90         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  91         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  92 }, {
  93         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  94         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  95         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  96         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  97 }, {
  98         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  99         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
 100         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 101         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 102 }, {
 103         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 104         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 105         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 106         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 107 }, {
 108         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 109         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 110         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 111         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 112 }, {
 113         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 114         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 115         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 116         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 117 } };
 118
 119 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
 120                                      u32 block_offset, u32 reg)
 121 {
 122         unsigned long flags;
 123         u32 r;
 124
 125         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 126         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 127         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 128         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 129
 130         return r;
 131 }
 132
 133 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
 134                                       u32 block_offset, u32 reg, u32 v)
 135 {
 136         unsigned long flags;
 137
 138         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 139         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 140         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 141         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 142 }
 143
 144 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 145 {
 146         if (crtc >= adev->mode_info.num_crtc)
 147                 return 0;
 148         else
 149                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 150 }
 151
 152 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 153 {
 154         unsigned i;
 155
 156         /* Enable pflip interrupts */
 157         for (i = 0; i < adev->mode_info.num_crtc; i++)
 158                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 159 }
 160
 161 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 162 {
 163         unsigned i;
 164
 165         /* Disable pflip interrupts */
 166         for (i = 0; i < adev->mode_info.num_crtc; i++)
 167                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 168 }
 169
 170 /**
 171  * dce_v8_0_page_flip - pageflip callback.
 172  *
 173  * @adev: amdgpu_device pointer
 174  * @crtc_id: crtc to cleanup pageflip on
 175  * @crtc_base: new address of the crtc (GPU MC address)
 176  *
 177  * Triggers the actual pageflip by updating the primary
 178  * surface base address.
 179  */
 180 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
 181                                int crtc_id, u64 crtc_base, bool async)
 182 {
 183         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 184
 185         /* flip at hsync for async, default is vsync */
 186         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
 187                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
 188         /* update the primary scanout addresses */
 189         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 190                upper_32_bits(crtc_base));
 191         /* writing to the low address triggers the update */
 192         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 193                lower_32_bits(crtc_base));
 194         /* post the write */
 195         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 196 }
 197
 198 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 199                                         u32 *vbl, u32 *position)
 200 {
 201         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 202                 return -EINVAL;
 203
 204         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 205         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 206
 207         return 0;
 208 }
 209
 210 /**
 211  * dce_v8_0_hpd_sense - hpd sense callback.
 212  *
 213  * @adev: amdgpu_device pointer
 214  * @hpd: hpd (hotplug detect) pin
 215  *
 216  * Checks if a digital monitor is connected (evergreen+).
 217  * Returns true if connected, false if not connected.
 218  */
 219 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
 220                                enum amdgpu_hpd_id hpd)
 221 {
 222         bool connected = false;
 223
 224         if (hpd >= adev->mode_info.num_hpd)
 225                 return connected;
 226
 227         if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
 228             DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 229                 connected = true;
 230
 231         return connected;
 232 }
 233
 234 /**
 235  * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
 236  *
 237  * @adev: amdgpu_device pointer
 238  * @hpd: hpd (hotplug detect) pin
 239  *
 240  * Set the polarity of the hpd pin (evergreen+).
 241  */
 242 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
 243                                       enum amdgpu_hpd_id hpd)
 244 {
 245         u32 tmp;
 246         bool connected = dce_v8_0_hpd_sense(adev, hpd);
 247
 248         if (hpd >= adev->mode_info.num_hpd)
 249                 return;
 250
 251         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
 252         if (connected)
 253                 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 254         else
 255                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 256         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
 257 }
 258
 259 /**
 260  * dce_v8_0_hpd_init - hpd setup callback.
 261  *
 262  * @adev: amdgpu_device pointer
 263  *
 264  * Setup the hpd pins used by the card (evergreen+).
 265  * Enable the pin, set the polarity, and enable the hpd interrupts.
 266  */
 267 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
 268 {
 269         struct drm_device *dev = adev->ddev;
 270         struct drm_connector *connector;
 271         u32 tmp;
 272
 273         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 274                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 275
 276                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 277                         continue;
 278
 279                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 280                 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 281                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 282
 283                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 284                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 285                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 286                          * aux dp channel on imac and help (but not completely fix)
 287                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 288                          * also avoid interrupt storms during dpms.
 289                          */
 290                         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 291                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 292                         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 293                         continue;
 294                 }
 295
 296                 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 297                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 298         }
 299 }
 300
 301 /**
 302  * dce_v8_0_hpd_fini - hpd tear down callback.
 303  *
 304  * @adev: amdgpu_device pointer
 305  *
 306  * Tear down the hpd pins used by the card (evergreen+).
 307  * Disable the hpd interrupts.
 308  */
 309 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 310 {
 311         struct drm_device *dev = adev->ddev;
 312         struct drm_connector *connector;
 313         u32 tmp;
 314
 315         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 316                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 317
 318                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 319                         continue;
 320
 321                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 322                 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 323                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 324
 325                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 326         }
 327 }
 328
 329 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 330 {
 331         return mmDC_GPIO_HPD_A;
 332 }
 333
 334 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
 335 {
 336         u32 crtc_hung = 0;
 337         u32 crtc_status[6];
 338         u32 i, j, tmp;
 339
 340         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 341                 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
 342                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 343                         crtc_hung |= (1 << i);
 344                 }
 345         }
 346
 347         for (j = 0; j < 10; j++) {
 348                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 349                         if (crtc_hung & (1 << i)) {
 350                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 351                                 if (tmp != crtc_status[i])
 352                                         crtc_hung &= ~(1 << i);
 353                         }
 354                 }
 355                 if (crtc_hung == 0)
 356                         return false;
 357                 udelay(100);
 358         }
 359
 360         return true;
 361 }
 362
 363 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
 364                                           bool render)
 365 {
 366         u32 tmp;
 367
 368         /* Lockout access through VGA aperture*/
 369         tmp = RREG32(mmVGA_HDP_CONTROL);
 370         if (render)
 371                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 372         else
 373                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 374         WREG32(mmVGA_HDP_CONTROL, tmp);
 375
 376         /* disable VGA render */
 377         tmp = RREG32(mmVGA_RENDER_CONTROL);
 378         if (render)
 379                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 380         else
 381                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 382         WREG32(mmVGA_RENDER_CONTROL, tmp);
 383 }
 384
 385 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
 386 {
 387         int num_crtc = 0;
 388
 389         switch (adev->asic_type) {
 390         case CHIP_BONAIRE:
 391         case CHIP_HAWAII:
 392                 num_crtc = 6;
 393                 break;
 394         case CHIP_KAVERI:
 395                 num_crtc = 4;
 396                 break;
 397         case CHIP_KABINI:
 398         case CHIP_MULLINS:
 399                 num_crtc = 2;
 400                 break;
 401         default:
 402                 num_crtc = 0;
 403         }
 404         return num_crtc;
 405 }
 406
 407 void dce_v8_0_disable_dce(struct amdgpu_device *adev)
 408 {
 409         /*Disable VGA render and enabled crtc, if has DCE engine*/
 410         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 411                 u32 tmp;
 412                 int crtc_enabled, i;
 413
 414                 dce_v8_0_set_vga_render_state(adev, false);
 415
 416                 /*Disable crtc*/
 417                 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
 418                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 419                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 420                         if (crtc_enabled) {
 421                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 422                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 423                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 424                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 425                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 426                         }
 427                 }
 428         }
 429 }
 430
 431 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
 432 {
 433         struct drm_device *dev = encoder->dev;
 434         struct amdgpu_device *adev = dev->dev_private;
 435         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 436         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 437         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 438         int bpc = 0;
 439         u32 tmp = 0;
 440         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 441
 442         if (connector) {
 443                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 444                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 445                 dither = amdgpu_connector->dither;
 446         }
 447
 448         /* LVDS/eDP FMT is set up by atom */
 449         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 450                 return;
 451
 452         /* not needed for analog */
 453         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 454             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 455                 return;
 456
 457         if (bpc == 0)
 458                 return;
 459
 460         switch (bpc) {
 461         case 6:
 462                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 463                         /* XXX sort out optimal dither settings */
 464                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 465                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 466                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 467                                 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 468                 else
 469                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 470                         (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 471                 break;
 472         case 8:
 473                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 474                         /* XXX sort out optimal dither settings */
 475                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 476                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 477                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 478                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 479                                 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 480                 else
 481                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 482                         (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 483                 break;
 484         case 10:
 485                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 486                         /* XXX sort out optimal dither settings */
 487                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 488                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 489                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 490                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 491                                 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 492                 else
 493                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 494                         (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 495                 break;
 496         default:
 497                 /* not needed */
 498                 break;
 499         }
 500
 501         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 502 }
 503
 504
 505 /* display watermark setup */
 506 /**
 507  * dce_v8_0_line_buffer_adjust - Set up the line buffer
 508  *
 509  * @adev: amdgpu_device pointer
 510  * @amdgpu_crtc: the selected display controller
 511  * @mode: the current display mode on the selected display
 512  * controller
 513  *
 514  * Setup up the line buffer allocation for
 515  * the selected display controller (CIK).
 516  * Returns the line buffer size in pixels.
 517  */
 518 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
 519                                        struct amdgpu_crtc *amdgpu_crtc,
 520                                        struct drm_display_mode *mode)
 521 {
 522         u32 tmp, buffer_alloc, i;
 523         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 524         /*
 525          * Line Buffer Setup
 526          * There are 6 line buffers, one for each display controllers.
 527          * There are 3 partitions per LB. Select the number of partitions
 528          * to enable based on the display width.  For display widths larger
 529          * than 4096, you need use to use 2 display controllers and combine
 530          * them using the stereo blender.
 531          */
 532         if (amdgpu_crtc->base.enabled && mode) {
 533                 if (mode->crtc_hdisplay < 1920) {
 534                         tmp = 1;
 535                         buffer_alloc = 2;
 536                 } else if (mode->crtc_hdisplay < 2560) {
 537                         tmp = 2;
 538                         buffer_alloc = 2;
 539                 } else if (mode->crtc_hdisplay < 4096) {
 540                         tmp = 0;
 541                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 542                 } else {
 543                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 544                         tmp = 0;
 545                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 546                 }
 547         } else {
 548                 tmp = 1;
 549                 buffer_alloc = 0;
 550         }
 551
 552         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
 553               (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
 554               (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
 555
 556         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
 557                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
 558         for (i = 0; i < adev->usec_timeout; i++) {
 559                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
 560                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
 561                         break;
 562                 udelay(1);
 563         }
 564
 565         if (amdgpu_crtc->base.enabled && mode) {
 566                 switch (tmp) {
 567                 case 0:
 568                 default:
 569                         return 4096 * 2;
 570                 case 1:
 571                         return 1920 * 2;
 572                 case 2:
 573                         return 2560 * 2;
 574                 }
 575         }
 576
 577         /* controller not enabled, so no lb used */
 578         return 0;
 579 }
 580
 581 /**
 582  * cik_get_number_of_dram_channels - get the number of dram channels
 583  *
 584  * @adev: amdgpu_device pointer
 585  *
 586  * Look up the number of video ram channels (CIK).
 587  * Used for display watermark bandwidth calculations
 588  * Returns the number of dram channels
 589  */
 590 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 591 {
 592         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 593
 594         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 595         case 0:
 596         default:
 597                 return 1;
 598         case 1:
 599                 return 2;
 600         case 2:
 601                 return 4;
 602         case 3:
 603                 return 8;
 604         case 4:
 605                 return 3;
 606         case 5:
 607                 return 6;
 608         case 6:
 609                 return 10;
 610         case 7:
 611                 return 12;
 612         case 8:
 613                 return 16;
 614         }
 615 }
 616
 617 struct dce8_wm_params {
 618         u32 dram_channels; /* number of dram channels */
 619         u32 yclk;          /* bandwidth per dram data pin in kHz */
 620         u32 sclk;          /* engine clock in kHz */
 621         u32 disp_clk;      /* display clock in kHz */
 622         u32 src_width;     /* viewport width */
 623         u32 active_time;   /* active display time in ns */
 624         u32 blank_time;    /* blank time in ns */
 625         bool interlaced;    /* mode is interlaced */
 626         fixed20_12 vsc;    /* vertical scale ratio */
 627         u32 num_heads;     /* number of active crtcs */
 628         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 629         u32 lb_size;       /* line buffer allocated to pipe */
 630         u32 vtaps;         /* vertical scaler taps */
 631 };
 632
 633 /**
 634  * dce_v8_0_dram_bandwidth - get the dram bandwidth
 635  *
 636  * @wm: watermark calculation data
 637  *
 638  * Calculate the raw dram bandwidth (CIK).
 639  * Used for display watermark bandwidth calculations
 640  * Returns the dram bandwidth in MBytes/s
 641  */
 642 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
 643 {
 644         /* Calculate raw DRAM Bandwidth */
 645         fixed20_12 dram_efficiency; /* 0.7 */
 646         fixed20_12 yclk, dram_channels, bandwidth;
 647         fixed20_12 a;
 648
 649         a.full = dfixed_const(1000);
 650         yclk.full = dfixed_const(wm->yclk);
 651         yclk.full = dfixed_div(yclk, a);
 652         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 653         a.full = dfixed_const(10);
 654         dram_efficiency.full = dfixed_const(7);
 655         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 656         bandwidth.full = dfixed_mul(dram_channels, yclk);
 657         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 658
 659         return dfixed_trunc(bandwidth);
 660 }
 661
 662 /**
 663  * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
 664  *
 665  * @wm: watermark calculation data
 666  *
 667  * Calculate the dram bandwidth used for display (CIK).
 668  * Used for display watermark bandwidth calculations
 669  * Returns the dram bandwidth for display in MBytes/s
 670  */
 671 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 672 {
 673         /* Calculate DRAM Bandwidth and the part allocated to display. */
 674         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 675         fixed20_12 yclk, dram_channels, bandwidth;
 676         fixed20_12 a;
 677
 678         a.full = dfixed_const(1000);
 679         yclk.full = dfixed_const(wm->yclk);
 680         yclk.full = dfixed_div(yclk, a);
 681         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 682         a.full = dfixed_const(10);
 683         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 684         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 685         bandwidth.full = dfixed_mul(dram_channels, yclk);
 686         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 687
 688         return dfixed_trunc(bandwidth);
 689 }
 690
 691 /**
 692  * dce_v8_0_data_return_bandwidth - get the data return bandwidth
 693  *
 694  * @wm: watermark calculation data
 695  *
 696  * Calculate the data return bandwidth used for display (CIK).
 697  * Used for display watermark bandwidth calculations
 698  * Returns the data return bandwidth in MBytes/s
 699  */
 700 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
 701 {
 702         /* Calculate the display Data return Bandwidth */
 703         fixed20_12 return_efficiency; /* 0.8 */
 704         fixed20_12 sclk, bandwidth;
 705         fixed20_12 a;
 706
 707         a.full = dfixed_const(1000);
 708         sclk.full = dfixed_const(wm->sclk);
 709         sclk.full = dfixed_div(sclk, a);
 710         a.full = dfixed_const(10);
 711         return_efficiency.full = dfixed_const(8);
 712         return_efficiency.full = dfixed_div(return_efficiency, a);
 713         a.full = dfixed_const(32);
 714         bandwidth.full = dfixed_mul(a, sclk);
 715         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 716
 717         return dfixed_trunc(bandwidth);
 718 }
 719
 720 /**
 721  * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
 722  *
 723  * @wm: watermark calculation data
 724  *
 725  * Calculate the dmif bandwidth used for display (CIK).
 726  * Used for display watermark bandwidth calculations
 727  * Returns the dmif bandwidth in MBytes/s
 728  */
 729 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
 730 {
 731         /* Calculate the DMIF Request Bandwidth */
 732         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 733         fixed20_12 disp_clk, bandwidth;
 734         fixed20_12 a, b;
 735
 736         a.full = dfixed_const(1000);
 737         disp_clk.full = dfixed_const(wm->disp_clk);
 738         disp_clk.full = dfixed_div(disp_clk, a);
 739         a.full = dfixed_const(32);
 740         b.full = dfixed_mul(a, disp_clk);
 741
 742         a.full = dfixed_const(10);
 743         disp_clk_request_efficiency.full = dfixed_const(8);
 744         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 745
 746         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 747
 748         return dfixed_trunc(bandwidth);
 749 }
 750
 751 /**
 752  * dce_v8_0_available_bandwidth - get the min available bandwidth
 753  *
 754  * @wm: watermark calculation data
 755  *
 756  * Calculate the min available bandwidth used for display (CIK).
 757  * Used for display watermark bandwidth calculations
 758  * Returns the min available bandwidth in MBytes/s
 759  */
 760 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
 761 {
 762         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 763         u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
 764         u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
 765         u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
 766
 767         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 768 }
 769
 770 /**
 771  * dce_v8_0_average_bandwidth - get the average available bandwidth
 772  *
 773  * @wm: watermark calculation data
 774  *
 775  * Calculate the average available bandwidth used for display (CIK).
 776  * Used for display watermark bandwidth calculations
 777  * Returns the average available bandwidth in MBytes/s
 778  */
 779 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
 780 {
 781         /* Calculate the display mode Average Bandwidth
 782          * DisplayMode should contain the source and destination dimensions,
 783          * timing, etc.
 784          */
 785         fixed20_12 bpp;
 786         fixed20_12 line_time;
 787         fixed20_12 src_width;
 788         fixed20_12 bandwidth;
 789         fixed20_12 a;
 790
 791         a.full = dfixed_const(1000);
 792         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 793         line_time.full = dfixed_div(line_time, a);
 794         bpp.full = dfixed_const(wm->bytes_per_pixel);
 795         src_width.full = dfixed_const(wm->src_width);
 796         bandwidth.full = dfixed_mul(src_width, bpp);
 797         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 798         bandwidth.full = dfixed_div(bandwidth, line_time);
 799
 800         return dfixed_trunc(bandwidth);
 801 }
 802
 803 /**
 804  * dce_v8_0_latency_watermark - get the latency watermark
 805  *
 806  * @wm: watermark calculation data
 807  *
 808  * Calculate the latency watermark (CIK).
 809  * Used for display watermark bandwidth calculations
 810  * Returns the latency watermark in ns
 811  */
 812 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
 813 {
 814         /* First calculate the latency in ns */
 815         u32 mc_latency = 2000; /* 2000 ns. */
 816         u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
 817         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 818         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 819         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 820         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 821                 (wm->num_heads * cursor_line_pair_return_time);
 822         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 823         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 824         u32 tmp, dmif_size = 12288;
 825         fixed20_12 a, b, c;
 826
 827         if (wm->num_heads == 0)
 828                 return 0;
 829
 830         a.full = dfixed_const(2);
 831         b.full = dfixed_const(1);
 832         if ((wm->vsc.full > a.full) ||
 833             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 834             (wm->vtaps >= 5) ||
 835             ((wm->vsc.full >= a.full) && wm->interlaced))
 836                 max_src_lines_per_dst_line = 4;
 837         else
 838                 max_src_lines_per_dst_line = 2;
 839
 840         a.full = dfixed_const(available_bandwidth);
 841         b.full = dfixed_const(wm->num_heads);
 842         a.full = dfixed_div(a, b);
 843         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 844         tmp = min(dfixed_trunc(a), tmp);
 845
 846         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 847
 848         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 849         b.full = dfixed_const(1000);
 850         c.full = dfixed_const(lb_fill_bw);
 851         b.full = dfixed_div(c, b);
 852         a.full = dfixed_div(a, b);
 853         line_fill_time = dfixed_trunc(a);
 854
 855         if (line_fill_time < wm->active_time)
 856                 return latency;
 857         else
 858                 return latency + (line_fill_time - wm->active_time);
 859
 860 }
 861
 862 /**
 863  * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 864  * average and available dram bandwidth
 865  *
 866  * @wm: watermark calculation data
 867  *
 868  * Check if the display average bandwidth fits in the display
 869  * dram bandwidth (CIK).
 870  * Used for display watermark bandwidth calculations
 871  * Returns true if the display fits, false if not.
 872  */
 873 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 874 {
 875         if (dce_v8_0_average_bandwidth(wm) <=
 876             (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 877                 return true;
 878         else
 879                 return false;
 880 }
 881
 882 /**
 883  * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
 884  * average and available bandwidth
 885  *
 886  * @wm: watermark calculation data
 887  *
 888  * Check if the display average bandwidth fits in the display
 889  * available bandwidth (CIK).
 890  * Used for display watermark bandwidth calculations
 891  * Returns true if the display fits, false if not.
 892  */
 893 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
 894 {
 895         if (dce_v8_0_average_bandwidth(wm) <=
 896             (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
 897                 return true;
 898         else
 899                 return false;
 900 }
 901
 902 /**
 903  * dce_v8_0_check_latency_hiding - check latency hiding
 904  *
 905  * @wm: watermark calculation data
 906  *
 907  * Check latency hiding (CIK).
 908  * Used for display watermark bandwidth calculations
 909  * Returns true if the display fits, false if not.
 910  */
 911 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
 912 {
 913         u32 lb_partitions = wm->lb_size / wm->src_width;
 914         u32 line_time = wm->active_time + wm->blank_time;
 915         u32 latency_tolerant_lines;
 916         u32 latency_hiding;
 917         fixed20_12 a;
 918
 919         a.full = dfixed_const(1);
 920         if (wm->vsc.full > a.full)
 921                 latency_tolerant_lines = 1;
 922         else {
 923                 if (lb_partitions <= (wm->vtaps + 1))
 924                         latency_tolerant_lines = 1;
 925                 else
 926                         latency_tolerant_lines = 2;
 927         }
 928
 929         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 930
 931         if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
 932                 return true;
 933         else
 934                 return false;
 935 }
 936
 937 /**
 938  * dce_v8_0_program_watermarks - program display watermarks
 939  *
 940  * @adev: amdgpu_device pointer
 941  * @amdgpu_crtc: the selected display controller
 942  * @lb_size: line buffer size
 943  * @num_heads: number of display controllers in use
 944  *
 945  * Calculate and program the display watermarks for the
 946  * selected display controller (CIK).
 947  */
 948 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 949                                         struct amdgpu_crtc *amdgpu_crtc,
 950                                         u32 lb_size, u32 num_heads)
 951 {
 952         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 953         struct dce8_wm_params wm_low, wm_high;
 954         u32 active_time;
 955         u32 line_time = 0;
 956         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 957         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 958
 959         if (amdgpu_crtc->base.enabled && num_heads && mode) {
 960                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
 961                                             (u32)mode->clock);
 962                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
 963                                           (u32)mode->clock);
 964                 line_time = min(line_time, (u32)65535);
 965
 966                 /* watermark for high clocks */
 967                 if (adev->pm.dpm_enabled) {
 968                         wm_high.yclk =
 969                                 amdgpu_dpm_get_mclk(adev, false) * 10;
 970                         wm_high.sclk =
 971                                 amdgpu_dpm_get_sclk(adev, false) * 10;
 972                 } else {
 973                         wm_high.yclk = adev->pm.current_mclk * 10;
 974                         wm_high.sclk = adev->pm.current_sclk * 10;
 975                 }
 976
 977                 wm_high.disp_clk = mode->clock;
 978                 wm_high.src_width = mode->crtc_hdisplay;
 979                 wm_high.active_time = active_time;
 980                 wm_high.blank_time = line_time - wm_high.active_time;
 981                 wm_high.interlaced = false;
 982                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 983                         wm_high.interlaced = true;
 984                 wm_high.vsc = amdgpu_crtc->vsc;
 985                 wm_high.vtaps = 1;
 986                 if (amdgpu_crtc->rmx_type != RMX_OFF)
 987                         wm_high.vtaps = 2;
 988                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
 989                 wm_high.lb_size = lb_size;
 990                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
 991                 wm_high.num_heads = num_heads;
 992
 993                 /* set for high clocks */
 994                 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
 995
 996                 /* possibly force display priority to high */
 997                 /* should really do this at mode validation time... */
 998                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
 999                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1000                     !dce_v8_0_check_latency_hiding(&wm_high) ||
1001                     (adev->mode_info.disp_priority == 2)) {
1002                         DRM_DEBUG_KMS("force priority to high\n");
1003                 }
1004
1005                 /* watermark for low clocks */
1006                 if (adev->pm.dpm_enabled) {
1007                         wm_low.yclk =
1008                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1009                         wm_low.sclk =
1010                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1011                 } else {
1012                         wm_low.yclk = adev->pm.current_mclk * 10;
1013                         wm_low.sclk = adev->pm.current_sclk * 10;
1014                 }
1015
1016                 wm_low.disp_clk = mode->clock;
1017                 wm_low.src_width = mode->crtc_hdisplay;
1018                 wm_low.active_time = active_time;
1019                 wm_low.blank_time = line_time - wm_low.active_time;
1020                 wm_low.interlaced = false;
1021                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1022                         wm_low.interlaced = true;
1023                 wm_low.vsc = amdgpu_crtc->vsc;
1024                 wm_low.vtaps = 1;
1025                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1026                         wm_low.vtaps = 2;
1027                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1028                 wm_low.lb_size = lb_size;
1029                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1030                 wm_low.num_heads = num_heads;
1031
1032                 /* set for low clocks */
1033                 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1034
1035                 /* possibly force display priority to high */
1036                 /* should really do this at mode validation time... */
1037                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1038                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1039                     !dce_v8_0_check_latency_hiding(&wm_low) ||
1040                     (adev->mode_info.disp_priority == 2)) {
1041                         DRM_DEBUG_KMS("force priority to high\n");
1042                 }
1043                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1044         }
1045
1046         /* select wm A */
1047         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1048         tmp = wm_mask;
1049         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1050         tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1051         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1052         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1053                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1054                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1055         /* select wm B */
1056         tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1057         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1058         tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1059         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1060         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1061                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1062                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1063         /* restore original selection */
1064         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1065
1066         /* save values for DPM */
1067         amdgpu_crtc->line_time = line_time;
1068         amdgpu_crtc->wm_high = latency_watermark_a;
1069         amdgpu_crtc->wm_low = latency_watermark_b;
1070         /* Save number of lines the linebuffer leads before the scanout */
1071         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1072 }
1073
1074 /**
1075  * dce_v8_0_bandwidth_update - program display watermarks
1076  *
1077  * @adev: amdgpu_device pointer
1078  *
1079  * Calculate and program the display watermarks and line
1080  * buffer allocation (CIK).
1081  */
1082 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1083 {
1084         struct drm_display_mode *mode = NULL;
1085         u32 num_heads = 0, lb_size;
1086         int i;
1087
1088         amdgpu_display_update_priority(adev);
1089
1090         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1091                 if (adev->mode_info.crtcs[i]->base.enabled)
1092                         num_heads++;
1093         }
1094         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1095                 mode = &adev->mode_info.crtcs[i]->base.mode;
1096                 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1097                 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1098                                             lb_size, num_heads);
1099         }
1100 }
1101
1102 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1103 {
1104         int i;
1105         u32 offset, tmp;
1106
1107         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1108                 offset = adev->mode_info.audio.pin[i].offset;
1109                 tmp = RREG32_AUDIO_ENDPT(offset,
1110                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1111                 if (((tmp &
1112                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1113                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1114                         adev->mode_info.audio.pin[i].connected = false;
1115                 else
1116                         adev->mode_info.audio.pin[i].connected = true;
1117         }
1118 }
1119
1120 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1121 {
1122         int i;
1123
1124         dce_v8_0_audio_get_connected_pins(adev);
1125
1126         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1127                 if (adev->mode_info.audio.pin[i].connected)
1128                         return &adev->mode_info.audio.pin[i];
1129         }
1130         DRM_ERROR("No connected audio pins found!\n");
1131         return NULL;
1132 }
1133
1134 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1135 {
1136         struct amdgpu_device *adev = encoder->dev->dev_private;
1137         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1138         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1139         u32 offset;
1140
1141         if (!dig || !dig->afmt || !dig->afmt->pin)
1142                 return;
1143
1144         offset = dig->afmt->offset;
1145
1146         WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1147                (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1148 }
1149
1150 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1151                                                 struct drm_display_mode *mode)
1152 {
1153         struct amdgpu_device *adev = encoder->dev->dev_private;
1154         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1155         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1156         struct drm_connector *connector;
1157         struct amdgpu_connector *amdgpu_connector = NULL;
1158         u32 tmp = 0, offset;
1159
1160         if (!dig || !dig->afmt || !dig->afmt->pin)
1161                 return;
1162
1163         offset = dig->afmt->pin->offset;
1164
1165         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1166                 if (connector->encoder == encoder) {
1167                         amdgpu_connector = to_amdgpu_connector(connector);
1168                         break;
1169                 }
1170         }
1171
1172         if (!amdgpu_connector) {
1173                 DRM_ERROR("Couldn't find encoder's connector\n");
1174                 return;
1175         }
1176
1177         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1178                 if (connector->latency_present[1])
1179                         tmp =
1180                         (connector->video_latency[1] <<
1181                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1182                         (connector->audio_latency[1] <<
1183                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1184                 else
1185                         tmp =
1186                         (0 <<
1187                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1188                         (0 <<
1189                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1190         } else {
1191                 if (connector->latency_present[0])
1192                         tmp =
1193                         (connector->video_latency[0] <<
1194                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1195                         (connector->audio_latency[0] <<
1196                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1197                 else
1198                         tmp =
1199                         (0 <<
1200                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1201                         (0 <<
1202                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1203
1204         }
1205         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1206 }
1207
1208 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1209 {
1210         struct amdgpu_device *adev = encoder->dev->dev_private;
1211         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1212         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1213         struct drm_connector *connector;
1214         struct amdgpu_connector *amdgpu_connector = NULL;
1215         u32 offset, tmp;
1216         u8 *sadb = NULL;
1217         int sad_count;
1218
1219         if (!dig || !dig->afmt || !dig->afmt->pin)
1220                 return;
1221
1222         offset = dig->afmt->pin->offset;
1223
1224         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1225                 if (connector->encoder == encoder) {
1226                         amdgpu_connector = to_amdgpu_connector(connector);
1227                         break;
1228                 }
1229         }
1230
1231         if (!amdgpu_connector) {
1232                 DRM_ERROR("Couldn't find encoder's connector\n");
1233                 return;
1234         }
1235
1236         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1237         if (sad_count < 0) {
1238                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1239                 sad_count = 0;
1240         }
1241
1242         /* program the speaker allocation */
1243         tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1244         tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1245                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1246         /* set HDMI mode */
1247         tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1248         if (sad_count)
1249                 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1250         else
1251                 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1252         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1253
1254         kfree(sadb);
1255 }
1256
1257 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1258 {
1259         struct amdgpu_device *adev = encoder->dev->dev_private;
1260         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1261         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1262         u32 offset;
1263         struct drm_connector *connector;
1264         struct amdgpu_connector *amdgpu_connector = NULL;
1265         struct cea_sad *sads;
1266         int i, sad_count;
1267
1268         static const u16 eld_reg_to_type[][2] = {
1269                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1270                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1271                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1272                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1273                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1274                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1275                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1276                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1277                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1278                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1279                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1280                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1281         };
1282
1283         if (!dig || !dig->afmt || !dig->afmt->pin)
1284                 return;
1285
1286         offset = dig->afmt->pin->offset;
1287
1288         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1289                 if (connector->encoder == encoder) {
1290                         amdgpu_connector = to_amdgpu_connector(connector);
1291                         break;
1292                 }
1293         }
1294
1295         if (!amdgpu_connector) {
1296                 DRM_ERROR("Couldn't find encoder's connector\n");
1297                 return;
1298         }
1299
1300         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1301         if (sad_count <= 0) {
1302                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1303                 return;
1304         }
1305         BUG_ON(!sads);
1306
1307         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1308                 u32 value = 0;
1309                 u8 stereo_freqs = 0;
1310                 int max_channels = -1;
1311                 int j;
1312
1313                 for (j = 0; j < sad_count; j++) {
1314                         struct cea_sad *sad = &sads[j];
1315
1316                         if (sad->format == eld_reg_to_type[i][1]) {
1317                                 if (sad->channels > max_channels) {
1318                                         value = (sad->channels <<
1319                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1320                                                 (sad->byte2 <<
1321                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1322                                                 (sad->freq <<
1323                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1324                                         max_channels = sad->channels;
1325                                 }
1326
1327                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1328                                         stereo_freqs |= sad->freq;
1329                                 else
1330                                         break;
1331                         }
1332                 }
1333
1334                 value |= (stereo_freqs <<
1335                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1336
1337                 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1338         }
1339
1340         kfree(sads);
1341 }
1342
1343 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1344                                   struct amdgpu_audio_pin *pin,
1345                                   bool enable)
1346 {
1347         if (!pin)
1348                 return;
1349
1350         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1351                 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1352 }
1353
1354 static const u32 pin_offsets[7] =
1355 {
1356         (0x1780 - 0x1780),
1357         (0x1786 - 0x1780),
1358         (0x178c - 0x1780),
1359         (0x1792 - 0x1780),
1360         (0x1798 - 0x1780),
1361         (0x179d - 0x1780),
1362         (0x17a4 - 0x1780),
1363 };
1364
1365 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1366 {
1367         int i;
1368
1369         if (!amdgpu_audio)
1370                 return 0;
1371
1372         adev->mode_info.audio.enabled = true;
1373
1374         if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1375                 adev->mode_info.audio.num_pins = 7;
1376         else if ((adev->asic_type == CHIP_KABINI) ||
1377                  (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1378                 adev->mode_info.audio.num_pins = 3;
1379         else if ((adev->asic_type == CHIP_BONAIRE) ||
1380                  (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1381                 adev->mode_info.audio.num_pins = 7;
1382         else
1383                 adev->mode_info.audio.num_pins = 3;
1384
1385         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1386                 adev->mode_info.audio.pin[i].channels = -1;
1387                 adev->mode_info.audio.pin[i].rate = -1;
1388                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1389                 adev->mode_info.audio.pin[i].status_bits = 0;
1390                 adev->mode_info.audio.pin[i].category_code = 0;
1391                 adev->mode_info.audio.pin[i].connected = false;
1392                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1393                 adev->mode_info.audio.pin[i].id = i;
1394                 /* disable audio.  it will be set up later */
1395                 /* XXX remove once we switch to ip funcs */
1396                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1397         }
1398
1399         return 0;
1400 }
1401
1402 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1403 {
1404         int i;
1405
1406         if (!amdgpu_audio)
1407                 return;
1408
1409         if (!adev->mode_info.audio.enabled)
1410                 return;
1411
1412         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1413                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1414
1415         adev->mode_info.audio.enabled = false;
1416 }
1417
1418 /*
1419  * update the N and CTS parameters for a given pixel clock rate
1420  */
1421 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1422 {
1423         struct drm_device *dev = encoder->dev;
1424         struct amdgpu_device *adev = dev->dev_private;
1425         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1426         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1427         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1428         uint32_t offset = dig->afmt->offset;
1429
1430         WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1431         WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1432
1433         WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1434         WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1435
1436         WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1437         WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1438 }
1439
1440 /*
1441  * build a HDMI Video Info Frame
1442  */
1443 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1444                                                void *buffer, size_t size)
1445 {
1446         struct drm_device *dev = encoder->dev;
1447         struct amdgpu_device *adev = dev->dev_private;
1448         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1449         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1450         uint32_t offset = dig->afmt->offset;
1451         uint8_t *frame = buffer + 3;
1452         uint8_t *header = buffer;
1453
1454         WREG32(mmAFMT_AVI_INFO0 + offset,
1455                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1456         WREG32(mmAFMT_AVI_INFO1 + offset,
1457                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1458         WREG32(mmAFMT_AVI_INFO2 + offset,
1459                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1460         WREG32(mmAFMT_AVI_INFO3 + offset,
1461                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1462 }
1463
1464 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1465 {
1466         struct drm_device *dev = encoder->dev;
1467         struct amdgpu_device *adev = dev->dev_private;
1468         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1469         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1470         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1471         u32 dto_phase = 24 * 1000;
1472         u32 dto_modulo = clock;
1473
1474         if (!dig || !dig->afmt)
1475                 return;
1476
1477         /* XXX two dtos; generally use dto0 for hdmi */
1478         /* Express [24MHz / target pixel clock] as an exact rational
1479          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1480          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1481          */
1482         WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1483         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1484         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1485 }
1486
1487 /*
1488  * update the info frames with the data from the current display mode
1489  */
1490 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1491                                   struct drm_display_mode *mode)
1492 {
1493         struct drm_device *dev = encoder->dev;
1494         struct amdgpu_device *adev = dev->dev_private;
1495         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1496         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1497         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1498         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1499         struct hdmi_avi_infoframe frame;
1500         uint32_t offset, val;
1501         ssize_t err;
1502         int bpc = 8;
1503
1504         if (!dig || !dig->afmt)
1505                 return;
1506
1507         /* Silent, r600_hdmi_enable will raise WARN for us */
1508         if (!dig->afmt->enabled)
1509                 return;
1510
1511         offset = dig->afmt->offset;
1512
1513         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1514         if (encoder->crtc) {
1515                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1516                 bpc = amdgpu_crtc->bpc;
1517         }
1518
1519         /* disable audio prior to setting up hw */
1520         dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1521         dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1522
1523         dce_v8_0_audio_set_dto(encoder, mode->clock);
1524
1525         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1526                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1527
1528         WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1529
1530         val = RREG32(mmHDMI_CONTROL + offset);
1531         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1532         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1533
1534         switch (bpc) {
1535         case 0:
1536         case 6:
1537         case 8:
1538         case 16:
1539         default:
1540                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1541                           connector->name, bpc);
1542                 break;
1543         case 10:
1544                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1545                 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1546                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1547                           connector->name);
1548                 break;
1549         case 12:
1550                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1551                 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1552                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1553                           connector->name);
1554                 break;
1555         }
1556
1557         WREG32(mmHDMI_CONTROL + offset, val);
1558
1559         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1560                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1561                HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1562                HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1563
1564         WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1565                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1566                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1567
1568         WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1569                AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1570
1571         WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1572                (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1573
1574         WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1575
1576         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1577                (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1578                (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1579
1580         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1581                AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1582
1583         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1584
1585         if (bpc > 8)
1586                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1587                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1588         else
1589                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1590                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1591                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1592
1593         dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1594
1595         WREG32(mmAFMT_60958_0 + offset,
1596                (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1597
1598         WREG32(mmAFMT_60958_1 + offset,
1599                (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1600
1601         WREG32(mmAFMT_60958_2 + offset,
1602                (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1603                (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1604                (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1605                (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1606                (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1607                (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1608
1609         dce_v8_0_audio_write_speaker_allocation(encoder);
1610
1611
1612         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1613                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1614
1615         dce_v8_0_afmt_audio_select_pin(encoder);
1616         dce_v8_0_audio_write_sad_regs(encoder);
1617         dce_v8_0_audio_write_latency_fields(encoder, mode);
1618
1619         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1620         if (err < 0) {
1621                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1622                 return;
1623         }
1624
1625         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1626         if (err < 0) {
1627                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1628                 return;
1629         }
1630
1631         dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1632
1633         WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1634                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1635                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1636
1637         WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1638                  (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1639                  ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1640
1641         WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1642                   AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1643
1644         WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1645         WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1646         WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1647         WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1648
1649         /* enable audio after setting up hw */
1650         dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1651 }
1652
1653 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1654 {
1655         struct drm_device *dev = encoder->dev;
1656         struct amdgpu_device *adev = dev->dev_private;
1657         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1658         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1659
1660         if (!dig || !dig->afmt)
1661                 return;
1662
1663         /* Silent, r600_hdmi_enable will raise WARN for us */
1664         if (enable && dig->afmt->enabled)
1665                 return;
1666         if (!enable && !dig->afmt->enabled)
1667                 return;
1668
1669         if (!enable && dig->afmt->pin) {
1670                 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1671                 dig->afmt->pin = NULL;
1672         }
1673
1674         dig->afmt->enabled = enable;
1675
1676         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1677                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1678 }
1679
1680 static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1681 {
1682         int i;
1683
1684         for (i = 0; i < adev->mode_info.num_dig; i++)
1685                 adev->mode_info.afmt[i] = NULL;
1686
1687         /* DCE8 has audio blocks tied to DIG encoders */
1688         for (i = 0; i < adev->mode_info.num_dig; i++) {
1689                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1690                 if (adev->mode_info.afmt[i]) {
1691                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1692                         adev->mode_info.afmt[i]->id = i;
1693                 } else {
1694                         int j;
1695                         for (j = 0; j < i; j++) {
1696                                 kfree(adev->mode_info.afmt[j]);
1697                                 adev->mode_info.afmt[j] = NULL;
1698                         }
1699                         return -ENOMEM;
1700                 }
1701         }
1702         return 0;
1703 }
1704
1705 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1706 {
1707         int i;
1708
1709         for (i = 0; i < adev->mode_info.num_dig; i++) {
1710                 kfree(adev->mode_info.afmt[i]);
1711                 adev->mode_info.afmt[i] = NULL;
1712         }
1713 }
1714
1715 static const u32 vga_control_regs[6] =
1716 {
1717         mmD1VGA_CONTROL,
1718         mmD2VGA_CONTROL,
1719         mmD3VGA_CONTROL,
1720         mmD4VGA_CONTROL,
1721         mmD5VGA_CONTROL,
1722         mmD6VGA_CONTROL,
1723 };
1724
1725 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1726 {
1727         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1728         struct drm_device *dev = crtc->dev;
1729         struct amdgpu_device *adev = dev->dev_private;
1730         u32 vga_control;
1731
1732         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1733         if (enable)
1734                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1735         else
1736                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1737 }
1738
1739 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1740 {
1741         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1742         struct drm_device *dev = crtc->dev;
1743         struct amdgpu_device *adev = dev->dev_private;
1744
1745         if (enable)
1746                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1747         else
1748                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1749 }
1750
1751 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1752                                      struct drm_framebuffer *fb,
1753                                      int x, int y, int atomic)
1754 {
1755         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1756         struct drm_device *dev = crtc->dev;
1757         struct amdgpu_device *adev = dev->dev_private;
1758         struct drm_framebuffer *target_fb;
1759         struct drm_gem_object *obj;
1760         struct amdgpu_bo *abo;
1761         uint64_t fb_location, tiling_flags;
1762         uint32_t fb_format, fb_pitch_pixels;
1763         u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1764         u32 pipe_config;
1765         u32 viewport_w, viewport_h;
1766         int r;
1767         bool bypass_lut = false;
1768         struct drm_format_name_buf format_name;
1769
1770         /* no fb bound */
1771         if (!atomic && !crtc->primary->fb) {
1772                 DRM_DEBUG_KMS("No FB bound\n");
1773                 return 0;
1774         }
1775
1776         if (atomic)
1777                 target_fb = fb;
1778         else
1779                 target_fb = crtc->primary->fb;
1780
1781         /* If atomic, assume fb object is pinned & idle & fenced and
1782          * just update base pointers
1783          */
1784         obj = target_fb->obj[0];
1785         abo = gem_to_amdgpu_bo(obj);
1786         r = amdgpu_bo_reserve(abo, false);
1787         if (unlikely(r != 0))
1788                 return r;
1789
1790         if (!atomic) {
1791                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1792                 if (unlikely(r != 0)) {
1793                         amdgpu_bo_unreserve(abo);
1794                         return -EINVAL;
1795                 }
1796         }
1797         fb_location = amdgpu_bo_gpu_offset(abo);
1798
1799         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1800         amdgpu_bo_unreserve(abo);
1801
1802         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1803
1804         switch (target_fb->format->format) {
1805         case DRM_FORMAT_C8:
1806                 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1807                              (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1808                 break;
1809         case DRM_FORMAT_XRGB4444:
1810         case DRM_FORMAT_ARGB4444:
1811                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1812                              (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1813 #ifdef __BIG_ENDIAN
1814                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1815 #endif
1816                 break;
1817         case DRM_FORMAT_XRGB1555:
1818         case DRM_FORMAT_ARGB1555:
1819                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1820                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1821 #ifdef __BIG_ENDIAN
1822                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1823 #endif
1824                 break;
1825         case DRM_FORMAT_BGRX5551:
1826         case DRM_FORMAT_BGRA5551:
1827                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1828                              (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1829 #ifdef __BIG_ENDIAN
1830                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1831 #endif
1832                 break;
1833         case DRM_FORMAT_RGB565:
1834                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1835                              (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1836 #ifdef __BIG_ENDIAN
1837                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1838 #endif
1839                 break;
1840         case DRM_FORMAT_XRGB8888:
1841         case DRM_FORMAT_ARGB8888:
1842                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1843                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1844 #ifdef __BIG_ENDIAN
1845                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1846 #endif
1847                 break;
1848         case DRM_FORMAT_XRGB2101010:
1849         case DRM_FORMAT_ARGB2101010:
1850                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1851                              (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1852 #ifdef __BIG_ENDIAN
1853                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1854 #endif
1855                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1856                 bypass_lut = true;
1857                 break;
1858         case DRM_FORMAT_BGRX1010102:
1859         case DRM_FORMAT_BGRA1010102:
1860                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1861                              (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1862 #ifdef __BIG_ENDIAN
1863                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1864 #endif
1865                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1866                 bypass_lut = true;
1867                 break;
1868         case DRM_FORMAT_XBGR8888:
1869         case DRM_FORMAT_ABGR8888:
1870                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1871                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1872                 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1873                            (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1874 #ifdef __BIG_ENDIAN
1875                 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1876 #endif
1877                 break;
1878         default:
1879                 DRM_ERROR("Unsupported screen format %s\n",
1880                           drm_get_format_name(target_fb->format->format, &format_name));
1881                 return -EINVAL;
1882         }
1883
1884         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1885                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1886
1887                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1888                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1889                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1890                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1891                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1892
1893                 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1894                 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1895                 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1896                 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1897                 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1898                 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1899                 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1900         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1901                 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1902         }
1903
1904         fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1905
1906         dce_v8_0_vga_enable(crtc, false);
1907
1908         /* Make sure surface address is updated at vertical blank rather than
1909          * horizontal blank
1910          */
1911         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1912
1913         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1914                upper_32_bits(fb_location));
1915         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1916                upper_32_bits(fb_location));
1917         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1918                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1919         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1920                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1921         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1922         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1923
1924         /*
1925          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1926          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1927          * retain the full precision throughout the pipeline.
1928          */
1929         WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1930                  (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1931                  ~LUT_10BIT_BYPASS_EN);
1932
1933         if (bypass_lut)
1934                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1935
1936         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1937         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1938         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1939         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1940         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1941         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1942
1943         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1944         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1945
1946         dce_v8_0_grph_enable(crtc, true);
1947
1948         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1949                target_fb->height);
1950
1951         x &= ~3;
1952         y &= ~1;
1953         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1954                (x << 16) | y);
1955         viewport_w = crtc->mode.hdisplay;
1956         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1957         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1958                (viewport_w << 16) | viewport_h);
1959
1960         /* set pageflip to happen anywhere in vblank interval */
1961         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1962
1963         if (!atomic && fb && fb != crtc->primary->fb) {
1964                 abo = gem_to_amdgpu_bo(fb->obj[0]);
1965                 r = amdgpu_bo_reserve(abo, true);
1966                 if (unlikely(r != 0))
1967                         return r;
1968                 amdgpu_bo_unpin(abo);
1969                 amdgpu_bo_unreserve(abo);
1970         }
1971
1972         /* Bytes per pixel may have changed */
1973         dce_v8_0_bandwidth_update(adev);
1974
1975         return 0;
1976 }
1977
1978 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
1979                                     struct drm_display_mode *mode)
1980 {
1981         struct drm_device *dev = crtc->dev;
1982         struct amdgpu_device *adev = dev->dev_private;
1983         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1984
1985         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1986                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
1987                        LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
1988         else
1989                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
1990 }
1991
1992 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
1993 {
1994         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1995         struct drm_device *dev = crtc->dev;
1996         struct amdgpu_device *adev = dev->dev_private;
1997         u16 *r, *g, *b;
1998         int i;
1999
2000         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2001
2002         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2003                ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2004                 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2005         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2006                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2007         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2008                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2009         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2010                ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2011                 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2012
2013         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2014
2015         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2016         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2017         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2018
2019         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2020         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2021         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2022
2023         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2024         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2025
2026         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2027         r = crtc->gamma_store;
2028         g = r + crtc->gamma_size;
2029         b = g + crtc->gamma_size;
2030         for (i = 0; i < 256; i++) {
2031                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2032                        ((*r++ & 0xffc0) << 14) |
2033                        ((*g++ & 0xffc0) << 4) |
2034                        (*b++ >> 6));
2035         }
2036
2037         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2038                ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2039                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2040                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2041         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2042                ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2043                 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2044         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2045                ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2046                 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2047         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2048                ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2049                 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2050         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2051         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2052         /* XXX this only needs to be programmed once per crtc at startup,
2053          * not sure where the best place for it is
2054          */
2055         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2056                ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2057 }
2058
2059 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2060 {
2061         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2062         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2063
2064         switch (amdgpu_encoder->encoder_id) {
2065         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2066                 if (dig->linkb)
2067                         return 1;
2068                 else
2069                         return 0;
2070                 break;
2071         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2072                 if (dig->linkb)
2073                         return 3;
2074                 else
2075                         return 2;
2076                 break;
2077         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2078                 if (dig->linkb)
2079                         return 5;
2080                 else
2081                         return 4;
2082                 break;
2083         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2084                 return 6;
2085                 break;
2086         default:
2087                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2088                 return 0;
2089         }
2090 }
2091
2092 /**
2093  * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2094  *
2095  * @crtc: drm crtc
2096  *
2097  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2098  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2099  * monitors a dedicated PPLL must be used.  If a particular board has
2100  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2101  * as there is no need to program the PLL itself.  If we are not able to
2102  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2103  * avoid messing up an existing monitor.
2104  *
2105  * Asic specific PLL information
2106  *
2107  * DCE 8.x
2108  * KB/KV
2109  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2110  * CI
2111  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2112  *
2113  */
2114 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2115 {
2116         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2117         struct drm_device *dev = crtc->dev;
2118         struct amdgpu_device *adev = dev->dev_private;
2119         u32 pll_in_use;
2120         int pll;
2121
2122         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2123                 if (adev->clock.dp_extclk)
2124                         /* skip PPLL programming if using ext clock */
2125                         return ATOM_PPLL_INVALID;
2126                 else {
2127                         /* use the same PPLL for all DP monitors */
2128                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2129                         if (pll != ATOM_PPLL_INVALID)
2130                                 return pll;
2131                 }
2132         } else {
2133                 /* use the same PPLL for all monitors with the same clock */
2134                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2135                 if (pll != ATOM_PPLL_INVALID)
2136                         return pll;
2137         }
2138         /* otherwise, pick one of the plls */
2139         if ((adev->asic_type == CHIP_KABINI) ||
2140             (adev->asic_type == CHIP_MULLINS)) {
2141                 /* KB/ML has PPLL1 and PPLL2 */
2142                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2143                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2144                         return ATOM_PPLL2;
2145                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2146                         return ATOM_PPLL1;
2147                 DRM_ERROR("unable to allocate a PPLL\n");
2148                 return ATOM_PPLL_INVALID;
2149         } else {
2150                 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2151                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2152                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2153                         return ATOM_PPLL2;
2154                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2155                         return ATOM_PPLL1;
2156                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2157                         return ATOM_PPLL0;
2158                 DRM_ERROR("unable to allocate a PPLL\n");
2159                 return ATOM_PPLL_INVALID;
2160         }
2161         return ATOM_PPLL_INVALID;
2162 }
2163
2164 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2165 {
2166         struct amdgpu_device *adev = crtc->dev->dev_private;
2167         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2168         uint32_t cur_lock;
2169
2170         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2171         if (lock)
2172                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2173         else
2174                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2175         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2176 }
2177
2178 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2179 {
2180         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2181         struct amdgpu_device *adev = crtc->dev->dev_private;
2182
2183         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2184                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2185                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2186 }
2187
2188 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2189 {
2190         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2191         struct amdgpu_device *adev = crtc->dev->dev_private;
2192
2193         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2194                upper_32_bits(amdgpu_crtc->cursor_addr));
2195         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2196                lower_32_bits(amdgpu_crtc->cursor_addr));
2197
2198         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2199                    CUR_CONTROL__CURSOR_EN_MASK |
2200                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2201                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2202 }
2203
2204 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2205                                        int x, int y)
2206 {
2207         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2208         struct amdgpu_device *adev = crtc->dev->dev_private;
2209         int xorigin = 0, yorigin = 0;
2210
2211         amdgpu_crtc->cursor_x = x;
2212         amdgpu_crtc->cursor_y = y;
2213
2214         /* avivo cursor are offset into the total surface */
2215         x += crtc->x;
2216         y += crtc->y;
2217         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2218
2219         if (x < 0) {
2220                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2221                 x = 0;
2222         }
2223         if (y < 0) {
2224                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2225                 y = 0;
2226         }
2227
2228         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2229         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2230         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2231                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2232
2233         return 0;
2234 }
2235
2236 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2237                                      int x, int y)
2238 {
2239         int ret;
2240
2241         dce_v8_0_lock_cursor(crtc, true);
2242         ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2243         dce_v8_0_lock_cursor(crtc, false);
2244
2245         return ret;
2246 }
2247
2248 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2249                                      struct drm_file *file_priv,
2250                                      uint32_t handle,
2251                                      uint32_t width,
2252                                      uint32_t height,
2253                                      int32_t hot_x,
2254                                      int32_t hot_y)
2255 {
2256         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2257         struct drm_gem_object *obj;
2258         struct amdgpu_bo *aobj;
2259         int ret;
2260
2261         if (!handle) {
2262                 /* turn off cursor */
2263                 dce_v8_0_hide_cursor(crtc);
2264                 obj = NULL;
2265                 goto unpin;
2266         }
2267
2268         if ((width > amdgpu_crtc->max_cursor_width) ||
2269             (height > amdgpu_crtc->max_cursor_height)) {
2270                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2271                 return -EINVAL;
2272         }
2273
2274         obj = drm_gem_object_lookup(file_priv, handle);
2275         if (!obj) {
2276                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2277                 return -ENOENT;
2278         }
2279
2280         aobj = gem_to_amdgpu_bo(obj);
2281         ret = amdgpu_bo_reserve(aobj, false);
2282         if (ret != 0) {
2283                 drm_gem_object_put_unlocked(obj);
2284                 return ret;
2285         }
2286
2287         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2288         amdgpu_bo_unreserve(aobj);
2289         if (ret) {
2290                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2291                 drm_gem_object_put_unlocked(obj);
2292                 return ret;
2293         }
2294         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2295
2296         dce_v8_0_lock_cursor(crtc, true);
2297
2298         if (width != amdgpu_crtc->cursor_width ||
2299             height != amdgpu_crtc->cursor_height ||
2300             hot_x != amdgpu_crtc->cursor_hot_x ||
2301             hot_y != amdgpu_crtc->cursor_hot_y) {
2302                 int x, y;
2303
2304                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2305                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2306
2307                 dce_v8_0_cursor_move_locked(crtc, x, y);
2308
2309                 amdgpu_crtc->cursor_width = width;
2310                 amdgpu_crtc->cursor_height = height;
2311                 amdgpu_crtc->cursor_hot_x = hot_x;
2312                 amdgpu_crtc->cursor_hot_y = hot_y;
2313         }
2314
2315         dce_v8_0_show_cursor(crtc);
2316         dce_v8_0_lock_cursor(crtc, false);
2317
2318 unpin:
2319         if (amdgpu_crtc->cursor_bo) {
2320                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2321                 ret = amdgpu_bo_reserve(aobj, true);
2322                 if (likely(ret == 0)) {
2323                         amdgpu_bo_unpin(aobj);
2324                         amdgpu_bo_unreserve(aobj);
2325                 }
2326                 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2327         }
2328
2329         amdgpu_crtc->cursor_bo = obj;
2330         return 0;
2331 }
2332
2333 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2334 {
2335         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2336
2337         if (amdgpu_crtc->cursor_bo) {
2338                 dce_v8_0_lock_cursor(crtc, true);
2339
2340                 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2341                                             amdgpu_crtc->cursor_y);
2342
2343                 dce_v8_0_show_cursor(crtc);
2344
2345                 dce_v8_0_lock_cursor(crtc, false);
2346         }
2347 }
2348
2349 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2350                                    u16 *blue, uint32_t size,
2351                                    struct drm_modeset_acquire_ctx *ctx)
2352 {
2353         dce_v8_0_crtc_load_lut(crtc);
2354
2355         return 0;
2356 }
2357
2358 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2359 {
2360         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2361
2362         drm_crtc_cleanup(crtc);
2363         kfree(amdgpu_crtc);
2364 }
2365
2366 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2367         .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2368         .cursor_move = dce_v8_0_crtc_cursor_move,
2369         .gamma_set = dce_v8_0_crtc_gamma_set,
2370         .set_config = amdgpu_display_crtc_set_config,
2371         .destroy = dce_v8_0_crtc_destroy,
2372         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2373 };
2374
2375 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2376 {
2377         struct drm_device *dev = crtc->dev;
2378         struct amdgpu_device *adev = dev->dev_private;
2379         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2380         unsigned type;
2381
2382         switch (mode) {
2383         case DRM_MODE_DPMS_ON:
2384                 amdgpu_crtc->enabled = true;
2385                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2386                 dce_v8_0_vga_enable(crtc, true);
2387                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2388                 dce_v8_0_vga_enable(crtc, false);
2389                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2390                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2391                                                 amdgpu_crtc->crtc_id);
2392                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2393                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2394                 drm_crtc_vblank_on(crtc);
2395                 dce_v8_0_crtc_load_lut(crtc);
2396                 break;
2397         case DRM_MODE_DPMS_STANDBY:
2398         case DRM_MODE_DPMS_SUSPEND:
2399         case DRM_MODE_DPMS_OFF:
2400                 drm_crtc_vblank_off(crtc);
2401                 if (amdgpu_crtc->enabled) {
2402                         dce_v8_0_vga_enable(crtc, true);
2403                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2404                         dce_v8_0_vga_enable(crtc, false);
2405                 }
2406                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2407                 amdgpu_crtc->enabled = false;
2408                 break;
2409         }
2410         /* adjust pm to dpms */
2411         amdgpu_pm_compute_clocks(adev);
2412 }
2413
2414 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2415 {
2416         /* disable crtc pair power gating before programming */
2417         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2418         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2419         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2420 }
2421
2422 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2423 {
2424         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2425         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2426 }
2427
2428 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2429 {
2430         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2431         struct drm_device *dev = crtc->dev;
2432         struct amdgpu_device *adev = dev->dev_private;
2433         struct amdgpu_atom_ss ss;
2434         int i;
2435
2436         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2437         if (crtc->primary->fb) {
2438                 int r;
2439                 struct amdgpu_bo *abo;
2440
2441                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2442                 r = amdgpu_bo_reserve(abo, true);
2443                 if (unlikely(r))
2444                         DRM_ERROR("failed to reserve abo before unpin\n");
2445                 else {
2446                         amdgpu_bo_unpin(abo);
2447                         amdgpu_bo_unreserve(abo);
2448                 }
2449         }
2450         /* disable the GRPH */
2451         dce_v8_0_grph_enable(crtc, false);
2452
2453         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2454
2455         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2456                 if (adev->mode_info.crtcs[i] &&
2457                     adev->mode_info.crtcs[i]->enabled &&
2458                     i != amdgpu_crtc->crtc_id &&
2459                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2460                         /* one other crtc is using this pll don't turn
2461                          * off the pll
2462                          */
2463                         goto done;
2464                 }
2465         }
2466
2467         switch (amdgpu_crtc->pll_id) {
2468         case ATOM_PPLL1:
2469         case ATOM_PPLL2:
2470                 /* disable the ppll */
2471                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2472                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2473                 break;
2474         case ATOM_PPLL0:
2475                 /* disable the ppll */
2476                 if ((adev->asic_type == CHIP_KAVERI) ||
2477                     (adev->asic_type == CHIP_BONAIRE) ||
2478                     (adev->asic_type == CHIP_HAWAII))
2479                         amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2480                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2481                 break;
2482         default:
2483                 break;
2484         }
2485 done:
2486         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2487         amdgpu_crtc->adjusted_clock = 0;
2488         amdgpu_crtc->encoder = NULL;
2489         amdgpu_crtc->connector = NULL;
2490 }
2491
2492 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2493                                   struct drm_display_mode *mode,
2494                                   struct drm_display_mode *adjusted_mode,
2495                                   int x, int y, struct drm_framebuffer *old_fb)
2496 {
2497         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2498
2499         if (!amdgpu_crtc->adjusted_clock)
2500                 return -EINVAL;
2501
2502         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2503         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2504         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2505         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2506         amdgpu_atombios_crtc_scaler_setup(crtc);
2507         dce_v8_0_cursor_reset(crtc);
2508         /* update the hw version fpr dpm */
2509         amdgpu_crtc->hw_mode = *adjusted_mode;
2510
2511         return 0;
2512 }
2513
2514 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2515                                      const struct drm_display_mode *mode,
2516                                      struct drm_display_mode *adjusted_mode)
2517 {
2518         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2519         struct drm_device *dev = crtc->dev;
2520         struct drm_encoder *encoder;
2521
2522         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2523         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2524                 if (encoder->crtc == crtc) {
2525                         amdgpu_crtc->encoder = encoder;
2526                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2527                         break;
2528                 }
2529         }
2530         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2531                 amdgpu_crtc->encoder = NULL;
2532                 amdgpu_crtc->connector = NULL;
2533                 return false;
2534         }
2535         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2536                 return false;
2537         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2538                 return false;
2539         /* pick pll */
2540         amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2541         /* if we can't get a PPLL for a non-DP encoder, fail */
2542         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2543             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2544                 return false;
2545
2546         return true;
2547 }
2548
2549 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2550                                   struct drm_framebuffer *old_fb)
2551 {
2552         return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2553 }
2554
2555 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2556                                          struct drm_framebuffer *fb,
2557                                          int x, int y, enum mode_set_atomic state)
2558 {
2559        return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2560 }
2561
2562 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2563         .dpms = dce_v8_0_crtc_dpms,
2564         .mode_fixup = dce_v8_0_crtc_mode_fixup,
2565         .mode_set = dce_v8_0_crtc_mode_set,
2566         .mode_set_base = dce_v8_0_crtc_set_base,
2567         .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2568         .prepare = dce_v8_0_crtc_prepare,
2569         .commit = dce_v8_0_crtc_commit,
2570         .disable = dce_v8_0_crtc_disable,
2571 };
2572
2573 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2574 {
2575         struct amdgpu_crtc *amdgpu_crtc;
2576
2577         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2578                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2579         if (amdgpu_crtc == NULL)
2580                 return -ENOMEM;
2581
2582         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2583
2584         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2585         amdgpu_crtc->crtc_id = index;
2586         adev->mode_info.crtcs[index] = amdgpu_crtc;
2587
2588         amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2589         amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2590         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2591         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2592
2593         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2594
2595         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2596         amdgpu_crtc->adjusted_clock = 0;
2597         amdgpu_crtc->encoder = NULL;
2598         amdgpu_crtc->connector = NULL;
2599         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2600
2601         return 0;
2602 }
2603
2604 static int dce_v8_0_early_init(void *handle)
2605 {
2606         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2607
2608         adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2609         adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2610
2611         dce_v8_0_set_display_funcs(adev);
2612
2613         adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2614
2615         switch (adev->asic_type) {
2616         case CHIP_BONAIRE:
2617         case CHIP_HAWAII:
2618                 adev->mode_info.num_hpd = 6;
2619                 adev->mode_info.num_dig = 6;
2620                 break;
2621         case CHIP_KAVERI:
2622                 adev->mode_info.num_hpd = 6;
2623                 adev->mode_info.num_dig = 7;
2624                 break;
2625         case CHIP_KABINI:
2626         case CHIP_MULLINS:
2627                 adev->mode_info.num_hpd = 6;
2628                 adev->mode_info.num_dig = 6; /* ? */
2629                 break;
2630         default:
2631                 /* FIXME: not supported yet */
2632                 return -EINVAL;
2633         }
2634
2635         dce_v8_0_set_irq_funcs(adev);
2636
2637         return 0;
2638 }
2639
2640 static int dce_v8_0_sw_init(void *handle)
2641 {
2642         int r, i;
2643         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2644
2645         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2646                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2647                 if (r)
2648                         return r;
2649         }
2650
2651         for (i = 8; i < 20; i += 2) {
2652                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2653                 if (r)
2654                         return r;
2655         }
2656
2657         /* HPD hotplug */
2658         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2659         if (r)
2660                 return r;
2661
2662         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2663
2664         adev->ddev->mode_config.async_page_flip = true;
2665
2666         adev->ddev->mode_config.max_width = 16384;
2667         adev->ddev->mode_config.max_height = 16384;
2668
2669         adev->ddev->mode_config.preferred_depth = 24;
2670         adev->ddev->mode_config.prefer_shadow = 1;
2671
2672         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2673
2674         r = amdgpu_display_modeset_create_props(adev);
2675         if (r)
2676                 return r;
2677
2678         adev->ddev->mode_config.max_width = 16384;
2679         adev->ddev->mode_config.max_height = 16384;
2680
2681         /* allocate crtcs */
2682         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2683                 r = dce_v8_0_crtc_init(adev, i);
2684                 if (r)
2685                         return r;
2686         }
2687
2688         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2689                 amdgpu_display_print_display_setup(adev->ddev);
2690         else
2691                 return -EINVAL;
2692
2693         /* setup afmt */
2694         r = dce_v8_0_afmt_init(adev);
2695         if (r)
2696                 return r;
2697
2698         r = dce_v8_0_audio_init(adev);
2699         if (r)
2700                 return r;
2701
2702         drm_kms_helper_poll_init(adev->ddev);
2703
2704         adev->mode_info.mode_config_initialized = true;
2705         return 0;
2706 }
2707
2708 static int dce_v8_0_sw_fini(void *handle)
2709 {
2710         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2711
2712         kfree(adev->mode_info.bios_hardcoded_edid);
2713
2714         drm_kms_helper_poll_fini(adev->ddev);
2715
2716         dce_v8_0_audio_fini(adev);
2717
2718         dce_v8_0_afmt_fini(adev);
2719
2720         drm_mode_config_cleanup(adev->ddev);
2721         adev->mode_info.mode_config_initialized = false;
2722
2723         return 0;
2724 }
2725
2726 static int dce_v8_0_hw_init(void *handle)
2727 {
2728         int i;
2729         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2730
2731         /* disable vga render */
2732         dce_v8_0_set_vga_render_state(adev, false);
2733         /* init dig PHYs, disp eng pll */
2734         amdgpu_atombios_encoder_init_dig(adev);
2735         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2736
2737         /* initialize hpd */
2738         dce_v8_0_hpd_init(adev);
2739
2740         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2741                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2742         }
2743
2744         dce_v8_0_pageflip_interrupt_init(adev);
2745
2746         return 0;
2747 }
2748
2749 static int dce_v8_0_hw_fini(void *handle)
2750 {
2751         int i;
2752         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2753
2754         dce_v8_0_hpd_fini(adev);
2755
2756         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2757                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2758         }
2759
2760         dce_v8_0_pageflip_interrupt_fini(adev);
2761
2762         return 0;
2763 }
2764
2765 static int dce_v8_0_suspend(void *handle)
2766 {
2767         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2768
2769         adev->mode_info.bl_level =
2770                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2771
2772         return dce_v8_0_hw_fini(handle);
2773 }
2774
2775 static int dce_v8_0_resume(void *handle)
2776 {
2777         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2778         int ret;
2779
2780         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2781                                                            adev->mode_info.bl_level);
2782
2783         ret = dce_v8_0_hw_init(handle);
2784
2785         /* turn on the BL */
2786         if (adev->mode_info.bl_encoder) {
2787                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2788                                                                   adev->mode_info.bl_encoder);
2789                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2790                                                     bl_level);
2791         }
2792
2793         return ret;
2794 }
2795
2796 static bool dce_v8_0_is_idle(void *handle)
2797 {
2798         return true;
2799 }
2800
2801 static int dce_v8_0_wait_for_idle(void *handle)
2802 {
2803         return 0;
2804 }
2805
2806 static int dce_v8_0_soft_reset(void *handle)
2807 {
2808         u32 srbm_soft_reset = 0, tmp;
2809         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2810
2811         if (dce_v8_0_is_display_hung(adev))
2812                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2813
2814         if (srbm_soft_reset) {
2815                 tmp = RREG32(mmSRBM_SOFT_RESET);
2816                 tmp |= srbm_soft_reset;
2817                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2818                 WREG32(mmSRBM_SOFT_RESET, tmp);
2819                 tmp = RREG32(mmSRBM_SOFT_RESET);
2820
2821                 udelay(50);
2822
2823                 tmp &= ~srbm_soft_reset;
2824                 WREG32(mmSRBM_SOFT_RESET, tmp);
2825                 tmp = RREG32(mmSRBM_SOFT_RESET);
2826
2827                 /* Wait a little for things to settle down */
2828                 udelay(50);
2829         }
2830         return 0;
2831 }
2832
2833 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2834                                                      int crtc,
2835                                                      enum amdgpu_interrupt_state state)
2836 {
2837         u32 reg_block, lb_interrupt_mask;
2838
2839         if (crtc >= adev->mode_info.num_crtc) {
2840                 DRM_DEBUG("invalid crtc %d\n", crtc);
2841                 return;
2842         }
2843
2844         switch (crtc) {
2845         case 0:
2846                 reg_block = CRTC0_REGISTER_OFFSET;
2847                 break;
2848         case 1:
2849                 reg_block = CRTC1_REGISTER_OFFSET;
2850                 break;
2851         case 2:
2852                 reg_block = CRTC2_REGISTER_OFFSET;
2853                 break;
2854         case 3:
2855                 reg_block = CRTC3_REGISTER_OFFSET;
2856                 break;
2857         case 4:
2858                 reg_block = CRTC4_REGISTER_OFFSET;
2859                 break;
2860         case 5:
2861                 reg_block = CRTC5_REGISTER_OFFSET;
2862                 break;
2863         default:
2864                 DRM_DEBUG("invalid crtc %d\n", crtc);
2865                 return;
2866         }
2867
2868         switch (state) {
2869         case AMDGPU_IRQ_STATE_DISABLE:
2870                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2871                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2872                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2873                 break;
2874         case AMDGPU_IRQ_STATE_ENABLE:
2875                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2876                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2877                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2878                 break;
2879         default:
2880                 break;
2881         }
2882 }
2883
2884 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2885                                                     int crtc,
2886                                                     enum amdgpu_interrupt_state state)
2887 {
2888         u32 reg_block, lb_interrupt_mask;
2889
2890         if (crtc >= adev->mode_info.num_crtc) {
2891                 DRM_DEBUG("invalid crtc %d\n", crtc);
2892                 return;
2893         }
2894
2895         switch (crtc) {
2896         case 0:
2897                 reg_block = CRTC0_REGISTER_OFFSET;
2898                 break;
2899         case 1:
2900                 reg_block = CRTC1_REGISTER_OFFSET;
2901                 break;
2902         case 2:
2903                 reg_block = CRTC2_REGISTER_OFFSET;
2904                 break;
2905         case 3:
2906                 reg_block = CRTC3_REGISTER_OFFSET;
2907                 break;
2908         case 4:
2909                 reg_block = CRTC4_REGISTER_OFFSET;
2910                 break;
2911         case 5:
2912                 reg_block = CRTC5_REGISTER_OFFSET;
2913                 break;
2914         default:
2915                 DRM_DEBUG("invalid crtc %d\n", crtc);
2916                 return;
2917         }
2918
2919         switch (state) {
2920         case AMDGPU_IRQ_STATE_DISABLE:
2921                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2922                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2923                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2924                 break;
2925         case AMDGPU_IRQ_STATE_ENABLE:
2926                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2927                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2928                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2929                 break;
2930         default:
2931                 break;
2932         }
2933 }
2934
2935 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2936                                             struct amdgpu_irq_src *src,
2937                                             unsigned type,
2938                                             enum amdgpu_interrupt_state state)
2939 {
2940         u32 dc_hpd_int_cntl;
2941
2942         if (type >= adev->mode_info.num_hpd) {
2943                 DRM_DEBUG("invalid hdp %d\n", type);
2944                 return 0;
2945         }
2946
2947         switch (state) {
2948         case AMDGPU_IRQ_STATE_DISABLE:
2949                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2950                 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2951                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2952                 break;
2953         case AMDGPU_IRQ_STATE_ENABLE:
2954                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2955                 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2956                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2957                 break;
2958         default:
2959                 break;
2960         }
2961
2962         return 0;
2963 }
2964
2965 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2966                                              struct amdgpu_irq_src *src,
2967                                              unsigned type,
2968                                              enum amdgpu_interrupt_state state)
2969 {
2970         switch (type) {
2971         case AMDGPU_CRTC_IRQ_VBLANK1:
2972                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2973                 break;
2974         case AMDGPU_CRTC_IRQ_VBLANK2:
2975                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2976                 break;
2977         case AMDGPU_CRTC_IRQ_VBLANK3:
2978                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2979                 break;
2980         case AMDGPU_CRTC_IRQ_VBLANK4:
2981                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2982                 break;
2983         case AMDGPU_CRTC_IRQ_VBLANK5:
2984                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2985                 break;
2986         case AMDGPU_CRTC_IRQ_VBLANK6:
2987                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2988                 break;
2989         case AMDGPU_CRTC_IRQ_VLINE1:
2990                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
2991                 break;
2992         case AMDGPU_CRTC_IRQ_VLINE2:
2993                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
2994                 break;
2995         case AMDGPU_CRTC_IRQ_VLINE3:
2996                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
2997                 break;
2998         case AMDGPU_CRTC_IRQ_VLINE4:
2999                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3000                 break;
3001         case AMDGPU_CRTC_IRQ_VLINE5:
3002                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3003                 break;
3004         case AMDGPU_CRTC_IRQ_VLINE6:
3005                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3006                 break;
3007         default:
3008                 break;
3009         }
3010         return 0;
3011 }
3012
3013 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3014                              struct amdgpu_irq_src *source,
3015                              struct amdgpu_iv_entry *entry)
3016 {
3017         unsigned crtc = entry->src_id - 1;
3018         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3019         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3020                                                                     crtc);
3021
3022         switch (entry->src_data[0]) {
3023         case 0: /* vblank */
3024                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3025                         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3026                 else
3027                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3028
3029                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3030                         drm_handle_vblank(adev->ddev, crtc);
3031                 }
3032                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3033                 break;
3034         case 1: /* vline */
3035                 if (disp_int & interrupt_status_offsets[crtc].vline)
3036                         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3037                 else
3038                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3039
3040                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3041                 break;
3042         default:
3043                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3044                 break;
3045         }
3046
3047         return 0;
3048 }
3049
3050 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3051                                                  struct amdgpu_irq_src *src,
3052                                                  unsigned type,
3053                                                  enum amdgpu_interrupt_state state)
3054 {
3055         u32 reg;
3056
3057         if (type >= adev->mode_info.num_crtc) {
3058                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3059                 return -EINVAL;
3060         }
3061
3062         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3063         if (state == AMDGPU_IRQ_STATE_DISABLE)
3064                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3065                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3066         else
3067                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3068                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3069
3070         return 0;
3071 }
3072
3073 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3074                                 struct amdgpu_irq_src *source,
3075                                 struct amdgpu_iv_entry *entry)
3076 {
3077         unsigned long flags;
3078         unsigned crtc_id;
3079         struct amdgpu_crtc *amdgpu_crtc;
3080         struct amdgpu_flip_work *works;
3081
3082         crtc_id = (entry->src_id - 8) >> 1;
3083         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3084
3085         if (crtc_id >= adev->mode_info.num_crtc) {
3086                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3087                 return -EINVAL;
3088         }
3089
3090         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3091             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3092                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3093                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3094
3095         /* IRQ could occur when in initial stage */
3096         if (amdgpu_crtc == NULL)
3097                 return 0;
3098
3099         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3100         works = amdgpu_crtc->pflip_works;
3101         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3102                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3103                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3104                                                 amdgpu_crtc->pflip_status,
3105                                                 AMDGPU_FLIP_SUBMITTED);
3106                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3107                 return 0;
3108         }
3109
3110         /* page flip completed. clean up */
3111         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3112         amdgpu_crtc->pflip_works = NULL;
3113
3114         /* wakeup usersapce */
3115         if (works->event)
3116                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3117
3118         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3119
3120         drm_crtc_vblank_put(&amdgpu_crtc->base);
3121         schedule_work(&works->unpin_work);
3122
3123         return 0;
3124 }
3125
3126 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3127                             struct amdgpu_irq_src *source,
3128                             struct amdgpu_iv_entry *entry)
3129 {
3130         uint32_t disp_int, mask, tmp;
3131         unsigned hpd;
3132
3133         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3134                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3135                 return 0;
3136         }
3137
3138         hpd = entry->src_data[0];
3139         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3140         mask = interrupt_status_offsets[hpd].hpd;
3141
3142         if (disp_int & mask) {
3143                 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3144                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3145                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3146                 schedule_work(&adev->hotplug_work);
3147                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3148         }
3149
3150         return 0;
3151
3152 }
3153
3154 static int dce_v8_0_set_clockgating_state(void *handle,
3155                                           enum amd_clockgating_state state)
3156 {
3157         return 0;
3158 }
3159
3160 static int dce_v8_0_set_powergating_state(void *handle,
3161                                           enum amd_powergating_state state)
3162 {
3163         return 0;
3164 }
3165
3166 static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3167         .name = "dce_v8_0",
3168         .early_init = dce_v8_0_early_init,
3169         .late_init = NULL,
3170         .sw_init = dce_v8_0_sw_init,
3171         .sw_fini = dce_v8_0_sw_fini,
3172         .hw_init = dce_v8_0_hw_init,
3173         .hw_fini = dce_v8_0_hw_fini,
3174         .suspend = dce_v8_0_suspend,
3175         .resume = dce_v8_0_resume,
3176         .is_idle = dce_v8_0_is_idle,
3177         .wait_for_idle = dce_v8_0_wait_for_idle,
3178         .soft_reset = dce_v8_0_soft_reset,
3179         .set_clockgating_state = dce_v8_0_set_clockgating_state,
3180         .set_powergating_state = dce_v8_0_set_powergating_state,
3181 };
3182
3183 static void
3184 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3185                           struct drm_display_mode *mode,
3186                           struct drm_display_mode *adjusted_mode)
3187 {
3188         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3189
3190         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3191
3192         /* need to call this here rather than in prepare() since we need some crtc info */
3193         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3194
3195         /* set scaler clears this on some chips */
3196         dce_v8_0_set_interleave(encoder->crtc, mode);
3197
3198         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3199                 dce_v8_0_afmt_enable(encoder, true);
3200                 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3201         }
3202 }
3203
3204 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3205 {
3206         struct amdgpu_device *adev = encoder->dev->dev_private;
3207         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3208         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3209
3210         if ((amdgpu_encoder->active_device &
3211              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3212             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3213              ENCODER_OBJECT_ID_NONE)) {
3214                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3215                 if (dig) {
3216                         dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3217                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3218                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3219                 }
3220         }
3221
3222         amdgpu_atombios_scratch_regs_lock(adev, true);
3223
3224         if (connector) {
3225                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3226
3227                 /* select the clock/data port if it uses a router */
3228                 if (amdgpu_connector->router.cd_valid)
3229                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3230
3231                 /* turn eDP panel on for mode set */
3232                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3233                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3234                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3235         }
3236
3237         /* this is needed for the pll/ss setup to work correctly in some cases */
3238         amdgpu_atombios_encoder_set_crtc_source(encoder);
3239         /* set up the FMT blocks */
3240         dce_v8_0_program_fmt(encoder);
3241 }
3242
3243 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3244 {
3245         struct drm_device *dev = encoder->dev;
3246         struct amdgpu_device *adev = dev->dev_private;
3247
3248         /* need to call this here as we need the crtc set up */
3249         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3250         amdgpu_atombios_scratch_regs_lock(adev, false);
3251 }
3252
3253 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3254 {
3255         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3256         struct amdgpu_encoder_atom_dig *dig;
3257
3258         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3259
3260         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3261                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3262                         dce_v8_0_afmt_enable(encoder, false);
3263                 dig = amdgpu_encoder->enc_priv;
3264                 dig->dig_encoder = -1;
3265         }
3266         amdgpu_encoder->active_device = 0;
3267 }
3268
3269 /* these are handled by the primary encoders */
3270 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3271 {
3272
3273 }
3274
3275 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3276 {
3277
3278 }
3279
3280 static void
3281 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3282                       struct drm_display_mode *mode,
3283                       struct drm_display_mode *adjusted_mode)
3284 {
3285
3286 }
3287
3288 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3289 {
3290
3291 }
3292
3293 static void
3294 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3295 {
3296
3297 }
3298
3299 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3300         .dpms = dce_v8_0_ext_dpms,
3301         .prepare = dce_v8_0_ext_prepare,
3302         .mode_set = dce_v8_0_ext_mode_set,
3303         .commit = dce_v8_0_ext_commit,
3304         .disable = dce_v8_0_ext_disable,
3305         /* no detect for TMDS/LVDS yet */
3306 };
3307
3308 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3309         .dpms = amdgpu_atombios_encoder_dpms,
3310         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3311         .prepare = dce_v8_0_encoder_prepare,
3312         .mode_set = dce_v8_0_encoder_mode_set,
3313         .commit = dce_v8_0_encoder_commit,
3314         .disable = dce_v8_0_encoder_disable,
3315         .detect = amdgpu_atombios_encoder_dig_detect,
3316 };
3317
3318 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3319         .dpms = amdgpu_atombios_encoder_dpms,
3320         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3321         .prepare = dce_v8_0_encoder_prepare,
3322         .mode_set = dce_v8_0_encoder_mode_set,
3323         .commit = dce_v8_0_encoder_commit,
3324         .detect = amdgpu_atombios_encoder_dac_detect,
3325 };
3326
3327 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3328 {
3329         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3330         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3331                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3332         kfree(amdgpu_encoder->enc_priv);
3333         drm_encoder_cleanup(encoder);
3334         kfree(amdgpu_encoder);
3335 }
3336
3337 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3338         .destroy = dce_v8_0_encoder_destroy,
3339 };
3340
3341 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3342                                  uint32_t encoder_enum,
3343                                  uint32_t supported_device,
3344                                  u16 caps)
3345 {
3346         struct drm_device *dev = adev->ddev;
3347         struct drm_encoder *encoder;
3348         struct amdgpu_encoder *amdgpu_encoder;
3349
3350         /* see if we already added it */
3351         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3352                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3353                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3354                         amdgpu_encoder->devices |= supported_device;
3355                         return;
3356                 }
3357
3358         }
3359
3360         /* add a new one */
3361         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3362         if (!amdgpu_encoder)
3363                 return;
3364
3365         encoder = &amdgpu_encoder->base;
3366         switch (adev->mode_info.num_crtc) {
3367         case 1:
3368                 encoder->possible_crtcs = 0x1;
3369                 break;
3370         case 2:
3371         default:
3372                 encoder->possible_crtcs = 0x3;
3373                 break;
3374         case 4:
3375                 encoder->possible_crtcs = 0xf;
3376                 break;
3377         case 6:
3378                 encoder->possible_crtcs = 0x3f;
3379                 break;
3380         }
3381
3382         amdgpu_encoder->enc_priv = NULL;
3383
3384         amdgpu_encoder->encoder_enum = encoder_enum;
3385         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3386         amdgpu_encoder->devices = supported_device;
3387         amdgpu_encoder->rmx_type = RMX_OFF;
3388         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3389         amdgpu_encoder->is_ext_encoder = false;
3390         amdgpu_encoder->caps = caps;
3391
3392         switch (amdgpu_encoder->encoder_id) {
3393         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3394         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3395                 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3396                                  DRM_MODE_ENCODER_DAC, NULL);
3397                 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3398                 break;
3399         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3400         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3401         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3402         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3403         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3404                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3405                         amdgpu_encoder->rmx_type = RMX_FULL;
3406                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3407                                          DRM_MODE_ENCODER_LVDS, NULL);
3408                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3409                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3410                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3411                                          DRM_MODE_ENCODER_DAC, NULL);
3412                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3413                 } else {
3414                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3415                                          DRM_MODE_ENCODER_TMDS, NULL);
3416                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3417                 }
3418                 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3419                 break;
3420         case ENCODER_OBJECT_ID_SI170B:
3421         case ENCODER_OBJECT_ID_CH7303:
3422         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3423         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3424         case ENCODER_OBJECT_ID_TITFP513:
3425         case ENCODER_OBJECT_ID_VT1623:
3426         case ENCODER_OBJECT_ID_HDMI_SI1930:
3427         case ENCODER_OBJECT_ID_TRAVIS:
3428         case ENCODER_OBJECT_ID_NUTMEG:
3429                 /* these are handled by the primary encoders */
3430                 amdgpu_encoder->is_ext_encoder = true;
3431                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3432                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3433                                          DRM_MODE_ENCODER_LVDS, NULL);
3434                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3435                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3436                                          DRM_MODE_ENCODER_DAC, NULL);
3437                 else
3438                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3439                                          DRM_MODE_ENCODER_TMDS, NULL);
3440                 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3441                 break;
3442         }
3443 }
3444
3445 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3446         .bandwidth_update = &dce_v8_0_bandwidth_update,
3447         .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3448         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3449         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3450         .hpd_sense = &dce_v8_0_hpd_sense,
3451         .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3452         .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3453         .page_flip = &dce_v8_0_page_flip,
3454         .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3455         .add_encoder = &dce_v8_0_encoder_add,
3456         .add_connector = &amdgpu_connector_add,
3457 };
3458
3459 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3460 {
3461         adev->mode_info.funcs = &dce_v8_0_display_funcs;
3462 }
3463
3464 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3465         .set = dce_v8_0_set_crtc_interrupt_state,
3466         .process = dce_v8_0_crtc_irq,
3467 };
3468
3469 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3470         .set = dce_v8_0_set_pageflip_interrupt_state,
3471         .process = dce_v8_0_pageflip_irq,
3472 };
3473
3474 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3475         .set = dce_v8_0_set_hpd_interrupt_state,
3476         .process = dce_v8_0_hpd_irq,
3477 };
3478
3479 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3480 {
3481         if (adev->mode_info.num_crtc > 0)
3482                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3483         else
3484                 adev->crtc_irq.num_types = 0;
3485         adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3486
3487         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3488         adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3489
3490         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3491         adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3492 }
3493
3494 const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3495 {
3496         .type = AMD_IP_BLOCK_TYPE_DCE,
3497         .major = 8,
3498         .minor = 0,
3499         .rev = 0,
3500         .funcs = &dce_v8_0_ip_funcs,
3501 };
3502
3503 const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3504 {
3505         .type = AMD_IP_BLOCK_TYPE_DCE,
3506         .major = 8,
3507         .minor = 1,
3508         .rev = 0,
3509         .funcs = &dce_v8_0_ip_funcs,
3510 };
3511
3512 const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3513 {
3514         .type = AMD_IP_BLOCK_TYPE_DCE,
3515         .major = 8,
3516         .minor = 2,
3517         .rev = 0,
3518         .funcs = &dce_v8_0_ip_funcs,
3519 };
3520
3521 const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3522 {
3523         .type = AMD_IP_BLOCK_TYPE_DCE,
3524         .major = 8,
3525         .minor = 3,
3526         .rev = 0,
3527         .funcs = &dce_v8_0_ip_funcs,
3528 };
3529
3530 const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3531 {
3532         .type = AMD_IP_BLOCK_TYPE_DCE,
3533         .major = 8,
3534         .minor = 5,
3535         .rev = 0,
3536         .funcs = &dce_v8_0_ip_funcs,
3537 };