2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
36 #include "amdgpu_trace.h"
37 #include "amdgpu_amdkfd.h"
38 #include "amdgpu_gmc.h"
39 #include "amdgpu_xgmi.h"
40 #include "amdgpu_dma_buf.h"
46 * GPUVM is similar to the legacy gart on older asics, however
47 * rather than there being a single global gart table
48 * for the entire GPU, there are multiple VM page tables active
49 * at any given time. The VM page tables can contain a mix
50 * vram pages and system memory pages and system memory pages
51 * can be mapped as snooped (cached system pages) or unsnooped
52 * (uncached system pages).
53 * Each VM has an ID associated with it and there is a page table
54 * associated with each VMID. When execting a command buffer,
55 * the kernel tells the the ring what VMID to use for that command
56 * buffer. VMIDs are allocated dynamically as commands are submitted.
57 * The userspace drivers maintain their own address space and the kernel
58 * sets up their pages tables accordingly when they submit their
59 * command buffers and a VMID is assigned.
60 * Cayman/Trinity support up to 8 active VMs at any given time;
64 #define START(node) ((node)->start)
65 #define LAST(node) ((node)->last)
67 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
68 START, LAST, static, amdgpu_vm_it)
74 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
76 struct amdgpu_prt_cb {
79 * @adev: amdgpu device
81 struct amdgpu_device *adev;
86 struct dma_fence_cb cb;
90 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
91 * happens while holding this lock anywhere to prevent deadlocks when
92 * an MMU notifier runs in reclaim-FS context.
94 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
96 mutex_lock(&vm->eviction_lock);
97 vm->saved_flags = memalloc_noreclaim_save();
100 static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
102 if (mutex_trylock(&vm->eviction_lock)) {
103 vm->saved_flags = memalloc_noreclaim_save();
109 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
111 memalloc_noreclaim_restore(vm->saved_flags);
112 mutex_unlock(&vm->eviction_lock);
116 * amdgpu_vm_level_shift - return the addr shift for each level
118 * @adev: amdgpu_device pointer
122 * The number of bits the pfn needs to be right shifted for a level.
124 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
131 return 9 * (AMDGPU_VM_PDB0 - level) +
132 adev->vm_manager.block_size;
141 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
143 * @adev: amdgpu_device pointer
147 * The number of entries in a page directory or page table.
149 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
152 unsigned shift = amdgpu_vm_level_shift(adev,
153 adev->vm_manager.root_level);
155 if (level == adev->vm_manager.root_level)
156 /* For the root directory */
157 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
159 else if (level != AMDGPU_VM_PTB)
160 /* Everything in between */
163 /* For the page tables on the leaves */
164 return AMDGPU_VM_PTE_COUNT(adev);
168 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
170 * @adev: amdgpu_device pointer
173 * The number of entries in the root page directory which needs the ATS setting.
175 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
179 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
180 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
184 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
186 * @adev: amdgpu_device pointer
190 * The mask to extract the entry number of a PD/PT from an address.
192 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
195 if (level <= adev->vm_manager.root_level)
197 else if (level != AMDGPU_VM_PTB)
200 return AMDGPU_VM_PTE_COUNT(adev) - 1;
204 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
206 * @adev: amdgpu_device pointer
210 * The size of the BO for a page directory or page table in bytes.
212 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
214 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
218 * amdgpu_vm_bo_evicted - vm_bo is evicted
220 * @vm_bo: vm_bo which is evicted
222 * State for PDs/PTs and per VM BOs which are not at the location they should
225 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
227 struct amdgpu_vm *vm = vm_bo->vm;
228 struct amdgpu_bo *bo = vm_bo->bo;
231 if (bo->tbo.type == ttm_bo_type_kernel)
232 list_move(&vm_bo->vm_status, &vm->evicted);
234 list_move_tail(&vm_bo->vm_status, &vm->evicted);
237 * amdgpu_vm_bo_moved - vm_bo is moved
239 * @vm_bo: vm_bo which is moved
241 * State for per VM BOs which are moved, but that change is not yet reflected
242 * in the page tables.
244 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
246 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
250 * amdgpu_vm_bo_idle - vm_bo is idle
252 * @vm_bo: vm_bo which is now idle
254 * State for PDs/PTs and per VM BOs which have gone through the state machine
257 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
259 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
260 vm_bo->moved = false;
264 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
266 * @vm_bo: vm_bo which is now invalidated
268 * State for normal BOs which are invalidated and that change not yet reflected
271 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
273 spin_lock(&vm_bo->vm->invalidated_lock);
274 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
275 spin_unlock(&vm_bo->vm->invalidated_lock);
279 * amdgpu_vm_bo_relocated - vm_bo is reloacted
281 * @vm_bo: vm_bo which is relocated
283 * State for PDs/PTs which needs to update their parent PD.
284 * For the root PD, just move to idle state.
286 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
288 if (vm_bo->bo->parent)
289 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
291 amdgpu_vm_bo_idle(vm_bo);
295 * amdgpu_vm_bo_done - vm_bo is done
297 * @vm_bo: vm_bo which is now done
299 * State for normal BOs which are invalidated and that change has been updated
302 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
304 spin_lock(&vm_bo->vm->invalidated_lock);
305 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
306 spin_unlock(&vm_bo->vm->invalidated_lock);
310 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
312 * @base: base structure for tracking BO usage in a VM
313 * @vm: vm to which bo is to be added
314 * @bo: amdgpu buffer object
316 * Initialize a bo_va_base structure and add it to the appropriate lists
319 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
320 struct amdgpu_vm *vm,
321 struct amdgpu_bo *bo)
326 INIT_LIST_HEAD(&base->vm_status);
330 base->next = bo->vm_bo;
333 if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
336 vm->bulk_moveable = false;
337 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
338 amdgpu_vm_bo_relocated(base);
340 amdgpu_vm_bo_idle(base);
342 if (bo->preferred_domains &
343 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
347 * we checked all the prerequisites, but it looks like this per vm bo
348 * is currently evicted. add the bo to the evicted list to make sure it
349 * is validated on next vm use to avoid fault.
351 amdgpu_vm_bo_evicted(base);
355 * amdgpu_vm_pt_parent - get the parent page directory
357 * @pt: child page table
359 * Helper to get the parent entry for the child page table. NULL if we are at
360 * the root page directory.
362 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
364 struct amdgpu_bo *parent = pt->base.bo->parent;
369 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
373 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
375 struct amdgpu_vm_pt_cursor {
377 struct amdgpu_vm_pt *parent;
378 struct amdgpu_vm_pt *entry;
383 * amdgpu_vm_pt_start - start PD/PT walk
385 * @adev: amdgpu_device pointer
386 * @vm: amdgpu_vm structure
387 * @start: start address of the walk
388 * @cursor: state to initialize
390 * Initialize a amdgpu_vm_pt_cursor to start a walk.
392 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
393 struct amdgpu_vm *vm, uint64_t start,
394 struct amdgpu_vm_pt_cursor *cursor)
397 cursor->parent = NULL;
398 cursor->entry = &vm->root;
399 cursor->level = adev->vm_manager.root_level;
403 * amdgpu_vm_pt_descendant - go to child node
405 * @adev: amdgpu_device pointer
406 * @cursor: current state
408 * Walk to the child node of the current node.
410 * True if the walk was possible, false otherwise.
412 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
413 struct amdgpu_vm_pt_cursor *cursor)
415 unsigned mask, shift, idx;
417 if (!cursor->entry->entries)
420 BUG_ON(!cursor->entry->base.bo);
421 mask = amdgpu_vm_entries_mask(adev, cursor->level);
422 shift = amdgpu_vm_level_shift(adev, cursor->level);
425 idx = (cursor->pfn >> shift) & mask;
426 cursor->parent = cursor->entry;
427 cursor->entry = &cursor->entry->entries[idx];
432 * amdgpu_vm_pt_sibling - go to sibling node
434 * @adev: amdgpu_device pointer
435 * @cursor: current state
437 * Walk to the sibling node of the current node.
439 * True if the walk was possible, false otherwise.
441 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
442 struct amdgpu_vm_pt_cursor *cursor)
444 unsigned shift, num_entries;
446 /* Root doesn't have a sibling */
450 /* Go to our parents and see if we got a sibling */
451 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
452 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
454 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
457 cursor->pfn += 1ULL << shift;
458 cursor->pfn &= ~((1ULL << shift) - 1);
464 * amdgpu_vm_pt_ancestor - go to parent node
466 * @cursor: current state
468 * Walk to the parent node of the current node.
470 * True if the walk was possible, false otherwise.
472 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
478 cursor->entry = cursor->parent;
479 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
484 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
486 * @adev: amdgpu_device pointer
487 * @cursor: current state
489 * Walk the PD/PT tree to the next node.
491 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
492 struct amdgpu_vm_pt_cursor *cursor)
494 /* First try a newborn child */
495 if (amdgpu_vm_pt_descendant(adev, cursor))
498 /* If that didn't worked try to find a sibling */
499 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
500 /* No sibling, go to our parents and grandparents */
501 if (!amdgpu_vm_pt_ancestor(cursor)) {
509 * amdgpu_vm_pt_first_dfs - start a deep first search
511 * @adev: amdgpu_device structure
512 * @vm: amdgpu_vm structure
513 * @start: optional cursor to start with
514 * @cursor: state to initialize
516 * Starts a deep first traversal of the PD/PT tree.
518 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
519 struct amdgpu_vm *vm,
520 struct amdgpu_vm_pt_cursor *start,
521 struct amdgpu_vm_pt_cursor *cursor)
526 amdgpu_vm_pt_start(adev, vm, 0, cursor);
527 while (amdgpu_vm_pt_descendant(adev, cursor));
531 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
533 * @start: starting point for the search
534 * @entry: current entry
537 * True when the search should continue, false otherwise.
539 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
540 struct amdgpu_vm_pt *entry)
542 return entry && (!start || entry != start->entry);
546 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
548 * @adev: amdgpu_device structure
549 * @cursor: current state
551 * Move the cursor to the next node in a deep first search.
553 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
554 struct amdgpu_vm_pt_cursor *cursor)
560 cursor->entry = NULL;
561 else if (amdgpu_vm_pt_sibling(adev, cursor))
562 while (amdgpu_vm_pt_descendant(adev, cursor));
564 amdgpu_vm_pt_ancestor(cursor);
568 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
570 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
571 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
572 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
573 amdgpu_vm_pt_continue_dfs((start), (entry)); \
574 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
577 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
579 * @vm: vm providing the BOs
580 * @validated: head of validation list
581 * @entry: entry to add
583 * Add the page directory to the list of BOs to
584 * validate for command submission.
586 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
587 struct list_head *validated,
588 struct amdgpu_bo_list_entry *entry)
591 entry->tv.bo = &vm->root.base.bo->tbo;
592 /* Two for VM updates, one for TTM and one for the CS job */
593 entry->tv.num_shared = 4;
594 entry->user_pages = NULL;
595 list_add(&entry->tv.head, validated);
599 * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
601 * @bo: BO which was removed from the LRU
603 * Make sure the bulk_moveable flag is updated when a BO is removed from the
606 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
608 struct amdgpu_bo *abo;
609 struct amdgpu_vm_bo_base *bo_base;
611 if (!amdgpu_bo_is_amdgpu_bo(bo))
617 abo = ttm_to_amdgpu_bo(bo);
620 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
621 struct amdgpu_vm *vm = bo_base->vm;
623 if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
624 vm->bulk_moveable = false;
629 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
631 * @adev: amdgpu device pointer
632 * @vm: vm providing the BOs
634 * Move all BOs to the end of LRU and remember their positions to put them
637 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
638 struct amdgpu_vm *vm)
640 struct amdgpu_vm_bo_base *bo_base;
642 if (vm->bulk_moveable) {
643 spin_lock(&adev->mman.bdev.lru_lock);
644 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
645 spin_unlock(&adev->mman.bdev.lru_lock);
649 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
651 spin_lock(&adev->mman.bdev.lru_lock);
652 list_for_each_entry(bo_base, &vm->idle, vm_status) {
653 struct amdgpu_bo *bo = bo_base->bo;
658 ttm_bo_move_to_lru_tail(&bo->tbo, &bo->tbo.mem,
661 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
662 &bo->shadow->tbo.mem,
665 spin_unlock(&adev->mman.bdev.lru_lock);
667 vm->bulk_moveable = true;
671 * amdgpu_vm_validate_pt_bos - validate the page table BOs
673 * @adev: amdgpu device pointer
674 * @vm: vm providing the BOs
675 * @validate: callback to do the validation
676 * @param: parameter for the validation callback
678 * Validate the page table BOs on command submission if neccessary.
683 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
684 int (*validate)(void *p, struct amdgpu_bo *bo),
687 struct amdgpu_vm_bo_base *bo_base, *tmp;
690 vm->bulk_moveable &= list_empty(&vm->evicted);
692 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
693 struct amdgpu_bo *bo = bo_base->bo;
695 r = validate(param, bo);
699 if (bo->tbo.type != ttm_bo_type_kernel) {
700 amdgpu_vm_bo_moved(bo_base);
702 vm->update_funcs->map_table(bo);
703 amdgpu_vm_bo_relocated(bo_base);
707 amdgpu_vm_eviction_lock(vm);
708 vm->evicting = false;
709 amdgpu_vm_eviction_unlock(vm);
715 * amdgpu_vm_ready - check VM is ready for updates
719 * Check if all VM PDs/PTs are ready for updates
722 * True if eviction list is empty.
724 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
726 return list_empty(&vm->evicted);
730 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
732 * @adev: amdgpu_device pointer
733 * @vm: VM to clear BO from
735 * @immediate: use an immediate update
737 * Root PD needs to be reserved when calling this.
740 * 0 on success, errno otherwise.
742 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
743 struct amdgpu_vm *vm,
744 struct amdgpu_bo *bo,
747 struct ttm_operation_ctx ctx = { true, false };
748 unsigned level = adev->vm_manager.root_level;
749 struct amdgpu_vm_update_params params;
750 struct amdgpu_bo *ancestor = bo;
751 unsigned entries, ats_entries;
755 /* Figure out our place in the hierarchy */
756 if (ancestor->parent) {
758 while (ancestor->parent->parent) {
760 ancestor = ancestor->parent;
764 entries = amdgpu_bo_size(bo) / 8;
765 if (!vm->pte_support_ats) {
768 } else if (!bo->parent) {
769 ats_entries = amdgpu_vm_num_ats_entries(adev);
770 ats_entries = min(ats_entries, entries);
771 entries -= ats_entries;
774 struct amdgpu_vm_pt *pt;
776 pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
777 ats_entries = amdgpu_vm_num_ats_entries(adev);
778 if ((pt - vm->root.entries) >= ats_entries) {
781 ats_entries = entries;
786 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
791 r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
797 r = vm->update_funcs->map_table(bo);
801 memset(¶ms, 0, sizeof(params));
804 params.immediate = immediate;
806 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
812 uint64_t value = 0, flags;
814 flags = AMDGPU_PTE_DEFAULT_ATC;
815 if (level != AMDGPU_VM_PTB) {
816 /* Handle leaf PDEs as PTEs */
817 flags |= AMDGPU_PDE_PTE;
818 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
821 r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries,
826 addr += ats_entries * 8;
830 uint64_t value = 0, flags = 0;
832 if (adev->asic_type >= CHIP_VEGA10) {
833 if (level != AMDGPU_VM_PTB) {
834 /* Handle leaf PDEs as PTEs */
835 flags |= AMDGPU_PDE_PTE;
836 amdgpu_gmc_get_vm_pde(adev, level,
839 /* Workaround for fault priority problem on GMC9 */
840 flags = AMDGPU_PTE_EXECUTABLE;
844 r = vm->update_funcs->update(¶ms, bo, addr, 0, entries,
850 return vm->update_funcs->commit(¶ms, NULL);
854 * amdgpu_vm_pt_create - create bo for PD/PT
856 * @adev: amdgpu_device pointer
858 * @level: the page table level
859 * @immediate: use a immediate update
860 * @bo: pointer to the buffer object pointer
862 static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
863 struct amdgpu_vm *vm,
864 int level, bool immediate,
865 struct amdgpu_bo **bo)
867 struct amdgpu_bo_param bp;
870 memset(&bp, 0, sizeof(bp));
872 bp.size = amdgpu_vm_bo_size(adev, level);
873 bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
874 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
875 bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
876 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
877 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
878 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
879 if (vm->use_cpu_for_update)
880 bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
882 bp.type = ttm_bo_type_kernel;
883 bp.no_wait_gpu = immediate;
884 if (vm->root.base.bo)
885 bp.resv = vm->root.base.bo->tbo.base.resv;
887 r = amdgpu_bo_create(adev, &bp, bo);
891 if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
895 WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
897 r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
900 dma_resv_unlock((*bo)->tbo.base.resv);
911 * amdgpu_vm_alloc_pts - Allocate a specific page table
913 * @adev: amdgpu_device pointer
914 * @vm: VM to allocate page tables for
915 * @cursor: Which page table to allocate
916 * @immediate: use an immediate update
918 * Make sure a specific page table or directory is allocated.
921 * 1 if page table needed to be allocated, 0 if page table was already
922 * allocated, negative errno if an error occurred.
924 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
925 struct amdgpu_vm *vm,
926 struct amdgpu_vm_pt_cursor *cursor,
929 struct amdgpu_vm_pt *entry = cursor->entry;
930 struct amdgpu_bo *pt;
933 if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
934 unsigned num_entries;
936 num_entries = amdgpu_vm_num_entries(adev, cursor->level);
937 entry->entries = kvmalloc_array(num_entries,
938 sizeof(*entry->entries),
939 GFP_KERNEL | __GFP_ZERO);
947 r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
951 /* Keep a reference to the root directory to avoid
952 * freeing them up in the wrong order.
954 pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
955 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
957 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
964 amdgpu_bo_unref(&pt->shadow);
965 amdgpu_bo_unref(&pt);
970 * amdgpu_vm_free_table - fre one PD/PT
972 * @entry: PDE to free
974 static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
976 if (entry->base.bo) {
977 entry->base.bo->vm_bo = NULL;
978 list_del(&entry->base.vm_status);
979 amdgpu_bo_unref(&entry->base.bo->shadow);
980 amdgpu_bo_unref(&entry->base.bo);
982 kvfree(entry->entries);
983 entry->entries = NULL;
987 * amdgpu_vm_free_pts - free PD/PT levels
989 * @adev: amdgpu device structure
990 * @vm: amdgpu vm structure
991 * @start: optional cursor where to start freeing PDs/PTs
993 * Free the page directory or page table level and all sub levels.
995 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
996 struct amdgpu_vm *vm,
997 struct amdgpu_vm_pt_cursor *start)
999 struct amdgpu_vm_pt_cursor cursor;
1000 struct amdgpu_vm_pt *entry;
1002 vm->bulk_moveable = false;
1004 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
1005 amdgpu_vm_free_table(entry);
1008 amdgpu_vm_free_table(start->entry);
1012 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
1014 * @adev: amdgpu_device pointer
1016 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1018 const struct amdgpu_ip_block *ip_block;
1019 bool has_compute_vm_bug;
1020 struct amdgpu_ring *ring;
1023 has_compute_vm_bug = false;
1025 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1027 /* Compute has a VM bug for GFX version < 7.
1028 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1029 if (ip_block->version->major <= 7)
1030 has_compute_vm_bug = true;
1031 else if (ip_block->version->major == 8)
1032 if (adev->gfx.mec_fw_version < 673)
1033 has_compute_vm_bug = true;
1036 for (i = 0; i < adev->num_rings; i++) {
1037 ring = adev->rings[i];
1038 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1039 /* only compute rings */
1040 ring->has_compute_vm_bug = has_compute_vm_bug;
1042 ring->has_compute_vm_bug = false;
1047 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1049 * @ring: ring on which the job will be submitted
1050 * @job: job to submit
1053 * True if sync is needed.
1055 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1056 struct amdgpu_job *job)
1058 struct amdgpu_device *adev = ring->adev;
1059 unsigned vmhub = ring->funcs->vmhub;
1060 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1061 struct amdgpu_vmid *id;
1062 bool gds_switch_needed;
1063 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1067 id = &id_mgr->ids[job->vmid];
1068 gds_switch_needed = ring->funcs->emit_gds_switch && (
1069 id->gds_base != job->gds_base ||
1070 id->gds_size != job->gds_size ||
1071 id->gws_base != job->gws_base ||
1072 id->gws_size != job->gws_size ||
1073 id->oa_base != job->oa_base ||
1074 id->oa_size != job->oa_size);
1076 if (amdgpu_vmid_had_gpu_reset(adev, id))
1079 return vm_flush_needed || gds_switch_needed;
1083 * amdgpu_vm_flush - hardware flush the vm
1085 * @ring: ring to use for flush
1087 * @need_pipe_sync: is pipe sync needed
1089 * Emit a VM flush when it is necessary.
1092 * 0 on success, errno otherwise.
1094 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1095 bool need_pipe_sync)
1097 struct amdgpu_device *adev = ring->adev;
1098 unsigned vmhub = ring->funcs->vmhub;
1099 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1100 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1101 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1102 id->gds_base != job->gds_base ||
1103 id->gds_size != job->gds_size ||
1104 id->gws_base != job->gws_base ||
1105 id->gws_size != job->gws_size ||
1106 id->oa_base != job->oa_base ||
1107 id->oa_size != job->oa_size);
1108 bool vm_flush_needed = job->vm_needs_flush;
1109 struct dma_fence *fence = NULL;
1110 bool pasid_mapping_needed = false;
1111 unsigned patch_offset = 0;
1112 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1115 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1116 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1118 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1119 gds_switch_needed = true;
1120 vm_flush_needed = true;
1121 pasid_mapping_needed = true;
1124 mutex_lock(&id_mgr->lock);
1125 if (id->pasid != job->pasid || !id->pasid_mapping ||
1126 !dma_fence_is_signaled(id->pasid_mapping))
1127 pasid_mapping_needed = true;
1128 mutex_unlock(&id_mgr->lock);
1130 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1131 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1132 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1133 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1134 ring->funcs->emit_wreg;
1136 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1139 if (ring->funcs->init_cond_exec)
1140 patch_offset = amdgpu_ring_init_cond_exec(ring);
1143 amdgpu_ring_emit_pipeline_sync(ring);
1145 if (vm_flush_needed) {
1146 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1147 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1150 if (pasid_mapping_needed)
1151 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1153 if (vm_flush_needed || pasid_mapping_needed) {
1154 r = amdgpu_fence_emit(ring, &fence, 0);
1159 if (vm_flush_needed) {
1160 mutex_lock(&id_mgr->lock);
1161 dma_fence_put(id->last_flush);
1162 id->last_flush = dma_fence_get(fence);
1163 id->current_gpu_reset_count =
1164 atomic_read(&adev->gpu_reset_counter);
1165 mutex_unlock(&id_mgr->lock);
1168 if (pasid_mapping_needed) {
1169 mutex_lock(&id_mgr->lock);
1170 id->pasid = job->pasid;
1171 dma_fence_put(id->pasid_mapping);
1172 id->pasid_mapping = dma_fence_get(fence);
1173 mutex_unlock(&id_mgr->lock);
1175 dma_fence_put(fence);
1177 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1178 id->gds_base = job->gds_base;
1179 id->gds_size = job->gds_size;
1180 id->gws_base = job->gws_base;
1181 id->gws_size = job->gws_size;
1182 id->oa_base = job->oa_base;
1183 id->oa_size = job->oa_size;
1184 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1185 job->gds_size, job->gws_base,
1186 job->gws_size, job->oa_base,
1190 if (ring->funcs->patch_cond_exec)
1191 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1193 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1194 if (ring->funcs->emit_switch_buffer) {
1195 amdgpu_ring_emit_switch_buffer(ring);
1196 amdgpu_ring_emit_switch_buffer(ring);
1202 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1205 * @bo: requested buffer object
1207 * Find @bo inside the requested vm.
1208 * Search inside the @bos vm list for the requested vm
1209 * Returns the found bo_va or NULL if none is found
1211 * Object has to be reserved!
1214 * Found bo_va or NULL.
1216 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1217 struct amdgpu_bo *bo)
1219 struct amdgpu_vm_bo_base *base;
1221 for (base = bo->vm_bo; base; base = base->next) {
1225 return container_of(base, struct amdgpu_bo_va, base);
1231 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1233 * @pages_addr: optional DMA address to use for lookup
1234 * @addr: the unmapped addr
1236 * Look up the physical address of the page that the pte resolves
1240 * The pointer for the page table entry.
1242 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1246 /* page table offset */
1247 result = pages_addr[addr >> PAGE_SHIFT];
1249 /* in case cpu page size != gpu page size*/
1250 result |= addr & (~PAGE_MASK);
1252 result &= 0xFFFFFFFFFFFFF000ULL;
1258 * amdgpu_vm_update_pde - update a single level in the hierarchy
1260 * @params: parameters for the update
1262 * @entry: entry to update
1264 * Makes sure the requested entry in parent is up to date.
1266 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1267 struct amdgpu_vm *vm,
1268 struct amdgpu_vm_pt *entry)
1270 struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
1271 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1272 uint64_t pde, pt, flags;
1275 for (level = 0, pbo = bo->parent; pbo; ++level)
1278 level += params->adev->vm_manager.root_level;
1279 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1280 pde = (entry - parent->entries) * 8;
1281 return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
1285 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1287 * @adev: amdgpu_device pointer
1290 * Mark all PD level as invalid after an error.
1292 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1293 struct amdgpu_vm *vm)
1295 struct amdgpu_vm_pt_cursor cursor;
1296 struct amdgpu_vm_pt *entry;
1298 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1299 if (entry->base.bo && !entry->base.moved)
1300 amdgpu_vm_bo_relocated(&entry->base);
1304 * amdgpu_vm_update_pdes - make sure that all directories are valid
1306 * @adev: amdgpu_device pointer
1308 * @immediate: submit immediately to the paging queue
1310 * Makes sure all directories are up to date.
1313 * 0 for success, error for failure.
1315 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1316 struct amdgpu_vm *vm, bool immediate)
1318 struct amdgpu_vm_update_params params;
1321 if (list_empty(&vm->relocated))
1324 memset(¶ms, 0, sizeof(params));
1327 params.immediate = immediate;
1329 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1333 while (!list_empty(&vm->relocated)) {
1334 struct amdgpu_vm_pt *entry;
1336 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1338 amdgpu_vm_bo_idle(&entry->base);
1340 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1345 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1351 amdgpu_vm_invalidate_pds(adev, vm);
1356 * amdgpu_vm_update_flags - figure out flags for PTE updates
1358 * Make sure to set the right flags for the PTEs at the desired level.
1360 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1361 struct amdgpu_bo *bo, unsigned level,
1362 uint64_t pe, uint64_t addr,
1363 unsigned count, uint32_t incr,
1367 if (level != AMDGPU_VM_PTB) {
1368 flags |= AMDGPU_PDE_PTE;
1369 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1371 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1372 !(flags & AMDGPU_PTE_VALID) &&
1373 !(flags & AMDGPU_PTE_PRT)) {
1375 /* Workaround for fault priority problem on GMC9 */
1376 flags |= AMDGPU_PTE_EXECUTABLE;
1379 params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
1384 * amdgpu_vm_fragment - get fragment for PTEs
1386 * @params: see amdgpu_vm_update_params definition
1387 * @start: first PTE to handle
1388 * @end: last PTE to handle
1389 * @flags: hw mapping flags
1390 * @frag: resulting fragment size
1391 * @frag_end: end of this fragment
1393 * Returns the first possible fragment for the start and end address.
1395 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1396 uint64_t start, uint64_t end, uint64_t flags,
1397 unsigned int *frag, uint64_t *frag_end)
1400 * The MC L1 TLB supports variable sized pages, based on a fragment
1401 * field in the PTE. When this field is set to a non-zero value, page
1402 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1403 * flags are considered valid for all PTEs within the fragment range
1404 * and corresponding mappings are assumed to be physically contiguous.
1406 * The L1 TLB can store a single PTE for the whole fragment,
1407 * significantly increasing the space available for translation
1408 * caching. This leads to large improvements in throughput when the
1409 * TLB is under pressure.
1411 * The L2 TLB distributes small and large fragments into two
1412 * asymmetric partitions. The large fragment cache is significantly
1413 * larger. Thus, we try to use large fragments wherever possible.
1414 * Userspace can support this by aligning virtual base address and
1415 * allocation size to the fragment size.
1417 * Starting with Vega10 the fragment size only controls the L1. The L2
1418 * is now directly feed with small/huge/giant pages from the walker.
1422 if (params->adev->asic_type < CHIP_VEGA10)
1423 max_frag = params->adev->vm_manager.fragment_size;
1427 /* system pages are non continuously */
1428 if (params->pages_addr) {
1434 /* This intentionally wraps around if no bit is set */
1435 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1436 if (*frag >= max_frag) {
1438 *frag_end = end & ~((1ULL << max_frag) - 1);
1440 *frag_end = start + (1 << *frag);
1445 * amdgpu_vm_update_ptes - make sure that page tables are valid
1447 * @params: see amdgpu_vm_update_params definition
1448 * @start: start of GPU address range
1449 * @end: end of GPU address range
1450 * @dst: destination address to map to, the next dst inside the function
1451 * @flags: mapping flags
1453 * Update the page tables in the range @start - @end.
1456 * 0 for success, -EINVAL for failure.
1458 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1459 uint64_t start, uint64_t end,
1460 uint64_t dst, uint64_t flags)
1462 struct amdgpu_device *adev = params->adev;
1463 struct amdgpu_vm_pt_cursor cursor;
1464 uint64_t frag_start = start, frag_end;
1468 /* figure out the initial fragment */
1469 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1471 /* walk over the address space and update the PTs */
1472 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1473 while (cursor.pfn < end) {
1474 unsigned shift, parent_shift, mask;
1475 uint64_t incr, entry_end, pe_start;
1476 struct amdgpu_bo *pt;
1478 if (!params->unlocked) {
1479 /* make sure that the page tables covering the
1480 * address range are actually allocated
1482 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1483 &cursor, params->immediate);
1488 shift = amdgpu_vm_level_shift(adev, cursor.level);
1489 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1490 if (params->unlocked) {
1491 /* Unlocked updates are only allowed on the leaves */
1492 if (amdgpu_vm_pt_descendant(adev, &cursor))
1494 } else if (adev->asic_type < CHIP_VEGA10 &&
1495 (flags & AMDGPU_PTE_VALID)) {
1496 /* No huge page support before GMC v9 */
1497 if (cursor.level != AMDGPU_VM_PTB) {
1498 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1502 } else if (frag < shift) {
1503 /* We can't use this level when the fragment size is
1504 * smaller than the address shift. Go to the next
1505 * child entry and try again.
1507 if (amdgpu_vm_pt_descendant(adev, &cursor))
1509 } else if (frag >= parent_shift) {
1510 /* If the fragment size is even larger than the parent
1511 * shift we should go up one level and check it again.
1513 if (!amdgpu_vm_pt_ancestor(&cursor))
1518 pt = cursor.entry->base.bo;
1520 /* We need all PDs and PTs for mapping something, */
1521 if (flags & AMDGPU_PTE_VALID)
1524 /* but unmapping something can happen at a higher
1527 if (!amdgpu_vm_pt_ancestor(&cursor))
1530 pt = cursor.entry->base.bo;
1531 shift = parent_shift;
1532 frag_end = max(frag_end, ALIGN(frag_start + 1,
1536 /* Looks good so far, calculate parameters for the update */
1537 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1538 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1539 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1540 entry_end = ((uint64_t)mask + 1) << shift;
1541 entry_end += cursor.pfn & ~(entry_end - 1);
1542 entry_end = min(entry_end, end);
1545 struct amdgpu_vm *vm = params->vm;
1546 uint64_t upd_end = min(entry_end, frag_end);
1547 unsigned nptes = (upd_end - frag_start) >> shift;
1548 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1550 /* This can happen when we set higher level PDs to
1551 * silent to stop fault floods.
1553 nptes = max(nptes, 1u);
1555 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1556 nptes, dst, incr, upd_flags,
1558 vm->immediate.fence_context);
1559 amdgpu_vm_update_flags(params, pt, cursor.level,
1560 pe_start, dst, nptes, incr,
1563 pe_start += nptes * 8;
1564 dst += nptes * incr;
1566 frag_start = upd_end;
1567 if (frag_start >= frag_end) {
1568 /* figure out the next fragment */
1569 amdgpu_vm_fragment(params, frag_start, end,
1570 flags, &frag, &frag_end);
1574 } while (frag_start < entry_end);
1576 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1577 /* Free all child entries.
1578 * Update the tables with the flags and addresses and free up subsequent
1579 * tables in the case of huge pages or freed up areas.
1580 * This is the maximum you can free, because all other page tables are not
1581 * completely covered by the range and so potentially still in use.
1583 while (cursor.pfn < frag_start) {
1584 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1585 amdgpu_vm_pt_next(adev, &cursor);
1588 } else if (frag >= shift) {
1589 /* or just move on to the next on the same level. */
1590 amdgpu_vm_pt_next(adev, &cursor);
1598 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1600 * @adev: amdgpu_device pointer of the VM
1601 * @bo_adev: amdgpu_device pointer of the mapped BO
1603 * @immediate: immediate submission in a page fault
1604 * @unlocked: unlocked invalidation during MM callback
1605 * @resv: fences we need to sync to
1606 * @start: start of mapped range
1607 * @last: last mapped entry
1608 * @flags: flags for the entries
1609 * @offset: offset into nodes and pages_addr
1610 * @nodes: array of drm_mm_nodes with the MC addresses
1611 * @pages_addr: DMA addresses to use for mapping
1612 * @fence: optional resulting fence
1614 * Fill in the page table entries between @start and @last.
1617 * 0 for success, -EINVAL for failure.
1619 int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1620 struct amdgpu_device *bo_adev,
1621 struct amdgpu_vm *vm, bool immediate,
1622 bool unlocked, struct dma_resv *resv,
1623 uint64_t start, uint64_t last,
1624 uint64_t flags, uint64_t offset,
1625 struct drm_mm_node *nodes,
1626 dma_addr_t *pages_addr,
1627 struct dma_fence **fence)
1629 struct amdgpu_vm_update_params params;
1630 enum amdgpu_sync_mode sync_mode;
1634 memset(¶ms, 0, sizeof(params));
1637 params.immediate = immediate;
1638 params.pages_addr = pages_addr;
1639 params.unlocked = unlocked;
1641 /* Implicitly sync to command submissions in the same VM before
1642 * unmapping. Sync to moving fences before mapping.
1644 if (!(flags & AMDGPU_PTE_VALID))
1645 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1647 sync_mode = AMDGPU_SYNC_EXPLICIT;
1649 pfn = offset >> PAGE_SHIFT;
1651 while (pfn >= nodes->size) {
1657 amdgpu_vm_eviction_lock(vm);
1663 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1664 struct dma_fence *tmp = dma_fence_get_stub();
1666 amdgpu_bo_fence(vm->root.base.bo, vm->last_unlocked, true);
1667 swap(vm->last_unlocked, tmp);
1671 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1676 uint64_t tmp, num_entries, addr;
1679 num_entries = last - start + 1;
1681 addr = nodes->start << PAGE_SHIFT;
1682 num_entries = min((nodes->size - pfn) *
1683 AMDGPU_GPU_PAGES_IN_CPU_PAGE, num_entries);
1689 bool contiguous = true;
1691 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1694 contiguous = pages_addr[pfn + 1] ==
1695 pages_addr[pfn] + PAGE_SIZE;
1698 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1699 for (count = 2; count < tmp; ++count) {
1700 uint64_t idx = pfn + count;
1702 if (contiguous != (pages_addr[idx] ==
1703 pages_addr[idx - 1] + PAGE_SIZE))
1706 num_entries = count *
1707 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1711 addr = pfn << PAGE_SHIFT;
1712 params.pages_addr = pages_addr;
1714 addr = pages_addr[pfn];
1715 params.pages_addr = NULL;
1718 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1719 addr += bo_adev->vm_manager.vram_base_offset;
1720 addr += pfn << PAGE_SHIFT;
1723 tmp = start + num_entries;
1724 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1728 pfn += num_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1729 if (nodes && nodes->size == pfn) {
1735 } while (unlikely(start != last + 1));
1737 r = vm->update_funcs->commit(¶ms, fence);
1740 amdgpu_vm_eviction_unlock(vm);
1744 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1745 uint64_t *gtt_mem, uint64_t *cpu_mem)
1747 struct amdgpu_bo_va *bo_va, *tmp;
1749 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1750 if (!bo_va->base.bo)
1752 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1755 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1756 if (!bo_va->base.bo)
1758 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1761 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1762 if (!bo_va->base.bo)
1764 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1767 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1768 if (!bo_va->base.bo)
1770 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1773 spin_lock(&vm->invalidated_lock);
1774 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1775 if (!bo_va->base.bo)
1777 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1780 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1781 if (!bo_va->base.bo)
1783 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1786 spin_unlock(&vm->invalidated_lock);
1789 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1791 * @adev: amdgpu_device pointer
1792 * @bo_va: requested BO and VM object
1793 * @clear: if true clear the entries
1795 * Fill in the page table entries for @bo_va.
1798 * 0 for success, -EINVAL for failure.
1800 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1803 struct amdgpu_bo *bo = bo_va->base.bo;
1804 struct amdgpu_vm *vm = bo_va->base.vm;
1805 struct amdgpu_bo_va_mapping *mapping;
1806 dma_addr_t *pages_addr = NULL;
1807 struct ttm_resource *mem;
1808 struct drm_mm_node *nodes;
1809 struct dma_fence **last_update;
1810 struct dma_resv *resv;
1812 struct amdgpu_device *bo_adev = adev;
1818 resv = vm->root.base.bo->tbo.base.resv;
1820 struct drm_gem_object *obj = &bo->tbo.base;
1822 resv = bo->tbo.base.resv;
1823 if (obj->import_attach && bo_va->is_xgmi) {
1824 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1825 struct drm_gem_object *gobj = dma_buf->priv;
1826 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1828 if (abo->tbo.mem.mem_type == TTM_PL_VRAM)
1829 bo = gem_to_amdgpu_bo(gobj);
1832 nodes = mem->mm_node;
1833 if (mem->mem_type == TTM_PL_TT)
1834 pages_addr = bo->tbo.ttm->dma_address;
1838 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1840 if (amdgpu_bo_encrypted(bo))
1841 flags |= AMDGPU_PTE_TMZ;
1843 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1848 if (clear || (bo && bo->tbo.base.resv ==
1849 vm->root.base.bo->tbo.base.resv))
1850 last_update = &vm->last_update;
1852 last_update = &bo_va->last_pt_update;
1854 if (!clear && bo_va->base.moved) {
1855 bo_va->base.moved = false;
1856 list_splice_init(&bo_va->valids, &bo_va->invalids);
1858 } else if (bo_va->cleared != clear) {
1859 list_splice_init(&bo_va->valids, &bo_va->invalids);
1862 list_for_each_entry(mapping, &bo_va->invalids, list) {
1863 uint64_t update_flags = flags;
1865 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1866 * but in case of something, we filter the flags in first place
1868 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1869 update_flags &= ~AMDGPU_PTE_READABLE;
1870 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1871 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1873 /* Apply ASIC specific mapping flags */
1874 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1876 trace_amdgpu_vm_bo_update(mapping);
1878 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1879 resv, mapping->start,
1880 mapping->last, update_flags,
1881 mapping->offset, nodes,
1882 pages_addr, last_update);
1887 /* If the BO is not in its preferred location add it back to
1888 * the evicted list so that it gets validated again on the
1889 * next command submission.
1891 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
1892 uint32_t mem_type = bo->tbo.mem.mem_type;
1894 if (!(bo->preferred_domains &
1895 amdgpu_mem_type_to_domain(mem_type)))
1896 amdgpu_vm_bo_evicted(&bo_va->base);
1898 amdgpu_vm_bo_idle(&bo_va->base);
1900 amdgpu_vm_bo_done(&bo_va->base);
1903 list_splice_init(&bo_va->invalids, &bo_va->valids);
1904 bo_va->cleared = clear;
1906 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1907 list_for_each_entry(mapping, &bo_va->valids, list)
1908 trace_amdgpu_vm_bo_mapping(mapping);
1915 * amdgpu_vm_update_prt_state - update the global PRT state
1917 * @adev: amdgpu_device pointer
1919 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1921 unsigned long flags;
1924 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1925 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1926 adev->gmc.gmc_funcs->set_prt(adev, enable);
1927 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1931 * amdgpu_vm_prt_get - add a PRT user
1933 * @adev: amdgpu_device pointer
1935 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1937 if (!adev->gmc.gmc_funcs->set_prt)
1940 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1941 amdgpu_vm_update_prt_state(adev);
1945 * amdgpu_vm_prt_put - drop a PRT user
1947 * @adev: amdgpu_device pointer
1949 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1951 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1952 amdgpu_vm_update_prt_state(adev);
1956 * amdgpu_vm_prt_cb - callback for updating the PRT status
1958 * @fence: fence for the callback
1959 * @_cb: the callback function
1961 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1963 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1965 amdgpu_vm_prt_put(cb->adev);
1970 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1972 * @adev: amdgpu_device pointer
1973 * @fence: fence for the callback
1975 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1976 struct dma_fence *fence)
1978 struct amdgpu_prt_cb *cb;
1980 if (!adev->gmc.gmc_funcs->set_prt)
1983 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1985 /* Last resort when we are OOM */
1987 dma_fence_wait(fence, false);
1989 amdgpu_vm_prt_put(adev);
1992 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1994 amdgpu_vm_prt_cb(fence, &cb->cb);
1999 * amdgpu_vm_free_mapping - free a mapping
2001 * @adev: amdgpu_device pointer
2003 * @mapping: mapping to be freed
2004 * @fence: fence of the unmap operation
2006 * Free a mapping and make sure we decrease the PRT usage count if applicable.
2008 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2009 struct amdgpu_vm *vm,
2010 struct amdgpu_bo_va_mapping *mapping,
2011 struct dma_fence *fence)
2013 if (mapping->flags & AMDGPU_PTE_PRT)
2014 amdgpu_vm_add_prt_cb(adev, fence);
2019 * amdgpu_vm_prt_fini - finish all prt mappings
2021 * @adev: amdgpu_device pointer
2024 * Register a cleanup callback to disable PRT support after VM dies.
2026 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2028 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
2029 struct dma_fence *excl, **shared;
2030 unsigned i, shared_count;
2033 r = dma_resv_get_fences_rcu(resv, &excl,
2034 &shared_count, &shared);
2036 /* Not enough memory to grab the fence list, as last resort
2037 * block for all the fences to complete.
2039 dma_resv_wait_timeout_rcu(resv, true, false,
2040 MAX_SCHEDULE_TIMEOUT);
2044 /* Add a callback for each fence in the reservation object */
2045 amdgpu_vm_prt_get(adev);
2046 amdgpu_vm_add_prt_cb(adev, excl);
2048 for (i = 0; i < shared_count; ++i) {
2049 amdgpu_vm_prt_get(adev);
2050 amdgpu_vm_add_prt_cb(adev, shared[i]);
2057 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2059 * @adev: amdgpu_device pointer
2061 * @fence: optional resulting fence (unchanged if no work needed to be done
2062 * or if an error occurred)
2064 * Make sure all freed BOs are cleared in the PT.
2065 * PTs have to be reserved and mutex must be locked!
2071 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2072 struct amdgpu_vm *vm,
2073 struct dma_fence **fence)
2075 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
2076 struct amdgpu_bo_va_mapping *mapping;
2077 uint64_t init_pte_value = 0;
2078 struct dma_fence *f = NULL;
2081 while (!list_empty(&vm->freed)) {
2082 mapping = list_first_entry(&vm->freed,
2083 struct amdgpu_bo_va_mapping, list);
2084 list_del(&mapping->list);
2086 if (vm->pte_support_ats &&
2087 mapping->start < AMDGPU_GMC_HOLE_START)
2088 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2090 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2091 resv, mapping->start,
2092 mapping->last, init_pte_value,
2094 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2102 dma_fence_put(*fence);
2113 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2115 * @adev: amdgpu_device pointer
2118 * Make sure all BOs which are moved are updated in the PTs.
2123 * PTs have to be reserved!
2125 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2126 struct amdgpu_vm *vm)
2128 struct amdgpu_bo_va *bo_va, *tmp;
2129 struct dma_resv *resv;
2133 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2134 /* Per VM BOs never need to bo cleared in the page tables */
2135 r = amdgpu_vm_bo_update(adev, bo_va, false);
2140 spin_lock(&vm->invalidated_lock);
2141 while (!list_empty(&vm->invalidated)) {
2142 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2144 resv = bo_va->base.bo->tbo.base.resv;
2145 spin_unlock(&vm->invalidated_lock);
2147 /* Try to reserve the BO to avoid clearing its ptes */
2148 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2150 /* Somebody else is using the BO right now */
2154 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2159 dma_resv_unlock(resv);
2160 spin_lock(&vm->invalidated_lock);
2162 spin_unlock(&vm->invalidated_lock);
2168 * amdgpu_vm_bo_add - add a bo to a specific vm
2170 * @adev: amdgpu_device pointer
2172 * @bo: amdgpu buffer object
2174 * Add @bo into the requested vm.
2175 * Add @bo to the list of bos associated with the vm
2178 * Newly added bo_va or NULL for failure
2180 * Object has to be reserved!
2182 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2183 struct amdgpu_vm *vm,
2184 struct amdgpu_bo *bo)
2186 struct amdgpu_bo_va *bo_va;
2188 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2189 if (bo_va == NULL) {
2192 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2194 bo_va->ref_count = 1;
2195 INIT_LIST_HEAD(&bo_va->valids);
2196 INIT_LIST_HEAD(&bo_va->invalids);
2201 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2202 bo_va->is_xgmi = true;
2203 /* Power up XGMI if it can be potentially used */
2204 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2212 * amdgpu_vm_bo_insert_map - insert a new mapping
2214 * @adev: amdgpu_device pointer
2215 * @bo_va: bo_va to store the address
2216 * @mapping: the mapping to insert
2218 * Insert a new mapping into all structures.
2220 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2221 struct amdgpu_bo_va *bo_va,
2222 struct amdgpu_bo_va_mapping *mapping)
2224 struct amdgpu_vm *vm = bo_va->base.vm;
2225 struct amdgpu_bo *bo = bo_va->base.bo;
2227 mapping->bo_va = bo_va;
2228 list_add(&mapping->list, &bo_va->invalids);
2229 amdgpu_vm_it_insert(mapping, &vm->va);
2231 if (mapping->flags & AMDGPU_PTE_PRT)
2232 amdgpu_vm_prt_get(adev);
2234 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
2235 !bo_va->base.moved) {
2236 list_move(&bo_va->base.vm_status, &vm->moved);
2238 trace_amdgpu_vm_bo_map(bo_va, mapping);
2242 * amdgpu_vm_bo_map - map bo inside a vm
2244 * @adev: amdgpu_device pointer
2245 * @bo_va: bo_va to store the address
2246 * @saddr: where to map the BO
2247 * @offset: requested offset in the BO
2248 * @size: BO size in bytes
2249 * @flags: attributes of pages (read/write/valid/etc.)
2251 * Add a mapping of the BO at the specefied addr into the VM.
2254 * 0 for success, error for failure.
2256 * Object has to be reserved and unreserved outside!
2258 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2259 struct amdgpu_bo_va *bo_va,
2260 uint64_t saddr, uint64_t offset,
2261 uint64_t size, uint64_t flags)
2263 struct amdgpu_bo_va_mapping *mapping, *tmp;
2264 struct amdgpu_bo *bo = bo_va->base.bo;
2265 struct amdgpu_vm *vm = bo_va->base.vm;
2268 /* validate the parameters */
2269 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2270 size == 0 || size & ~PAGE_MASK)
2273 /* make sure object fit at this offset */
2274 eaddr = saddr + size - 1;
2275 if (saddr >= eaddr ||
2276 (bo && offset + size > amdgpu_bo_size(bo)) ||
2277 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2280 saddr /= AMDGPU_GPU_PAGE_SIZE;
2281 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2283 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2285 /* bo and tmp overlap, invalid addr */
2286 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2287 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2288 tmp->start, tmp->last + 1);
2292 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2296 mapping->start = saddr;
2297 mapping->last = eaddr;
2298 mapping->offset = offset;
2299 mapping->flags = flags;
2301 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2307 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2309 * @adev: amdgpu_device pointer
2310 * @bo_va: bo_va to store the address
2311 * @saddr: where to map the BO
2312 * @offset: requested offset in the BO
2313 * @size: BO size in bytes
2314 * @flags: attributes of pages (read/write/valid/etc.)
2316 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2317 * mappings as we do so.
2320 * 0 for success, error for failure.
2322 * Object has to be reserved and unreserved outside!
2324 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2325 struct amdgpu_bo_va *bo_va,
2326 uint64_t saddr, uint64_t offset,
2327 uint64_t size, uint64_t flags)
2329 struct amdgpu_bo_va_mapping *mapping;
2330 struct amdgpu_bo *bo = bo_va->base.bo;
2334 /* validate the parameters */
2335 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2336 size == 0 || size & ~PAGE_MASK)
2339 /* make sure object fit at this offset */
2340 eaddr = saddr + size - 1;
2341 if (saddr >= eaddr ||
2342 (bo && offset + size > amdgpu_bo_size(bo)) ||
2343 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2346 /* Allocate all the needed memory */
2347 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2351 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2357 saddr /= AMDGPU_GPU_PAGE_SIZE;
2358 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2360 mapping->start = saddr;
2361 mapping->last = eaddr;
2362 mapping->offset = offset;
2363 mapping->flags = flags;
2365 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2371 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2373 * @adev: amdgpu_device pointer
2374 * @bo_va: bo_va to remove the address from
2375 * @saddr: where to the BO is mapped
2377 * Remove a mapping of the BO at the specefied addr from the VM.
2380 * 0 for success, error for failure.
2382 * Object has to be reserved and unreserved outside!
2384 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2385 struct amdgpu_bo_va *bo_va,
2388 struct amdgpu_bo_va_mapping *mapping;
2389 struct amdgpu_vm *vm = bo_va->base.vm;
2392 saddr /= AMDGPU_GPU_PAGE_SIZE;
2394 list_for_each_entry(mapping, &bo_va->valids, list) {
2395 if (mapping->start == saddr)
2399 if (&mapping->list == &bo_va->valids) {
2402 list_for_each_entry(mapping, &bo_va->invalids, list) {
2403 if (mapping->start == saddr)
2407 if (&mapping->list == &bo_va->invalids)
2411 list_del(&mapping->list);
2412 amdgpu_vm_it_remove(mapping, &vm->va);
2413 mapping->bo_va = NULL;
2414 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2417 list_add(&mapping->list, &vm->freed);
2419 amdgpu_vm_free_mapping(adev, vm, mapping,
2420 bo_va->last_pt_update);
2426 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2428 * @adev: amdgpu_device pointer
2429 * @vm: VM structure to use
2430 * @saddr: start of the range
2431 * @size: size of the range
2433 * Remove all mappings in a range, split them as appropriate.
2436 * 0 for success, error for failure.
2438 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2439 struct amdgpu_vm *vm,
2440 uint64_t saddr, uint64_t size)
2442 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2446 eaddr = saddr + size - 1;
2447 saddr /= AMDGPU_GPU_PAGE_SIZE;
2448 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2450 /* Allocate all the needed memory */
2451 before = kzalloc(sizeof(*before), GFP_KERNEL);
2454 INIT_LIST_HEAD(&before->list);
2456 after = kzalloc(sizeof(*after), GFP_KERNEL);
2461 INIT_LIST_HEAD(&after->list);
2463 /* Now gather all removed mappings */
2464 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2466 /* Remember mapping split at the start */
2467 if (tmp->start < saddr) {
2468 before->start = tmp->start;
2469 before->last = saddr - 1;
2470 before->offset = tmp->offset;
2471 before->flags = tmp->flags;
2472 before->bo_va = tmp->bo_va;
2473 list_add(&before->list, &tmp->bo_va->invalids);
2476 /* Remember mapping split at the end */
2477 if (tmp->last > eaddr) {
2478 after->start = eaddr + 1;
2479 after->last = tmp->last;
2480 after->offset = tmp->offset;
2481 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2482 after->flags = tmp->flags;
2483 after->bo_va = tmp->bo_va;
2484 list_add(&after->list, &tmp->bo_va->invalids);
2487 list_del(&tmp->list);
2488 list_add(&tmp->list, &removed);
2490 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2493 /* And free them up */
2494 list_for_each_entry_safe(tmp, next, &removed, list) {
2495 amdgpu_vm_it_remove(tmp, &vm->va);
2496 list_del(&tmp->list);
2498 if (tmp->start < saddr)
2500 if (tmp->last > eaddr)
2504 list_add(&tmp->list, &vm->freed);
2505 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2508 /* Insert partial mapping before the range */
2509 if (!list_empty(&before->list)) {
2510 amdgpu_vm_it_insert(before, &vm->va);
2511 if (before->flags & AMDGPU_PTE_PRT)
2512 amdgpu_vm_prt_get(adev);
2517 /* Insert partial mapping after the range */
2518 if (!list_empty(&after->list)) {
2519 amdgpu_vm_it_insert(after, &vm->va);
2520 if (after->flags & AMDGPU_PTE_PRT)
2521 amdgpu_vm_prt_get(adev);
2530 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2532 * @vm: the requested VM
2533 * @addr: the address
2535 * Find a mapping by it's address.
2538 * The amdgpu_bo_va_mapping matching for addr or NULL
2541 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2544 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2548 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2550 * @vm: the requested vm
2551 * @ticket: CS ticket
2553 * Trace all mappings of BOs reserved during a command submission.
2555 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2557 struct amdgpu_bo_va_mapping *mapping;
2559 if (!trace_amdgpu_vm_bo_cs_enabled())
2562 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2563 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2564 if (mapping->bo_va && mapping->bo_va->base.bo) {
2565 struct amdgpu_bo *bo;
2567 bo = mapping->bo_va->base.bo;
2568 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2573 trace_amdgpu_vm_bo_cs(mapping);
2578 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2580 * @adev: amdgpu_device pointer
2581 * @bo_va: requested bo_va
2583 * Remove @bo_va->bo from the requested vm.
2585 * Object have to be reserved!
2587 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2588 struct amdgpu_bo_va *bo_va)
2590 struct amdgpu_bo_va_mapping *mapping, *next;
2591 struct amdgpu_bo *bo = bo_va->base.bo;
2592 struct amdgpu_vm *vm = bo_va->base.vm;
2593 struct amdgpu_vm_bo_base **base;
2596 if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2597 vm->bulk_moveable = false;
2599 for (base = &bo_va->base.bo->vm_bo; *base;
2600 base = &(*base)->next) {
2601 if (*base != &bo_va->base)
2604 *base = bo_va->base.next;
2609 spin_lock(&vm->invalidated_lock);
2610 list_del(&bo_va->base.vm_status);
2611 spin_unlock(&vm->invalidated_lock);
2613 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2614 list_del(&mapping->list);
2615 amdgpu_vm_it_remove(mapping, &vm->va);
2616 mapping->bo_va = NULL;
2617 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2618 list_add(&mapping->list, &vm->freed);
2620 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2621 list_del(&mapping->list);
2622 amdgpu_vm_it_remove(mapping, &vm->va);
2623 amdgpu_vm_free_mapping(adev, vm, mapping,
2624 bo_va->last_pt_update);
2627 dma_fence_put(bo_va->last_pt_update);
2629 if (bo && bo_va->is_xgmi)
2630 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2636 * amdgpu_vm_evictable - check if we can evict a VM
2638 * @bo: A page table of the VM.
2640 * Check if it is possible to evict a VM.
2642 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2644 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2646 /* Page tables of a destroyed VM can go away immediately */
2647 if (!bo_base || !bo_base->vm)
2650 /* Don't evict VM page tables while they are busy */
2651 if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
2654 /* Try to block ongoing updates */
2655 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2658 /* Don't evict VM page tables while they are updated */
2659 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2660 amdgpu_vm_eviction_unlock(bo_base->vm);
2664 bo_base->vm->evicting = true;
2665 amdgpu_vm_eviction_unlock(bo_base->vm);
2670 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2672 * @adev: amdgpu_device pointer
2673 * @bo: amdgpu buffer object
2674 * @evicted: is the BO evicted
2676 * Mark @bo as invalid.
2678 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2679 struct amdgpu_bo *bo, bool evicted)
2681 struct amdgpu_vm_bo_base *bo_base;
2683 /* shadow bo doesn't have bo base, its validation needs its parent */
2684 if (bo->parent && bo->parent->shadow == bo)
2687 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2688 struct amdgpu_vm *vm = bo_base->vm;
2690 if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
2691 amdgpu_vm_bo_evicted(bo_base);
2697 bo_base->moved = true;
2699 if (bo->tbo.type == ttm_bo_type_kernel)
2700 amdgpu_vm_bo_relocated(bo_base);
2701 else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2702 amdgpu_vm_bo_moved(bo_base);
2704 amdgpu_vm_bo_invalidated(bo_base);
2709 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2714 * VM page table as power of two
2716 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2718 /* Total bits covered by PD + PTs */
2719 unsigned bits = ilog2(vm_size) + 18;
2721 /* Make sure the PD is 4K in size up to 8GB address space.
2722 Above that split equal between PD and PTs */
2726 return ((bits + 3) / 2);
2730 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2732 * @adev: amdgpu_device pointer
2733 * @min_vm_size: the minimum vm size in GB if it's set auto
2734 * @fragment_size_default: Default PTE fragment size
2735 * @max_level: max VMPT level
2736 * @max_bits: max address space size in bits
2739 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2740 uint32_t fragment_size_default, unsigned max_level,
2743 unsigned int max_size = 1 << (max_bits - 30);
2744 unsigned int vm_size;
2747 /* adjust vm size first */
2748 if (amdgpu_vm_size != -1) {
2749 vm_size = amdgpu_vm_size;
2750 if (vm_size > max_size) {
2751 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2752 amdgpu_vm_size, max_size);
2757 unsigned int phys_ram_gb;
2759 /* Optimal VM size depends on the amount of physical
2760 * RAM available. Underlying requirements and
2763 * - Need to map system memory and VRAM from all GPUs
2764 * - VRAM from other GPUs not known here
2765 * - Assume VRAM <= system memory
2766 * - On GFX8 and older, VM space can be segmented for
2768 * - Need to allow room for fragmentation, guard pages etc.
2770 * This adds up to a rough guess of system memory x3.
2771 * Round up to power of two to maximize the available
2772 * VM size with the given page table size.
2775 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2776 (1 << 30) - 1) >> 30;
2777 vm_size = roundup_pow_of_two(
2778 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2781 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2783 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2784 if (amdgpu_vm_block_size != -1)
2785 tmp >>= amdgpu_vm_block_size - 9;
2786 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2787 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2788 switch (adev->vm_manager.num_level) {
2790 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2793 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2796 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2799 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2801 /* block size depends on vm size and hw setup*/
2802 if (amdgpu_vm_block_size != -1)
2803 adev->vm_manager.block_size =
2804 min((unsigned)amdgpu_vm_block_size, max_bits
2805 - AMDGPU_GPU_PAGE_SHIFT
2806 - 9 * adev->vm_manager.num_level);
2807 else if (adev->vm_manager.num_level > 1)
2808 adev->vm_manager.block_size = 9;
2810 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2812 if (amdgpu_vm_fragment_size == -1)
2813 adev->vm_manager.fragment_size = fragment_size_default;
2815 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2817 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2818 vm_size, adev->vm_manager.num_level + 1,
2819 adev->vm_manager.block_size,
2820 adev->vm_manager.fragment_size);
2824 * amdgpu_vm_wait_idle - wait for the VM to become idle
2826 * @vm: VM object to wait for
2827 * @timeout: timeout to wait for VM to become idle
2829 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2831 timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
2832 true, true, timeout);
2836 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2840 * amdgpu_vm_init - initialize a vm instance
2842 * @adev: amdgpu_device pointer
2844 * @pasid: Process address space identifier
2849 * 0 for success, error for failure.
2851 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
2853 struct amdgpu_bo *root;
2856 vm->va = RB_ROOT_CACHED;
2857 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2858 vm->reserved_vmid[i] = NULL;
2859 INIT_LIST_HEAD(&vm->evicted);
2860 INIT_LIST_HEAD(&vm->relocated);
2861 INIT_LIST_HEAD(&vm->moved);
2862 INIT_LIST_HEAD(&vm->idle);
2863 INIT_LIST_HEAD(&vm->invalidated);
2864 spin_lock_init(&vm->invalidated_lock);
2865 INIT_LIST_HEAD(&vm->freed);
2866 INIT_LIST_HEAD(&vm->done);
2868 /* create scheduler entities for page table updates */
2869 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2870 adev->vm_manager.vm_pte_scheds,
2871 adev->vm_manager.vm_pte_num_scheds, NULL);
2875 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2876 adev->vm_manager.vm_pte_scheds,
2877 adev->vm_manager.vm_pte_num_scheds, NULL);
2879 goto error_free_immediate;
2881 vm->pte_support_ats = false;
2882 vm->is_compute_context = false;
2884 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2885 AMDGPU_VM_USE_CPU_FOR_GFX);
2887 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2888 vm->use_cpu_for_update ? "CPU" : "SDMA");
2889 WARN_ONCE((vm->use_cpu_for_update &&
2890 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2891 "CPU update of VM recommended only for large BAR system\n");
2893 if (vm->use_cpu_for_update)
2894 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2896 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2897 vm->last_update = NULL;
2898 vm->last_unlocked = dma_fence_get_stub();
2900 mutex_init(&vm->eviction_lock);
2901 vm->evicting = false;
2903 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2906 goto error_free_delayed;
2908 r = amdgpu_bo_reserve(root, true);
2910 goto error_free_root;
2912 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
2914 goto error_unreserve;
2916 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2918 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2920 goto error_unreserve;
2922 amdgpu_bo_unreserve(vm->root.base.bo);
2925 unsigned long flags;
2927 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2928 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2930 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2932 goto error_free_root;
2937 INIT_KFIFO(vm->faults);
2942 amdgpu_bo_unreserve(vm->root.base.bo);
2945 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2946 amdgpu_bo_unref(&vm->root.base.bo);
2947 vm->root.base.bo = NULL;
2950 dma_fence_put(vm->last_unlocked);
2951 drm_sched_entity_destroy(&vm->delayed);
2953 error_free_immediate:
2954 drm_sched_entity_destroy(&vm->immediate);
2960 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2962 * @adev: amdgpu_device pointer
2963 * @vm: the VM to check
2965 * check all entries of the root PD, if any subsequent PDs are allocated,
2966 * it means there are page table creating and filling, and is no a clean
2970 * 0 if this VM is clean
2972 static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2973 struct amdgpu_vm *vm)
2975 enum amdgpu_vm_level root = adev->vm_manager.root_level;
2976 unsigned int entries = amdgpu_vm_num_entries(adev, root);
2979 if (!(vm->root.entries))
2982 for (i = 0; i < entries; i++) {
2983 if (vm->root.entries[i].base.bo)
2991 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2993 * @adev: amdgpu_device pointer
2995 * @pasid: pasid to use
2997 * This only works on GFX VMs that don't have any BOs added and no
2998 * page tables allocated yet.
3000 * Changes the following VM parameters:
3001 * - use_cpu_for_update
3002 * - pte_supports_ats
3003 * - pasid (old PASID is released, because compute manages its own PASIDs)
3005 * Reinitializes the page directory to reflect the changed ATS
3009 * 0 for success, -errno for errors.
3011 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
3014 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3017 r = amdgpu_bo_reserve(vm->root.base.bo, true);
3022 r = amdgpu_vm_check_clean_reserved(adev, vm);
3027 unsigned long flags;
3029 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3030 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3032 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3039 /* Check if PD needs to be reinitialized and do it before
3040 * changing any other state, in case it fails.
3042 if (pte_support_ats != vm->pte_support_ats) {
3043 vm->pte_support_ats = pte_support_ats;
3044 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false);
3049 /* Update VM state */
3050 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3051 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3052 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3053 vm->use_cpu_for_update ? "CPU" : "SDMA");
3054 WARN_ONCE((vm->use_cpu_for_update &&
3055 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3056 "CPU update of VM recommended only for large BAR system\n");
3058 if (vm->use_cpu_for_update) {
3059 /* Sync with last SDMA update/clear before switching to CPU */
3060 r = amdgpu_bo_sync_wait(vm->root.base.bo,
3061 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3065 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3067 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3069 dma_fence_put(vm->last_update);
3070 vm->last_update = NULL;
3071 vm->is_compute_context = true;
3074 unsigned long flags;
3076 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3077 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3078 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3080 /* Free the original amdgpu allocated pasid
3081 * Will be replaced with kfd allocated pasid
3083 amdgpu_pasid_free(vm->pasid);
3087 /* Free the shadow bo for compute VM */
3088 amdgpu_bo_unref(&vm->root.base.bo->shadow);
3097 unsigned long flags;
3099 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3100 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3101 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3104 amdgpu_bo_unreserve(vm->root.base.bo);
3109 * amdgpu_vm_release_compute - release a compute vm
3110 * @adev: amdgpu_device pointer
3111 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3113 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3114 * pasid from vm. Compute should stop use of vm after this call.
3116 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3119 unsigned long flags;
3121 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3122 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3123 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3126 vm->is_compute_context = false;
3130 * amdgpu_vm_fini - tear down a vm instance
3132 * @adev: amdgpu_device pointer
3136 * Unbind the VM and remove all bos from the vm bo list
3138 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3140 struct amdgpu_bo_va_mapping *mapping, *tmp;
3141 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3142 struct amdgpu_bo *root;
3145 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3147 root = amdgpu_bo_ref(vm->root.base.bo);
3148 amdgpu_bo_reserve(root, true);
3150 unsigned long flags;
3152 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3153 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3154 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3158 dma_fence_wait(vm->last_unlocked, false);
3159 dma_fence_put(vm->last_unlocked);
3161 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3162 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3163 amdgpu_vm_prt_fini(adev, vm);
3164 prt_fini_needed = false;
3167 list_del(&mapping->list);
3168 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3171 amdgpu_vm_free_pts(adev, vm, NULL);
3172 amdgpu_bo_unreserve(root);
3173 amdgpu_bo_unref(&root);
3174 WARN_ON(vm->root.base.bo);
3176 drm_sched_entity_destroy(&vm->immediate);
3177 drm_sched_entity_destroy(&vm->delayed);
3179 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3180 dev_err(adev->dev, "still active bo inside vm\n");
3182 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3183 &vm->va.rb_root, rb) {
3184 /* Don't remove the mapping here, we don't want to trigger a
3185 * rebalance and the tree is about to be destroyed anyway.
3187 list_del(&mapping->list);
3191 dma_fence_put(vm->last_update);
3192 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3193 amdgpu_vmid_free_reserved(adev, vm, i);
3197 * amdgpu_vm_manager_init - init the VM manager
3199 * @adev: amdgpu_device pointer
3201 * Initialize the VM manager structures
3203 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3207 /* Concurrent flushes are only possible starting with Vega10 and
3208 * are broken on Navi10 and Navi14.
3210 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3211 adev->asic_type == CHIP_NAVI10 ||
3212 adev->asic_type == CHIP_NAVI14);
3213 amdgpu_vmid_mgr_init(adev);
3215 adev->vm_manager.fence_context =
3216 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3217 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3218 adev->vm_manager.seqno[i] = 0;
3220 spin_lock_init(&adev->vm_manager.prt_lock);
3221 atomic_set(&adev->vm_manager.num_prt_users, 0);
3223 /* If not overridden by the user, by default, only in large BAR systems
3224 * Compute VM tables will be updated by CPU
3226 #ifdef CONFIG_X86_64
3227 if (amdgpu_vm_update_mode == -1) {
3228 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3229 adev->vm_manager.vm_update_mode =
3230 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3232 adev->vm_manager.vm_update_mode = 0;
3234 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3236 adev->vm_manager.vm_update_mode = 0;
3239 idr_init(&adev->vm_manager.pasid_idr);
3240 spin_lock_init(&adev->vm_manager.pasid_lock);
3244 * amdgpu_vm_manager_fini - cleanup VM manager
3246 * @adev: amdgpu_device pointer
3248 * Cleanup the VM manager and free resources.
3250 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3252 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3253 idr_destroy(&adev->vm_manager.pasid_idr);
3255 amdgpu_vmid_mgr_fini(adev);
3259 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3261 * @dev: drm device pointer
3262 * @data: drm_amdgpu_vm
3263 * @filp: drm file pointer
3266 * 0 for success, -errno for errors.
3268 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3270 union drm_amdgpu_vm *args = data;
3271 struct amdgpu_device *adev = drm_to_adev(dev);
3272 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3273 long timeout = msecs_to_jiffies(2000);
3276 switch (args->in.op) {
3277 case AMDGPU_VM_OP_RESERVE_VMID:
3278 /* We only have requirement to reserve vmid from gfxhub */
3279 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3284 case AMDGPU_VM_OP_UNRESERVE_VMID:
3285 if (amdgpu_sriov_runtime(adev))
3286 timeout = 8 * timeout;
3288 /* Wait vm idle to make sure the vmid set in SPM_VMID is
3289 * not referenced anymore.
3291 r = amdgpu_bo_reserve(fpriv->vm.root.base.bo, true);
3295 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3299 amdgpu_bo_unreserve(fpriv->vm.root.base.bo);
3300 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3310 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3312 * @adev: drm device pointer
3313 * @pasid: PASID identifier for VM
3314 * @task_info: task_info to fill.
3316 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3317 struct amdgpu_task_info *task_info)
3319 struct amdgpu_vm *vm;
3320 unsigned long flags;
3322 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3324 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3326 *task_info = vm->task_info;
3328 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3332 * amdgpu_vm_set_task_info - Sets VMs task info.
3334 * @vm: vm for which to set the info
3336 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3338 if (vm->task_info.pid)
3341 vm->task_info.pid = current->pid;
3342 get_task_comm(vm->task_info.task_name, current);
3344 if (current->group_leader->mm != current->mm)
3347 vm->task_info.tgid = current->group_leader->pid;
3348 get_task_comm(vm->task_info.process_name, current->group_leader);
3352 * amdgpu_vm_handle_fault - graceful handling of VM faults.
3353 * @adev: amdgpu device pointer
3354 * @pasid: PASID of the VM
3355 * @addr: Address of the fault
3357 * Try to gracefully handle a VM fault. Return true if the fault was handled and
3358 * shouldn't be reported any more.
3360 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3363 bool is_compute_context = false;
3364 struct amdgpu_bo *root;
3365 uint64_t value, flags;
3366 struct amdgpu_vm *vm;
3369 spin_lock(&adev->vm_manager.pasid_lock);
3370 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3372 root = amdgpu_bo_ref(vm->root.base.bo);
3373 is_compute_context = vm->is_compute_context;
3377 spin_unlock(&adev->vm_manager.pasid_lock);
3382 addr /= AMDGPU_GPU_PAGE_SIZE;
3384 if (is_compute_context &&
3385 !svm_range_restore_pages(adev, pasid, addr)) {
3386 amdgpu_bo_unref(&root);
3390 r = amdgpu_bo_reserve(root, true);
3394 /* Double check that the VM still exists */
3395 spin_lock(&adev->vm_manager.pasid_lock);
3396 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3397 if (vm && vm->root.base.bo != root)
3399 spin_unlock(&adev->vm_manager.pasid_lock);
3403 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3406 if (is_compute_context) {
3407 /* Intentionally setting invalid PTE flag
3408 * combination to force a no-retry-fault
3410 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3413 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3414 /* Redirect the access to the dummy page */
3415 value = adev->dummy_page_addr;
3416 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3417 AMDGPU_PTE_WRITEABLE;
3420 /* Let the hw retry silently on the PTE */
3424 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3426 pr_debug("failed %d to reserve fence slot\n", r);
3430 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3431 addr, flags, value, NULL, NULL,
3436 r = amdgpu_vm_update_pdes(adev, vm, true);
3439 amdgpu_bo_unreserve(root);
3441 DRM_ERROR("Can't handle page fault (%d)\n", r);
3444 amdgpu_bo_unref(&root);
3449 #if defined(CONFIG_DEBUG_FS)
3451 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
3453 * @vm: Requested VM for printing BO info
3456 * Print BO information in debugfs file for the VM
3458 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3460 struct amdgpu_bo_va *bo_va, *tmp;
3462 u64 total_evicted = 0;
3463 u64 total_relocated = 0;
3464 u64 total_moved = 0;
3465 u64 total_invalidated = 0;
3467 unsigned int total_idle_objs = 0;
3468 unsigned int total_evicted_objs = 0;
3469 unsigned int total_relocated_objs = 0;
3470 unsigned int total_moved_objs = 0;
3471 unsigned int total_invalidated_objs = 0;
3472 unsigned int total_done_objs = 0;
3473 unsigned int id = 0;
3475 seq_puts(m, "\tIdle BOs:\n");
3476 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3477 if (!bo_va->base.bo)
3479 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3481 total_idle_objs = id;
3484 seq_puts(m, "\tEvicted BOs:\n");
3485 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3486 if (!bo_va->base.bo)
3488 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3490 total_evicted_objs = id;
3493 seq_puts(m, "\tRelocated BOs:\n");
3494 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3495 if (!bo_va->base.bo)
3497 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3499 total_relocated_objs = id;
3502 seq_puts(m, "\tMoved BOs:\n");
3503 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3504 if (!bo_va->base.bo)
3506 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3508 total_moved_objs = id;
3511 seq_puts(m, "\tInvalidated BOs:\n");
3512 spin_lock(&vm->invalidated_lock);
3513 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3514 if (!bo_va->base.bo)
3516 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3518 total_invalidated_objs = id;
3521 seq_puts(m, "\tDone BOs:\n");
3522 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3523 if (!bo_va->base.bo)
3525 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3527 spin_unlock(&vm->invalidated_lock);
3528 total_done_objs = id;
3530 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3532 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3533 total_evicted_objs);
3534 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3535 total_relocated_objs);
3536 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3538 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3539 total_invalidated_objs);
3540 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,