drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38 #include <linux/pci.h>
  39 #include <linux/pm_runtime.h>
  40 #include "amdgpu_amdkfd.h"
  41 #include "amdgpu_gem.h"
  42 #include "amdgpu_display.h"
  43 #include "amdgpu_ras.h"
  44
  45 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  46 {
  47         struct amdgpu_gpu_instance *gpu_instance;
  48         int i;
  49
  50         mutex_lock(&mgpu_info.mutex);
  51
  52         for (i = 0; i < mgpu_info.num_gpu; i++) {
  53                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  54                 if (gpu_instance->adev == adev) {
  55                         mgpu_info.gpu_ins[i] =
  56                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  57                         mgpu_info.num_gpu--;
  58                         if (adev->flags & AMD_IS_APU)
  59                                 mgpu_info.num_apu--;
  60                         else
  61                                 mgpu_info.num_dgpu--;
  62                         break;
  63                 }
  64         }
  65
  66         mutex_unlock(&mgpu_info.mutex);
  67 }
  68
  69 /**
  70  * amdgpu_driver_unload_kms - Main unload function for KMS.
  71  *
  72  * @dev: drm dev pointer
  73  *
  74  * This is the main unload function for KMS (all asics).
  75  * Returns 0 on success.
  76  */
  77 void amdgpu_driver_unload_kms(struct drm_device *dev)
  78 {
  79         struct amdgpu_device *adev = drm_to_adev(dev);
  80
  81         if (adev == NULL)
  82                 return;
  83
  84         amdgpu_unregister_gpu_instance(adev);
  85
  86         if (adev->rmmio == NULL)
  87                 return;
  88
  89         if (adev->runpm) {
  90                 pm_runtime_get_sync(dev->dev);
  91                 pm_runtime_forbid(dev->dev);
  92         }
  93
  94         amdgpu_acpi_fini(adev);
  95         amdgpu_device_fini(adev);
  96 }
  97
  98 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
  99 {
 100         struct amdgpu_gpu_instance *gpu_instance;
 101
 102         mutex_lock(&mgpu_info.mutex);
 103
 104         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 105                 DRM_ERROR("Cannot register more gpu instance\n");
 106                 mutex_unlock(&mgpu_info.mutex);
 107                 return;
 108         }
 109
 110         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 111         gpu_instance->adev = adev;
 112         gpu_instance->mgpu_fan_enabled = 0;
 113
 114         mgpu_info.num_gpu++;
 115         if (adev->flags & AMD_IS_APU)
 116                 mgpu_info.num_apu++;
 117         else
 118                 mgpu_info.num_dgpu++;
 119
 120         mutex_unlock(&mgpu_info.mutex);
 121 }
 122
 123 /**
 124  * amdgpu_driver_load_kms - Main load function for KMS.
 125  *
 126  * @adev: pointer to struct amdgpu_device
 127  * @flags: device flags
 128  *
 129  * This is the main load function for KMS (all asics).
 130  * Returns 0 on success, error on failure.
 131  */
 132 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 133 {
 134         struct drm_device *dev;
 135         struct pci_dev *parent;
 136         int r, acpi_status;
 137
 138         dev = adev_to_drm(adev);
 139
 140         if (amdgpu_has_atpx() &&
 141             (amdgpu_is_atpx_hybrid() ||
 142              amdgpu_has_atpx_dgpu_power_cntl()) &&
 143             ((flags & AMD_IS_APU) == 0) &&
 144             !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
 145                 flags |= AMD_IS_PX;
 146
 147         parent = pci_upstream_bridge(adev->pdev);
 148         adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
 149
 150         /* amdgpu_device_init should report only fatal error
 151          * like memory allocation failure or iomapping failure,
 152          * or memory manager initialization failure, it must
 153          * properly initialize the GPU MC controller and permit
 154          * VRAM allocation
 155          */
 156         r = amdgpu_device_init(adev, flags);
 157         if (r) {
 158                 dev_err(dev->dev, "Fatal error during GPU init\n");
 159                 goto out;
 160         }
 161
 162         if (amdgpu_device_supports_px(dev) &&
 163             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
 164                 adev->runpm = true;
 165                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 166         } else if (amdgpu_device_supports_boco(dev) &&
 167                    (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 168                 adev->runpm = true;
 169                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 170         } else if (amdgpu_device_supports_baco(dev) &&
 171                    (amdgpu_runtime_pm != 0)) {
 172                 switch (adev->asic_type) {
 173                 case CHIP_VEGA20:
 174                 case CHIP_ARCTURUS:
 175                         /* enable runpm if runpm=1 */
 176                         if (amdgpu_runtime_pm > 0)
 177                                 adev->runpm = true;
 178                         break;
 179                 case CHIP_VEGA10:
 180                         /* turn runpm on if noretry=0 */
 181                         if (!adev->gmc.noretry)
 182                                 adev->runpm = true;
 183                         break;
 184                 default:
 185                         /* enable runpm on CI+ */
 186                         adev->runpm = true;
 187                         break;
 188                 }
 189                 if (adev->runpm)
 190                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 191         }
 192
 193         /* Call ACPI methods: require modeset init
 194          * but failure is not fatal
 195          */
 196
 197         acpi_status = amdgpu_acpi_init(adev);
 198         if (acpi_status)
 199                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 200
 201         if (adev->runpm) {
 202                 /* only need to skip on ATPX */
 203                 if (amdgpu_device_supports_px(dev))
 204                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 205                 /* we want direct complete for BOCO */
 206                 if (amdgpu_device_supports_boco(dev))
 207                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE |
 208                                                 DPM_FLAG_SMART_SUSPEND |
 209                                                 DPM_FLAG_MAY_SKIP_RESUME);
 210                 pm_runtime_use_autosuspend(dev->dev);
 211                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 212                 pm_runtime_allow(dev->dev);
 213                 pm_runtime_mark_last_busy(dev->dev);
 214                 pm_runtime_put_autosuspend(dev->dev);
 215         }
 216
 217 out:
 218         if (r) {
 219                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 220                 if (adev->rmmio && adev->runpm)
 221                         pm_runtime_put_noidle(dev->dev);
 222                 amdgpu_driver_unload_kms(dev);
 223         }
 224
 225         return r;
 226 }
 227
 228 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 229                                 struct drm_amdgpu_query_fw *query_fw,
 230                                 struct amdgpu_device *adev)
 231 {
 232         switch (query_fw->fw_type) {
 233         case AMDGPU_INFO_FW_VCE:
 234                 fw_info->ver = adev->vce.fw_version;
 235                 fw_info->feature = adev->vce.fb_version;
 236                 break;
 237         case AMDGPU_INFO_FW_UVD:
 238                 fw_info->ver = adev->uvd.fw_version;
 239                 fw_info->feature = 0;
 240                 break;
 241         case AMDGPU_INFO_FW_VCN:
 242                 fw_info->ver = adev->vcn.fw_version;
 243                 fw_info->feature = 0;
 244                 break;
 245         case AMDGPU_INFO_FW_GMC:
 246                 fw_info->ver = adev->gmc.fw_version;
 247                 fw_info->feature = 0;
 248                 break;
 249         case AMDGPU_INFO_FW_GFX_ME:
 250                 fw_info->ver = adev->gfx.me_fw_version;
 251                 fw_info->feature = adev->gfx.me_feature_version;
 252                 break;
 253         case AMDGPU_INFO_FW_GFX_PFP:
 254                 fw_info->ver = adev->gfx.pfp_fw_version;
 255                 fw_info->feature = adev->gfx.pfp_feature_version;
 256                 break;
 257         case AMDGPU_INFO_FW_GFX_CE:
 258                 fw_info->ver = adev->gfx.ce_fw_version;
 259                 fw_info->feature = adev->gfx.ce_feature_version;
 260                 break;
 261         case AMDGPU_INFO_FW_GFX_RLC:
 262                 fw_info->ver = adev->gfx.rlc_fw_version;
 263                 fw_info->feature = adev->gfx.rlc_feature_version;
 264                 break;
 265         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 266                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 267                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 268                 break;
 269         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 270                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 271                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 272                 break;
 273         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 274                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 275                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 276                 break;
 277         case AMDGPU_INFO_FW_GFX_MEC:
 278                 if (query_fw->index == 0) {
 279                         fw_info->ver = adev->gfx.mec_fw_version;
 280                         fw_info->feature = adev->gfx.mec_feature_version;
 281                 } else if (query_fw->index == 1) {
 282                         fw_info->ver = adev->gfx.mec2_fw_version;
 283                         fw_info->feature = adev->gfx.mec2_feature_version;
 284                 } else
 285                         return -EINVAL;
 286                 break;
 287         case AMDGPU_INFO_FW_SMC:
 288                 fw_info->ver = adev->pm.fw_version;
 289                 fw_info->feature = 0;
 290                 break;
 291         case AMDGPU_INFO_FW_TA:
 292                 switch (query_fw->index) {
 293                 case TA_FW_TYPE_PSP_XGMI:
 294                         fw_info->ver = adev->psp.ta_fw_version;
 295                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 296                         break;
 297                 case TA_FW_TYPE_PSP_RAS:
 298                         fw_info->ver = adev->psp.ta_fw_version;
 299                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 300                         break;
 301                 case TA_FW_TYPE_PSP_HDCP:
 302                         fw_info->ver = adev->psp.ta_fw_version;
 303                         fw_info->feature = adev->psp.ta_hdcp_ucode_version;
 304                         break;
 305                 case TA_FW_TYPE_PSP_DTM:
 306                         fw_info->ver = adev->psp.ta_fw_version;
 307                         fw_info->feature = adev->psp.ta_dtm_ucode_version;
 308                         break;
 309                 case TA_FW_TYPE_PSP_RAP:
 310                         fw_info->ver = adev->psp.ta_fw_version;
 311                         fw_info->feature = adev->psp.ta_rap_ucode_version;
 312                         break;
 313                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 314                         fw_info->ver = adev->psp.ta_fw_version;
 315                         fw_info->feature = adev->psp.ta_securedisplay_ucode_version;
 316                         break;
 317                 default:
 318                         return -EINVAL;
 319                 }
 320                 break;
 321         case AMDGPU_INFO_FW_SDMA:
 322                 if (query_fw->index >= adev->sdma.num_instances)
 323                         return -EINVAL;
 324                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 325                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 326                 break;
 327         case AMDGPU_INFO_FW_SOS:
 328                 fw_info->ver = adev->psp.sos_fw_version;
 329                 fw_info->feature = adev->psp.sos_feature_version;
 330                 break;
 331         case AMDGPU_INFO_FW_ASD:
 332                 fw_info->ver = adev->psp.asd_fw_version;
 333                 fw_info->feature = adev->psp.asd_feature_version;
 334                 break;
 335         case AMDGPU_INFO_FW_DMCU:
 336                 fw_info->ver = adev->dm.dmcu_fw_version;
 337                 fw_info->feature = 0;
 338                 break;
 339         case AMDGPU_INFO_FW_DMCUB:
 340                 fw_info->ver = adev->dm.dmcub_fw_version;
 341                 fw_info->feature = 0;
 342                 break;
 343         case AMDGPU_INFO_FW_TOC:
 344                 fw_info->ver = adev->psp.toc_fw_version;
 345                 fw_info->feature = adev->psp.toc_feature_version;
 346                 break;
 347         default:
 348                 return -EINVAL;
 349         }
 350         return 0;
 351 }
 352
 353 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 354                              struct drm_amdgpu_info *info,
 355                              struct drm_amdgpu_info_hw_ip *result)
 356 {
 357         uint32_t ib_start_alignment = 0;
 358         uint32_t ib_size_alignment = 0;
 359         enum amd_ip_block_type type;
 360         unsigned int num_rings = 0;
 361         unsigned int i, j;
 362
 363         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 364                 return -EINVAL;
 365
 366         switch (info->query_hw_ip.type) {
 367         case AMDGPU_HW_IP_GFX:
 368                 type = AMD_IP_BLOCK_TYPE_GFX;
 369                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 370                         if (adev->gfx.gfx_ring[i].sched.ready)
 371                                 ++num_rings;
 372                 ib_start_alignment = 32;
 373                 ib_size_alignment = 32;
 374                 break;
 375         case AMDGPU_HW_IP_COMPUTE:
 376                 type = AMD_IP_BLOCK_TYPE_GFX;
 377                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 378                         if (adev->gfx.compute_ring[i].sched.ready)
 379                                 ++num_rings;
 380                 ib_start_alignment = 32;
 381                 ib_size_alignment = 32;
 382                 break;
 383         case AMDGPU_HW_IP_DMA:
 384                 type = AMD_IP_BLOCK_TYPE_SDMA;
 385                 for (i = 0; i < adev->sdma.num_instances; i++)
 386                         if (adev->sdma.instance[i].ring.sched.ready)
 387                                 ++num_rings;
 388                 ib_start_alignment = 256;
 389                 ib_size_alignment = 4;
 390                 break;
 391         case AMDGPU_HW_IP_UVD:
 392                 type = AMD_IP_BLOCK_TYPE_UVD;
 393                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 394                         if (adev->uvd.harvest_config & (1 << i))
 395                                 continue;
 396
 397                         if (adev->uvd.inst[i].ring.sched.ready)
 398                                 ++num_rings;
 399                 }
 400                 ib_start_alignment = 64;
 401                 ib_size_alignment = 64;
 402                 break;
 403         case AMDGPU_HW_IP_VCE:
 404                 type = AMD_IP_BLOCK_TYPE_VCE;
 405                 for (i = 0; i < adev->vce.num_rings; i++)
 406                         if (adev->vce.ring[i].sched.ready)
 407                                 ++num_rings;
 408                 ib_start_alignment = 4;
 409                 ib_size_alignment = 1;
 410                 break;
 411         case AMDGPU_HW_IP_UVD_ENC:
 412                 type = AMD_IP_BLOCK_TYPE_UVD;
 413                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 414                         if (adev->uvd.harvest_config & (1 << i))
 415                                 continue;
 416
 417                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 418                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 419                                         ++num_rings;
 420                 }
 421                 ib_start_alignment = 64;
 422                 ib_size_alignment = 64;
 423                 break;
 424         case AMDGPU_HW_IP_VCN_DEC:
 425                 type = AMD_IP_BLOCK_TYPE_VCN;
 426                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 427                         if (adev->uvd.harvest_config & (1 << i))
 428                                 continue;
 429
 430                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 431                                 ++num_rings;
 432                 }
 433                 ib_start_alignment = 16;
 434                 ib_size_alignment = 16;
 435                 break;
 436         case AMDGPU_HW_IP_VCN_ENC:
 437                 type = AMD_IP_BLOCK_TYPE_VCN;
 438                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 439                         if (adev->uvd.harvest_config & (1 << i))
 440                                 continue;
 441
 442                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 443                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 444                                         ++num_rings;
 445                 }
 446                 ib_start_alignment = 64;
 447                 ib_size_alignment = 1;
 448                 break;
 449         case AMDGPU_HW_IP_VCN_JPEG:
 450                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 451                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 452
 453                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 454                         if (adev->jpeg.harvest_config & (1 << i))
 455                                 continue;
 456
 457                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 458                                 ++num_rings;
 459                 }
 460                 ib_start_alignment = 16;
 461                 ib_size_alignment = 16;
 462                 break;
 463         default:
 464                 return -EINVAL;
 465         }
 466
 467         for (i = 0; i < adev->num_ip_blocks; i++)
 468                 if (adev->ip_blocks[i].version->type == type &&
 469                     adev->ip_blocks[i].status.valid)
 470                         break;
 471
 472         if (i == adev->num_ip_blocks)
 473                 return 0;
 474
 475         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 476                         num_rings);
 477
 478         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 479         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 480         result->capabilities_flags = 0;
 481         result->available_rings = (1 << num_rings) - 1;
 482         result->ib_start_alignment = ib_start_alignment;
 483         result->ib_size_alignment = ib_size_alignment;
 484         return 0;
 485 }
 486
 487 /*
 488  * Userspace get information ioctl
 489  */
 490 /**
 491  * amdgpu_info_ioctl - answer a device specific request.
 492  *
 493  * @dev: drm device pointer
 494  * @data: request object
 495  * @filp: drm filp
 496  *
 497  * This function is used to pass device specific parameters to the userspace
 498  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 499  * etc. (all asics).
 500  * Returns 0 on success, -EINVAL on failure.
 501  */
 502 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 503 {
 504         struct amdgpu_device *adev = drm_to_adev(dev);
 505         struct drm_amdgpu_info *info = data;
 506         struct amdgpu_mode_info *minfo = &adev->mode_info;
 507         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 508         uint32_t size = info->return_size;
 509         struct drm_crtc *crtc;
 510         uint32_t ui32 = 0;
 511         uint64_t ui64 = 0;
 512         int i, found;
 513         int ui32_size = sizeof(ui32);
 514
 515         if (!info->return_size || !info->return_pointer)
 516                 return -EINVAL;
 517
 518         switch (info->query) {
 519         case AMDGPU_INFO_ACCEL_WORKING:
 520                 ui32 = adev->accel_working;
 521                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 522         case AMDGPU_INFO_CRTC_FROM_ID:
 523                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 524                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 525                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 526                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 527                                 ui32 = amdgpu_crtc->crtc_id;
 528                                 found = 1;
 529                                 break;
 530                         }
 531                 }
 532                 if (!found) {
 533                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 534                         return -EINVAL;
 535                 }
 536                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 537         case AMDGPU_INFO_HW_IP_INFO: {
 538                 struct drm_amdgpu_info_hw_ip ip = {};
 539                 int ret;
 540
 541                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 542                 if (ret)
 543                         return ret;
 544
 545                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 546                 return ret ? -EFAULT : 0;
 547         }
 548         case AMDGPU_INFO_HW_IP_COUNT: {
 549                 enum amd_ip_block_type type;
 550                 uint32_t count = 0;
 551
 552                 switch (info->query_hw_ip.type) {
 553                 case AMDGPU_HW_IP_GFX:
 554                         type = AMD_IP_BLOCK_TYPE_GFX;
 555                         break;
 556                 case AMDGPU_HW_IP_COMPUTE:
 557                         type = AMD_IP_BLOCK_TYPE_GFX;
 558                         break;
 559                 case AMDGPU_HW_IP_DMA:
 560                         type = AMD_IP_BLOCK_TYPE_SDMA;
 561                         break;
 562                 case AMDGPU_HW_IP_UVD:
 563                         type = AMD_IP_BLOCK_TYPE_UVD;
 564                         break;
 565                 case AMDGPU_HW_IP_VCE:
 566                         type = AMD_IP_BLOCK_TYPE_VCE;
 567                         break;
 568                 case AMDGPU_HW_IP_UVD_ENC:
 569                         type = AMD_IP_BLOCK_TYPE_UVD;
 570                         break;
 571                 case AMDGPU_HW_IP_VCN_DEC:
 572                 case AMDGPU_HW_IP_VCN_ENC:
 573                         type = AMD_IP_BLOCK_TYPE_VCN;
 574                         break;
 575                 case AMDGPU_HW_IP_VCN_JPEG:
 576                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 577                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 578                         break;
 579                 default:
 580                         return -EINVAL;
 581                 }
 582
 583                 for (i = 0; i < adev->num_ip_blocks; i++)
 584                         if (adev->ip_blocks[i].version->type == type &&
 585                             adev->ip_blocks[i].status.valid &&
 586                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 587                                 count++;
 588
 589                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 590         }
 591         case AMDGPU_INFO_TIMESTAMP:
 592                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 593                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 594         case AMDGPU_INFO_FW_VERSION: {
 595                 struct drm_amdgpu_info_firmware fw_info;
 596                 int ret;
 597
 598                 /* We only support one instance of each IP block right now. */
 599                 if (info->query_fw.ip_instance != 0)
 600                         return -EINVAL;
 601
 602                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 603                 if (ret)
 604                         return ret;
 605
 606                 return copy_to_user(out, &fw_info,
 607                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 608         }
 609         case AMDGPU_INFO_NUM_BYTES_MOVED:
 610                 ui64 = atomic64_read(&adev->num_bytes_moved);
 611                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 612         case AMDGPU_INFO_NUM_EVICTIONS:
 613                 ui64 = atomic64_read(&adev->num_evictions);
 614                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 615         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 616                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 617                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 618         case AMDGPU_INFO_VRAM_USAGE:
 619                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 620                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 621         case AMDGPU_INFO_VIS_VRAM_USAGE:
 622                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 623                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 624         case AMDGPU_INFO_GTT_USAGE:
 625                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 626                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 627         case AMDGPU_INFO_GDS_CONFIG: {
 628                 struct drm_amdgpu_info_gds gds_info;
 629
 630                 memset(&gds_info, 0, sizeof(gds_info));
 631                 gds_info.compute_partition_size = adev->gds.gds_size;
 632                 gds_info.gds_total_size = adev->gds.gds_size;
 633                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 634                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 635                 return copy_to_user(out, &gds_info,
 636                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 637         }
 638         case AMDGPU_INFO_VRAM_GTT: {
 639                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 640
 641                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 642                         atomic64_read(&adev->vram_pin_size) -
 643                         AMDGPU_VM_RESERVED_VRAM;
 644                 vram_gtt.vram_cpu_accessible_size =
 645                         min(adev->gmc.visible_vram_size -
 646                             atomic64_read(&adev->visible_pin_size),
 647                             vram_gtt.vram_size);
 648                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 649                 vram_gtt.gtt_size *= PAGE_SIZE;
 650                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 651                 return copy_to_user(out, &vram_gtt,
 652                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 653         }
 654         case AMDGPU_INFO_MEMORY: {
 655                 struct drm_amdgpu_memory_info mem;
 656                 struct ttm_resource_manager *vram_man =
 657                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 658                 struct ttm_resource_manager *gtt_man =
 659                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 660                 memset(&mem, 0, sizeof(mem));
 661                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 662                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 663                         atomic64_read(&adev->vram_pin_size) -
 664                         AMDGPU_VM_RESERVED_VRAM;
 665                 mem.vram.heap_usage =
 666                         amdgpu_vram_mgr_usage(vram_man);
 667                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 668
 669                 mem.cpu_accessible_vram.total_heap_size =
 670                         adev->gmc.visible_vram_size;
 671                 mem.cpu_accessible_vram.usable_heap_size =
 672                         min(adev->gmc.visible_vram_size -
 673                             atomic64_read(&adev->visible_pin_size),
 674                             mem.vram.usable_heap_size);
 675                 mem.cpu_accessible_vram.heap_usage =
 676                         amdgpu_vram_mgr_vis_usage(vram_man);
 677                 mem.cpu_accessible_vram.max_allocation =
 678                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 679
 680                 mem.gtt.total_heap_size = gtt_man->size;
 681                 mem.gtt.total_heap_size *= PAGE_SIZE;
 682                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 683                         atomic64_read(&adev->gart_pin_size);
 684                 mem.gtt.heap_usage =
 685                         amdgpu_gtt_mgr_usage(gtt_man);
 686                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 687
 688                 return copy_to_user(out, &mem,
 689                                     min((size_t)size, sizeof(mem)))
 690                                     ? -EFAULT : 0;
 691         }
 692         case AMDGPU_INFO_READ_MMR_REG: {
 693                 unsigned n, alloc_size;
 694                 uint32_t *regs;
 695                 unsigned se_num = (info->read_mmr_reg.instance >>
 696                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 697                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 698                 unsigned sh_num = (info->read_mmr_reg.instance >>
 699                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 700                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 701
 702                 /* set full masks if the userspace set all bits
 703                  * in the bitfields */
 704                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 705                         se_num = 0xffffffff;
 706                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 707                         return -EINVAL;
 708                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 709                         sh_num = 0xffffffff;
 710                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 711                         return -EINVAL;
 712
 713                 if (info->read_mmr_reg.count > 128)
 714                         return -EINVAL;
 715
 716                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 717                 if (!regs)
 718                         return -ENOMEM;
 719                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 720
 721                 amdgpu_gfx_off_ctrl(adev, false);
 722                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 723                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 724                                                       info->read_mmr_reg.dword_offset + i,
 725                                                       &regs[i])) {
 726                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 727                                               info->read_mmr_reg.dword_offset + i);
 728                                 kfree(regs);
 729                                 amdgpu_gfx_off_ctrl(adev, true);
 730                                 return -EFAULT;
 731                         }
 732                 }
 733                 amdgpu_gfx_off_ctrl(adev, true);
 734                 n = copy_to_user(out, regs, min(size, alloc_size));
 735                 kfree(regs);
 736                 return n ? -EFAULT : 0;
 737         }
 738         case AMDGPU_INFO_DEV_INFO: {
 739                 struct drm_amdgpu_info_device *dev_info;
 740                 uint64_t vm_size;
 741                 int ret;
 742
 743                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 744                 if (!dev_info)
 745                         return -ENOMEM;
 746
 747                 dev_info->device_id = adev->pdev->device;
 748                 dev_info->chip_rev = adev->rev_id;
 749                 dev_info->external_rev = adev->external_rev_id;
 750                 dev_info->pci_rev = adev->pdev->revision;
 751                 dev_info->family = adev->family;
 752                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 753                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 754                 /* return all clocks in KHz */
 755                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 756                 if (adev->pm.dpm_enabled) {
 757                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 758                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 759                 } else {
 760                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 761                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 762                 }
 763                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 764                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 765                         adev->gfx.config.max_shader_engines;
 766                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 767                 dev_info->_pad = 0;
 768                 dev_info->ids_flags = 0;
 769                 if (adev->flags & AMD_IS_APU)
 770                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 771                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 772                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 773                 if (amdgpu_is_tmz(adev))
 774                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 775
 776                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 777                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 778
 779                 /* Older VCE FW versions are buggy and can handle only 40bits */
 780                 if (adev->vce.fw_version &&
 781                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 782                         vm_size = min(vm_size, 1ULL << 40);
 783
 784                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 785                 dev_info->virtual_address_max =
 786                         min(vm_size, AMDGPU_GMC_HOLE_START);
 787
 788                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 789                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 790                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 791                 }
 792                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 793                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 794                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 795                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 796                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 797                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 798                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 799                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 800                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 801                        sizeof(adev->gfx.cu_info.bitmap));
 802                 dev_info->vram_type = adev->gmc.vram_type;
 803                 dev_info->vram_bit_width = adev->gmc.vram_width;
 804                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 805                 dev_info->gc_double_offchip_lds_buf =
 806                         adev->gfx.config.double_offchip_lds_buf;
 807                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 808                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 809                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 810                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 811                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 812                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 813                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 814
 815                 if (adev->family >= AMDGPU_FAMILY_NV)
 816                         dev_info->pa_sc_tile_steering_override =
 817                                 adev->gfx.config.pa_sc_tile_steering_override;
 818
 819                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 820
 821                 ret = copy_to_user(out, dev_info,
 822                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 823                 kfree(dev_info);
 824                 return ret;
 825         }
 826         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 827                 unsigned i;
 828                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 829                 struct amd_vce_state *vce_state;
 830
 831                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 832                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 833                         if (vce_state) {
 834                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 835                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 836                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 837                                 vce_clk_table.num_valid_entries++;
 838                         }
 839                 }
 840
 841                 return copy_to_user(out, &vce_clk_table,
 842                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 843         }
 844         case AMDGPU_INFO_VBIOS: {
 845                 uint32_t bios_size = adev->bios_size;
 846
 847                 switch (info->vbios_info.type) {
 848                 case AMDGPU_INFO_VBIOS_SIZE:
 849                         return copy_to_user(out, &bios_size,
 850                                         min((size_t)size, sizeof(bios_size)))
 851                                         ? -EFAULT : 0;
 852                 case AMDGPU_INFO_VBIOS_IMAGE: {
 853                         uint8_t *bios;
 854                         uint32_t bios_offset = info->vbios_info.offset;
 855
 856                         if (bios_offset >= bios_size)
 857                                 return -EINVAL;
 858
 859                         bios = adev->bios + bios_offset;
 860                         return copy_to_user(out, bios,
 861                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 862                                         ? -EFAULT : 0;
 863                 }
 864                 default:
 865                         DRM_DEBUG_KMS("Invalid request %d\n",
 866                                         info->vbios_info.type);
 867                         return -EINVAL;
 868                 }
 869         }
 870         case AMDGPU_INFO_NUM_HANDLES: {
 871                 struct drm_amdgpu_info_num_handles handle;
 872
 873                 switch (info->query_hw_ip.type) {
 874                 case AMDGPU_HW_IP_UVD:
 875                         /* Starting Polaris, we support unlimited UVD handles */
 876                         if (adev->asic_type < CHIP_POLARIS10) {
 877                                 handle.uvd_max_handles = adev->uvd.max_handles;
 878                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 879
 880                                 return copy_to_user(out, &handle,
 881                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 882                         } else {
 883                                 return -ENODATA;
 884                         }
 885
 886                         break;
 887                 default:
 888                         return -EINVAL;
 889                 }
 890         }
 891         case AMDGPU_INFO_SENSOR: {
 892                 if (!adev->pm.dpm_enabled)
 893                         return -ENOENT;
 894
 895                 switch (info->sensor_info.type) {
 896                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 897                         /* get sclk in Mhz */
 898                         if (amdgpu_dpm_read_sensor(adev,
 899                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 900                                                    (void *)&ui32, &ui32_size)) {
 901                                 return -EINVAL;
 902                         }
 903                         ui32 /= 100;
 904                         break;
 905                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 906                         /* get mclk in Mhz */
 907                         if (amdgpu_dpm_read_sensor(adev,
 908                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 909                                                    (void *)&ui32, &ui32_size)) {
 910                                 return -EINVAL;
 911                         }
 912                         ui32 /= 100;
 913                         break;
 914                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 915                         /* get temperature in millidegrees C */
 916                         if (amdgpu_dpm_read_sensor(adev,
 917                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 918                                                    (void *)&ui32, &ui32_size)) {
 919                                 return -EINVAL;
 920                         }
 921                         break;
 922                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 923                         /* get GPU load */
 924                         if (amdgpu_dpm_read_sensor(adev,
 925                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 926                                                    (void *)&ui32, &ui32_size)) {
 927                                 return -EINVAL;
 928                         }
 929                         break;
 930                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 931                         /* get average GPU power */
 932                         if (amdgpu_dpm_read_sensor(adev,
 933                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 934                                                    (void *)&ui32, &ui32_size)) {
 935                                 return -EINVAL;
 936                         }
 937                         ui32 >>= 8;
 938                         break;
 939                 case AMDGPU_INFO_SENSOR_VDDNB:
 940                         /* get VDDNB in millivolts */
 941                         if (amdgpu_dpm_read_sensor(adev,
 942                                                    AMDGPU_PP_SENSOR_VDDNB,
 943                                                    (void *)&ui32, &ui32_size)) {
 944                                 return -EINVAL;
 945                         }
 946                         break;
 947                 case AMDGPU_INFO_SENSOR_VDDGFX:
 948                         /* get VDDGFX in millivolts */
 949                         if (amdgpu_dpm_read_sensor(adev,
 950                                                    AMDGPU_PP_SENSOR_VDDGFX,
 951                                                    (void *)&ui32, &ui32_size)) {
 952                                 return -EINVAL;
 953                         }
 954                         break;
 955                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 956                         /* get stable pstate sclk in Mhz */
 957                         if (amdgpu_dpm_read_sensor(adev,
 958                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 959                                                    (void *)&ui32, &ui32_size)) {
 960                                 return -EINVAL;
 961                         }
 962                         ui32 /= 100;
 963                         break;
 964                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 965                         /* get stable pstate mclk in Mhz */
 966                         if (amdgpu_dpm_read_sensor(adev,
 967                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 968                                                    (void *)&ui32, &ui32_size)) {
 969                                 return -EINVAL;
 970                         }
 971                         ui32 /= 100;
 972                         break;
 973                 default:
 974                         DRM_DEBUG_KMS("Invalid request %d\n",
 975                                       info->sensor_info.type);
 976                         return -EINVAL;
 977                 }
 978                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 979         }
 980         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 981                 ui32 = atomic_read(&adev->vram_lost_counter);
 982                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 983         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 984                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 985                 uint64_t ras_mask;
 986
 987                 if (!ras)
 988                         return -EINVAL;
 989                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
 990
 991                 return copy_to_user(out, &ras_mask,
 992                                 min_t(u64, size, sizeof(ras_mask))) ?
 993                         -EFAULT : 0;
 994         }
 995         case AMDGPU_INFO_VIDEO_CAPS: {
 996                 const struct amdgpu_video_codecs *codecs;
 997                 struct drm_amdgpu_info_video_caps *caps;
 998                 int r;
 999
1000                 switch (info->video_cap.type) {
1001                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1002                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1003                         if (r)
1004                                 return -EINVAL;
1005                         break;
1006                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1007                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1008                         if (r)
1009                                 return -EINVAL;
1010                         break;
1011                 default:
1012                         DRM_DEBUG_KMS("Invalid request %d\n",
1013                                       info->video_cap.type);
1014                         return -EINVAL;
1015                 }
1016
1017                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1018                 if (!caps)
1019                         return -ENOMEM;
1020
1021                 for (i = 0; i < codecs->codec_count; i++) {
1022                         int idx = codecs->codec_array[i].codec_type;
1023
1024                         switch (idx) {
1025                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1026                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1027                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1028                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1029                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1030                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1031                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1032                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1033                                 caps->codec_info[idx].valid = 1;
1034                                 caps->codec_info[idx].max_width =
1035                                         codecs->codec_array[i].max_width;
1036                                 caps->codec_info[idx].max_height =
1037                                         codecs->codec_array[i].max_height;
1038                                 caps->codec_info[idx].max_pixels_per_frame =
1039                                         codecs->codec_array[i].max_pixels_per_frame;
1040                                 caps->codec_info[idx].max_level =
1041                                         codecs->codec_array[i].max_level;
1042                                 break;
1043                         default:
1044                                 break;
1045                         }
1046                 }
1047                 r = copy_to_user(out, caps,
1048                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1049                 kfree(caps);
1050                 return r;
1051         }
1052         default:
1053                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1054                 return -EINVAL;
1055         }
1056         return 0;
1057 }
1058
1059
1060 /*
1061  * Outdated mess for old drm with Xorg being in charge (void function now).
1062  */
1063 /**
1064  * amdgpu_driver_lastclose_kms - drm callback for last close
1065  *
1066  * @dev: drm dev pointer
1067  *
1068  * Switch vga_switcheroo state after last close (all asics).
1069  */
1070 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1071 {
1072         drm_fb_helper_lastclose(dev);
1073         vga_switcheroo_process_delayed_switch();
1074 }
1075
1076 /**
1077  * amdgpu_driver_open_kms - drm callback for open
1078  *
1079  * @dev: drm dev pointer
1080  * @file_priv: drm file
1081  *
1082  * On device open, init vm on cayman+ (all asics).
1083  * Returns 0 on success, error on failure.
1084  */
1085 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1086 {
1087         struct amdgpu_device *adev = drm_to_adev(dev);
1088         struct amdgpu_fpriv *fpriv;
1089         int r, pasid;
1090
1091         /* Ensure IB tests are run on ring */
1092         flush_delayed_work(&adev->delayed_init_work);
1093
1094
1095         if (amdgpu_ras_intr_triggered()) {
1096                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1097                 return -EHWPOISON;
1098         }
1099
1100         file_priv->driver_priv = NULL;
1101
1102         r = pm_runtime_get_sync(dev->dev);
1103         if (r < 0)
1104                 goto pm_put;
1105
1106         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1107         if (unlikely(!fpriv)) {
1108                 r = -ENOMEM;
1109                 goto out_suspend;
1110         }
1111
1112         pasid = amdgpu_pasid_alloc(16);
1113         if (pasid < 0) {
1114                 dev_warn(adev->dev, "No more PASIDs available!");
1115                 pasid = 0;
1116         }
1117
1118         r = amdgpu_vm_init(adev, &fpriv->vm, pasid);
1119         if (r)
1120                 goto error_pasid;
1121
1122         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1123         if (!fpriv->prt_va) {
1124                 r = -ENOMEM;
1125                 goto error_vm;
1126         }
1127
1128         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1129                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1130
1131                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1132                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1133                 if (r)
1134                         goto error_vm;
1135         }
1136
1137         mutex_init(&fpriv->bo_list_lock);
1138         idr_init(&fpriv->bo_list_handles);
1139
1140         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1141
1142         file_priv->driver_priv = fpriv;
1143         goto out_suspend;
1144
1145 error_vm:
1146         amdgpu_vm_fini(adev, &fpriv->vm);
1147
1148 error_pasid:
1149         if (pasid)
1150                 amdgpu_pasid_free(pasid);
1151
1152         kfree(fpriv);
1153
1154 out_suspend:
1155         pm_runtime_mark_last_busy(dev->dev);
1156 pm_put:
1157         pm_runtime_put_autosuspend(dev->dev);
1158
1159         return r;
1160 }
1161
1162 /**
1163  * amdgpu_driver_postclose_kms - drm callback for post close
1164  *
1165  * @dev: drm dev pointer
1166  * @file_priv: drm file
1167  *
1168  * On device post close, tear down vm on cayman+ (all asics).
1169  */
1170 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1171                                  struct drm_file *file_priv)
1172 {
1173         struct amdgpu_device *adev = drm_to_adev(dev);
1174         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1175         struct amdgpu_bo_list *list;
1176         struct amdgpu_bo *pd;
1177         u32 pasid;
1178         int handle;
1179
1180         if (!fpriv)
1181                 return;
1182
1183         pm_runtime_get_sync(dev->dev);
1184
1185         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1186                 amdgpu_uvd_free_handles(adev, file_priv);
1187         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1188                 amdgpu_vce_free_handles(adev, file_priv);
1189
1190         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1191
1192         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1193                 /* TODO: how to handle reserve failure */
1194                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1195                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1196                 fpriv->csa_va = NULL;
1197                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1198         }
1199
1200         pasid = fpriv->vm.pasid;
1201         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1202
1203         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1204         amdgpu_vm_fini(adev, &fpriv->vm);
1205
1206         if (pasid)
1207                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1208         amdgpu_bo_unref(&pd);
1209
1210         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1211                 amdgpu_bo_list_put(list);
1212
1213         idr_destroy(&fpriv->bo_list_handles);
1214         mutex_destroy(&fpriv->bo_list_lock);
1215
1216         kfree(fpriv);
1217         file_priv->driver_priv = NULL;
1218
1219         pm_runtime_mark_last_busy(dev->dev);
1220         pm_runtime_put_autosuspend(dev->dev);
1221 }
1222
1223 /*
1224  * VBlank related functions.
1225  */
1226 /**
1227  * amdgpu_get_vblank_counter_kms - get frame count
1228  *
1229  * @crtc: crtc to get the frame count from
1230  *
1231  * Gets the frame count on the requested crtc (all asics).
1232  * Returns frame count on success, -EINVAL on failure.
1233  */
1234 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1235 {
1236         struct drm_device *dev = crtc->dev;
1237         unsigned int pipe = crtc->index;
1238         struct amdgpu_device *adev = drm_to_adev(dev);
1239         int vpos, hpos, stat;
1240         u32 count;
1241
1242         if (pipe >= adev->mode_info.num_crtc) {
1243                 DRM_ERROR("Invalid crtc %u\n", pipe);
1244                 return -EINVAL;
1245         }
1246
1247         /* The hw increments its frame counter at start of vsync, not at start
1248          * of vblank, as is required by DRM core vblank counter handling.
1249          * Cook the hw count here to make it appear to the caller as if it
1250          * incremented at start of vblank. We measure distance to start of
1251          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1252          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1253          * result by 1 to give the proper appearance to caller.
1254          */
1255         if (adev->mode_info.crtcs[pipe]) {
1256                 /* Repeat readout if needed to provide stable result if
1257                  * we cross start of vsync during the queries.
1258                  */
1259                 do {
1260                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1261                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1262                          * vpos as distance to start of vblank, instead of
1263                          * regular vertical scanout pos.
1264                          */
1265                         stat = amdgpu_display_get_crtc_scanoutpos(
1266                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1267                                 &vpos, &hpos, NULL, NULL,
1268                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1269                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1270
1271                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1272                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1273                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1274                 } else {
1275                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1276                                       pipe, vpos);
1277
1278                         /* Bump counter if we are at >= leading edge of vblank,
1279                          * but before vsync where vpos would turn negative and
1280                          * the hw counter really increments.
1281                          */
1282                         if (vpos >= 0)
1283                                 count++;
1284                 }
1285         } else {
1286                 /* Fallback to use value as is. */
1287                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1288                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1289         }
1290
1291         return count;
1292 }
1293
1294 /**
1295  * amdgpu_enable_vblank_kms - enable vblank interrupt
1296  *
1297  * @crtc: crtc to enable vblank interrupt for
1298  *
1299  * Enable the interrupt on the requested crtc (all asics).
1300  * Returns 0 on success, -EINVAL on failure.
1301  */
1302 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1303 {
1304         struct drm_device *dev = crtc->dev;
1305         unsigned int pipe = crtc->index;
1306         struct amdgpu_device *adev = drm_to_adev(dev);
1307         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1308
1309         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1310 }
1311
1312 /**
1313  * amdgpu_disable_vblank_kms - disable vblank interrupt
1314  *
1315  * @crtc: crtc to disable vblank interrupt for
1316  *
1317  * Disable the interrupt on the requested crtc (all asics).
1318  */
1319 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1320 {
1321         struct drm_device *dev = crtc->dev;
1322         unsigned int pipe = crtc->index;
1323         struct amdgpu_device *adev = drm_to_adev(dev);
1324         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1325
1326         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1327 }
1328
1329 /*
1330  * Debugfs info
1331  */
1332 #if defined(CONFIG_DEBUG_FS)
1333
1334 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1335 {
1336         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1337         struct drm_amdgpu_info_firmware fw_info;
1338         struct drm_amdgpu_query_fw query_fw;
1339         struct atom_context *ctx = adev->mode_info.atom_context;
1340         int ret, i;
1341
1342         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1343 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1344                 TA_FW_NAME(XGMI),
1345                 TA_FW_NAME(RAS),
1346                 TA_FW_NAME(HDCP),
1347                 TA_FW_NAME(DTM),
1348                 TA_FW_NAME(RAP),
1349                 TA_FW_NAME(SECUREDISPLAY),
1350 #undef TA_FW_NAME
1351         };
1352
1353         /* VCE */
1354         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1355         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1356         if (ret)
1357                 return ret;
1358         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1359                    fw_info.feature, fw_info.ver);
1360
1361         /* UVD */
1362         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1363         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1364         if (ret)
1365                 return ret;
1366         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1367                    fw_info.feature, fw_info.ver);
1368
1369         /* GMC */
1370         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1371         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1372         if (ret)
1373                 return ret;
1374         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1375                    fw_info.feature, fw_info.ver);
1376
1377         /* ME */
1378         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1379         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1380         if (ret)
1381                 return ret;
1382         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1383                    fw_info.feature, fw_info.ver);
1384
1385         /* PFP */
1386         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1387         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1388         if (ret)
1389                 return ret;
1390         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1391                    fw_info.feature, fw_info.ver);
1392
1393         /* CE */
1394         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1395         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1396         if (ret)
1397                 return ret;
1398         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1399                    fw_info.feature, fw_info.ver);
1400
1401         /* RLC */
1402         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1403         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1404         if (ret)
1405                 return ret;
1406         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1407                    fw_info.feature, fw_info.ver);
1408
1409         /* RLC SAVE RESTORE LIST CNTL */
1410         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1411         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1412         if (ret)
1413                 return ret;
1414         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1415                    fw_info.feature, fw_info.ver);
1416
1417         /* RLC SAVE RESTORE LIST GPM MEM */
1418         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1419         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1420         if (ret)
1421                 return ret;
1422         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1423                    fw_info.feature, fw_info.ver);
1424
1425         /* RLC SAVE RESTORE LIST SRM MEM */
1426         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1427         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1428         if (ret)
1429                 return ret;
1430         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1431                    fw_info.feature, fw_info.ver);
1432
1433         /* MEC */
1434         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1435         query_fw.index = 0;
1436         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1437         if (ret)
1438                 return ret;
1439         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1440                    fw_info.feature, fw_info.ver);
1441
1442         /* MEC2 */
1443         if (adev->gfx.mec2_fw) {
1444                 query_fw.index = 1;
1445                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1446                 if (ret)
1447                         return ret;
1448                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1449                            fw_info.feature, fw_info.ver);
1450         }
1451
1452         /* PSP SOS */
1453         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1454         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1455         if (ret)
1456                 return ret;
1457         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1458                    fw_info.feature, fw_info.ver);
1459
1460
1461         /* PSP ASD */
1462         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1463         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1464         if (ret)
1465                 return ret;
1466         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1467                    fw_info.feature, fw_info.ver);
1468
1469         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1470         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1471                 query_fw.index = i;
1472                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1473                 if (ret)
1474                         continue;
1475
1476                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1477                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1478         }
1479
1480         /* SMC */
1481         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1482         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1483         if (ret)
1484                 return ret;
1485         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1486                    fw_info.feature, fw_info.ver);
1487
1488         /* SDMA */
1489         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1490         for (i = 0; i < adev->sdma.num_instances; i++) {
1491                 query_fw.index = i;
1492                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1493                 if (ret)
1494                         return ret;
1495                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1496                            i, fw_info.feature, fw_info.ver);
1497         }
1498
1499         /* VCN */
1500         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1501         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1502         if (ret)
1503                 return ret;
1504         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1505                    fw_info.feature, fw_info.ver);
1506
1507         /* DMCU */
1508         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1509         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1510         if (ret)
1511                 return ret;
1512         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1513                    fw_info.feature, fw_info.ver);
1514
1515         /* DMCUB */
1516         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1517         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1518         if (ret)
1519                 return ret;
1520         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1521                    fw_info.feature, fw_info.ver);
1522
1523         /* TOC */
1524         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1525         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1526         if (ret)
1527                 return ret;
1528         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1529                    fw_info.feature, fw_info.ver);
1530
1531         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1532
1533         return 0;
1534 }
1535
1536 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1537
1538 #endif
1539
1540 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1541 {
1542 #if defined(CONFIG_DEBUG_FS)
1543         struct drm_minor *minor = adev_to_drm(adev)->primary;
1544         struct dentry *root = minor->debugfs_root;
1545
1546         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1547                             adev, &amdgpu_debugfs_firmware_info_fops);
1548
1549 #endif
1550 }