2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
56 #include "amdgpu_vf_error.h"
58 #include "amdgpu_amdkfd.h"
59 #include "amdgpu_pm.h"
61 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
62 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
64 #define AMDGPU_RESUME_MS 2000
66 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
67 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
68 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
69 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev);
71 static const char *amdgpu_asic_name[] = {
95 bool amdgpu_device_is_px(struct drm_device *dev)
97 struct amdgpu_device *adev = dev->dev_private;
99 if (adev->flags & AMD_IS_PX)
105 * MMIO register access helper functions.
107 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
112 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
113 BUG_ON(in_interrupt());
114 return amdgpu_virt_kiq_rreg(adev, reg);
117 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
118 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
122 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
123 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
124 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
125 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
127 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
131 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
134 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
136 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
137 adev->last_mm_index = v;
140 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
141 BUG_ON(in_interrupt());
142 return amdgpu_virt_kiq_wreg(adev, reg, v);
145 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
146 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
150 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
151 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
152 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
153 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
156 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
161 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
163 if ((reg * 4) < adev->rio_mem_size)
164 return ioread32(adev->rio_mem + (reg * 4));
166 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
167 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
171 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
173 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
174 adev->last_mm_index = v;
177 if ((reg * 4) < adev->rio_mem_size)
178 iowrite32(v, adev->rio_mem + (reg * 4));
180 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
181 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
184 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
190 * amdgpu_mm_rdoorbell - read a doorbell dword
192 * @adev: amdgpu_device pointer
193 * @index: doorbell index
195 * Returns the value in the doorbell aperture at the
196 * requested doorbell index (CIK).
198 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
200 if (index < adev->doorbell.num_doorbells) {
201 return readl(adev->doorbell.ptr + index);
203 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
209 * amdgpu_mm_wdoorbell - write a doorbell dword
211 * @adev: amdgpu_device pointer
212 * @index: doorbell index
215 * Writes @v to the doorbell aperture at the
216 * requested doorbell index (CIK).
218 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
220 if (index < adev->doorbell.num_doorbells) {
221 writel(v, adev->doorbell.ptr + index);
223 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
228 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
230 * @adev: amdgpu_device pointer
231 * @index: doorbell index
233 * Returns the value in the doorbell aperture at the
234 * requested doorbell index (VEGA10+).
236 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
238 if (index < adev->doorbell.num_doorbells) {
239 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
241 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
247 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
249 * @adev: amdgpu_device pointer
250 * @index: doorbell index
253 * Writes @v to the doorbell aperture at the
254 * requested doorbell index (VEGA10+).
256 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
258 if (index < adev->doorbell.num_doorbells) {
259 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
261 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
266 * amdgpu_invalid_rreg - dummy reg read function
268 * @adev: amdgpu device pointer
269 * @reg: offset of register
271 * Dummy register read function. Used for register blocks
272 * that certain asics don't have (all asics).
273 * Returns the value in the register.
275 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
277 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
283 * amdgpu_invalid_wreg - dummy reg write function
285 * @adev: amdgpu device pointer
286 * @reg: offset of register
287 * @v: value to write to the register
289 * Dummy register read function. Used for register blocks
290 * that certain asics don't have (all asics).
292 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
294 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
300 * amdgpu_block_invalid_rreg - dummy reg read function
302 * @adev: amdgpu device pointer
303 * @block: offset of instance
304 * @reg: offset of register
306 * Dummy register read function. Used for register blocks
307 * that certain asics don't have (all asics).
308 * Returns the value in the register.
310 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
311 uint32_t block, uint32_t reg)
313 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
320 * amdgpu_block_invalid_wreg - dummy reg write function
322 * @adev: amdgpu device pointer
323 * @block: offset of instance
324 * @reg: offset of register
325 * @v: value to write to the register
327 * Dummy register read function. Used for register blocks
328 * that certain asics don't have (all asics).
330 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
332 uint32_t reg, uint32_t v)
334 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
339 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
341 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
342 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
343 &adev->vram_scratch.robj,
344 &adev->vram_scratch.gpu_addr,
345 (void **)&adev->vram_scratch.ptr);
348 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
350 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
354 * amdgpu_program_register_sequence - program an array of registers.
356 * @adev: amdgpu_device pointer
357 * @registers: pointer to the register array
358 * @array_size: size of the register array
360 * Programs an array or registers with and and or masks.
361 * This is a helper for setting golden registers.
363 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
364 const u32 *registers,
365 const u32 array_size)
367 u32 tmp, reg, and_mask, or_mask;
373 for (i = 0; i < array_size; i +=3) {
374 reg = registers[i + 0];
375 and_mask = registers[i + 1];
376 or_mask = registers[i + 2];
378 if (and_mask == 0xffffffff) {
389 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
391 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
395 * GPU doorbell aperture helpers function.
398 * amdgpu_doorbell_init - Init doorbell driver information.
400 * @adev: amdgpu_device pointer
402 * Init doorbell driver information (CIK)
403 * Returns 0 on success, error on failure.
405 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
407 /* No doorbell on SI hardware generation */
408 if (adev->asic_type < CHIP_BONAIRE) {
409 adev->doorbell.base = 0;
410 adev->doorbell.size = 0;
411 adev->doorbell.num_doorbells = 0;
412 adev->doorbell.ptr = NULL;
416 /* doorbell bar mapping */
417 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
418 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
420 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
421 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
422 if (adev->doorbell.num_doorbells == 0)
425 adev->doorbell.ptr = ioremap(adev->doorbell.base,
426 adev->doorbell.num_doorbells *
428 if (adev->doorbell.ptr == NULL)
435 * amdgpu_doorbell_fini - Tear down doorbell driver information.
437 * @adev: amdgpu_device pointer
439 * Tear down doorbell driver information (CIK)
441 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
443 iounmap(adev->doorbell.ptr);
444 adev->doorbell.ptr = NULL;
448 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
451 * @adev: amdgpu_device pointer
452 * @aperture_base: output returning doorbell aperture base physical address
453 * @aperture_size: output returning doorbell aperture size in bytes
454 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
456 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
457 * takes doorbells required for its own rings and reports the setup to amdkfd.
458 * amdgpu reserved doorbells are at the start of the doorbell aperture.
460 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
461 phys_addr_t *aperture_base,
462 size_t *aperture_size,
463 size_t *start_offset)
466 * The first num_doorbells are used by amdgpu.
467 * amdkfd takes whatever's left in the aperture.
469 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
470 *aperture_base = adev->doorbell.base;
471 *aperture_size = adev->doorbell.size;
472 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
482 * Writeback is the method by which the GPU updates special pages in memory
483 * with the status of certain GPU events (fences, ring pointers,etc.).
487 * amdgpu_wb_fini - Disable Writeback and free memory
489 * @adev: amdgpu_device pointer
491 * Disables Writeback and frees the Writeback memory (all asics).
492 * Used at driver shutdown.
494 static void amdgpu_wb_fini(struct amdgpu_device *adev)
496 if (adev->wb.wb_obj) {
497 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
499 (void **)&adev->wb.wb);
500 adev->wb.wb_obj = NULL;
505 * amdgpu_wb_init- Init Writeback driver info and allocate memory
507 * @adev: amdgpu_device pointer
509 * Initializes writeback and allocates writeback memory (all asics).
510 * Used at driver startup.
511 * Returns 0 on success or an -error on failure.
513 static int amdgpu_wb_init(struct amdgpu_device *adev)
517 if (adev->wb.wb_obj == NULL) {
518 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
519 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
520 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
521 &adev->wb.wb_obj, &adev->wb.gpu_addr,
522 (void **)&adev->wb.wb);
524 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
528 adev->wb.num_wb = AMDGPU_MAX_WB;
529 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
531 /* clear wb memory */
532 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
539 * amdgpu_wb_get - Allocate a wb entry
541 * @adev: amdgpu_device pointer
544 * Allocate a wb slot for use by the driver (all asics).
545 * Returns 0 on success or -EINVAL on failure.
547 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
549 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
551 if (offset < adev->wb.num_wb) {
552 __set_bit(offset, adev->wb.used);
553 *wb = offset * 8; /* convert to dw offset */
561 * amdgpu_wb_free - Free a wb entry
563 * @adev: amdgpu_device pointer
566 * Free a wb slot allocated for use by the driver (all asics)
568 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
570 if (wb < adev->wb.num_wb)
571 __clear_bit(wb, adev->wb.used);
575 * amdgpu_vram_location - try to find VRAM location
576 * @adev: amdgpu device structure holding all necessary informations
577 * @mc: memory controller structure holding memory informations
578 * @base: base address at which to put VRAM
580 * Function will try to place VRAM at base address provided
581 * as parameter (which is so far either PCI aperture address or
582 * for IGP TOM base address).
584 * If there is not enough space to fit the unvisible VRAM in the 32bits
585 * address space then we limit the VRAM size to the aperture.
587 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
588 * this shouldn't be a problem as we are using the PCI aperture as a reference.
589 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
592 * Note: we use mc_vram_size as on some board we need to program the mc to
593 * cover the whole aperture even if VRAM size is inferior to aperture size
594 * Novell bug 204882 + along with lots of ubuntu ones
596 * Note: when limiting vram it's safe to overwritte real_vram_size because
597 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
598 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
601 * Note: IGP TOM addr should be the same as the aperture addr, we don't
602 * explicitly check for that though.
604 * FIXME: when reducing VRAM size align new size on power of 2.
606 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
608 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
610 mc->vram_start = base;
611 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
612 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
613 mc->real_vram_size = mc->aper_size;
614 mc->mc_vram_size = mc->aper_size;
616 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
617 if (limit && limit < mc->real_vram_size)
618 mc->real_vram_size = limit;
619 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
620 mc->mc_vram_size >> 20, mc->vram_start,
621 mc->vram_end, mc->real_vram_size >> 20);
625 * amdgpu_gart_location - try to find GTT location
626 * @adev: amdgpu device structure holding all necessary informations
627 * @mc: memory controller structure holding memory informations
629 * Function will place try to place GTT before or after VRAM.
631 * If GTT size is bigger than space left then we ajust GTT size.
632 * Thus function will never fails.
634 * FIXME: when reducing GTT size align new size on power of 2.
636 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
638 u64 size_af, size_bf;
640 size_af = adev->mc.mc_mask - mc->vram_end;
641 size_bf = mc->vram_start;
642 if (size_bf > size_af) {
643 if (mc->gart_size > size_bf) {
644 dev_warn(adev->dev, "limiting GTT\n");
645 mc->gart_size = size_bf;
649 if (mc->gart_size > size_af) {
650 dev_warn(adev->dev, "limiting GTT\n");
651 mc->gart_size = size_af;
653 mc->gart_start = mc->vram_end + 1;
655 mc->gart_end = mc->gart_start + mc->gart_size - 1;
656 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
657 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
661 * Firmware Reservation functions
664 * amdgpu_fw_reserve_vram_fini - free fw reserved vram
666 * @adev: amdgpu_device pointer
668 * free fw reserved vram if it has been reserved.
670 void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
672 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
673 NULL, &adev->fw_vram_usage.va);
677 * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
679 * @adev: amdgpu_device pointer
681 * create bo vram reservation from fw.
683 int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
687 u64 vram_size = adev->mc.visible_vram_size;
689 adev->fw_vram_usage.va = NULL;
690 adev->fw_vram_usage.reserved_bo = NULL;
692 if (adev->fw_vram_usage.size > 0 &&
693 adev->fw_vram_usage.size <= vram_size) {
695 r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
697 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
698 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
699 &adev->fw_vram_usage.reserved_bo);
703 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
706 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
707 AMDGPU_GEM_DOMAIN_VRAM,
708 adev->fw_vram_usage.start_offset,
709 (adev->fw_vram_usage.start_offset +
710 adev->fw_vram_usage.size), &gpu_addr);
713 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
714 &adev->fw_vram_usage.va);
718 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
723 amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
725 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
727 amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
729 adev->fw_vram_usage.va = NULL;
730 adev->fw_vram_usage.reserved_bo = NULL;
736 * GPU helpers function.
739 * amdgpu_need_post - check if the hw need post or not
741 * @adev: amdgpu_device pointer
743 * Check if the asic has been initialized (all asics) at driver startup
744 * or post is needed if hw reset is performed.
745 * Returns true if need or false if not.
747 bool amdgpu_need_post(struct amdgpu_device *adev)
751 if (adev->has_hw_reset) {
752 adev->has_hw_reset = false;
756 /* bios scratch used on CIK+ */
757 if (adev->asic_type >= CHIP_BONAIRE)
758 return amdgpu_atombios_scratch_need_asic_init(adev);
760 /* check MEM_SIZE for older asics */
761 reg = amdgpu_asic_get_config_memsize(adev);
763 if ((reg != 0) && (reg != 0xffffffff))
770 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
772 if (amdgpu_sriov_vf(adev))
775 if (amdgpu_passthrough(adev)) {
776 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
777 * some old smc fw still need driver do vPost otherwise gpu hang, while
778 * those smc fw version above 22.15 doesn't have this flaw, so we force
779 * vpost executed for smc version below 22.15
781 if (adev->asic_type == CHIP_FIJI) {
784 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
785 /* force vPost if error occured */
789 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
790 if (fw_ver < 0x00160e00)
794 return amdgpu_need_post(adev);
798 * amdgpu_dummy_page_init - init dummy page used by the driver
800 * @adev: amdgpu_device pointer
802 * Allocate the dummy page used by the driver (all asics).
803 * This dummy page is used by the driver as a filler for gart entries
804 * when pages are taken out of the GART
805 * Returns 0 on sucess, -ENOMEM on failure.
807 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
809 if (adev->dummy_page.page)
811 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
812 if (adev->dummy_page.page == NULL)
814 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
815 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
816 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
817 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
818 __free_page(adev->dummy_page.page);
819 adev->dummy_page.page = NULL;
826 * amdgpu_dummy_page_fini - free dummy page used by the driver
828 * @adev: amdgpu_device pointer
830 * Frees the dummy page used by the driver (all asics).
832 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
834 if (adev->dummy_page.page == NULL)
836 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
837 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
838 __free_page(adev->dummy_page.page);
839 adev->dummy_page.page = NULL;
843 /* ATOM accessor methods */
845 * ATOM is an interpreted byte code stored in tables in the vbios. The
846 * driver registers callbacks to access registers and the interpreter
847 * in the driver parses the tables and executes then to program specific
848 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
849 * atombios.h, and atom.c
853 * cail_pll_read - read PLL register
855 * @info: atom card_info pointer
856 * @reg: PLL register offset
858 * Provides a PLL register accessor for the atom interpreter (r4xx+).
859 * Returns the value of the PLL register.
861 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
867 * cail_pll_write - write PLL register
869 * @info: atom card_info pointer
870 * @reg: PLL register offset
871 * @val: value to write to the pll register
873 * Provides a PLL register accessor for the atom interpreter (r4xx+).
875 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
881 * cail_mc_read - read MC (Memory Controller) register
883 * @info: atom card_info pointer
884 * @reg: MC register offset
886 * Provides an MC register accessor for the atom interpreter (r4xx+).
887 * Returns the value of the MC register.
889 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
895 * cail_mc_write - write MC (Memory Controller) register
897 * @info: atom card_info pointer
898 * @reg: MC register offset
899 * @val: value to write to the pll register
901 * Provides a MC register accessor for the atom interpreter (r4xx+).
903 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
909 * cail_reg_write - write MMIO register
911 * @info: atom card_info pointer
912 * @reg: MMIO register offset
913 * @val: value to write to the pll register
915 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
917 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
919 struct amdgpu_device *adev = info->dev->dev_private;
925 * cail_reg_read - read MMIO register
927 * @info: atom card_info pointer
928 * @reg: MMIO register offset
930 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
931 * Returns the value of the MMIO register.
933 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
935 struct amdgpu_device *adev = info->dev->dev_private;
943 * cail_ioreg_write - write IO register
945 * @info: atom card_info pointer
946 * @reg: IO register offset
947 * @val: value to write to the pll register
949 * Provides a IO register accessor for the atom interpreter (r4xx+).
951 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
953 struct amdgpu_device *adev = info->dev->dev_private;
959 * cail_ioreg_read - read IO register
961 * @info: atom card_info pointer
962 * @reg: IO register offset
964 * Provides an IO register accessor for the atom interpreter (r4xx+).
965 * Returns the value of the IO register.
967 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
969 struct amdgpu_device *adev = info->dev->dev_private;
976 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
977 struct device_attribute *attr,
980 struct drm_device *ddev = dev_get_drvdata(dev);
981 struct amdgpu_device *adev = ddev->dev_private;
982 struct atom_context *ctx = adev->mode_info.atom_context;
984 return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
987 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
991 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
993 * @adev: amdgpu_device pointer
995 * Frees the driver info and register access callbacks for the ATOM
996 * interpreter (r4xx+).
997 * Called at driver shutdown.
999 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
1001 if (adev->mode_info.atom_context) {
1002 kfree(adev->mode_info.atom_context->scratch);
1003 kfree(adev->mode_info.atom_context->iio);
1005 kfree(adev->mode_info.atom_context);
1006 adev->mode_info.atom_context = NULL;
1007 kfree(adev->mode_info.atom_card_info);
1008 adev->mode_info.atom_card_info = NULL;
1009 device_remove_file(adev->dev, &dev_attr_vbios_version);
1013 * amdgpu_atombios_init - init the driver info and callbacks for atombios
1015 * @adev: amdgpu_device pointer
1017 * Initializes the driver info and register access callbacks for the
1018 * ATOM interpreter (r4xx+).
1019 * Returns 0 on sucess, -ENOMEM on failure.
1020 * Called at driver startup.
1022 static int amdgpu_atombios_init(struct amdgpu_device *adev)
1024 struct card_info *atom_card_info =
1025 kzalloc(sizeof(struct card_info), GFP_KERNEL);
1028 if (!atom_card_info)
1031 adev->mode_info.atom_card_info = atom_card_info;
1032 atom_card_info->dev = adev->ddev;
1033 atom_card_info->reg_read = cail_reg_read;
1034 atom_card_info->reg_write = cail_reg_write;
1035 /* needed for iio ops */
1036 if (adev->rio_mem) {
1037 atom_card_info->ioreg_read = cail_ioreg_read;
1038 atom_card_info->ioreg_write = cail_ioreg_write;
1040 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
1041 atom_card_info->ioreg_read = cail_reg_read;
1042 atom_card_info->ioreg_write = cail_reg_write;
1044 atom_card_info->mc_read = cail_mc_read;
1045 atom_card_info->mc_write = cail_mc_write;
1046 atom_card_info->pll_read = cail_pll_read;
1047 atom_card_info->pll_write = cail_pll_write;
1049 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
1050 if (!adev->mode_info.atom_context) {
1051 amdgpu_atombios_fini(adev);
1055 mutex_init(&adev->mode_info.atom_context->mutex);
1056 if (adev->is_atom_fw) {
1057 amdgpu_atomfirmware_scratch_regs_init(adev);
1058 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1060 amdgpu_atombios_scratch_regs_init(adev);
1061 amdgpu_atombios_allocate_fb_scratch(adev);
1064 ret = device_create_file(adev->dev, &dev_attr_vbios_version);
1066 DRM_ERROR("Failed to create device file for VBIOS version\n");
1073 /* if we get transitioned to only one device, take VGA back */
1075 * amdgpu_vga_set_decode - enable/disable vga decode
1077 * @cookie: amdgpu_device pointer
1078 * @state: enable/disable vga decode
1080 * Enable/disable vga decode (all asics).
1081 * Returns VGA resource flags.
1083 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
1085 struct amdgpu_device *adev = cookie;
1086 amdgpu_asic_set_vga_state(adev, state);
1088 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1089 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1091 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1094 static void amdgpu_check_block_size(struct amdgpu_device *adev)
1096 /* defines number of bits in page table versus page directory,
1097 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1098 * page table and the remaining bits are in the page directory */
1099 if (amdgpu_vm_block_size == -1)
1102 if (amdgpu_vm_block_size < 9) {
1103 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1104 amdgpu_vm_block_size);
1108 if (amdgpu_vm_block_size > 24 ||
1109 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1110 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1111 amdgpu_vm_block_size);
1118 amdgpu_vm_block_size = -1;
1121 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1123 /* no need to check the default value */
1124 if (amdgpu_vm_size == -1)
1127 if (!is_power_of_2(amdgpu_vm_size)) {
1128 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1133 if (amdgpu_vm_size < 1) {
1134 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1140 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1142 if (amdgpu_vm_size > 1024) {
1143 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1151 amdgpu_vm_size = -1;
1155 * amdgpu_check_arguments - validate module params
1157 * @adev: amdgpu_device pointer
1159 * Validates certain module parameters and updates
1160 * the associated values used by the driver (all asics).
1162 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1164 if (amdgpu_sched_jobs < 4) {
1165 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1167 amdgpu_sched_jobs = 4;
1168 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1169 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1171 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1174 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1175 /* gart size must be greater or equal to 32M */
1176 dev_warn(adev->dev, "gart size (%d) too small\n",
1178 amdgpu_gart_size = -1;
1181 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1182 /* gtt size must be greater or equal to 32M */
1183 dev_warn(adev->dev, "gtt size (%d) too small\n",
1185 amdgpu_gtt_size = -1;
1188 /* valid range is between 4 and 9 inclusive */
1189 if (amdgpu_vm_fragment_size != -1 &&
1190 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1191 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1192 amdgpu_vm_fragment_size = -1;
1195 amdgpu_check_vm_size(adev);
1197 amdgpu_check_block_size(adev);
1199 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1200 !is_power_of_2(amdgpu_vram_page_split))) {
1201 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1202 amdgpu_vram_page_split);
1203 amdgpu_vram_page_split = 1024;
1208 * amdgpu_switcheroo_set_state - set switcheroo state
1210 * @pdev: pci dev pointer
1211 * @state: vga_switcheroo state
1213 * Callback for the switcheroo driver. Suspends or resumes the
1214 * the asics before or after it is powered up using ACPI methods.
1216 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1218 struct drm_device *dev = pci_get_drvdata(pdev);
1220 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1223 if (state == VGA_SWITCHEROO_ON) {
1224 pr_info("amdgpu: switched on\n");
1225 /* don't suspend or resume card normally */
1226 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1228 amdgpu_device_resume(dev, true, true);
1230 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1231 drm_kms_helper_poll_enable(dev);
1233 pr_info("amdgpu: switched off\n");
1234 drm_kms_helper_poll_disable(dev);
1235 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1236 amdgpu_device_suspend(dev, true, true);
1237 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1242 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1244 * @pdev: pci dev pointer
1246 * Callback for the switcheroo driver. Check of the switcheroo
1247 * state can be changed.
1248 * Returns true if the state can be changed, false if not.
1250 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1252 struct drm_device *dev = pci_get_drvdata(pdev);
1255 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1256 * locking inversion with the driver load path. And the access here is
1257 * completely racy anyway. So don't bother with locking for now.
1259 return dev->open_count == 0;
1262 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1263 .set_gpu_state = amdgpu_switcheroo_set_state,
1265 .can_switch = amdgpu_switcheroo_can_switch,
1268 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1269 enum amd_ip_block_type block_type,
1270 enum amd_clockgating_state state)
1274 for (i = 0; i < adev->num_ip_blocks; i++) {
1275 if (!adev->ip_blocks[i].status.valid)
1277 if (adev->ip_blocks[i].version->type != block_type)
1279 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1281 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1282 (void *)adev, state);
1284 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1285 adev->ip_blocks[i].version->funcs->name, r);
1290 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1291 enum amd_ip_block_type block_type,
1292 enum amd_powergating_state state)
1296 for (i = 0; i < adev->num_ip_blocks; i++) {
1297 if (!adev->ip_blocks[i].status.valid)
1299 if (adev->ip_blocks[i].version->type != block_type)
1301 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1303 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1304 (void *)adev, state);
1306 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1307 adev->ip_blocks[i].version->funcs->name, r);
1312 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1316 for (i = 0; i < adev->num_ip_blocks; i++) {
1317 if (!adev->ip_blocks[i].status.valid)
1319 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1320 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1324 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1325 enum amd_ip_block_type block_type)
1329 for (i = 0; i < adev->num_ip_blocks; i++) {
1330 if (!adev->ip_blocks[i].status.valid)
1332 if (adev->ip_blocks[i].version->type == block_type) {
1333 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1343 bool amdgpu_is_idle(struct amdgpu_device *adev,
1344 enum amd_ip_block_type block_type)
1348 for (i = 0; i < adev->num_ip_blocks; i++) {
1349 if (!adev->ip_blocks[i].status.valid)
1351 if (adev->ip_blocks[i].version->type == block_type)
1352 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1358 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1359 enum amd_ip_block_type type)
1363 for (i = 0; i < adev->num_ip_blocks; i++)
1364 if (adev->ip_blocks[i].version->type == type)
1365 return &adev->ip_blocks[i];
1371 * amdgpu_ip_block_version_cmp
1373 * @adev: amdgpu_device pointer
1374 * @type: enum amd_ip_block_type
1375 * @major: major version
1376 * @minor: minor version
1378 * return 0 if equal or greater
1379 * return 1 if smaller or the ip_block doesn't exist
1381 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1382 enum amd_ip_block_type type,
1383 u32 major, u32 minor)
1385 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1387 if (ip_block && ((ip_block->version->major > major) ||
1388 ((ip_block->version->major == major) &&
1389 (ip_block->version->minor >= minor))))
1396 * amdgpu_ip_block_add
1398 * @adev: amdgpu_device pointer
1399 * @ip_block_version: pointer to the IP to add
1401 * Adds the IP block driver information to the collection of IPs
1404 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1405 const struct amdgpu_ip_block_version *ip_block_version)
1407 if (!ip_block_version)
1410 DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
1411 ip_block_version->funcs->name);
1413 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1418 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1420 adev->enable_virtual_display = false;
1422 if (amdgpu_virtual_display) {
1423 struct drm_device *ddev = adev->ddev;
1424 const char *pci_address_name = pci_name(ddev->pdev);
1425 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1427 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1428 pciaddstr_tmp = pciaddstr;
1429 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1430 pciaddname = strsep(&pciaddname_tmp, ",");
1431 if (!strcmp("all", pciaddname)
1432 || !strcmp(pci_address_name, pciaddname)) {
1436 adev->enable_virtual_display = true;
1439 res = kstrtol(pciaddname_tmp, 10,
1447 adev->mode_info.num_crtc = num_crtc;
1449 adev->mode_info.num_crtc = 1;
1455 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1456 amdgpu_virtual_display, pci_address_name,
1457 adev->enable_virtual_display, adev->mode_info.num_crtc);
1463 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1465 const char *chip_name;
1468 const struct gpu_info_firmware_header_v1_0 *hdr;
1470 adev->firmware.gpu_info_fw = NULL;
1472 switch (adev->asic_type) {
1476 case CHIP_POLARIS11:
1477 case CHIP_POLARIS10:
1478 case CHIP_POLARIS12:
1481 #ifdef CONFIG_DRM_AMDGPU_SI
1488 #ifdef CONFIG_DRM_AMDGPU_CIK
1498 chip_name = "vega10";
1501 chip_name = "raven";
1505 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1506 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1509 "Failed to load gpu_info firmware \"%s\"\n",
1513 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1516 "Failed to validate gpu_info firmware \"%s\"\n",
1521 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1522 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1524 switch (hdr->version_major) {
1527 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1528 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1529 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1531 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1532 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1533 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1534 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1535 adev->gfx.config.max_texture_channel_caches =
1536 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1537 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1538 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1539 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1540 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1541 adev->gfx.config.double_offchip_lds_buf =
1542 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1543 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1544 adev->gfx.cu_info.max_waves_per_simd =
1545 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1546 adev->gfx.cu_info.max_scratch_slots_per_cu =
1547 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1548 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1553 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1561 static int amdgpu_early_init(struct amdgpu_device *adev)
1565 amdgpu_device_enable_virtual_display(adev);
1567 switch (adev->asic_type) {
1571 case CHIP_POLARIS11:
1572 case CHIP_POLARIS10:
1573 case CHIP_POLARIS12:
1576 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1577 adev->family = AMDGPU_FAMILY_CZ;
1579 adev->family = AMDGPU_FAMILY_VI;
1581 r = vi_set_ip_blocks(adev);
1585 #ifdef CONFIG_DRM_AMDGPU_SI
1591 adev->family = AMDGPU_FAMILY_SI;
1592 r = si_set_ip_blocks(adev);
1597 #ifdef CONFIG_DRM_AMDGPU_CIK
1603 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1604 adev->family = AMDGPU_FAMILY_CI;
1606 adev->family = AMDGPU_FAMILY_KV;
1608 r = cik_set_ip_blocks(adev);
1615 if (adev->asic_type == CHIP_RAVEN)
1616 adev->family = AMDGPU_FAMILY_RV;
1618 adev->family = AMDGPU_FAMILY_AI;
1620 r = soc15_set_ip_blocks(adev);
1625 /* FIXME: not supported yet */
1629 r = amdgpu_device_parse_gpu_info_fw(adev);
1633 if (amdgpu_sriov_vf(adev)) {
1634 r = amdgpu_virt_request_full_gpu(adev, true);
1639 for (i = 0; i < adev->num_ip_blocks; i++) {
1640 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1641 DRM_ERROR("disabled ip block: %d <%s>\n",
1642 i, adev->ip_blocks[i].version->funcs->name);
1643 adev->ip_blocks[i].status.valid = false;
1645 if (adev->ip_blocks[i].version->funcs->early_init) {
1646 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1648 adev->ip_blocks[i].status.valid = false;
1650 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1651 adev->ip_blocks[i].version->funcs->name, r);
1654 adev->ip_blocks[i].status.valid = true;
1657 adev->ip_blocks[i].status.valid = true;
1662 adev->cg_flags &= amdgpu_cg_mask;
1663 adev->pg_flags &= amdgpu_pg_mask;
1668 static int amdgpu_init(struct amdgpu_device *adev)
1672 for (i = 0; i < adev->num_ip_blocks; i++) {
1673 if (!adev->ip_blocks[i].status.valid)
1675 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1677 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1678 adev->ip_blocks[i].version->funcs->name, r);
1681 adev->ip_blocks[i].status.sw = true;
1683 /* need to do gmc hw init early so we can allocate gpu mem */
1684 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1685 r = amdgpu_vram_scratch_init(adev);
1687 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1690 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1692 DRM_ERROR("hw_init %d failed %d\n", i, r);
1695 r = amdgpu_wb_init(adev);
1697 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1700 adev->ip_blocks[i].status.hw = true;
1702 /* right after GMC hw init, we create CSA */
1703 if (amdgpu_sriov_vf(adev)) {
1704 r = amdgpu_allocate_static_csa(adev);
1706 DRM_ERROR("allocate CSA failed %d\n", r);
1713 mutex_lock(&adev->firmware.mutex);
1714 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
1715 amdgpu_ucode_init_bo(adev);
1716 mutex_unlock(&adev->firmware.mutex);
1718 for (i = 0; i < adev->num_ip_blocks; i++) {
1719 if (!adev->ip_blocks[i].status.sw)
1721 /* gmc hw init is done early */
1722 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1724 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1726 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1727 adev->ip_blocks[i].version->funcs->name, r);
1730 adev->ip_blocks[i].status.hw = true;
1736 static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
1738 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1741 static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
1743 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1744 AMDGPU_RESET_MAGIC_NUM);
1747 static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
1751 for (i = 0; i < adev->num_ip_blocks; i++) {
1752 if (!adev->ip_blocks[i].status.valid)
1754 /* skip CG for VCE/UVD, it's handled specially */
1755 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1756 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1757 /* enable clockgating to save power */
1758 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1761 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1762 adev->ip_blocks[i].version->funcs->name, r);
1770 static int amdgpu_late_init(struct amdgpu_device *adev)
1774 for (i = 0; i < adev->num_ip_blocks; i++) {
1775 if (!adev->ip_blocks[i].status.valid)
1777 if (adev->ip_blocks[i].version->funcs->late_init) {
1778 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1780 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1781 adev->ip_blocks[i].version->funcs->name, r);
1784 adev->ip_blocks[i].status.late_initialized = true;
1788 mod_delayed_work(system_wq, &adev->late_init_work,
1789 msecs_to_jiffies(AMDGPU_RESUME_MS));
1791 amdgpu_fill_reset_magic(adev);
1796 static int amdgpu_fini(struct amdgpu_device *adev)
1800 /* need to disable SMC first */
1801 for (i = 0; i < adev->num_ip_blocks; i++) {
1802 if (!adev->ip_blocks[i].status.hw)
1804 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1805 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1806 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1807 AMD_CG_STATE_UNGATE);
1809 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1810 adev->ip_blocks[i].version->funcs->name, r);
1813 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1814 /* XXX handle errors */
1816 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1817 adev->ip_blocks[i].version->funcs->name, r);
1819 adev->ip_blocks[i].status.hw = false;
1824 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1825 if (!adev->ip_blocks[i].status.hw)
1827 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1828 amdgpu_wb_fini(adev);
1829 amdgpu_vram_scratch_fini(adev);
1832 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1833 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1834 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1835 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1836 AMD_CG_STATE_UNGATE);
1838 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1839 adev->ip_blocks[i].version->funcs->name, r);
1844 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1845 /* XXX handle errors */
1847 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1848 adev->ip_blocks[i].version->funcs->name, r);
1851 adev->ip_blocks[i].status.hw = false;
1853 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
1854 amdgpu_ucode_fini_bo(adev);
1856 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1857 if (!adev->ip_blocks[i].status.sw)
1859 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1860 /* XXX handle errors */
1862 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1863 adev->ip_blocks[i].version->funcs->name, r);
1865 adev->ip_blocks[i].status.sw = false;
1866 adev->ip_blocks[i].status.valid = false;
1869 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1870 if (!adev->ip_blocks[i].status.late_initialized)
1872 if (adev->ip_blocks[i].version->funcs->late_fini)
1873 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1874 adev->ip_blocks[i].status.late_initialized = false;
1877 if (amdgpu_sriov_vf(adev))
1878 amdgpu_virt_release_full_gpu(adev, false);
1883 static void amdgpu_late_init_func_handler(struct work_struct *work)
1885 struct amdgpu_device *adev =
1886 container_of(work, struct amdgpu_device, late_init_work.work);
1887 amdgpu_late_set_cg_state(adev);
1890 int amdgpu_suspend(struct amdgpu_device *adev)
1894 if (amdgpu_sriov_vf(adev))
1895 amdgpu_virt_request_full_gpu(adev, false);
1897 /* ungate SMC block first */
1898 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1899 AMD_CG_STATE_UNGATE);
1901 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1904 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1905 if (!adev->ip_blocks[i].status.valid)
1907 /* ungate blocks so that suspend can properly shut them down */
1908 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1909 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1910 AMD_CG_STATE_UNGATE);
1912 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1913 adev->ip_blocks[i].version->funcs->name, r);
1916 /* XXX handle errors */
1917 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1918 /* XXX handle errors */
1920 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1921 adev->ip_blocks[i].version->funcs->name, r);
1925 if (amdgpu_sriov_vf(adev))
1926 amdgpu_virt_release_full_gpu(adev, false);
1931 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1935 static enum amd_ip_block_type ip_order[] = {
1936 AMD_IP_BLOCK_TYPE_GMC,
1937 AMD_IP_BLOCK_TYPE_COMMON,
1938 AMD_IP_BLOCK_TYPE_IH,
1941 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1943 struct amdgpu_ip_block *block;
1945 for (j = 0; j < adev->num_ip_blocks; j++) {
1946 block = &adev->ip_blocks[j];
1948 if (block->version->type != ip_order[i] ||
1949 !block->status.valid)
1952 r = block->version->funcs->hw_init(adev);
1953 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1960 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
1964 static enum amd_ip_block_type ip_order[] = {
1965 AMD_IP_BLOCK_TYPE_SMC,
1966 AMD_IP_BLOCK_TYPE_DCE,
1967 AMD_IP_BLOCK_TYPE_GFX,
1968 AMD_IP_BLOCK_TYPE_SDMA,
1969 AMD_IP_BLOCK_TYPE_UVD,
1970 AMD_IP_BLOCK_TYPE_VCE
1973 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1975 struct amdgpu_ip_block *block;
1977 for (j = 0; j < adev->num_ip_blocks; j++) {
1978 block = &adev->ip_blocks[j];
1980 if (block->version->type != ip_order[i] ||
1981 !block->status.valid)
1984 r = block->version->funcs->hw_init(adev);
1985 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1992 static int amdgpu_resume_phase1(struct amdgpu_device *adev)
1996 for (i = 0; i < adev->num_ip_blocks; i++) {
1997 if (!adev->ip_blocks[i].status.valid)
1999 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2000 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2001 adev->ip_blocks[i].version->type ==
2002 AMD_IP_BLOCK_TYPE_IH) {
2003 r = adev->ip_blocks[i].version->funcs->resume(adev);
2005 DRM_ERROR("resume of IP block <%s> failed %d\n",
2006 adev->ip_blocks[i].version->funcs->name, r);
2015 static int amdgpu_resume_phase2(struct amdgpu_device *adev)
2019 for (i = 0; i < adev->num_ip_blocks; i++) {
2020 if (!adev->ip_blocks[i].status.valid)
2022 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2023 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2024 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
2026 r = adev->ip_blocks[i].version->funcs->resume(adev);
2028 DRM_ERROR("resume of IP block <%s> failed %d\n",
2029 adev->ip_blocks[i].version->funcs->name, r);
2037 static int amdgpu_resume(struct amdgpu_device *adev)
2041 r = amdgpu_resume_phase1(adev);
2044 r = amdgpu_resume_phase2(adev);
2049 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2051 if (adev->is_atom_fw) {
2052 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2053 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2055 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2056 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2061 * amdgpu_device_init - initialize the driver
2063 * @adev: amdgpu_device pointer
2064 * @pdev: drm dev pointer
2065 * @pdev: pci dev pointer
2066 * @flags: driver flags
2068 * Initializes the driver info and hw (all asics).
2069 * Returns 0 for success or an error on failure.
2070 * Called at driver startup.
2072 int amdgpu_device_init(struct amdgpu_device *adev,
2073 struct drm_device *ddev,
2074 struct pci_dev *pdev,
2078 bool runtime = false;
2081 adev->shutdown = false;
2082 adev->dev = &pdev->dev;
2085 adev->flags = flags;
2086 adev->asic_type = flags & AMD_ASIC_MASK;
2087 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2088 adev->mc.gart_size = 512 * 1024 * 1024;
2089 adev->accel_working = false;
2090 adev->num_rings = 0;
2091 adev->mman.buffer_funcs = NULL;
2092 adev->mman.buffer_funcs_ring = NULL;
2093 adev->vm_manager.vm_pte_funcs = NULL;
2094 adev->vm_manager.vm_pte_num_rings = 0;
2095 adev->gart.gart_funcs = NULL;
2096 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2097 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2099 adev->smc_rreg = &amdgpu_invalid_rreg;
2100 adev->smc_wreg = &amdgpu_invalid_wreg;
2101 adev->pcie_rreg = &amdgpu_invalid_rreg;
2102 adev->pcie_wreg = &amdgpu_invalid_wreg;
2103 adev->pciep_rreg = &amdgpu_invalid_rreg;
2104 adev->pciep_wreg = &amdgpu_invalid_wreg;
2105 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2106 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2107 adev->didt_rreg = &amdgpu_invalid_rreg;
2108 adev->didt_wreg = &amdgpu_invalid_wreg;
2109 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2110 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2111 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2112 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2115 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2116 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2117 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2119 /* mutex initialization are all done here so we
2120 * can recall function without having locking issues */
2121 atomic_set(&adev->irq.ih.lock, 0);
2122 mutex_init(&adev->firmware.mutex);
2123 mutex_init(&adev->pm.mutex);
2124 mutex_init(&adev->gfx.gpu_clock_mutex);
2125 mutex_init(&adev->srbm_mutex);
2126 mutex_init(&adev->gfx.pipe_reserve_mutex);
2127 mutex_init(&adev->grbm_idx_mutex);
2128 mutex_init(&adev->mn_lock);
2129 mutex_init(&adev->virt.vf_errors.lock);
2130 hash_init(adev->mn_hash);
2132 amdgpu_check_arguments(adev);
2134 spin_lock_init(&adev->mmio_idx_lock);
2135 spin_lock_init(&adev->smc_idx_lock);
2136 spin_lock_init(&adev->pcie_idx_lock);
2137 spin_lock_init(&adev->uvd_ctx_idx_lock);
2138 spin_lock_init(&adev->didt_idx_lock);
2139 spin_lock_init(&adev->gc_cac_idx_lock);
2140 spin_lock_init(&adev->se_cac_idx_lock);
2141 spin_lock_init(&adev->audio_endpt_idx_lock);
2142 spin_lock_init(&adev->mm_stats.lock);
2144 INIT_LIST_HEAD(&adev->shadow_list);
2145 mutex_init(&adev->shadow_list_lock);
2147 INIT_LIST_HEAD(&adev->gtt_list);
2148 spin_lock_init(&adev->gtt_list_lock);
2150 INIT_LIST_HEAD(&adev->ring_lru_list);
2151 spin_lock_init(&adev->ring_lru_list_lock);
2153 INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
2155 /* Registers mapping */
2156 /* TODO: block userspace mapping of io register */
2157 if (adev->asic_type >= CHIP_BONAIRE) {
2158 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2159 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2161 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2162 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2165 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2166 if (adev->rmmio == NULL) {
2169 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2170 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2172 /* doorbell bar mapping */
2173 amdgpu_doorbell_init(adev);
2175 /* io port mapping */
2176 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2177 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2178 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2179 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2183 if (adev->rio_mem == NULL)
2184 DRM_INFO("PCI I/O BAR is not found.\n");
2186 /* early init functions */
2187 r = amdgpu_early_init(adev);
2191 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2192 /* this will fail for cards that aren't VGA class devices, just
2194 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
2196 if (amdgpu_runtime_pm == 1)
2198 if (amdgpu_device_is_px(ddev))
2200 if (!pci_is_thunderbolt_attached(adev->pdev))
2201 vga_switcheroo_register_client(adev->pdev,
2202 &amdgpu_switcheroo_ops, runtime);
2204 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2207 if (!amdgpu_get_bios(adev)) {
2212 r = amdgpu_atombios_init(adev);
2214 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2215 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2219 /* detect if we are with an SRIOV vbios */
2220 amdgpu_device_detect_sriov_bios(adev);
2222 /* Post card if necessary */
2223 if (amdgpu_vpost_needed(adev)) {
2225 dev_err(adev->dev, "no vBIOS found\n");
2226 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2230 DRM_INFO("GPU posting now...\n");
2231 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2233 dev_err(adev->dev, "gpu post error!\n");
2234 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0);
2238 DRM_INFO("GPU post is not needed\n");
2241 if (adev->is_atom_fw) {
2242 /* Initialize clocks */
2243 r = amdgpu_atomfirmware_get_clock_info(adev);
2245 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2246 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2250 /* Initialize clocks */
2251 r = amdgpu_atombios_get_clock_info(adev);
2253 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2254 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2257 /* init i2c buses */
2258 amdgpu_atombios_i2c_init(adev);
2262 r = amdgpu_fence_driver_init(adev);
2264 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2265 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2269 /* init the mode config */
2270 drm_mode_config_init(adev->ddev);
2272 r = amdgpu_init(adev);
2274 dev_err(adev->dev, "amdgpu_init failed\n");
2275 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2280 adev->accel_working = true;
2282 amdgpu_vm_check_compute_bug(adev);
2284 /* Initialize the buffer migration limit. */
2285 if (amdgpu_moverate >= 0)
2286 max_MBps = amdgpu_moverate;
2288 max_MBps = 8; /* Allow 8 MB/s. */
2289 /* Get a log2 for easy divisions. */
2290 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2292 r = amdgpu_ib_pool_init(adev);
2294 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2295 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2299 r = amdgpu_ib_ring_tests(adev);
2301 DRM_ERROR("ib ring test failed (%d).\n", r);
2303 if (amdgpu_sriov_vf(adev))
2304 amdgpu_virt_init_data_exchange(adev);
2306 amdgpu_fbdev_init(adev);
2308 r = amdgpu_pm_sysfs_init(adev);
2310 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2312 r = amdgpu_gem_debugfs_init(adev);
2314 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2316 r = amdgpu_debugfs_regs_init(adev);
2318 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2320 r = amdgpu_debugfs_test_ib_ring_init(adev);
2322 DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);
2324 r = amdgpu_debugfs_firmware_init(adev);
2326 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2328 r = amdgpu_debugfs_vbios_dump_init(adev);
2330 DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r);
2332 if ((amdgpu_testing & 1)) {
2333 if (adev->accel_working)
2334 amdgpu_test_moves(adev);
2336 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2338 if (amdgpu_benchmarking) {
2339 if (adev->accel_working)
2340 amdgpu_benchmark(adev, amdgpu_benchmarking);
2342 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2345 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2346 * explicit gating rather than handling it automatically.
2348 r = amdgpu_late_init(adev);
2350 dev_err(adev->dev, "amdgpu_late_init failed\n");
2351 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2358 amdgpu_vf_error_trans_all(adev);
2360 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2365 * amdgpu_device_fini - tear down the driver
2367 * @adev: amdgpu_device pointer
2369 * Tear down the driver info (all asics).
2370 * Called at driver shutdown.
2372 void amdgpu_device_fini(struct amdgpu_device *adev)
2376 DRM_INFO("amdgpu: finishing device.\n");
2377 adev->shutdown = true;
2378 if (adev->mode_info.mode_config_initialized)
2379 drm_crtc_force_disable_all(adev->ddev);
2380 /* evict vram memory */
2381 amdgpu_bo_evict_vram(adev);
2382 amdgpu_ib_pool_fini(adev);
2383 amdgpu_fw_reserve_vram_fini(adev);
2384 amdgpu_fence_driver_fini(adev);
2385 amdgpu_fbdev_fini(adev);
2386 r = amdgpu_fini(adev);
2387 if (adev->firmware.gpu_info_fw) {
2388 release_firmware(adev->firmware.gpu_info_fw);
2389 adev->firmware.gpu_info_fw = NULL;
2391 adev->accel_working = false;
2392 cancel_delayed_work_sync(&adev->late_init_work);
2393 /* free i2c buses */
2394 amdgpu_i2c_fini(adev);
2395 amdgpu_atombios_fini(adev);
2398 if (!pci_is_thunderbolt_attached(adev->pdev))
2399 vga_switcheroo_unregister_client(adev->pdev);
2400 if (adev->flags & AMD_IS_PX)
2401 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2402 vga_client_register(adev->pdev, NULL, NULL, NULL);
2404 pci_iounmap(adev->pdev, adev->rio_mem);
2405 adev->rio_mem = NULL;
2406 iounmap(adev->rmmio);
2408 amdgpu_doorbell_fini(adev);
2409 amdgpu_pm_sysfs_fini(adev);
2410 amdgpu_debugfs_regs_cleanup(adev);
2418 * amdgpu_device_suspend - initiate device suspend
2420 * @pdev: drm dev pointer
2421 * @state: suspend state
2423 * Puts the hw in the suspend state (all asics).
2424 * Returns 0 for success or an error on failure.
2425 * Called at driver suspend.
2427 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2429 struct amdgpu_device *adev;
2430 struct drm_crtc *crtc;
2431 struct drm_connector *connector;
2434 if (dev == NULL || dev->dev_private == NULL) {
2438 adev = dev->dev_private;
2440 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2443 drm_kms_helper_poll_disable(dev);
2445 /* turn off display hw */
2446 drm_modeset_lock_all(dev);
2447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2448 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2450 drm_modeset_unlock_all(dev);
2452 amdgpu_amdkfd_suspend(adev);
2454 /* unpin the front buffers and cursors */
2455 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2456 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2457 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2458 struct amdgpu_bo *robj;
2460 if (amdgpu_crtc->cursor_bo) {
2461 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2462 r = amdgpu_bo_reserve(aobj, true);
2464 amdgpu_bo_unpin(aobj);
2465 amdgpu_bo_unreserve(aobj);
2469 if (rfb == NULL || rfb->obj == NULL) {
2472 robj = gem_to_amdgpu_bo(rfb->obj);
2473 /* don't unpin kernel fb objects */
2474 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2475 r = amdgpu_bo_reserve(robj, true);
2477 amdgpu_bo_unpin(robj);
2478 amdgpu_bo_unreserve(robj);
2482 /* evict vram memory */
2483 amdgpu_bo_evict_vram(adev);
2485 amdgpu_fence_driver_suspend(adev);
2487 r = amdgpu_suspend(adev);
2489 /* evict remaining vram memory
2490 * This second call to evict vram is to evict the gart page table
2493 amdgpu_bo_evict_vram(adev);
2495 amdgpu_atombios_scratch_regs_save(adev);
2496 pci_save_state(dev->pdev);
2498 /* Shut down the device */
2499 pci_disable_device(dev->pdev);
2500 pci_set_power_state(dev->pdev, PCI_D3hot);
2502 r = amdgpu_asic_reset(adev);
2504 DRM_ERROR("amdgpu asic reset failed\n");
2509 amdgpu_fbdev_set_suspend(adev, 1);
2516 * amdgpu_device_resume - initiate device resume
2518 * @pdev: drm dev pointer
2520 * Bring the hw back to operating state (all asics).
2521 * Returns 0 for success or an error on failure.
2522 * Called at driver resume.
2524 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2526 struct drm_connector *connector;
2527 struct amdgpu_device *adev = dev->dev_private;
2528 struct drm_crtc *crtc;
2531 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2538 pci_set_power_state(dev->pdev, PCI_D0);
2539 pci_restore_state(dev->pdev);
2540 r = pci_enable_device(dev->pdev);
2544 amdgpu_atombios_scratch_regs_restore(adev);
2547 if (amdgpu_need_post(adev)) {
2548 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2550 DRM_ERROR("amdgpu asic init failed\n");
2553 r = amdgpu_resume(adev);
2555 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2558 amdgpu_fence_driver_resume(adev);
2561 r = amdgpu_ib_ring_tests(adev);
2563 DRM_ERROR("ib ring test failed (%d).\n", r);
2566 r = amdgpu_late_init(adev);
2571 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2572 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2574 if (amdgpu_crtc->cursor_bo) {
2575 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2576 r = amdgpu_bo_reserve(aobj, true);
2578 r = amdgpu_bo_pin(aobj,
2579 AMDGPU_GEM_DOMAIN_VRAM,
2580 &amdgpu_crtc->cursor_addr);
2582 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2583 amdgpu_bo_unreserve(aobj);
2587 r = amdgpu_amdkfd_resume(adev);
2591 /* blat the mode back in */
2593 drm_helper_resume_force_mode(dev);
2594 /* turn on display hw */
2595 drm_modeset_lock_all(dev);
2596 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2597 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2599 drm_modeset_unlock_all(dev);
2602 drm_kms_helper_poll_enable(dev);
2605 * Most of the connector probing functions try to acquire runtime pm
2606 * refs to ensure that the GPU is powered on when connector polling is
2607 * performed. Since we're calling this from a runtime PM callback,
2608 * trying to acquire rpm refs will cause us to deadlock.
2610 * Since we're guaranteed to be holding the rpm lock, it's safe to
2611 * temporarily disable the rpm helpers so this doesn't deadlock us.
2614 dev->dev->power.disable_depth++;
2616 drm_helper_hpd_irq_event(dev);
2618 dev->dev->power.disable_depth--;
2622 amdgpu_fbdev_set_suspend(adev, 0);
2631 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2634 bool asic_hang = false;
2636 for (i = 0; i < adev->num_ip_blocks; i++) {
2637 if (!adev->ip_blocks[i].status.valid)
2639 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2640 adev->ip_blocks[i].status.hang =
2641 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2642 if (adev->ip_blocks[i].status.hang) {
2643 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2650 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2654 for (i = 0; i < adev->num_ip_blocks; i++) {
2655 if (!adev->ip_blocks[i].status.valid)
2657 if (adev->ip_blocks[i].status.hang &&
2658 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2659 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2668 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2672 for (i = 0; i < adev->num_ip_blocks; i++) {
2673 if (!adev->ip_blocks[i].status.valid)
2675 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2676 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2677 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2678 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2679 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2680 if (adev->ip_blocks[i].status.hang) {
2681 DRM_INFO("Some block need full reset!\n");
2689 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2693 for (i = 0; i < adev->num_ip_blocks; i++) {
2694 if (!adev->ip_blocks[i].status.valid)
2696 if (adev->ip_blocks[i].status.hang &&
2697 adev->ip_blocks[i].version->funcs->soft_reset) {
2698 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2707 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2711 for (i = 0; i < adev->num_ip_blocks; i++) {
2712 if (!adev->ip_blocks[i].status.valid)
2714 if (adev->ip_blocks[i].status.hang &&
2715 adev->ip_blocks[i].version->funcs->post_soft_reset)
2716 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2724 bool amdgpu_need_backup(struct amdgpu_device *adev)
2726 if (adev->flags & AMD_IS_APU)
2729 return amdgpu_lockup_timeout > 0 ? true : false;
2732 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2733 struct amdgpu_ring *ring,
2734 struct amdgpu_bo *bo,
2735 struct dma_fence **fence)
2743 r = amdgpu_bo_reserve(bo, true);
2746 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2747 /* if bo has been evicted, then no need to recover */
2748 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2749 r = amdgpu_bo_validate(bo->shadow);
2751 DRM_ERROR("bo validate failed!\n");
2755 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2758 DRM_ERROR("recover page table failed!\n");
2763 amdgpu_bo_unreserve(bo);
2768 * amdgpu_sriov_gpu_reset - reset the asic
2770 * @adev: amdgpu device pointer
2771 * @job: which job trigger hang
2773 * Attempt the reset the GPU if it has hung (all asics).
2775 * Returns 0 for success or an error on failure.
2777 int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
2781 struct amdgpu_bo *bo, *tmp;
2782 struct amdgpu_ring *ring;
2783 struct dma_fence *fence = NULL, *next = NULL;
2785 mutex_lock(&adev->virt.lock_reset);
2786 atomic_inc(&adev->gpu_reset_counter);
2787 adev->in_sriov_reset = true;
2790 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2792 /* we start from the ring trigger GPU hang */
2793 j = job ? job->ring->idx : 0;
2795 /* block scheduler */
2796 for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
2797 ring = adev->rings[i % AMDGPU_MAX_RINGS];
2798 if (!ring || !ring->sched.thread)
2801 kthread_park(ring->sched.thread);
2806 /* here give the last chance to check if job removed from mirror-list
2807 * since we already pay some time on kthread_park */
2808 if (job && list_empty(&job->base.node)) {
2809 kthread_unpark(ring->sched.thread);
2813 if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit))
2814 amd_sched_job_kickout(&job->base);
2816 /* only do job_reset on the hang ring if @job not NULL */
2817 amd_sched_hw_job_reset(&ring->sched);
2819 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2820 amdgpu_fence_driver_force_completion_ring(ring);
2823 /* request to take full control of GPU before re-initialization */
2825 amdgpu_virt_reset_gpu(adev);
2827 amdgpu_virt_request_full_gpu(adev, true);
2830 /* Resume IP prior to SMC */
2831 amdgpu_sriov_reinit_early(adev);
2833 /* we need recover gart prior to run SMC/CP/SDMA resume */
2834 amdgpu_ttm_recover_gart(adev);
2836 /* now we are okay to resume SMC/CP/SDMA */
2837 amdgpu_sriov_reinit_late(adev);
2839 amdgpu_irq_gpu_reset_resume_helper(adev);
2841 if (amdgpu_ib_ring_tests(adev))
2842 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2844 /* release full control of GPU after ib test */
2845 amdgpu_virt_release_full_gpu(adev, true);
2847 DRM_INFO("recover vram bo from shadow\n");
2849 ring = adev->mman.buffer_funcs_ring;
2850 mutex_lock(&adev->shadow_list_lock);
2851 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2853 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2855 r = dma_fence_wait(fence, false);
2857 WARN(r, "recovery from shadow isn't completed\n");
2862 dma_fence_put(fence);
2865 mutex_unlock(&adev->shadow_list_lock);
2868 r = dma_fence_wait(fence, false);
2870 WARN(r, "recovery from shadow isn't completed\n");
2872 dma_fence_put(fence);
2874 for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
2875 ring = adev->rings[i % AMDGPU_MAX_RINGS];
2876 if (!ring || !ring->sched.thread)
2879 if (job && j != i) {
2880 kthread_unpark(ring->sched.thread);
2884 amd_sched_job_recovery(&ring->sched);
2885 kthread_unpark(ring->sched.thread);
2888 drm_helper_resume_force_mode(adev->ddev);
2890 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2892 /* bad news, how to tell it to userspace ? */
2893 dev_info(adev->dev, "GPU reset failed\n");
2895 dev_info(adev->dev, "GPU reset successed!\n");
2898 adev->in_sriov_reset = false;
2899 mutex_unlock(&adev->virt.lock_reset);
2904 * amdgpu_gpu_reset - reset the asic
2906 * @adev: amdgpu device pointer
2908 * Attempt the reset the GPU if it has hung (all asics).
2909 * Returns 0 for success or an error on failure.
2911 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2915 bool need_full_reset, vram_lost = false;
2917 if (!amdgpu_check_soft_reset(adev)) {
2918 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2922 atomic_inc(&adev->gpu_reset_counter);
2925 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2927 /* block scheduler */
2928 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2929 struct amdgpu_ring *ring = adev->rings[i];
2931 if (!ring || !ring->sched.thread)
2933 kthread_park(ring->sched.thread);
2934 amd_sched_hw_job_reset(&ring->sched);
2936 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2937 amdgpu_fence_driver_force_completion(adev);
2939 need_full_reset = amdgpu_need_full_reset(adev);
2941 if (!need_full_reset) {
2942 amdgpu_pre_soft_reset(adev);
2943 r = amdgpu_soft_reset(adev);
2944 amdgpu_post_soft_reset(adev);
2945 if (r || amdgpu_check_soft_reset(adev)) {
2946 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2947 need_full_reset = true;
2951 if (need_full_reset) {
2952 r = amdgpu_suspend(adev);
2955 amdgpu_atombios_scratch_regs_save(adev);
2956 r = amdgpu_asic_reset(adev);
2957 amdgpu_atombios_scratch_regs_restore(adev);
2959 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2962 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2963 r = amdgpu_resume_phase1(adev);
2966 vram_lost = amdgpu_check_vram_lost(adev);
2968 DRM_ERROR("VRAM is lost!\n");
2969 atomic_inc(&adev->vram_lost_counter);
2971 r = amdgpu_ttm_recover_gart(adev);
2974 r = amdgpu_resume_phase2(adev);
2978 amdgpu_fill_reset_magic(adev);
2983 amdgpu_irq_gpu_reset_resume_helper(adev);
2984 r = amdgpu_ib_ring_tests(adev);
2986 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2987 r = amdgpu_suspend(adev);
2988 need_full_reset = true;
2992 * recovery vm page tables, since we cannot depend on VRAM is
2993 * consistent after gpu full reset.
2995 if (need_full_reset && amdgpu_need_backup(adev)) {
2996 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2997 struct amdgpu_bo *bo, *tmp;
2998 struct dma_fence *fence = NULL, *next = NULL;
3000 DRM_INFO("recover vram bo from shadow\n");
3001 mutex_lock(&adev->shadow_list_lock);
3002 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
3004 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
3006 r = dma_fence_wait(fence, false);
3008 WARN(r, "recovery from shadow isn't completed\n");
3013 dma_fence_put(fence);
3016 mutex_unlock(&adev->shadow_list_lock);
3018 r = dma_fence_wait(fence, false);
3020 WARN(r, "recovery from shadow isn't completed\n");
3022 dma_fence_put(fence);
3024 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3025 struct amdgpu_ring *ring = adev->rings[i];
3027 if (!ring || !ring->sched.thread)
3030 amd_sched_job_recovery(&ring->sched);
3031 kthread_unpark(ring->sched.thread);
3034 dev_err(adev->dev, "asic resume failed (%d).\n", r);
3035 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r);
3036 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3037 if (adev->rings[i] && adev->rings[i]->sched.thread) {
3038 kthread_unpark(adev->rings[i]->sched.thread);
3043 drm_helper_resume_force_mode(adev->ddev);
3045 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
3047 /* bad news, how to tell it to userspace ? */
3048 dev_info(adev->dev, "GPU reset failed\n");
3049 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3052 dev_info(adev->dev, "GPU reset successed!\n");
3055 amdgpu_vf_error_trans_all(adev);
3059 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
3064 if (amdgpu_pcie_gen_cap)
3065 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3067 if (amdgpu_pcie_lane_cap)
3068 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3070 /* covers APUs as well */
3071 if (pci_is_root_bus(adev->pdev->bus)) {
3072 if (adev->pm.pcie_gen_mask == 0)
3073 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3074 if (adev->pm.pcie_mlw_mask == 0)
3075 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3079 if (adev->pm.pcie_gen_mask == 0) {
3080 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
3082 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3083 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3084 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3086 if (mask & DRM_PCIE_SPEED_25)
3087 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3088 if (mask & DRM_PCIE_SPEED_50)
3089 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
3090 if (mask & DRM_PCIE_SPEED_80)
3091 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
3093 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3096 if (adev->pm.pcie_mlw_mask == 0) {
3097 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
3101 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3102 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3103 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3104 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3105 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3106 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3107 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3110 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3111 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3112 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3113 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3114 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3115 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3118 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3119 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3120 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3121 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3122 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3125 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3126 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3127 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3128 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3131 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3132 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3133 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3136 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3137 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3140 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3146 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3154 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3155 const struct drm_info_list *files,
3160 for (i = 0; i < adev->debugfs_count; i++) {
3161 if (adev->debugfs[i].files == files) {
3162 /* Already registered */
3167 i = adev->debugfs_count + 1;
3168 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
3169 DRM_ERROR("Reached maximum number of debugfs components.\n");
3170 DRM_ERROR("Report so we increase "
3171 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3174 adev->debugfs[adev->debugfs_count].files = files;
3175 adev->debugfs[adev->debugfs_count].num_files = nfiles;
3176 adev->debugfs_count = i;
3177 #if defined(CONFIG_DEBUG_FS)
3178 drm_debugfs_create_files(files, nfiles,
3179 adev->ddev->primary->debugfs_root,
3180 adev->ddev->primary);
3185 #if defined(CONFIG_DEBUG_FS)
3187 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3188 size_t size, loff_t *pos)
3190 struct amdgpu_device *adev = file_inode(f)->i_private;
3193 bool pm_pg_lock, use_bank;
3194 unsigned instance_bank, sh_bank, se_bank;
3196 if (size & 0x3 || *pos & 0x3)
3199 /* are we reading registers for which a PG lock is necessary? */
3200 pm_pg_lock = (*pos >> 23) & 1;
3202 if (*pos & (1ULL << 62)) {
3203 se_bank = (*pos >> 24) & 0x3FF;
3204 sh_bank = (*pos >> 34) & 0x3FF;
3205 instance_bank = (*pos >> 44) & 0x3FF;
3207 if (se_bank == 0x3FF)
3208 se_bank = 0xFFFFFFFF;
3209 if (sh_bank == 0x3FF)
3210 sh_bank = 0xFFFFFFFF;
3211 if (instance_bank == 0x3FF)
3212 instance_bank = 0xFFFFFFFF;
3218 *pos &= (1UL << 22) - 1;
3221 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3222 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3224 mutex_lock(&adev->grbm_idx_mutex);
3225 amdgpu_gfx_select_se_sh(adev, se_bank,
3226 sh_bank, instance_bank);
3230 mutex_lock(&adev->pm.mutex);
3235 if (*pos > adev->rmmio_size)
3238 value = RREG32(*pos >> 2);
3239 r = put_user(value, (uint32_t *)buf);
3253 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3254 mutex_unlock(&adev->grbm_idx_mutex);
3258 mutex_unlock(&adev->pm.mutex);
3263 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3264 size_t size, loff_t *pos)
3266 struct amdgpu_device *adev = file_inode(f)->i_private;
3269 bool pm_pg_lock, use_bank;
3270 unsigned instance_bank, sh_bank, se_bank;
3272 if (size & 0x3 || *pos & 0x3)
3275 /* are we reading registers for which a PG lock is necessary? */
3276 pm_pg_lock = (*pos >> 23) & 1;
3278 if (*pos & (1ULL << 62)) {
3279 se_bank = (*pos >> 24) & 0x3FF;
3280 sh_bank = (*pos >> 34) & 0x3FF;
3281 instance_bank = (*pos >> 44) & 0x3FF;
3283 if (se_bank == 0x3FF)
3284 se_bank = 0xFFFFFFFF;
3285 if (sh_bank == 0x3FF)
3286 sh_bank = 0xFFFFFFFF;
3287 if (instance_bank == 0x3FF)
3288 instance_bank = 0xFFFFFFFF;
3294 *pos &= (1UL << 22) - 1;
3297 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3298 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3300 mutex_lock(&adev->grbm_idx_mutex);
3301 amdgpu_gfx_select_se_sh(adev, se_bank,
3302 sh_bank, instance_bank);
3306 mutex_lock(&adev->pm.mutex);
3311 if (*pos > adev->rmmio_size)
3314 r = get_user(value, (uint32_t *)buf);
3318 WREG32(*pos >> 2, value);
3327 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3328 mutex_unlock(&adev->grbm_idx_mutex);
3332 mutex_unlock(&adev->pm.mutex);
3337 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
3338 size_t size, loff_t *pos)
3340 struct amdgpu_device *adev = file_inode(f)->i_private;
3344 if (size & 0x3 || *pos & 0x3)
3350 value = RREG32_PCIE(*pos >> 2);
3351 r = put_user(value, (uint32_t *)buf);
3364 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3365 size_t size, loff_t *pos)
3367 struct amdgpu_device *adev = file_inode(f)->i_private;
3371 if (size & 0x3 || *pos & 0x3)
3377 r = get_user(value, (uint32_t *)buf);
3381 WREG32_PCIE(*pos >> 2, value);
3392 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3393 size_t size, loff_t *pos)
3395 struct amdgpu_device *adev = file_inode(f)->i_private;
3399 if (size & 0x3 || *pos & 0x3)
3405 value = RREG32_DIDT(*pos >> 2);
3406 r = put_user(value, (uint32_t *)buf);
3419 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3420 size_t size, loff_t *pos)
3422 struct amdgpu_device *adev = file_inode(f)->i_private;
3426 if (size & 0x3 || *pos & 0x3)
3432 r = get_user(value, (uint32_t *)buf);
3436 WREG32_DIDT(*pos >> 2, value);
3447 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3448 size_t size, loff_t *pos)
3450 struct amdgpu_device *adev = file_inode(f)->i_private;
3454 if (size & 0x3 || *pos & 0x3)
3460 value = RREG32_SMC(*pos);
3461 r = put_user(value, (uint32_t *)buf);
3474 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3475 size_t size, loff_t *pos)
3477 struct amdgpu_device *adev = file_inode(f)->i_private;
3481 if (size & 0x3 || *pos & 0x3)
3487 r = get_user(value, (uint32_t *)buf);
3491 WREG32_SMC(*pos, value);
3502 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3503 size_t size, loff_t *pos)
3505 struct amdgpu_device *adev = file_inode(f)->i_private;
3508 uint32_t *config, no_regs = 0;
3510 if (size & 0x3 || *pos & 0x3)
3513 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3517 /* version, increment each time something is added */
3518 config[no_regs++] = 3;
3519 config[no_regs++] = adev->gfx.config.max_shader_engines;
3520 config[no_regs++] = adev->gfx.config.max_tile_pipes;
3521 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3522 config[no_regs++] = adev->gfx.config.max_sh_per_se;
3523 config[no_regs++] = adev->gfx.config.max_backends_per_se;
3524 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3525 config[no_regs++] = adev->gfx.config.max_gprs;
3526 config[no_regs++] = adev->gfx.config.max_gs_threads;
3527 config[no_regs++] = adev->gfx.config.max_hw_contexts;
3528 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3529 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3530 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3531 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3532 config[no_regs++] = adev->gfx.config.num_tile_pipes;
3533 config[no_regs++] = adev->gfx.config.backend_enable_mask;
3534 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3535 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3536 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3537 config[no_regs++] = adev->gfx.config.num_gpus;
3538 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3539 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3540 config[no_regs++] = adev->gfx.config.gb_addr_config;
3541 config[no_regs++] = adev->gfx.config.num_rbs;
3544 config[no_regs++] = adev->rev_id;
3545 config[no_regs++] = adev->pg_flags;
3546 config[no_regs++] = adev->cg_flags;
3549 config[no_regs++] = adev->family;
3550 config[no_regs++] = adev->external_rev_id;
3553 config[no_regs++] = adev->pdev->device;
3554 config[no_regs++] = adev->pdev->revision;
3555 config[no_regs++] = adev->pdev->subsystem_device;
3556 config[no_regs++] = adev->pdev->subsystem_vendor;
3558 while (size && (*pos < no_regs * 4)) {
3561 value = config[*pos >> 2];
3562 r = put_user(value, (uint32_t *)buf);
3578 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3579 size_t size, loff_t *pos)
3581 struct amdgpu_device *adev = file_inode(f)->i_private;
3582 int idx, x, outsize, r, valuesize;
3583 uint32_t values[16];
3585 if (size & 3 || *pos & 0x3)
3588 if (amdgpu_dpm == 0)
3591 /* convert offset to sensor number */
3594 valuesize = sizeof(values);
3595 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3596 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
3600 if (size > valuesize)
3607 r = put_user(values[x++], (int32_t *)buf);
3614 return !r ? outsize : r;
3617 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3618 size_t size, loff_t *pos)
3620 struct amdgpu_device *adev = f->f_inode->i_private;
3623 uint32_t offset, se, sh, cu, wave, simd, data[32];
3625 if (size & 3 || *pos & 3)
3629 offset = (*pos & 0x7F);
3630 se = ((*pos >> 7) & 0xFF);
3631 sh = ((*pos >> 15) & 0xFF);
3632 cu = ((*pos >> 23) & 0xFF);
3633 wave = ((*pos >> 31) & 0xFF);
3634 simd = ((*pos >> 37) & 0xFF);
3636 /* switch to the specific se/sh/cu */
3637 mutex_lock(&adev->grbm_idx_mutex);
3638 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3641 if (adev->gfx.funcs->read_wave_data)
3642 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3644 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3645 mutex_unlock(&adev->grbm_idx_mutex);
3650 while (size && (offset < x * 4)) {
3653 value = data[offset >> 2];
3654 r = put_user(value, (uint32_t *)buf);
3667 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3668 size_t size, loff_t *pos)
3670 struct amdgpu_device *adev = f->f_inode->i_private;
3673 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3675 if (size & 3 || *pos & 3)
3679 offset = (*pos & 0xFFF); /* in dwords */
3680 se = ((*pos >> 12) & 0xFF);
3681 sh = ((*pos >> 20) & 0xFF);
3682 cu = ((*pos >> 28) & 0xFF);
3683 wave = ((*pos >> 36) & 0xFF);
3684 simd = ((*pos >> 44) & 0xFF);
3685 thread = ((*pos >> 52) & 0xFF);
3686 bank = ((*pos >> 60) & 1);
3688 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3692 /* switch to the specific se/sh/cu */
3693 mutex_lock(&adev->grbm_idx_mutex);
3694 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3697 if (adev->gfx.funcs->read_wave_vgprs)
3698 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3700 if (adev->gfx.funcs->read_wave_sgprs)
3701 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3704 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3705 mutex_unlock(&adev->grbm_idx_mutex);
3710 value = data[offset++];
3711 r = put_user(value, (uint32_t *)buf);
3727 static const struct file_operations amdgpu_debugfs_regs_fops = {
3728 .owner = THIS_MODULE,
3729 .read = amdgpu_debugfs_regs_read,
3730 .write = amdgpu_debugfs_regs_write,
3731 .llseek = default_llseek
3733 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3734 .owner = THIS_MODULE,
3735 .read = amdgpu_debugfs_regs_didt_read,
3736 .write = amdgpu_debugfs_regs_didt_write,
3737 .llseek = default_llseek
3739 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3740 .owner = THIS_MODULE,
3741 .read = amdgpu_debugfs_regs_pcie_read,
3742 .write = amdgpu_debugfs_regs_pcie_write,
3743 .llseek = default_llseek
3745 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3746 .owner = THIS_MODULE,
3747 .read = amdgpu_debugfs_regs_smc_read,
3748 .write = amdgpu_debugfs_regs_smc_write,
3749 .llseek = default_llseek
3752 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3753 .owner = THIS_MODULE,
3754 .read = amdgpu_debugfs_gca_config_read,
3755 .llseek = default_llseek
3758 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3759 .owner = THIS_MODULE,
3760 .read = amdgpu_debugfs_sensor_read,
3761 .llseek = default_llseek
3764 static const struct file_operations amdgpu_debugfs_wave_fops = {
3765 .owner = THIS_MODULE,
3766 .read = amdgpu_debugfs_wave_read,
3767 .llseek = default_llseek
3769 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3770 .owner = THIS_MODULE,
3771 .read = amdgpu_debugfs_gpr_read,
3772 .llseek = default_llseek
3775 static const struct file_operations *debugfs_regs[] = {
3776 &amdgpu_debugfs_regs_fops,
3777 &amdgpu_debugfs_regs_didt_fops,
3778 &amdgpu_debugfs_regs_pcie_fops,
3779 &amdgpu_debugfs_regs_smc_fops,
3780 &amdgpu_debugfs_gca_config_fops,
3781 &amdgpu_debugfs_sensors_fops,
3782 &amdgpu_debugfs_wave_fops,
3783 &amdgpu_debugfs_gpr_fops,
3786 static const char *debugfs_regs_names[] = {
3791 "amdgpu_gca_config",
3797 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3799 struct drm_minor *minor = adev->ddev->primary;
3800 struct dentry *ent, *root = minor->debugfs_root;
3803 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3804 ent = debugfs_create_file(debugfs_regs_names[i],
3805 S_IFREG | S_IRUGO, root,
3806 adev, debugfs_regs[i]);
3808 for (j = 0; j < i; j++) {
3809 debugfs_remove(adev->debugfs_regs[i]);
3810 adev->debugfs_regs[i] = NULL;
3812 return PTR_ERR(ent);
3816 i_size_write(ent->d_inode, adev->rmmio_size);
3817 adev->debugfs_regs[i] = ent;
3823 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3827 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3828 if (adev->debugfs_regs[i]) {
3829 debugfs_remove(adev->debugfs_regs[i]);
3830 adev->debugfs_regs[i] = NULL;
3835 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
3837 struct drm_info_node *node = (struct drm_info_node *) m->private;
3838 struct drm_device *dev = node->minor->dev;
3839 struct amdgpu_device *adev = dev->dev_private;
3842 /* hold on the scheduler */
3843 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3844 struct amdgpu_ring *ring = adev->rings[i];
3846 if (!ring || !ring->sched.thread)
3848 kthread_park(ring->sched.thread);
3851 seq_printf(m, "run ib test:\n");
3852 r = amdgpu_ib_ring_tests(adev);
3854 seq_printf(m, "ib ring tests failed (%d).\n", r);
3856 seq_printf(m, "ib ring tests passed.\n");
3858 /* go on the scheduler */
3859 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3860 struct amdgpu_ring *ring = adev->rings[i];
3862 if (!ring || !ring->sched.thread)
3864 kthread_unpark(ring->sched.thread);
3870 static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
3871 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
3874 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
3876 return amdgpu_debugfs_add_files(adev,
3877 amdgpu_debugfs_test_ib_ring_list, 1);
3880 int amdgpu_debugfs_init(struct drm_minor *minor)
3885 static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
3887 struct drm_info_node *node = (struct drm_info_node *) m->private;
3888 struct drm_device *dev = node->minor->dev;
3889 struct amdgpu_device *adev = dev->dev_private;
3891 seq_write(m, adev->bios, adev->bios_size);
3895 static const struct drm_info_list amdgpu_vbios_dump_list[] = {
3897 amdgpu_debugfs_get_vbios_dump,
3901 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
3903 return amdgpu_debugfs_add_files(adev,
3904 amdgpu_vbios_dump_list, 1);
3907 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
3911 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3915 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
3919 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }