2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <drm/amdgpu_drm.h>
26 #include "atomfirmware.h"
27 #include "amdgpu_atomfirmware.h"
30 #include "soc15_hw_ip.h"
32 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
34 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
38 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
39 NULL, NULL, &data_offset)) {
40 struct atom_firmware_info_v3_1 *firmware_info =
41 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
44 if (le32_to_cpu(firmware_info->firmware_capability) &
45 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
51 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
53 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
57 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
58 NULL, NULL, &data_offset)) {
59 struct atom_firmware_info_v3_1 *firmware_info =
60 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
63 adev->bios_scratch_reg_offset =
64 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
68 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
70 struct atom_context *ctx = adev->mode_info.atom_context;
71 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
72 vram_usagebyfirmware);
73 struct vram_usagebyfirmware_v2_1 *firmware_usage;
74 uint32_t start_addr, size;
78 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
79 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
80 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
81 le32_to_cpu(firmware_usage->start_address_in_kb),
82 le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
83 le16_to_cpu(firmware_usage->used_by_driver_in_kb));
85 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
86 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
88 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
89 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
90 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
91 /* Firmware request VRAM reservation for SR-IOV */
92 adev->mman.fw_vram_usage_start_offset = (start_addr &
93 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
94 adev->mman.fw_vram_usage_size = size << 10;
95 /* Use the default scratch size */
98 usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
101 ctx->scratch_size_bytes = 0;
102 if (usage_bytes == 0)
103 usage_bytes = 20 * 1024;
104 /* allocate some scratch memory */
105 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
108 ctx->scratch_size_bytes = usage_bytes;
113 struct atom_integrated_system_info_v1_11 v11;
114 struct atom_integrated_system_info_v1_12 v12;
118 struct atom_umc_info_v3_1 v31;
122 struct atom_vram_info_header_v2_3 v23;
123 struct atom_vram_info_header_v2_4 v24;
124 struct atom_vram_info_header_v2_5 v25;
128 struct atom_vram_module_v9 v9;
129 struct atom_vram_module_v10 v10;
130 struct atom_vram_module_v11 v11;
133 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
138 if (adev->flags & AMD_IS_APU) {
139 switch (atom_mem_type) {
142 vram_type = AMDGPU_VRAM_TYPE_DDR2;
146 vram_type = AMDGPU_VRAM_TYPE_DDR3;
150 vram_type = AMDGPU_VRAM_TYPE_DDR4;
154 vram_type = AMDGPU_VRAM_TYPE_DDR5;
157 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
161 switch (atom_mem_type) {
162 case ATOM_DGPU_VRAM_TYPE_GDDR5:
163 vram_type = AMDGPU_VRAM_TYPE_GDDR5;
165 case ATOM_DGPU_VRAM_TYPE_HBM2:
166 vram_type = AMDGPU_VRAM_TYPE_HBM;
168 case ATOM_DGPU_VRAM_TYPE_GDDR6:
169 vram_type = AMDGPU_VRAM_TYPE_GDDR6;
172 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
182 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
183 int *vram_width, int *vram_type,
186 struct amdgpu_mode_info *mode_info = &adev->mode_info;
188 u16 data_offset, size;
189 union igp_info *igp_info;
190 union vram_info *vram_info;
191 union vram_module *vram_module;
195 u32 mem_channel_number;
196 u32 mem_channel_width;
199 if (adev->flags & AMD_IS_APU)
200 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
201 integratedsysteminfo);
203 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
206 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
208 &frev, &crev, &data_offset)) {
209 if (adev->flags & AMD_IS_APU) {
210 igp_info = (union igp_info *)
211 (mode_info->atom_context->bios + data_offset);
214 mem_channel_number = igp_info->v11.umachannelnumber;
215 /* channel width is 64 */
217 *vram_width = mem_channel_number * 64;
218 mem_type = igp_info->v11.memorytype;
220 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
223 mem_channel_number = igp_info->v12.umachannelnumber;
224 /* channel width is 64 */
226 *vram_width = mem_channel_number * 64;
227 mem_type = igp_info->v12.memorytype;
229 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
235 vram_info = (union vram_info *)
236 (mode_info->atom_context->bios + data_offset);
237 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
240 if (module_id > vram_info->v23.vram_module_num)
242 vram_module = (union vram_module *)vram_info->v23.vram_module;
243 while (i < module_id) {
244 vram_module = (union vram_module *)
245 ((u8 *)vram_module + vram_module->v9.vram_module_size);
248 mem_type = vram_module->v9.memory_type;
250 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
251 mem_channel_number = vram_module->v9.channel_num;
252 mem_channel_width = vram_module->v9.channel_width;
254 *vram_width = mem_channel_number * (1 << mem_channel_width);
255 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
257 *vram_vendor = mem_vendor;
260 if (module_id > vram_info->v24.vram_module_num)
262 vram_module = (union vram_module *)vram_info->v24.vram_module;
263 while (i < module_id) {
264 vram_module = (union vram_module *)
265 ((u8 *)vram_module + vram_module->v10.vram_module_size);
268 mem_type = vram_module->v10.memory_type;
270 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
271 mem_channel_number = vram_module->v10.channel_num;
272 mem_channel_width = vram_module->v10.channel_width;
274 *vram_width = mem_channel_number * (1 << mem_channel_width);
275 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
277 *vram_vendor = mem_vendor;
280 if (module_id > vram_info->v25.vram_module_num)
282 vram_module = (union vram_module *)vram_info->v25.vram_module;
283 while (i < module_id) {
284 vram_module = (union vram_module *)
285 ((u8 *)vram_module + vram_module->v11.vram_module_size);
288 mem_type = vram_module->v11.memory_type;
290 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
291 mem_channel_number = vram_module->v11.channel_num;
292 mem_channel_width = vram_module->v11.channel_width;
294 *vram_width = mem_channel_number * (1 << mem_channel_width);
295 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
297 *vram_vendor = mem_vendor;
310 * Return true if vbios enabled ecc by default, if umc info table is available
311 * or false if ecc is not enabled or umc info table is not available
313 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
315 struct amdgpu_mode_info *mode_info = &adev->mode_info;
317 u16 data_offset, size;
318 union umc_info *umc_info;
320 bool ecc_default_enabled = false;
322 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
325 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
326 index, &size, &frev, &crev, &data_offset)) {
327 /* support umc_info 3.1+ */
328 if ((frev == 3 && crev >= 1) || (frev > 3)) {
329 umc_info = (union umc_info *)
330 (mode_info->atom_context->bios + data_offset);
331 ecc_default_enabled =
332 (le32_to_cpu(umc_info->v31.umc_config) &
333 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
337 return ecc_default_enabled;
340 union firmware_info {
341 struct atom_firmware_info_v3_1 v31;
342 struct atom_firmware_info_v3_2 v32;
343 struct atom_firmware_info_v3_3 v33;
344 struct atom_firmware_info_v3_4 v34;
348 * Return true if vbios supports sram ecc or false if not
350 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
352 struct amdgpu_mode_info *mode_info = &adev->mode_info;
354 u16 data_offset, size;
355 union firmware_info *firmware_info;
357 bool sram_ecc_supported = false;
359 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
362 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
363 index, &size, &frev, &crev, &data_offset)) {
364 /* support firmware_info 3.1 + */
365 if ((frev == 3 && crev >=1) || (frev > 3)) {
366 firmware_info = (union firmware_info *)
367 (mode_info->atom_context->bios + data_offset);
369 (le32_to_cpu(firmware_info->v31.firmware_capability) &
370 ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
374 return sram_ecc_supported;
378 struct atom_smu_info_v3_1 v31;
381 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
383 struct amdgpu_mode_info *mode_info = &adev->mode_info;
384 struct amdgpu_pll *spll = &adev->clock.spll;
385 struct amdgpu_pll *mpll = &adev->clock.mpll;
387 uint16_t data_offset;
388 int ret = -EINVAL, index;
390 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
392 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
393 &frev, &crev, &data_offset)) {
394 union firmware_info *firmware_info =
395 (union firmware_info *)(mode_info->atom_context->bios +
398 adev->clock.default_sclk =
399 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
400 adev->clock.default_mclk =
401 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
403 adev->pm.current_sclk = adev->clock.default_sclk;
404 adev->pm.current_mclk = adev->clock.default_mclk;
406 /* not technically a clock, but... */
407 adev->mode_info.firmware_flags =
408 le32_to_cpu(firmware_info->v31.firmware_capability);
413 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
415 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
416 &frev, &crev, &data_offset)) {
417 union smu_info *smu_info =
418 (union smu_info *)(mode_info->atom_context->bios +
422 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
424 spll->reference_div = 0;
425 spll->min_post_div = 1;
426 spll->max_post_div = 1;
427 spll->min_ref_div = 2;
428 spll->max_ref_div = 0xff;
429 spll->min_feedback_div = 4;
430 spll->max_feedback_div = 0xff;
436 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
438 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
439 &frev, &crev, &data_offset)) {
440 union umc_info *umc_info =
441 (union umc_info *)(mode_info->atom_context->bios +
445 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
447 mpll->reference_div = 0;
448 mpll->min_post_div = 1;
449 mpll->max_post_div = 1;
450 mpll->min_ref_div = 2;
451 mpll->max_ref_div = 0xff;
452 mpll->min_feedback_div = 4;
453 mpll->max_feedback_div = 0xff;
463 struct atom_gfx_info_v2_4 v24;
466 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
468 struct amdgpu_mode_info *mode_info = &adev->mode_info;
471 uint16_t data_offset;
473 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
475 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
476 &frev, &crev, &data_offset)) {
477 union gfx_info *gfx_info = (union gfx_info *)
478 (mode_info->atom_context->bios + data_offset);
481 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
482 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
483 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
484 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
485 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
486 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
487 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
488 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
489 adev->gfx.config.gs_prim_buffer_depth =
490 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
491 adev->gfx.config.double_offchip_lds_buf =
492 gfx_info->v24.gc_double_offchip_lds_buffer;
493 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
494 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
495 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
496 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
507 * Check if VBIOS supports GDDR6 training data save/restore
509 static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
511 uint16_t data_offset;
514 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
516 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
517 NULL, NULL, &data_offset)) {
518 struct atom_firmware_info_v3_1 *firmware_info =
519 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
522 DRM_DEBUG("atom firmware capability:0x%08x.\n",
523 le32_to_cpu(firmware_info->firmware_capability));
525 if (le32_to_cpu(firmware_info->firmware_capability) &
526 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
533 int amdgpu_mem_train_support(struct amdgpu_device *adev)
536 uint32_t major, minor, revision, hw_v;
538 if (gddr6_mem_train_vbios_support(adev)) {
539 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
540 hw_v = HW_REV(major, minor, revision);
542 * treat 0 revision as a special case since register for MP0 and MMHUB is missing
543 * for some Navi10 A0, preventing driver from discovering the hwip information since
544 * none of the functions will be initialized, it should not cause any problems
547 case HW_REV(11, 0, 0):
548 case HW_REV(11, 0, 5):
549 case HW_REV(11, 0, 7):
550 case HW_REV(11, 0, 11):
551 case HW_REV(11, 0, 12):
555 DRM_ERROR("memory training vbios supports but psp hw(%08x)"
556 " doesn't support!\n", hw_v);
566 DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
570 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
572 struct atom_context *ctx = adev->mode_info.atom_context;
573 union firmware_info *firmware_info;
575 u16 data_offset, size;
577 int fw_reserved_fb_size;
579 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
582 if (!amdgpu_atom_parse_data_header(ctx, index, &size,
583 &frev, &crev, &data_offset))
584 /* fail to parse data_header */
587 firmware_info = (union firmware_info *)(ctx->bios + data_offset);
594 fw_reserved_fb_size =
595 (firmware_info->v34.fw_reserved_size_in_kb << 10);
598 fw_reserved_fb_size = 0;
602 return fw_reserved_fb_size;