1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Spreadtrum Communications Inc.
4 * Copyright (C) 2018 Linaro Ltd.
7 #include <linux/bitops.h>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/spinlock.h>
16 /* EIC registers definition */
17 #define SPRD_EIC_DBNC_DATA 0x0
18 #define SPRD_EIC_DBNC_DMSK 0x4
19 #define SPRD_EIC_DBNC_IEV 0x14
20 #define SPRD_EIC_DBNC_IE 0x18
21 #define SPRD_EIC_DBNC_RIS 0x1c
22 #define SPRD_EIC_DBNC_MIS 0x20
23 #define SPRD_EIC_DBNC_IC 0x24
24 #define SPRD_EIC_DBNC_TRIG 0x28
25 #define SPRD_EIC_DBNC_CTRL0 0x40
27 #define SPRD_EIC_LATCH_INTEN 0x0
28 #define SPRD_EIC_LATCH_INTRAW 0x4
29 #define SPRD_EIC_LATCH_INTMSK 0x8
30 #define SPRD_EIC_LATCH_INTCLR 0xc
31 #define SPRD_EIC_LATCH_INTPOL 0x10
32 #define SPRD_EIC_LATCH_INTMODE 0x14
34 #define SPRD_EIC_ASYNC_INTIE 0x0
35 #define SPRD_EIC_ASYNC_INTRAW 0x4
36 #define SPRD_EIC_ASYNC_INTMSK 0x8
37 #define SPRD_EIC_ASYNC_INTCLR 0xc
38 #define SPRD_EIC_ASYNC_INTMODE 0x10
39 #define SPRD_EIC_ASYNC_INTBOTH 0x14
40 #define SPRD_EIC_ASYNC_INTPOL 0x18
41 #define SPRD_EIC_ASYNC_DATA 0x1c
43 #define SPRD_EIC_SYNC_INTIE 0x0
44 #define SPRD_EIC_SYNC_INTRAW 0x4
45 #define SPRD_EIC_SYNC_INTMSK 0x8
46 #define SPRD_EIC_SYNC_INTCLR 0xc
47 #define SPRD_EIC_SYNC_INTMODE 0x10
48 #define SPRD_EIC_SYNC_INTBOTH 0x14
49 #define SPRD_EIC_SYNC_INTPOL 0x18
50 #define SPRD_EIC_SYNC_DATA 0x1c
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
56 #define SPRD_EIC_MAX_BANK 3
57 #define SPRD_EIC_PER_BANK_NR 8
58 #define SPRD_EIC_DATA_MASK GENMASK(7, 0)
59 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
60 #define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
63 * The Spreadtrum EIC (external interrupt controller) can be used only in
64 * input mode to generate interrupts if detecting input signals.
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
67 * debounce EIC, latch EIC, async EIC and sync EIC,
69 * The debounce EIC is used to capture the input signals' stable status
70 * (millisecond resolution) and a single-trigger mechanism is introduced
71 * into this sub-module to enhance the input event detection reliability.
72 * The debounce range is from 1ms to 4s with a step size of 1ms.
74 * The latch EIC is used to latch some special power down signals and
75 * generate interrupts, since the latch EIC does not depend on the APB clock
78 * The async EIC uses a 32k clock to capture the short signals (microsecond
79 * resolution) to generate interrupts by level or edge trigger.
81 * The EIC-sync is similar with GPIO's input function, which is a synchronized
82 * signal input register.
93 struct gpio_chip chip;
95 void __iomem *base[SPRD_EIC_MAX_BANK];
96 enum sprd_eic_type type;
101 struct sprd_eic_variant_data {
102 enum sprd_eic_type type;
106 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
107 "eic-debounce", "eic-latch", "eic-async",
111 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
112 .type = SPRD_EIC_DEBOUNCE,
116 static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
117 .type = SPRD_EIC_LATCH,
121 static const struct sprd_eic_variant_data sc9860_eic_async_data = {
122 .type = SPRD_EIC_ASYNC,
126 static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
127 .type = SPRD_EIC_SYNC,
131 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
134 if (bank >= SPRD_EIC_MAX_BANK)
137 return sprd_eic->base[bank];
140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
141 u16 reg, unsigned int val)
143 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
145 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
149 spin_lock_irqsave(&sprd_eic->lock, flags);
150 tmp = readl_relaxed(base + reg);
153 tmp |= BIT(SPRD_EIC_BIT(offset));
155 tmp &= ~BIT(SPRD_EIC_BIT(offset));
157 writel_relaxed(tmp, base + reg);
158 spin_unlock_irqrestore(&sprd_eic->lock, flags);
161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
163 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
165 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
167 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
172 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
178 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
181 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
183 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
186 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
188 /* EICs are always input, nothing need to do here. */
192 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
194 /* EICs are always input, nothing need to do here. */
197 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
198 unsigned int debounce)
200 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
202 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
203 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
204 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
206 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
207 writel_relaxed(value, base + reg);
212 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
213 unsigned long config)
215 unsigned long param = pinconf_to_config_param(config);
216 u32 arg = pinconf_to_config_argument(config);
218 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
219 return sprd_eic_set_debounce(chip, offset, arg);
224 static void sprd_eic_irq_mask(struct irq_data *data)
226 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
227 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
228 u32 offset = irqd_to_hwirq(data);
230 switch (sprd_eic->type) {
231 case SPRD_EIC_DEBOUNCE:
232 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
233 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
236 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
239 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
242 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
245 dev_err(chip->parent, "Unsupported EIC type.\n");
249 static void sprd_eic_irq_unmask(struct irq_data *data)
251 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
252 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
253 u32 offset = irqd_to_hwirq(data);
255 switch (sprd_eic->type) {
256 case SPRD_EIC_DEBOUNCE:
257 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
258 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
261 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
264 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
267 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
270 dev_err(chip->parent, "Unsupported EIC type.\n");
274 static void sprd_eic_irq_ack(struct irq_data *data)
276 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
277 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
278 u32 offset = irqd_to_hwirq(data);
280 switch (sprd_eic->type) {
281 case SPRD_EIC_DEBOUNCE:
282 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
285 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
288 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
291 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
294 dev_err(chip->parent, "Unsupported EIC type.\n");
298 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
300 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
301 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
302 u32 offset = irqd_to_hwirq(data);
305 switch (sprd_eic->type) {
306 case SPRD_EIC_DEBOUNCE:
308 case IRQ_TYPE_LEVEL_HIGH:
309 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
311 case IRQ_TYPE_LEVEL_LOW:
312 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
314 case IRQ_TYPE_EDGE_RISING:
315 case IRQ_TYPE_EDGE_FALLING:
316 case IRQ_TYPE_EDGE_BOTH:
317 state = sprd_eic_get(chip, offset);
319 sprd_eic_update(chip, offset,
320 SPRD_EIC_DBNC_IEV, 0);
322 sprd_eic_update(chip, offset,
323 SPRD_EIC_DBNC_IEV, 1);
329 irq_set_handler_locked(data, handle_level_irq);
333 case IRQ_TYPE_LEVEL_HIGH:
334 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
336 case IRQ_TYPE_LEVEL_LOW:
337 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
339 case IRQ_TYPE_EDGE_RISING:
340 case IRQ_TYPE_EDGE_FALLING:
341 case IRQ_TYPE_EDGE_BOTH:
342 state = sprd_eic_get(chip, offset);
344 sprd_eic_update(chip, offset,
345 SPRD_EIC_LATCH_INTPOL, 0);
347 sprd_eic_update(chip, offset,
348 SPRD_EIC_LATCH_INTPOL, 1);
354 irq_set_handler_locked(data, handle_level_irq);
358 case IRQ_TYPE_EDGE_RISING:
359 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
360 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
361 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
362 irq_set_handler_locked(data, handle_edge_irq);
364 case IRQ_TYPE_EDGE_FALLING:
365 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
366 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
367 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
368 irq_set_handler_locked(data, handle_edge_irq);
370 case IRQ_TYPE_EDGE_BOTH:
371 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
372 irq_set_handler_locked(data, handle_edge_irq);
374 case IRQ_TYPE_LEVEL_HIGH:
375 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
376 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
377 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
378 irq_set_handler_locked(data, handle_level_irq);
380 case IRQ_TYPE_LEVEL_LOW:
381 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
382 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
383 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
384 irq_set_handler_locked(data, handle_level_irq);
392 case IRQ_TYPE_EDGE_RISING:
393 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
394 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
395 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
396 irq_set_handler_locked(data, handle_edge_irq);
398 case IRQ_TYPE_EDGE_FALLING:
399 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
400 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
401 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
402 irq_set_handler_locked(data, handle_edge_irq);
404 case IRQ_TYPE_EDGE_BOTH:
405 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
406 irq_set_handler_locked(data, handle_edge_irq);
408 case IRQ_TYPE_LEVEL_HIGH:
409 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
410 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
411 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
412 irq_set_handler_locked(data, handle_level_irq);
414 case IRQ_TYPE_LEVEL_LOW:
415 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
416 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
417 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
418 irq_set_handler_locked(data, handle_level_irq);
424 dev_err(chip->parent, "Unsupported EIC type.\n");
431 static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
434 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
435 struct irq_data *data = irq_get_irq_data(irq);
436 u32 trigger = irqd_get_trigger_type(data);
437 int state, post_state;
440 * The debounce EIC and latch EIC can only support level trigger, so we
441 * can toggle the level trigger to emulate the edge trigger.
443 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
444 sprd_eic->type != SPRD_EIC_LATCH) ||
445 !(trigger & IRQ_TYPE_EDGE_BOTH))
448 sprd_eic_irq_mask(data);
449 state = sprd_eic_get(chip, offset);
452 switch (sprd_eic->type) {
453 case SPRD_EIC_DEBOUNCE:
455 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
457 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
461 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
463 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
466 sprd_eic_irq_unmask(data);
470 post_state = sprd_eic_get(chip, offset);
471 if (state != post_state) {
472 dev_warn(chip->parent, "EIC level was changed.\n");
477 sprd_eic_irq_unmask(data);
480 static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data)
482 enum sprd_eic_type type = *(enum sprd_eic_type *)data;
484 return !strcmp(chip->label, sprd_eic_label_name[type]);
487 static void sprd_eic_handle_one_type(struct gpio_chip *chip)
489 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
492 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
493 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
496 switch (sprd_eic->type) {
497 case SPRD_EIC_DEBOUNCE:
498 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
502 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
506 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
510 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
514 dev_err(chip->parent, "Unsupported EIC type.\n");
518 for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) {
519 girq = irq_find_mapping(chip->irq.domain,
520 bank * SPRD_EIC_PER_BANK_NR + n);
522 generic_handle_irq(girq);
523 sprd_eic_toggle_trigger(chip, girq, n);
528 static void sprd_eic_irq_handler(struct irq_desc *desc)
530 struct irq_chip *ic = irq_desc_get_chip(desc);
531 struct gpio_chip *chip;
532 enum sprd_eic_type type;
534 chained_irq_enter(ic, desc);
537 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
538 * and sync) share one same interrupt line, we should iterate each
539 * EIC module to check if there are EIC interrupts were triggered.
541 for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) {
542 chip = gpiochip_find(&type, sprd_eic_match_chip_by_type);
546 sprd_eic_handle_one_type(chip);
549 chained_irq_exit(ic, desc);
552 static int sprd_eic_probe(struct platform_device *pdev)
554 const struct sprd_eic_variant_data *pdata;
555 struct gpio_irq_chip *irq;
556 struct sprd_eic *sprd_eic;
557 struct resource *res;
560 pdata = of_device_get_match_data(&pdev->dev);
562 dev_err(&pdev->dev, "No matching driver data found.\n");
566 sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL);
570 spin_lock_init(&sprd_eic->lock);
571 sprd_eic->type = pdata->type;
573 sprd_eic->irq = platform_get_irq(pdev, 0);
574 if (sprd_eic->irq < 0) {
575 dev_err(&pdev->dev, "Failed to get EIC interrupt.\n");
576 return sprd_eic->irq;
579 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
581 * We can have maximum 3 banks EICs, and each EIC has
582 * its own base address. But some platform maybe only
583 * have one bank EIC, thus base[1] and base[2] can be
586 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
590 sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
591 if (IS_ERR(sprd_eic->base[i]))
592 return PTR_ERR(sprd_eic->base[i]);
595 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
596 sprd_eic->chip.ngpio = pdata->num_eics;
597 sprd_eic->chip.base = -1;
598 sprd_eic->chip.parent = &pdev->dev;
599 sprd_eic->chip.of_node = pdev->dev.of_node;
600 sprd_eic->chip.direction_input = sprd_eic_direction_input;
601 switch (sprd_eic->type) {
602 case SPRD_EIC_DEBOUNCE:
603 sprd_eic->chip.request = sprd_eic_request;
604 sprd_eic->chip.free = sprd_eic_free;
605 sprd_eic->chip.set_config = sprd_eic_set_config;
606 sprd_eic->chip.set = sprd_eic_set;
611 sprd_eic->chip.get = sprd_eic_get;
619 sprd_eic->intc.name = dev_name(&pdev->dev);
620 sprd_eic->intc.irq_ack = sprd_eic_irq_ack;
621 sprd_eic->intc.irq_mask = sprd_eic_irq_mask;
622 sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask;
623 sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type;
624 sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
626 irq = &sprd_eic->chip.irq;
627 irq->chip = &sprd_eic->intc;
628 irq->handler = handle_bad_irq;
629 irq->default_type = IRQ_TYPE_NONE;
630 irq->parent_handler = sprd_eic_irq_handler;
631 irq->parent_handler_data = sprd_eic;
632 irq->num_parents = 1;
633 irq->parents = &sprd_eic->irq;
635 ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic);
637 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
641 platform_set_drvdata(pdev, sprd_eic);
645 static const struct of_device_id sprd_eic_of_match[] = {
647 .compatible = "sprd,sc9860-eic-debounce",
648 .data = &sc9860_eic_dbnc_data,
651 .compatible = "sprd,sc9860-eic-latch",
652 .data = &sc9860_eic_latch_data,
655 .compatible = "sprd,sc9860-eic-async",
656 .data = &sc9860_eic_async_data,
659 .compatible = "sprd,sc9860-eic-sync",
660 .data = &sc9860_eic_sync_data,
666 MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
668 static struct platform_driver sprd_eic_driver = {
669 .probe = sprd_eic_probe,
672 .of_match_table = sprd_eic_of_match,
676 module_platform_driver(sprd_eic_driver);
678 MODULE_DESCRIPTION("Spreadtrum EIC driver");
679 MODULE_LICENSE("GPL v2");