drivers/firewire/fw-ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/compiler.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/gfp.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/kernel.h>
  28 #include <linux/mm.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/spinlock.h>
  32
  33 #include <asm/page.h>
  34 #include <asm/system.h>
  35
  36 #include "fw-ohci.h"
  37 #include "fw-transaction.h"
  38
  39 #define DESCRIPTOR_OUTPUT_MORE          0
  40 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  41 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  42 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  43 #define DESCRIPTOR_STATUS               (1 << 11)
  44 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  45 #define DESCRIPTOR_PING                 (1 << 7)
  46 #define DESCRIPTOR_YY                   (1 << 6)
  47 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  48 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  49 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  50 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  51 #define DESCRIPTOR_WAIT                 (3 << 0)
  52
  53 struct descriptor {
  54         __le16 req_count;
  55         __le16 control;
  56         __le32 data_address;
  57         __le32 branch_address;
  58         __le16 res_count;
  59         __le16 transfer_status;
  60 } __attribute__((aligned(16)));
  61
  62 struct db_descriptor {
  63         __le16 first_size;
  64         __le16 control;
  65         __le16 second_req_count;
  66         __le16 first_req_count;
  67         __le32 branch_address;
  68         __le16 second_res_count;
  69         __le16 first_res_count;
  70         __le32 reserved0;
  71         __le32 first_buffer;
  72         __le32 second_buffer;
  73         __le32 reserved1;
  74 } __attribute__((aligned(16)));
  75
  76 #define CONTROL_SET(regs)       (regs)
  77 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  78 #define COMMAND_PTR(regs)       ((regs) + 12)
  79 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  80
  81 struct ar_buffer {
  82         struct descriptor descriptor;
  83         struct ar_buffer *next;
  84         __le32 data[0];
  85 };
  86
  87 struct ar_context {
  88         struct fw_ohci *ohci;
  89         struct ar_buffer *current_buffer;
  90         struct ar_buffer *last_buffer;
  91         void *pointer;
  92         u32 regs;
  93         struct tasklet_struct tasklet;
  94 };
  95
  96 struct context;
  97
  98 typedef int (*descriptor_callback_t)(struct context *ctx,
  99                                      struct descriptor *d,
 100                                      struct descriptor *last);
 101 struct context {
 102         struct fw_ohci *ohci;
 103         u32 regs;
 104
 105         struct descriptor *buffer;
 106         dma_addr_t buffer_bus;
 107         size_t buffer_size;
 108         struct descriptor *head_descriptor;
 109         struct descriptor *tail_descriptor;
 110         struct descriptor *tail_descriptor_last;
 111         struct descriptor *prev_descriptor;
 112
 113         descriptor_callback_t callback;
 114
 115         struct tasklet_struct tasklet;
 116 };
 117
 118 #define IT_HEADER_SY(v)          ((v) <<  0)
 119 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 120 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 121 #define IT_HEADER_TAG(v)         ((v) << 14)
 122 #define IT_HEADER_SPEED(v)       ((v) << 16)
 123 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 124
 125 struct iso_context {
 126         struct fw_iso_context base;
 127         struct context context;
 128         void *header;
 129         size_t header_length;
 130 };
 131
 132 #define CONFIG_ROM_SIZE 1024
 133
 134 struct fw_ohci {
 135         struct fw_card card;
 136
 137         u32 version;
 138         __iomem char *registers;
 139         dma_addr_t self_id_bus;
 140         __le32 *self_id_cpu;
 141         struct tasklet_struct bus_reset_tasklet;
 142         int node_id;
 143         int generation;
 144         int request_generation;
 145         u32 bus_seconds;
 146
 147         /*
 148          * Spinlock for accessing fw_ohci data.  Never call out of
 149          * this driver with this lock held.
 150          */
 151         spinlock_t lock;
 152         u32 self_id_buffer[512];
 153
 154         /* Config rom buffers */
 155         __be32 *config_rom;
 156         dma_addr_t config_rom_bus;
 157         __be32 *next_config_rom;
 158         dma_addr_t next_config_rom_bus;
 159         u32 next_header;
 160
 161         struct ar_context ar_request_ctx;
 162         struct ar_context ar_response_ctx;
 163         struct context at_request_ctx;
 164         struct context at_response_ctx;
 165
 166         u32 it_context_mask;
 167         struct iso_context *it_context_list;
 168         u32 ir_context_mask;
 169         struct iso_context *ir_context_list;
 170 };
 171
 172 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 173 {
 174         return container_of(card, struct fw_ohci, card);
 175 }
 176
 177 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 178 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 179 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 180 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 181 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 182 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 183
 184 #define CONTEXT_RUN     0x8000
 185 #define CONTEXT_WAKE    0x1000
 186 #define CONTEXT_DEAD    0x0800
 187 #define CONTEXT_ACTIVE  0x0400
 188
 189 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 190 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 191 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 192
 193 #define FW_OHCI_MAJOR                   240
 194 #define OHCI1394_REGISTER_SIZE          0x800
 195 #define OHCI_LOOP_COUNT                 500
 196 #define OHCI1394_PCI_HCI_Control        0x40
 197 #define SELF_ID_BUF_SIZE                0x800
 198 #define OHCI_TCODE_PHY_PACKET           0x0e
 199 #define OHCI_VERSION_1_1                0x010010
 200 #define ISO_BUFFER_SIZE                 (64 * 1024)
 201 #define AT_BUFFER_SIZE                  4096
 202
 203 static char ohci_driver_name[] = KBUILD_MODNAME;
 204
 205 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 206 {
 207         writel(data, ohci->registers + offset);
 208 }
 209
 210 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 211 {
 212         return readl(ohci->registers + offset);
 213 }
 214
 215 static inline void flush_writes(const struct fw_ohci *ohci)
 216 {
 217         /* Do a dummy read to flush writes. */
 218         reg_read(ohci, OHCI1394_Version);
 219 }
 220
 221 static int
 222 ohci_update_phy_reg(struct fw_card *card, int addr,
 223                     int clear_bits, int set_bits)
 224 {
 225         struct fw_ohci *ohci = fw_ohci(card);
 226         u32 val, old;
 227
 228         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 229         flush_writes(ohci);
 230         msleep(2);
 231         val = reg_read(ohci, OHCI1394_PhyControl);
 232         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 233                 fw_error("failed to set phy reg bits.\n");
 234                 return -EBUSY;
 235         }
 236
 237         old = OHCI1394_PhyControl_ReadData(val);
 238         old = (old & ~clear_bits) | set_bits;
 239         reg_write(ohci, OHCI1394_PhyControl,
 240                   OHCI1394_PhyControl_Write(addr, old));
 241
 242         return 0;
 243 }
 244
 245 static int ar_context_add_page(struct ar_context *ctx)
 246 {
 247         struct device *dev = ctx->ohci->card.device;
 248         struct ar_buffer *ab;
 249         dma_addr_t ab_bus;
 250         size_t offset;
 251
 252         ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
 253         if (ab == NULL)
 254                 return -ENOMEM;
 255
 256         ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
 257         if (dma_mapping_error(ab_bus)) {
 258                 free_page((unsigned long) ab);
 259                 return -ENOMEM;
 260         }
 261
 262         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 263         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 264                                                     DESCRIPTOR_STATUS |
 265                                                     DESCRIPTOR_BRANCH_ALWAYS);
 266         offset = offsetof(struct ar_buffer, data);
 267         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 268         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 269         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 270         ab->descriptor.branch_address = 0;
 271
 272         dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 273
 274         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 275         ctx->last_buffer->next = ab;
 276         ctx->last_buffer = ab;
 277
 278         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 279         flush_writes(ctx->ohci);
 280
 281         return 0;
 282 }
 283
 284 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 285 {
 286         struct fw_ohci *ohci = ctx->ohci;
 287         struct fw_packet p;
 288         u32 status, length, tcode;
 289
 290         p.header[0] = le32_to_cpu(buffer[0]);
 291         p.header[1] = le32_to_cpu(buffer[1]);
 292         p.header[2] = le32_to_cpu(buffer[2]);
 293
 294         tcode = (p.header[0] >> 4) & 0x0f;
 295         switch (tcode) {
 296         case TCODE_WRITE_QUADLET_REQUEST:
 297         case TCODE_READ_QUADLET_RESPONSE:
 298                 p.header[3] = (__force __u32) buffer[3];
 299                 p.header_length = 16;
 300                 p.payload_length = 0;
 301                 break;
 302
 303         case TCODE_READ_BLOCK_REQUEST :
 304                 p.header[3] = le32_to_cpu(buffer[3]);
 305                 p.header_length = 16;
 306                 p.payload_length = 0;
 307                 break;
 308
 309         case TCODE_WRITE_BLOCK_REQUEST:
 310         case TCODE_READ_BLOCK_RESPONSE:
 311         case TCODE_LOCK_REQUEST:
 312         case TCODE_LOCK_RESPONSE:
 313                 p.header[3] = le32_to_cpu(buffer[3]);
 314                 p.header_length = 16;
 315                 p.payload_length = p.header[3] >> 16;
 316                 break;
 317
 318         case TCODE_WRITE_RESPONSE:
 319         case TCODE_READ_QUADLET_REQUEST:
 320         case OHCI_TCODE_PHY_PACKET:
 321                 p.header_length = 12;
 322                 p.payload_length = 0;
 323                 break;
 324         }
 325
 326         p.payload = (void *) buffer + p.header_length;
 327
 328         /* FIXME: What to do about evt_* errors? */
 329         length = (p.header_length + p.payload_length + 3) / 4;
 330         status = le32_to_cpu(buffer[length]);
 331
 332         p.ack        = ((status >> 16) & 0x1f) - 16;
 333         p.speed      = (status >> 21) & 0x7;
 334         p.timestamp  = status & 0xffff;
 335         p.generation = ohci->request_generation;
 336
 337         /*
 338          * The OHCI bus reset handler synthesizes a phy packet with
 339          * the new generation number when a bus reset happens (see
 340          * section 8.4.2.3).  This helps us determine when a request
 341          * was received and make sure we send the response in the same
 342          * generation.  We only need this for requests; for responses
 343          * we use the unique tlabel for finding the matching
 344          * request.
 345          */
 346
 347         if (p.ack + 16 == 0x09)
 348                 ohci->request_generation = (buffer[2] >> 16) & 0xff;
 349         else if (ctx == &ohci->ar_request_ctx)
 350                 fw_core_handle_request(&ohci->card, &p);
 351         else
 352                 fw_core_handle_response(&ohci->card, &p);
 353
 354         return buffer + length + 1;
 355 }
 356
 357 static void ar_context_tasklet(unsigned long data)
 358 {
 359         struct ar_context *ctx = (struct ar_context *)data;
 360         struct fw_ohci *ohci = ctx->ohci;
 361         struct ar_buffer *ab;
 362         struct descriptor *d;
 363         void *buffer, *end;
 364
 365         ab = ctx->current_buffer;
 366         d = &ab->descriptor;
 367
 368         if (d->res_count == 0) {
 369                 size_t size, rest, offset;
 370
 371                 /*
 372                  * This descriptor is finished and we may have a
 373                  * packet split across this and the next buffer. We
 374                  * reuse the page for reassembling the split packet.
 375                  */
 376
 377                 offset = offsetof(struct ar_buffer, data);
 378                 dma_unmap_single(ohci->card.device,
 379                         le32_to_cpu(ab->descriptor.data_address) - offset,
 380                         PAGE_SIZE, DMA_BIDIRECTIONAL);
 381
 382                 buffer = ab;
 383                 ab = ab->next;
 384                 d = &ab->descriptor;
 385                 size = buffer + PAGE_SIZE - ctx->pointer;
 386                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 387                 memmove(buffer, ctx->pointer, size);
 388                 memcpy(buffer + size, ab->data, rest);
 389                 ctx->current_buffer = ab;
 390                 ctx->pointer = (void *) ab->data + rest;
 391                 end = buffer + size + rest;
 392
 393                 while (buffer < end)
 394                         buffer = handle_ar_packet(ctx, buffer);
 395
 396                 free_page((unsigned long)buffer);
 397                 ar_context_add_page(ctx);
 398         } else {
 399                 buffer = ctx->pointer;
 400                 ctx->pointer = end =
 401                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 402
 403                 while (buffer < end)
 404                         buffer = handle_ar_packet(ctx, buffer);
 405         }
 406 }
 407
 408 static int
 409 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
 410 {
 411         struct ar_buffer ab;
 412
 413         ctx->regs        = regs;
 414         ctx->ohci        = ohci;
 415         ctx->last_buffer = &ab;
 416         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 417
 418         ar_context_add_page(ctx);
 419         ar_context_add_page(ctx);
 420         ctx->current_buffer = ab.next;
 421         ctx->pointer = ctx->current_buffer->data;
 422
 423         return 0;
 424 }
 425
 426 static void ar_context_run(struct ar_context *ctx)
 427 {
 428         struct ar_buffer *ab = ctx->current_buffer;
 429         dma_addr_t ab_bus;
 430         size_t offset;
 431
 432         offset = offsetof(struct ar_buffer, data);
 433         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 434
 435         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 436         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 437         flush_writes(ctx->ohci);
 438 }
 439
 440 static void context_tasklet(unsigned long data)
 441 {
 442         struct context *ctx = (struct context *) data;
 443         struct fw_ohci *ohci = ctx->ohci;
 444         struct descriptor *d, *last;
 445         u32 address;
 446         int z;
 447
 448         dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
 449                                 ctx->buffer_size, DMA_TO_DEVICE);
 450
 451         d    = ctx->tail_descriptor;
 452         last = ctx->tail_descriptor_last;
 453
 454         while (last->branch_address != 0) {
 455                 address = le32_to_cpu(last->branch_address);
 456                 z = address & 0xf;
 457                 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
 458                 last = (z == 2) ? d : d + z - 1;
 459
 460                 if (!ctx->callback(ctx, d, last))
 461                         break;
 462
 463                 ctx->tail_descriptor      = d;
 464                 ctx->tail_descriptor_last = last;
 465         }
 466 }
 467
 468 static int
 469 context_init(struct context *ctx, struct fw_ohci *ohci,
 470              size_t buffer_size, u32 regs,
 471              descriptor_callback_t callback)
 472 {
 473         ctx->ohci = ohci;
 474         ctx->regs = regs;
 475         ctx->buffer_size = buffer_size;
 476         ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
 477         if (ctx->buffer == NULL)
 478                 return -ENOMEM;
 479
 480         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 481         ctx->callback = callback;
 482
 483         ctx->buffer_bus =
 484                 dma_map_single(ohci->card.device, ctx->buffer,
 485                                buffer_size, DMA_TO_DEVICE);
 486         if (dma_mapping_error(ctx->buffer_bus)) {
 487                 kfree(ctx->buffer);
 488                 return -ENOMEM;
 489         }
 490
 491         ctx->head_descriptor      = ctx->buffer;
 492         ctx->prev_descriptor      = ctx->buffer;
 493         ctx->tail_descriptor      = ctx->buffer;
 494         ctx->tail_descriptor_last = ctx->buffer;
 495
 496         /*
 497          * We put a dummy descriptor in the buffer that has a NULL
 498          * branch address and looks like it's been sent.  That way we
 499          * have a descriptor to append DMA programs to.  Also, the
 500          * ring buffer invariant is that it always has at least one
 501          * element so that head == tail means buffer full.
 502          */
 503
 504         memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
 505         ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 506         ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
 507         ctx->head_descriptor++;
 508
 509         return 0;
 510 }
 511
 512 static void
 513 context_release(struct context *ctx)
 514 {
 515         struct fw_card *card = &ctx->ohci->card;
 516
 517         dma_unmap_single(card->device, ctx->buffer_bus,
 518                          ctx->buffer_size, DMA_TO_DEVICE);
 519         kfree(ctx->buffer);
 520 }
 521
 522 static struct descriptor *
 523 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
 524 {
 525         struct descriptor *d, *tail, *end;
 526
 527         d = ctx->head_descriptor;
 528         tail = ctx->tail_descriptor;
 529         end = ctx->buffer + ctx->buffer_size / sizeof(*d);
 530
 531         if (d + z <= tail) {
 532                 goto has_space;
 533         } else if (d > tail && d + z <= end) {
 534                 goto has_space;
 535         } else if (d > tail && ctx->buffer + z <= tail) {
 536                 d = ctx->buffer;
 537                 goto has_space;
 538         }
 539
 540         return NULL;
 541
 542  has_space:
 543         memset(d, 0, z * sizeof(*d));
 544         *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
 545
 546         return d;
 547 }
 548
 549 static void context_run(struct context *ctx, u32 extra)
 550 {
 551         struct fw_ohci *ohci = ctx->ohci;
 552
 553         reg_write(ohci, COMMAND_PTR(ctx->regs),
 554                   le32_to_cpu(ctx->tail_descriptor_last->branch_address));
 555         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 556         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 557         flush_writes(ohci);
 558 }
 559
 560 static void context_append(struct context *ctx,
 561                            struct descriptor *d, int z, int extra)
 562 {
 563         dma_addr_t d_bus;
 564
 565         d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
 566
 567         ctx->head_descriptor = d + z + extra;
 568         ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
 569         ctx->prev_descriptor = z == 2 ? d : d + z - 1;
 570
 571         dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
 572                                    ctx->buffer_size, DMA_TO_DEVICE);
 573
 574         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 575         flush_writes(ctx->ohci);
 576 }
 577
 578 static void context_stop(struct context *ctx)
 579 {
 580         u32 reg;
 581         int i;
 582
 583         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 584         flush_writes(ctx->ohci);
 585
 586         for (i = 0; i < 10; i++) {
 587                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 588                 if ((reg & CONTEXT_ACTIVE) == 0)
 589                         break;
 590
 591                 fw_notify("context_stop: still active (0x%08x)\n", reg);
 592                 mdelay(1);
 593         }
 594 }
 595
 596 struct driver_data {
 597         struct fw_packet *packet;
 598 };
 599
 600 /*
 601  * This function apppends a packet to the DMA queue for transmission.
 602  * Must always be called with the ochi->lock held to ensure proper
 603  * generation handling and locking around packet queue manipulation.
 604  */
 605 static int
 606 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
 607 {
 608         struct fw_ohci *ohci = ctx->ohci;
 609         dma_addr_t d_bus, payload_bus;
 610         struct driver_data *driver_data;
 611         struct descriptor *d, *last;
 612         __le32 *header;
 613         int z, tcode;
 614         u32 reg;
 615
 616         d = context_get_descriptors(ctx, 4, &d_bus);
 617         if (d == NULL) {
 618                 packet->ack = RCODE_SEND_ERROR;
 619                 return -1;
 620         }
 621
 622         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 623         d[0].res_count = cpu_to_le16(packet->timestamp);
 624
 625         /*
 626          * The DMA format for asyncronous link packets is different
 627          * from the IEEE1394 layout, so shift the fields around
 628          * accordingly.  If header_length is 8, it's a PHY packet, to
 629          * which we need to prepend an extra quadlet.
 630          */
 631
 632         header = (__le32 *) &d[1];
 633         if (packet->header_length > 8) {
 634                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 635                                         (packet->speed << 16));
 636                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 637                                         (packet->header[0] & 0xffff0000));
 638                 header[2] = cpu_to_le32(packet->header[2]);
 639
 640                 tcode = (packet->header[0] >> 4) & 0x0f;
 641                 if (TCODE_IS_BLOCK_PACKET(tcode))
 642                         header[3] = cpu_to_le32(packet->header[3]);
 643                 else
 644                         header[3] = (__force __le32) packet->header[3];
 645
 646                 d[0].req_count = cpu_to_le16(packet->header_length);
 647         } else {
 648                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 649                                         (packet->speed << 16));
 650                 header[1] = cpu_to_le32(packet->header[0]);
 651                 header[2] = cpu_to_le32(packet->header[1]);
 652                 d[0].req_count = cpu_to_le16(12);
 653         }
 654
 655         driver_data = (struct driver_data *) &d[3];
 656         driver_data->packet = packet;
 657         packet->driver_data = driver_data;
 658
 659         if (packet->payload_length > 0) {
 660                 payload_bus =
 661                         dma_map_single(ohci->card.device, packet->payload,
 662                                        packet->payload_length, DMA_TO_DEVICE);
 663                 if (dma_mapping_error(payload_bus)) {
 664                         packet->ack = RCODE_SEND_ERROR;
 665                         return -1;
 666                 }
 667
 668                 d[2].req_count    = cpu_to_le16(packet->payload_length);
 669                 d[2].data_address = cpu_to_le32(payload_bus);
 670                 last = &d[2];
 671                 z = 3;
 672         } else {
 673                 last = &d[0];
 674                 z = 2;
 675         }
 676
 677         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 678                                      DESCRIPTOR_IRQ_ALWAYS |
 679                                      DESCRIPTOR_BRANCH_ALWAYS);
 680
 681         /* FIXME: Document how the locking works. */
 682         if (ohci->generation != packet->generation) {
 683                 if (packet->payload_length > 0)
 684                         dma_unmap_single(ohci->card.device, payload_bus,
 685                                          packet->payload_length, DMA_TO_DEVICE);
 686                 packet->ack = RCODE_GENERATION;
 687                 return -1;
 688         }
 689
 690         context_append(ctx, d, z, 4 - z);
 691
 692         /* If the context isn't already running, start it up. */
 693         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 694         if ((reg & CONTEXT_RUN) == 0)
 695                 context_run(ctx, 0);
 696
 697         return 0;
 698 }
 699
 700 static int handle_at_packet(struct context *context,
 701                             struct descriptor *d,
 702                             struct descriptor *last)
 703 {
 704         struct driver_data *driver_data;
 705         struct fw_packet *packet;
 706         struct fw_ohci *ohci = context->ohci;
 707         dma_addr_t payload_bus;
 708         int evt;
 709
 710         if (last->transfer_status == 0)
 711                 /* This descriptor isn't done yet, stop iteration. */
 712                 return 0;
 713
 714         driver_data = (struct driver_data *) &d[3];
 715         packet = driver_data->packet;
 716         if (packet == NULL)
 717                 /* This packet was cancelled, just continue. */
 718                 return 1;
 719
 720         payload_bus = le32_to_cpu(last->data_address);
 721         if (payload_bus != 0)
 722                 dma_unmap_single(ohci->card.device, payload_bus,
 723                                  packet->payload_length, DMA_TO_DEVICE);
 724
 725         evt = le16_to_cpu(last->transfer_status) & 0x1f;
 726         packet->timestamp = le16_to_cpu(last->res_count);
 727
 728         switch (evt) {
 729         case OHCI1394_evt_timeout:
 730                 /* Async response transmit timed out. */
 731                 packet->ack = RCODE_CANCELLED;
 732                 break;
 733
 734         case OHCI1394_evt_flushed:
 735                 /*
 736                  * The packet was flushed should give same error as
 737                  * when we try to use a stale generation count.
 738                  */
 739                 packet->ack = RCODE_GENERATION;
 740                 break;
 741
 742         case OHCI1394_evt_missing_ack:
 743                 /*
 744                  * Using a valid (current) generation count, but the
 745                  * node is not on the bus or not sending acks.
 746                  */
 747                 packet->ack = RCODE_NO_ACK;
 748                 break;
 749
 750         case ACK_COMPLETE + 0x10:
 751         case ACK_PENDING + 0x10:
 752         case ACK_BUSY_X + 0x10:
 753         case ACK_BUSY_A + 0x10:
 754         case ACK_BUSY_B + 0x10:
 755         case ACK_DATA_ERROR + 0x10:
 756         case ACK_TYPE_ERROR + 0x10:
 757                 packet->ack = evt - 0x10;
 758                 break;
 759
 760         default:
 761                 packet->ack = RCODE_SEND_ERROR;
 762                 break;
 763         }
 764
 765         packet->callback(packet, &ohci->card, packet->ack);
 766
 767         return 1;
 768 }
 769
 770 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
 771 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
 772 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
 773 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
 774 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
 775
 776 static void
 777 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 778 {
 779         struct fw_packet response;
 780         int tcode, length, i;
 781
 782         tcode = HEADER_GET_TCODE(packet->header[0]);
 783         if (TCODE_IS_BLOCK_PACKET(tcode))
 784                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 785         else
 786                 length = 4;
 787
 788         i = csr - CSR_CONFIG_ROM;
 789         if (i + length > CONFIG_ROM_SIZE) {
 790                 fw_fill_response(&response, packet->header,
 791                                  RCODE_ADDRESS_ERROR, NULL, 0);
 792         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
 793                 fw_fill_response(&response, packet->header,
 794                                  RCODE_TYPE_ERROR, NULL, 0);
 795         } else {
 796                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
 797                                  (void *) ohci->config_rom + i, length);
 798         }
 799
 800         fw_core_handle_response(&ohci->card, &response);
 801 }
 802
 803 static void
 804 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 805 {
 806         struct fw_packet response;
 807         int tcode, length, ext_tcode, sel;
 808         __be32 *payload, lock_old;
 809         u32 lock_arg, lock_data;
 810
 811         tcode = HEADER_GET_TCODE(packet->header[0]);
 812         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 813         payload = packet->payload;
 814         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
 815
 816         if (tcode == TCODE_LOCK_REQUEST &&
 817             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
 818                 lock_arg = be32_to_cpu(payload[0]);
 819                 lock_data = be32_to_cpu(payload[1]);
 820         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
 821                 lock_arg = 0;
 822                 lock_data = 0;
 823         } else {
 824                 fw_fill_response(&response, packet->header,
 825                                  RCODE_TYPE_ERROR, NULL, 0);
 826                 goto out;
 827         }
 828
 829         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
 830         reg_write(ohci, OHCI1394_CSRData, lock_data);
 831         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
 832         reg_write(ohci, OHCI1394_CSRControl, sel);
 833
 834         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
 835                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
 836         else
 837                 fw_notify("swap not done yet\n");
 838
 839         fw_fill_response(&response, packet->header,
 840                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
 841  out:
 842         fw_core_handle_response(&ohci->card, &response);
 843 }
 844
 845 static void
 846 handle_local_request(struct context *ctx, struct fw_packet *packet)
 847 {
 848         u64 offset;
 849         u32 csr;
 850
 851         if (ctx == &ctx->ohci->at_request_ctx) {
 852                 packet->ack = ACK_PENDING;
 853                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 854         }
 855
 856         offset =
 857                 ((unsigned long long)
 858                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
 859                 packet->header[2];
 860         csr = offset - CSR_REGISTER_BASE;
 861
 862         /* Handle config rom reads. */
 863         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
 864                 handle_local_rom(ctx->ohci, packet, csr);
 865         else switch (csr) {
 866         case CSR_BUS_MANAGER_ID:
 867         case CSR_BANDWIDTH_AVAILABLE:
 868         case CSR_CHANNELS_AVAILABLE_HI:
 869         case CSR_CHANNELS_AVAILABLE_LO:
 870                 handle_local_lock(ctx->ohci, packet, csr);
 871                 break;
 872         default:
 873                 if (ctx == &ctx->ohci->at_request_ctx)
 874                         fw_core_handle_request(&ctx->ohci->card, packet);
 875                 else
 876                         fw_core_handle_response(&ctx->ohci->card, packet);
 877                 break;
 878         }
 879
 880         if (ctx == &ctx->ohci->at_response_ctx) {
 881                 packet->ack = ACK_COMPLETE;
 882                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 883         }
 884 }
 885
 886 static void
 887 at_context_transmit(struct context *ctx, struct fw_packet *packet)
 888 {
 889         unsigned long flags;
 890         int retval;
 891
 892         spin_lock_irqsave(&ctx->ohci->lock, flags);
 893
 894         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
 895             ctx->ohci->generation == packet->generation) {
 896                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 897                 handle_local_request(ctx, packet);
 898                 return;
 899         }
 900
 901         retval = at_context_queue_packet(ctx, packet);
 902         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 903
 904         if (retval < 0)
 905                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 906
 907 }
 908
 909 static void bus_reset_tasklet(unsigned long data)
 910 {
 911         struct fw_ohci *ohci = (struct fw_ohci *)data;
 912         int self_id_count, i, j, reg;
 913         int generation, new_generation;
 914         unsigned long flags;
 915         void *free_rom = NULL;
 916         dma_addr_t free_rom_bus = 0;
 917
 918         reg = reg_read(ohci, OHCI1394_NodeID);
 919         if (!(reg & OHCI1394_NodeID_idValid)) {
 920                 fw_error("node ID not valid, new bus reset in progress\n");
 921                 return;
 922         }
 923         ohci->node_id = reg & 0xffff;
 924
 925         /*
 926          * The count in the SelfIDCount register is the number of
 927          * bytes in the self ID receive buffer.  Since we also receive
 928          * the inverted quadlets and a header quadlet, we shift one
 929          * bit extra to get the actual number of self IDs.
 930          */
 931
 932         self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
 933         generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
 934         rmb();
 935
 936         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
 937                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
 938                         fw_error("inconsistent self IDs\n");
 939                 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
 940         }
 941         rmb();
 942
 943         /*
 944          * Check the consistency of the self IDs we just read.  The
 945          * problem we face is that a new bus reset can start while we
 946          * read out the self IDs from the DMA buffer. If this happens,
 947          * the DMA buffer will be overwritten with new self IDs and we
 948          * will read out inconsistent data.  The OHCI specification
 949          * (section 11.2) recommends a technique similar to
 950          * linux/seqlock.h, where we remember the generation of the
 951          * self IDs in the buffer before reading them out and compare
 952          * it to the current generation after reading them out.  If
 953          * the two generations match we know we have a consistent set
 954          * of self IDs.
 955          */
 956
 957         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
 958         if (new_generation != generation) {
 959                 fw_notify("recursive bus reset detected, "
 960                           "discarding self ids\n");
 961                 return;
 962         }
 963
 964         /* FIXME: Document how the locking works. */
 965         spin_lock_irqsave(&ohci->lock, flags);
 966
 967         ohci->generation = generation;
 968         context_stop(&ohci->at_request_ctx);
 969         context_stop(&ohci->at_response_ctx);
 970         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
 971
 972         /*
 973          * This next bit is unrelated to the AT context stuff but we
 974          * have to do it under the spinlock also.  If a new config rom
 975          * was set up before this reset, the old one is now no longer
 976          * in use and we can free it. Update the config rom pointers
 977          * to point to the current config rom and clear the
 978          * next_config_rom pointer so a new udpate can take place.
 979          */
 980
 981         if (ohci->next_config_rom != NULL) {
 982                 free_rom     = ohci->config_rom;
 983                 free_rom_bus = ohci->config_rom_bus;
 984                 ohci->config_rom      = ohci->next_config_rom;
 985                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
 986                 ohci->next_config_rom = NULL;
 987
 988                 /*
 989                  * Restore config_rom image and manually update
 990                  * config_rom registers.  Writing the header quadlet
 991                  * will indicate that the config rom is ready, so we
 992                  * do that last.
 993                  */
 994                 reg_write(ohci, OHCI1394_BusOptions,
 995                           be32_to_cpu(ohci->config_rom[2]));
 996                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
 997                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
 998         }
 999
1000         spin_unlock_irqrestore(&ohci->lock, flags);
1001
1002         if (free_rom)
1003                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1004                                   free_rom, free_rom_bus);
1005
1006         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1007                                  self_id_count, ohci->self_id_buffer);
1008 }
1009
1010 static irqreturn_t irq_handler(int irq, void *data)
1011 {
1012         struct fw_ohci *ohci = data;
1013         u32 event, iso_event, cycle_time;
1014         int i;
1015
1016         event = reg_read(ohci, OHCI1394_IntEventClear);
1017
1018         if (!event || !~event)
1019                 return IRQ_NONE;
1020
1021         reg_write(ohci, OHCI1394_IntEventClear, event);
1022
1023         if (event & OHCI1394_selfIDComplete)
1024                 tasklet_schedule(&ohci->bus_reset_tasklet);
1025
1026         if (event & OHCI1394_RQPkt)
1027                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1028
1029         if (event & OHCI1394_RSPkt)
1030                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1031
1032         if (event & OHCI1394_reqTxComplete)
1033                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1034
1035         if (event & OHCI1394_respTxComplete)
1036                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1037
1038         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1039         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1040
1041         while (iso_event) {
1042                 i = ffs(iso_event) - 1;
1043                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1044                 iso_event &= ~(1 << i);
1045         }
1046
1047         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1048         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1049
1050         while (iso_event) {
1051                 i = ffs(iso_event) - 1;
1052                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1053                 iso_event &= ~(1 << i);
1054         }
1055
1056         if (unlikely(event & OHCI1394_postedWriteErr))
1057                 fw_error("PCI posted write error\n");
1058
1059         if (event & OHCI1394_cycle64Seconds) {
1060                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1061                 if ((cycle_time & 0x80000000) == 0)
1062                         ohci->bus_seconds++;
1063         }
1064
1065         return IRQ_HANDLED;
1066 }
1067
1068 static int software_reset(struct fw_ohci *ohci)
1069 {
1070         int i;
1071
1072         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1073
1074         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1075                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1076                      OHCI1394_HCControl_softReset) == 0)
1077                         return 0;
1078                 msleep(1);
1079         }
1080
1081         return -EBUSY;
1082 }
1083
1084 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1085 {
1086         struct fw_ohci *ohci = fw_ohci(card);
1087         struct pci_dev *dev = to_pci_dev(card->device);
1088
1089         if (software_reset(ohci)) {
1090                 fw_error("Failed to reset ohci card.\n");
1091                 return -EBUSY;
1092         }
1093
1094         /*
1095          * Now enable LPS, which we need in order to start accessing
1096          * most of the registers.  In fact, on some cards (ALI M5251),
1097          * accessing registers in the SClk domain without LPS enabled
1098          * will lock up the machine.  Wait 50msec to make sure we have
1099          * full link enabled.
1100          */
1101         reg_write(ohci, OHCI1394_HCControlSet,
1102                   OHCI1394_HCControl_LPS |
1103                   OHCI1394_HCControl_postedWriteEnable);
1104         flush_writes(ohci);
1105         msleep(50);
1106
1107         reg_write(ohci, OHCI1394_HCControlClear,
1108                   OHCI1394_HCControl_noByteSwapData);
1109
1110         reg_write(ohci, OHCI1394_LinkControlSet,
1111                   OHCI1394_LinkControl_rcvSelfID |
1112                   OHCI1394_LinkControl_cycleTimerEnable |
1113                   OHCI1394_LinkControl_cycleMaster);
1114
1115         reg_write(ohci, OHCI1394_ATRetries,
1116                   OHCI1394_MAX_AT_REQ_RETRIES |
1117                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1118                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1119
1120         ar_context_run(&ohci->ar_request_ctx);
1121         ar_context_run(&ohci->ar_response_ctx);
1122
1123         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1124         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1125         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1126         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1127         reg_write(ohci, OHCI1394_IntMaskSet,
1128                   OHCI1394_selfIDComplete |
1129                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1130                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1131                   OHCI1394_isochRx | OHCI1394_isochTx |
1132                   OHCI1394_postedWriteErr | OHCI1394_cycle64Seconds |
1133                   OHCI1394_masterIntEnable);
1134
1135         /* Activate link_on bit and contender bit in our self ID packets.*/
1136         if (ohci_update_phy_reg(card, 4, 0,
1137                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1138                 return -EIO;
1139
1140         /*
1141          * When the link is not yet enabled, the atomic config rom
1142          * update mechanism described below in ohci_set_config_rom()
1143          * is not active.  We have to update ConfigRomHeader and
1144          * BusOptions manually, and the write to ConfigROMmap takes
1145          * effect immediately.  We tie this to the enabling of the
1146          * link, so we have a valid config rom before enabling - the
1147          * OHCI requires that ConfigROMhdr and BusOptions have valid
1148          * values before enabling.
1149          *
1150          * However, when the ConfigROMmap is written, some controllers
1151          * always read back quadlets 0 and 2 from the config rom to
1152          * the ConfigRomHeader and BusOptions registers on bus reset.
1153          * They shouldn't do that in this initial case where the link
1154          * isn't enabled.  This means we have to use the same
1155          * workaround here, setting the bus header to 0 and then write
1156          * the right values in the bus reset tasklet.
1157          */
1158
1159         ohci->next_config_rom =
1160                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1161                                    &ohci->next_config_rom_bus, GFP_KERNEL);
1162         if (ohci->next_config_rom == NULL)
1163                 return -ENOMEM;
1164
1165         memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1166         fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1167
1168         ohci->next_header = config_rom[0];
1169         ohci->next_config_rom[0] = 0;
1170         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1171         reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
1172         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1173
1174         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1175
1176         if (request_irq(dev->irq, irq_handler,
1177                         IRQF_SHARED, ohci_driver_name, ohci)) {
1178                 fw_error("Failed to allocate shared interrupt %d.\n",
1179                          dev->irq);
1180                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1181                                   ohci->config_rom, ohci->config_rom_bus);
1182                 return -EIO;
1183         }
1184
1185         reg_write(ohci, OHCI1394_HCControlSet,
1186                   OHCI1394_HCControl_linkEnable |
1187                   OHCI1394_HCControl_BIBimageValid);
1188         flush_writes(ohci);
1189
1190         /*
1191          * We are ready to go, initiate bus reset to finish the
1192          * initialization.
1193          */
1194
1195         fw_core_initiate_bus_reset(&ohci->card, 1);
1196
1197         return 0;
1198 }
1199
1200 static int
1201 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1202 {
1203         struct fw_ohci *ohci;
1204         unsigned long flags;
1205         int retval = -EBUSY;
1206         __be32 *next_config_rom;
1207         dma_addr_t next_config_rom_bus;
1208
1209         ohci = fw_ohci(card);
1210
1211         /*
1212          * When the OHCI controller is enabled, the config rom update
1213          * mechanism is a bit tricky, but easy enough to use.  See
1214          * section 5.5.6 in the OHCI specification.
1215          *
1216          * The OHCI controller caches the new config rom address in a
1217          * shadow register (ConfigROMmapNext) and needs a bus reset
1218          * for the changes to take place.  When the bus reset is
1219          * detected, the controller loads the new values for the
1220          * ConfigRomHeader and BusOptions registers from the specified
1221          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1222          * shadow register. All automatically and atomically.
1223          *
1224          * Now, there's a twist to this story.  The automatic load of
1225          * ConfigRomHeader and BusOptions doesn't honor the
1226          * noByteSwapData bit, so with a be32 config rom, the
1227          * controller will load be32 values in to these registers
1228          * during the atomic update, even on litte endian
1229          * architectures.  The workaround we use is to put a 0 in the
1230          * header quadlet; 0 is endian agnostic and means that the
1231          * config rom isn't ready yet.  In the bus reset tasklet we
1232          * then set up the real values for the two registers.
1233          *
1234          * We use ohci->lock to avoid racing with the code that sets
1235          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1236          */
1237
1238         next_config_rom =
1239                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1240                                    &next_config_rom_bus, GFP_KERNEL);
1241         if (next_config_rom == NULL)
1242                 return -ENOMEM;
1243
1244         spin_lock_irqsave(&ohci->lock, flags);
1245
1246         if (ohci->next_config_rom == NULL) {
1247                 ohci->next_config_rom = next_config_rom;
1248                 ohci->next_config_rom_bus = next_config_rom_bus;
1249
1250                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1251                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1252                                   length * 4);
1253
1254                 ohci->next_header = config_rom[0];
1255                 ohci->next_config_rom[0] = 0;
1256
1257                 reg_write(ohci, OHCI1394_ConfigROMmap,
1258                           ohci->next_config_rom_bus);
1259                 retval = 0;
1260         }
1261
1262         spin_unlock_irqrestore(&ohci->lock, flags);
1263
1264         /*
1265          * Now initiate a bus reset to have the changes take
1266          * effect. We clean up the old config rom memory and DMA
1267          * mappings in the bus reset tasklet, since the OHCI
1268          * controller could need to access it before the bus reset
1269          * takes effect.
1270          */
1271         if (retval == 0)
1272                 fw_core_initiate_bus_reset(&ohci->card, 1);
1273         else
1274                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1275                                   next_config_rom, next_config_rom_bus);
1276
1277         return retval;
1278 }
1279
1280 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1281 {
1282         struct fw_ohci *ohci = fw_ohci(card);
1283
1284         at_context_transmit(&ohci->at_request_ctx, packet);
1285 }
1286
1287 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1288 {
1289         struct fw_ohci *ohci = fw_ohci(card);
1290
1291         at_context_transmit(&ohci->at_response_ctx, packet);
1292 }
1293
1294 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1295 {
1296         struct fw_ohci *ohci = fw_ohci(card);
1297         struct context *ctx = &ohci->at_request_ctx;
1298         struct driver_data *driver_data = packet->driver_data;
1299         int retval = -ENOENT;
1300
1301         tasklet_disable(&ctx->tasklet);
1302
1303         if (packet->ack != 0)
1304                 goto out;
1305
1306         driver_data->packet = NULL;
1307         packet->ack = RCODE_CANCELLED;
1308         packet->callback(packet, &ohci->card, packet->ack);
1309         retval = 0;
1310
1311  out:
1312         tasklet_enable(&ctx->tasklet);
1313
1314         return retval;
1315 }
1316
1317 static int
1318 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1319 {
1320         struct fw_ohci *ohci = fw_ohci(card);
1321         unsigned long flags;
1322         int n, retval = 0;
1323
1324         /*
1325          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1326          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1327          */
1328
1329         spin_lock_irqsave(&ohci->lock, flags);
1330
1331         if (ohci->generation != generation) {
1332                 retval = -ESTALE;
1333                 goto out;
1334         }
1335
1336         /*
1337          * Note, if the node ID contains a non-local bus ID, physical DMA is
1338          * enabled for _all_ nodes on remote buses.
1339          */
1340
1341         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1342         if (n < 32)
1343                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1344         else
1345                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1346
1347         flush_writes(ohci);
1348  out:
1349         spin_unlock_irqrestore(&ohci->lock, flags);
1350         return retval;
1351 }
1352
1353 static u64
1354 ohci_get_bus_time(struct fw_card *card)
1355 {
1356         struct fw_ohci *ohci = fw_ohci(card);
1357         u32 cycle_time;
1358         u64 bus_time;
1359
1360         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1361         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1362
1363         return bus_time;
1364 }
1365
1366 static int handle_ir_dualbuffer_packet(struct context *context,
1367                                        struct descriptor *d,
1368                                        struct descriptor *last)
1369 {
1370         struct iso_context *ctx =
1371                 container_of(context, struct iso_context, context);
1372         struct db_descriptor *db = (struct db_descriptor *) d;
1373         __le32 *ir_header;
1374         size_t header_length;
1375         void *p, *end;
1376         int i;
1377
1378         if (db->first_res_count > 0 && db->second_res_count > 0)
1379                 /* This descriptor isn't done yet, stop iteration. */
1380                 return 0;
1381
1382         header_length = le16_to_cpu(db->first_req_count) -
1383                 le16_to_cpu(db->first_res_count);
1384
1385         i = ctx->header_length;
1386         p = db + 1;
1387         end = p + header_length;
1388         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1389                 /*
1390                  * The iso header is byteswapped to little endian by
1391                  * the controller, but the remaining header quadlets
1392                  * are big endian.  We want to present all the headers
1393                  * as big endian, so we have to swap the first
1394                  * quadlet.
1395                  */
1396                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1397                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1398                 i += ctx->base.header_size;
1399                 p += ctx->base.header_size + 4;
1400         }
1401
1402         ctx->header_length = i;
1403
1404         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1405                 ir_header = (__le32 *) (db + 1);
1406                 ctx->base.callback(&ctx->base,
1407                                    le32_to_cpu(ir_header[0]) & 0xffff,
1408                                    ctx->header_length, ctx->header,
1409                                    ctx->base.callback_data);
1410                 ctx->header_length = 0;
1411         }
1412
1413         return 1;
1414 }
1415
1416 static int handle_it_packet(struct context *context,
1417                             struct descriptor *d,
1418                             struct descriptor *last)
1419 {
1420         struct iso_context *ctx =
1421                 container_of(context, struct iso_context, context);
1422
1423         if (last->transfer_status == 0)
1424                 /* This descriptor isn't done yet, stop iteration. */
1425                 return 0;
1426
1427         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1428                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1429                                    0, NULL, ctx->base.callback_data);
1430
1431         return 1;
1432 }
1433
1434 static struct fw_iso_context *
1435 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1436 {
1437         struct fw_ohci *ohci = fw_ohci(card);
1438         struct iso_context *ctx, *list;
1439         descriptor_callback_t callback;
1440         u32 *mask, regs;
1441         unsigned long flags;
1442         int index, retval = -ENOMEM;
1443
1444         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1445                 mask = &ohci->it_context_mask;
1446                 list = ohci->it_context_list;
1447                 callback = handle_it_packet;
1448         } else {
1449                 mask = &ohci->ir_context_mask;
1450                 list = ohci->ir_context_list;
1451                 callback = handle_ir_dualbuffer_packet;
1452         }
1453
1454         /* FIXME: We need a fallback for pre 1.1 OHCI. */
1455         if (callback == handle_ir_dualbuffer_packet &&
1456             ohci->version < OHCI_VERSION_1_1)
1457                 return ERR_PTR(-EINVAL);
1458
1459         spin_lock_irqsave(&ohci->lock, flags);
1460         index = ffs(*mask) - 1;
1461         if (index >= 0)
1462                 *mask &= ~(1 << index);
1463         spin_unlock_irqrestore(&ohci->lock, flags);
1464
1465         if (index < 0)
1466                 return ERR_PTR(-EBUSY);
1467
1468         if (type == FW_ISO_CONTEXT_TRANSMIT)
1469                 regs = OHCI1394_IsoXmitContextBase(index);
1470         else
1471                 regs = OHCI1394_IsoRcvContextBase(index);
1472
1473         ctx = &list[index];
1474         memset(ctx, 0, sizeof(*ctx));
1475         ctx->header_length = 0;
1476         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1477         if (ctx->header == NULL)
1478                 goto out;
1479
1480         retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
1481                               regs, callback);
1482         if (retval < 0)
1483                 goto out_with_header;
1484
1485         return &ctx->base;
1486
1487  out_with_header:
1488         free_page((unsigned long)ctx->header);
1489  out:
1490         spin_lock_irqsave(&ohci->lock, flags);
1491         *mask |= 1 << index;
1492         spin_unlock_irqrestore(&ohci->lock, flags);
1493
1494         return ERR_PTR(retval);
1495 }
1496
1497 static int ohci_start_iso(struct fw_iso_context *base,
1498                           s32 cycle, u32 sync, u32 tags)
1499 {
1500         struct iso_context *ctx = container_of(base, struct iso_context, base);
1501         struct fw_ohci *ohci = ctx->context.ohci;
1502         u32 control, match;
1503         int index;
1504
1505         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1506                 index = ctx - ohci->it_context_list;
1507                 match = 0;
1508                 if (cycle >= 0)
1509                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1510                                 (cycle & 0x7fff) << 16;
1511
1512                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1513                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1514                 context_run(&ctx->context, match);
1515         } else {
1516                 index = ctx - ohci->ir_context_list;
1517                 control = IR_CONTEXT_DUAL_BUFFER_MODE | IR_CONTEXT_ISOCH_HEADER;
1518                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1519                 if (cycle >= 0) {
1520                         match |= (cycle & 0x07fff) << 12;
1521                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1522                 }
1523
1524                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1525                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1526                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1527                 context_run(&ctx->context, control);
1528         }
1529
1530         return 0;
1531 }
1532
1533 static int ohci_stop_iso(struct fw_iso_context *base)
1534 {
1535         struct fw_ohci *ohci = fw_ohci(base->card);
1536         struct iso_context *ctx = container_of(base, struct iso_context, base);
1537         int index;
1538
1539         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1540                 index = ctx - ohci->it_context_list;
1541                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1542         } else {
1543                 index = ctx - ohci->ir_context_list;
1544                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1545         }
1546         flush_writes(ohci);
1547         context_stop(&ctx->context);
1548
1549         return 0;
1550 }
1551
1552 static void ohci_free_iso_context(struct fw_iso_context *base)
1553 {
1554         struct fw_ohci *ohci = fw_ohci(base->card);
1555         struct iso_context *ctx = container_of(base, struct iso_context, base);
1556         unsigned long flags;
1557         int index;
1558
1559         ohci_stop_iso(base);
1560         context_release(&ctx->context);
1561         free_page((unsigned long)ctx->header);
1562
1563         spin_lock_irqsave(&ohci->lock, flags);
1564
1565         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1566                 index = ctx - ohci->it_context_list;
1567                 ohci->it_context_mask |= 1 << index;
1568         } else {
1569                 index = ctx - ohci->ir_context_list;
1570                 ohci->ir_context_mask |= 1 << index;
1571         }
1572
1573         spin_unlock_irqrestore(&ohci->lock, flags);
1574 }
1575
1576 static int
1577 ohci_queue_iso_transmit(struct fw_iso_context *base,
1578                         struct fw_iso_packet *packet,
1579                         struct fw_iso_buffer *buffer,
1580                         unsigned long payload)
1581 {
1582         struct iso_context *ctx = container_of(base, struct iso_context, base);
1583         struct descriptor *d, *last, *pd;
1584         struct fw_iso_packet *p;
1585         __le32 *header;
1586         dma_addr_t d_bus, page_bus;
1587         u32 z, header_z, payload_z, irq;
1588         u32 payload_index, payload_end_index, next_page_index;
1589         int page, end_page, i, length, offset;
1590
1591         /*
1592          * FIXME: Cycle lost behavior should be configurable: lose
1593          * packet, retransmit or terminate..
1594          */
1595
1596         p = packet;
1597         payload_index = payload;
1598
1599         if (p->skip)
1600                 z = 1;
1601         else
1602                 z = 2;
1603         if (p->header_length > 0)
1604                 z++;
1605
1606         /* Determine the first page the payload isn't contained in. */
1607         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1608         if (p->payload_length > 0)
1609                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1610         else
1611                 payload_z = 0;
1612
1613         z += payload_z;
1614
1615         /* Get header size in number of descriptors. */
1616         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
1617
1618         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1619         if (d == NULL)
1620                 return -ENOMEM;
1621
1622         if (!p->skip) {
1623                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1624                 d[0].req_count = cpu_to_le16(8);
1625
1626                 header = (__le32 *) &d[1];
1627                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1628                                         IT_HEADER_TAG(p->tag) |
1629                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1630                                         IT_HEADER_CHANNEL(ctx->base.channel) |
1631                                         IT_HEADER_SPEED(ctx->base.speed));
1632                 header[1] =
1633                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
1634                                                           p->payload_length));
1635         }
1636
1637         if (p->header_length > 0) {
1638                 d[2].req_count    = cpu_to_le16(p->header_length);
1639                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
1640                 memcpy(&d[z], p->header, p->header_length);
1641         }
1642
1643         pd = d + z - payload_z;
1644         payload_end_index = payload_index + p->payload_length;
1645         for (i = 0; i < payload_z; i++) {
1646                 page               = payload_index >> PAGE_SHIFT;
1647                 offset             = payload_index & ~PAGE_MASK;
1648                 next_page_index    = (page + 1) << PAGE_SHIFT;
1649                 length             =
1650                         min(next_page_index, payload_end_index) - payload_index;
1651                 pd[i].req_count    = cpu_to_le16(length);
1652
1653                 page_bus = page_private(buffer->pages[page]);
1654                 pd[i].data_address = cpu_to_le32(page_bus + offset);
1655
1656                 payload_index += length;
1657         }
1658
1659         if (p->interrupt)
1660                 irq = DESCRIPTOR_IRQ_ALWAYS;
1661         else
1662                 irq = DESCRIPTOR_NO_IRQ;
1663
1664         last = z == 2 ? d : d + z - 1;
1665         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1666                                      DESCRIPTOR_STATUS |
1667                                      DESCRIPTOR_BRANCH_ALWAYS |
1668                                      irq);
1669
1670         context_append(&ctx->context, d, z, header_z);
1671
1672         return 0;
1673 }
1674
1675 static int
1676 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1677                                   struct fw_iso_packet *packet,
1678                                   struct fw_iso_buffer *buffer,
1679                                   unsigned long payload)
1680 {
1681         struct iso_context *ctx = container_of(base, struct iso_context, base);
1682         struct db_descriptor *db = NULL;
1683         struct descriptor *d;
1684         struct fw_iso_packet *p;
1685         dma_addr_t d_bus, page_bus;
1686         u32 z, header_z, length, rest;
1687         int page, offset, packet_count, header_size;
1688
1689         /*
1690          * FIXME: Cycle lost behavior should be configurable: lose
1691          * packet, retransmit or terminate..
1692          */
1693
1694         if (packet->skip) {
1695                 d = context_get_descriptors(&ctx->context, 2, &d_bus);
1696                 if (d == NULL)
1697                         return -ENOMEM;
1698
1699                 db = (struct db_descriptor *) d;
1700                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1701                                           DESCRIPTOR_BRANCH_ALWAYS |
1702                                           DESCRIPTOR_WAIT);
1703                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1704                 context_append(&ctx->context, d, 2, 0);
1705         }
1706
1707         p = packet;
1708         z = 2;
1709
1710         /*
1711          * The OHCI controller puts the status word in the header
1712          * buffer too, so we need 4 extra bytes per packet.
1713          */
1714         packet_count = p->header_length / ctx->base.header_size;
1715         header_size = packet_count * (ctx->base.header_size + 4);
1716
1717         /* Get header size in number of descriptors. */
1718         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1719         page     = payload >> PAGE_SHIFT;
1720         offset   = payload & ~PAGE_MASK;
1721         rest     = p->payload_length;
1722
1723         /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1724         /* FIXME: make packet-per-buffer/dual-buffer a context option */
1725         while (rest > 0) {
1726                 d = context_get_descriptors(&ctx->context,
1727                                             z + header_z, &d_bus);
1728                 if (d == NULL)
1729                         return -ENOMEM;
1730
1731                 db = (struct db_descriptor *) d;
1732                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1733                                           DESCRIPTOR_BRANCH_ALWAYS);
1734                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1735                 db->first_req_count = cpu_to_le16(header_size);
1736                 db->first_res_count = db->first_req_count;
1737                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
1738
1739                 if (offset + rest < PAGE_SIZE)
1740                         length = rest;
1741                 else
1742                         length = PAGE_SIZE - offset;
1743
1744                 db->second_req_count = cpu_to_le16(length);
1745                 db->second_res_count = db->second_req_count;
1746                 page_bus = page_private(buffer->pages[page]);
1747                 db->second_buffer = cpu_to_le32(page_bus + offset);
1748
1749                 if (p->interrupt && length == rest)
1750                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1751
1752                 context_append(&ctx->context, d, z, header_z);
1753                 offset = (offset + length) & ~PAGE_MASK;
1754                 rest -= length;
1755                 page++;
1756         }
1757
1758         return 0;
1759 }
1760
1761 static int
1762 ohci_queue_iso(struct fw_iso_context *base,
1763                struct fw_iso_packet *packet,
1764                struct fw_iso_buffer *buffer,
1765                unsigned long payload)
1766 {
1767         struct iso_context *ctx = container_of(base, struct iso_context, base);
1768
1769         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1770                 return ohci_queue_iso_transmit(base, packet, buffer, payload);
1771         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
1772                 return ohci_queue_iso_receive_dualbuffer(base, packet,
1773                                                          buffer, payload);
1774         else
1775                 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1776                 return -EINVAL;
1777 }
1778
1779 static const struct fw_card_driver ohci_driver = {
1780         .name                   = ohci_driver_name,
1781         .enable                 = ohci_enable,
1782         .update_phy_reg         = ohci_update_phy_reg,
1783         .set_config_rom         = ohci_set_config_rom,
1784         .send_request           = ohci_send_request,
1785         .send_response          = ohci_send_response,
1786         .cancel_packet          = ohci_cancel_packet,
1787         .enable_phys_dma        = ohci_enable_phys_dma,
1788         .get_bus_time           = ohci_get_bus_time,
1789
1790         .allocate_iso_context   = ohci_allocate_iso_context,
1791         .free_iso_context       = ohci_free_iso_context,
1792         .queue_iso              = ohci_queue_iso,
1793         .start_iso              = ohci_start_iso,
1794         .stop_iso               = ohci_stop_iso,
1795 };
1796
1797 static int __devinit
1798 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1799 {
1800         struct fw_ohci *ohci;
1801         u32 bus_options, max_receive, link_speed;
1802         u64 guid;
1803         int err;
1804         size_t size;
1805
1806         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
1807         if (ohci == NULL) {
1808                 fw_error("Could not malloc fw_ohci data.\n");
1809                 return -ENOMEM;
1810         }
1811
1812         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1813
1814         err = pci_enable_device(dev);
1815         if (err) {
1816                 fw_error("Failed to enable OHCI hardware.\n");
1817                 goto fail_put_card;
1818         }
1819
1820         pci_set_master(dev);
1821         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1822         pci_set_drvdata(dev, ohci);
1823
1824         spin_lock_init(&ohci->lock);
1825
1826         tasklet_init(&ohci->bus_reset_tasklet,
1827                      bus_reset_tasklet, (unsigned long)ohci);
1828
1829         err = pci_request_region(dev, 0, ohci_driver_name);
1830         if (err) {
1831                 fw_error("MMIO resource unavailable\n");
1832                 goto fail_disable;
1833         }
1834
1835         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1836         if (ohci->registers == NULL) {
1837                 fw_error("Failed to remap registers\n");
1838                 err = -ENXIO;
1839                 goto fail_iomem;
1840         }
1841
1842         ar_context_init(&ohci->ar_request_ctx, ohci,
1843                         OHCI1394_AsReqRcvContextControlSet);
1844
1845         ar_context_init(&ohci->ar_response_ctx, ohci,
1846                         OHCI1394_AsRspRcvContextControlSet);
1847
1848         context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
1849                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
1850
1851         context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
1852                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
1853
1854         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1855         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1856         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1857         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1858         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1859
1860         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1861         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1862         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1863         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1864         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1865
1866         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1867                 fw_error("Out of memory for it/ir contexts.\n");
1868                 err = -ENOMEM;
1869                 goto fail_registers;
1870         }
1871
1872         /* self-id dma buffer allocation */
1873         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1874                                                SELF_ID_BUF_SIZE,
1875                                                &ohci->self_id_bus,
1876                                                GFP_KERNEL);
1877         if (ohci->self_id_cpu == NULL) {
1878                 fw_error("Out of memory for self ID buffer.\n");
1879                 err = -ENOMEM;
1880                 goto fail_registers;
1881         }
1882
1883         bus_options = reg_read(ohci, OHCI1394_BusOptions);
1884         max_receive = (bus_options >> 12) & 0xf;
1885         link_speed = bus_options & 0x7;
1886         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1887                 reg_read(ohci, OHCI1394_GUIDLo);
1888
1889         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1890         if (err < 0)
1891                 goto fail_self_id;
1892
1893         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1894         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1895                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
1896
1897         return 0;
1898
1899  fail_self_id:
1900         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1901                           ohci->self_id_cpu, ohci->self_id_bus);
1902  fail_registers:
1903         kfree(ohci->it_context_list);
1904         kfree(ohci->ir_context_list);
1905         pci_iounmap(dev, ohci->registers);
1906  fail_iomem:
1907         pci_release_region(dev, 0);
1908  fail_disable:
1909         pci_disable_device(dev);
1910  fail_put_card:
1911         fw_card_put(&ohci->card);
1912
1913         return err;
1914 }
1915
1916 static void pci_remove(struct pci_dev *dev)
1917 {
1918         struct fw_ohci *ohci;
1919
1920         ohci = pci_get_drvdata(dev);
1921         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1922         flush_writes(ohci);
1923         fw_core_remove_card(&ohci->card);
1924
1925         /*
1926          * FIXME: Fail all pending packets here, now that the upper
1927          * layers can't queue any more.
1928          */
1929
1930         software_reset(ohci);
1931         free_irq(dev->irq, ohci);
1932         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1933                           ohci->self_id_cpu, ohci->self_id_bus);
1934         kfree(ohci->it_context_list);
1935         kfree(ohci->ir_context_list);
1936         pci_iounmap(dev, ohci->registers);
1937         pci_release_region(dev, 0);
1938         pci_disable_device(dev);
1939         fw_card_put(&ohci->card);
1940
1941         fw_notify("Removed fw-ohci device.\n");
1942 }
1943
1944 #ifdef CONFIG_PM
1945 static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
1946 {
1947         struct fw_ohci *ohci = pci_get_drvdata(pdev);
1948         int err;
1949
1950         software_reset(ohci);
1951         free_irq(pdev->irq, ohci);
1952         err = pci_save_state(pdev);
1953         if (err) {
1954                 fw_error("pci_save_state failed\n");
1955                 return err;
1956         }
1957         err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
1958         if (err)
1959                 fw_error("pci_set_power_state failed with %d\n", err);
1960
1961         return 0;
1962 }
1963
1964 static int pci_resume(struct pci_dev *pdev)
1965 {
1966         struct fw_ohci *ohci = pci_get_drvdata(pdev);
1967         int err;
1968
1969         pci_set_power_state(pdev, PCI_D0);
1970         pci_restore_state(pdev);
1971         err = pci_enable_device(pdev);
1972         if (err) {
1973                 fw_error("pci_enable_device failed\n");
1974                 return err;
1975         }
1976
1977         return ohci_enable(&ohci->card, ohci->config_rom, CONFIG_ROM_SIZE);
1978 }
1979 #endif
1980
1981 static struct pci_device_id pci_table[] = {
1982         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1983         { }
1984 };
1985
1986 MODULE_DEVICE_TABLE(pci, pci_table);
1987
1988 static struct pci_driver fw_ohci_pci_driver = {
1989         .name           = ohci_driver_name,
1990         .id_table       = pci_table,
1991         .probe          = pci_probe,
1992         .remove         = pci_remove,
1993 #ifdef CONFIG_PM
1994         .resume         = pci_resume,
1995         .suspend        = pci_suspend,
1996 #endif
1997 };
1998
1999 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2000 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2001 MODULE_LICENSE("GPL");
2002
2003 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2004 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2005 MODULE_ALIAS("ohci1394");
2006 #endif
2007
2008 static int __init fw_ohci_init(void)
2009 {
2010         return pci_register_driver(&fw_ohci_pci_driver);
2011 }
2012
2013 static void __exit fw_ohci_cleanup(void)
2014 {
2015         pci_unregister_driver(&fw_ohci_pci_driver);
2016 }
2017
2018 module_init(fw_ohci_init);
2019 module_exit(fw_ohci_cleanup);