1 /* Intel i7 core/Nehalem Memory Controller kernel module
3 * This driver supports the memory controllers found on the Intel
4 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
11 * Copyright (c) 2009-2010 by:
12 * Mauro Carvalho Chehab <mchehab@redhat.com>
14 * Red Hat Inc. http://www.redhat.com
16 * Forked and adapted from the i5400_edac driver
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/pci_ids.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/dmi.h>
35 #include <linux/edac.h>
36 #include <linux/mmzone.h>
37 #include <linux/smp.h>
39 #include <asm/processor.h>
40 #include <asm/div64.h>
42 #include "edac_core.h"
45 static LIST_HEAD(i7core_edac_list);
46 static DEFINE_MUTEX(i7core_edac_lock);
49 static int use_pci_fixup;
50 module_param(use_pci_fixup, int, 0444);
51 MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
53 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
54 * registers start at bus 255, and are not reported by BIOS.
55 * We currently find devices with only 2 sockets. In order to support more QPI
56 * Quick Path Interconnect, just increment this number.
58 #define MAX_SOCKET_BUSES 2
62 * Alter this version for the module when modifications are made
64 #define I7CORE_REVISION " Ver: 1.0.0"
65 #define EDAC_MOD_STR "i7core_edac"
70 #define i7core_printk(level, fmt, arg...) \
71 edac_printk(level, "i7core", fmt, ##arg)
73 #define i7core_mc_printk(mci, level, fmt, arg...) \
74 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
77 * i7core Memory Controller Registers
80 /* OFFSETS for Device 0 Function 0 */
82 #define MC_CFG_CONTROL 0x90
83 #define MC_CFG_UNLOCK 0x02
84 #define MC_CFG_LOCK 0x00
86 /* OFFSETS for Device 3 Function 0 */
88 #define MC_CONTROL 0x48
89 #define MC_STATUS 0x4c
90 #define MC_MAX_DOD 0x64
93 * OFFSETS for Device 3 Function 4, as indicated on Xeon 5500 datasheet:
94 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
97 #define MC_TEST_ERR_RCV1 0x60
98 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
100 #define MC_TEST_ERR_RCV0 0x64
101 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
102 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
104 /* OFFSETS for Device 3 Function 2, as indicated on Xeon 5500 datasheet */
105 #define MC_SSRCONTROL 0x48
106 #define SSR_MODE_DISABLE 0x00
107 #define SSR_MODE_ENABLE 0x01
108 #define SSR_MODE_MASK 0x03
110 #define MC_SCRUB_CONTROL 0x4c
111 #define STARTSCRUB (1 << 24)
112 #define SCRUBINTERVAL_MASK 0xffffff
114 #define MC_COR_ECC_CNT_0 0x80
115 #define MC_COR_ECC_CNT_1 0x84
116 #define MC_COR_ECC_CNT_2 0x88
117 #define MC_COR_ECC_CNT_3 0x8c
118 #define MC_COR_ECC_CNT_4 0x90
119 #define MC_COR_ECC_CNT_5 0x94
121 #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
122 #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
125 /* OFFSETS for Devices 4,5 and 6 Function 0 */
127 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
128 #define THREE_DIMMS_PRESENT (1 << 24)
129 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
130 #define QUAD_RANK_PRESENT (1 << 22)
131 #define REGISTERED_DIMM (1 << 15)
133 #define MC_CHANNEL_MAPPER 0x60
134 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
135 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
137 #define MC_CHANNEL_RANK_PRESENT 0x7c
138 #define RANK_PRESENT_MASK 0xffff
140 #define MC_CHANNEL_ADDR_MATCH 0xf0
141 #define MC_CHANNEL_ERROR_MASK 0xf8
142 #define MC_CHANNEL_ERROR_INJECT 0xfc
143 #define INJECT_ADDR_PARITY 0x10
144 #define INJECT_ECC 0x08
145 #define MASK_CACHELINE 0x06
146 #define MASK_FULL_CACHELINE 0x06
147 #define MASK_MSB32_CACHELINE 0x04
148 #define MASK_LSB32_CACHELINE 0x02
149 #define NO_MASK_CACHELINE 0x00
150 #define REPEAT_EN 0x01
152 /* OFFSETS for Devices 4,5 and 6 Function 1 */
154 #define MC_DOD_CH_DIMM0 0x48
155 #define MC_DOD_CH_DIMM1 0x4c
156 #define MC_DOD_CH_DIMM2 0x50
157 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
158 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
159 #define DIMM_PRESENT_MASK (1 << 9)
160 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
161 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
162 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
163 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
164 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
165 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
166 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
167 #define MC_DOD_NUMCOL_MASK 3
168 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
170 #define MC_RANK_PRESENT 0x7c
172 #define MC_SAG_CH_0 0x80
173 #define MC_SAG_CH_1 0x84
174 #define MC_SAG_CH_2 0x88
175 #define MC_SAG_CH_3 0x8c
176 #define MC_SAG_CH_4 0x90
177 #define MC_SAG_CH_5 0x94
178 #define MC_SAG_CH_6 0x98
179 #define MC_SAG_CH_7 0x9c
181 #define MC_RIR_LIMIT_CH_0 0x40
182 #define MC_RIR_LIMIT_CH_1 0x44
183 #define MC_RIR_LIMIT_CH_2 0x48
184 #define MC_RIR_LIMIT_CH_3 0x4C
185 #define MC_RIR_LIMIT_CH_4 0x50
186 #define MC_RIR_LIMIT_CH_5 0x54
187 #define MC_RIR_LIMIT_CH_6 0x58
188 #define MC_RIR_LIMIT_CH_7 0x5C
189 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
191 #define MC_RIR_WAY_CH 0x80
192 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
193 #define MC_RIR_WAY_RANK_MASK 0x7
200 #define MAX_DIMMS 3 /* Max DIMMS per channel */
201 #define MAX_MCR_FUNC 4
202 #define MAX_CHAN_FUNC 3
212 struct i7core_inject {
219 /* Error address mask */
220 int channel, dimm, rank, bank, page, col;
223 struct i7core_channel {
224 bool is_3dimms_present;
225 bool is_single_4rank;
230 struct pci_id_descr {
237 struct pci_id_table {
238 const struct pci_id_descr *descr;
243 struct list_head list;
245 struct pci_dev **pdev;
247 struct mem_ctl_info *mci;
251 struct device *addrmatch_dev, *chancounts_dev;
253 struct pci_dev *pci_noncore;
254 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
255 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
257 struct i7core_dev *i7core_dev;
259 struct i7core_info info;
260 struct i7core_inject inject;
261 struct i7core_channel channel[NUM_CHANS];
263 int ce_count_available;
265 /* ECC corrected errors counts per udimm */
266 unsigned long udimm_ce_count[MAX_DIMMS];
267 int udimm_last_ce_count[MAX_DIMMS];
268 /* ECC corrected errors counts per rdimm */
269 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
270 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
272 bool is_registered, enable_scrub;
274 /* Fifo double buffers */
275 struct mce mce_entry[MCE_LOG_LEN];
276 struct mce mce_outentry[MCE_LOG_LEN];
278 /* Fifo in/out counters */
279 unsigned mce_in, mce_out;
281 /* Count indicator to show errors not got */
282 unsigned mce_overrun;
284 /* DCLK Frequency used for computing scrub rate */
287 /* Struct to control EDAC polling */
288 struct edac_pci_ctl_info *i7core_pci;
291 #define PCI_DESCR(device, function, device_id) \
293 .func = (function), \
294 .dev_id = (device_id)
296 static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
297 /* Memory controller */
298 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
299 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
300 /* Exists only for RDIMM */
301 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
302 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
305 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
306 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
307 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
308 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
311 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
312 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
313 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
314 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
317 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
318 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
319 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
320 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
322 /* Generic Non-core registers */
324 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
325 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
326 * the probing code needs to test for the other address in case of
327 * failure of this one
329 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
333 static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
334 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
335 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
336 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
338 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
339 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
340 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
341 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
343 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
344 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
345 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
346 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
349 * This is the PCI device has an alternate address on some
350 * processors like Core i7 860
352 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
355 static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
356 /* Memory controller */
357 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
358 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
359 /* Exists only for RDIMM */
360 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
361 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
364 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
365 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
366 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
367 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
370 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
371 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
372 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
373 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
376 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
377 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
378 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
379 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
381 /* Generic Non-core registers */
382 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
386 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
387 static const struct pci_id_table pci_dev_table[] = {
388 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
389 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
390 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
391 {0,} /* 0 terminated list. */
395 * pci_device_id table for which devices we are looking for
397 static const struct pci_device_id i7core_pci_tbl[] = {
398 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
399 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
400 {0,} /* 0 terminated list. */
403 /****************************************************************************
404 Ancillary status routines
405 ****************************************************************************/
407 /* MC_CONTROL bits */
408 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
409 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
412 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
413 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
415 /* MC_MAX_DOD read functions */
416 static inline int numdimms(u32 dimms)
418 return (dimms & 0x3) + 1;
421 static inline int numrank(u32 rank)
423 static const int ranks[] = { 1, 2, 4, -EINVAL };
425 return ranks[rank & 0x3];
428 static inline int numbank(u32 bank)
430 static const int banks[] = { 4, 8, 16, -EINVAL };
432 return banks[bank & 0x3];
435 static inline int numrow(u32 row)
437 static const int rows[] = {
438 1 << 12, 1 << 13, 1 << 14, 1 << 15,
439 1 << 16, -EINVAL, -EINVAL, -EINVAL,
442 return rows[row & 0x7];
445 static inline int numcol(u32 col)
447 static const int cols[] = {
448 1 << 10, 1 << 11, 1 << 12, -EINVAL,
450 return cols[col & 0x3];
453 static struct i7core_dev *get_i7core_dev(u8 socket)
455 struct i7core_dev *i7core_dev;
457 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
458 if (i7core_dev->socket == socket)
465 static struct i7core_dev *alloc_i7core_dev(u8 socket,
466 const struct pci_id_table *table)
468 struct i7core_dev *i7core_dev;
470 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
474 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
476 if (!i7core_dev->pdev) {
481 i7core_dev->socket = socket;
482 i7core_dev->n_devs = table->n_devs;
483 list_add_tail(&i7core_dev->list, &i7core_edac_list);
488 static void free_i7core_dev(struct i7core_dev *i7core_dev)
490 list_del(&i7core_dev->list);
491 kfree(i7core_dev->pdev);
495 /****************************************************************************
496 Memory check routines
497 ****************************************************************************/
499 static int get_dimm_config(struct mem_ctl_info *mci)
501 struct i7core_pvt *pvt = mci->pvt_info;
502 struct pci_dev *pdev;
506 struct dimm_info *dimm;
508 /* Get data from the MC register, function 0 */
509 pdev = pvt->pci_mcr[0];
513 /* Device 3 function 0 reads */
514 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
515 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
516 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
517 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
519 edac_dbg(0, "QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
520 pvt->i7core_dev->socket, pvt->info.mc_control,
521 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map);
523 if (ECC_ENABLED(pvt)) {
524 edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
526 mode = EDAC_S8ECD8ED;
528 mode = EDAC_S4ECD4ED;
530 edac_dbg(0, "ECC disabled\n");
534 /* FIXME: need to handle the error codes */
535 edac_dbg(0, "DOD Max limits: DIMMS: %d, %d-ranked, %d-banked x%x x 0x%x\n",
536 numdimms(pvt->info.max_dod),
537 numrank(pvt->info.max_dod >> 2),
538 numbank(pvt->info.max_dod >> 4),
539 numrow(pvt->info.max_dod >> 6),
540 numcol(pvt->info.max_dod >> 9));
542 for (i = 0; i < NUM_CHANS; i++) {
543 u32 data, dimm_dod[3], value[8];
545 if (!pvt->pci_ch[i][0])
548 if (!CH_ACTIVE(pvt, i)) {
549 edac_dbg(0, "Channel %i is not active\n", i);
552 if (CH_DISABLED(pvt, i)) {
553 edac_dbg(0, "Channel %i is disabled\n", i);
557 /* Devices 4-6 function 0 */
558 pci_read_config_dword(pvt->pci_ch[i][0],
559 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
562 if (data & THREE_DIMMS_PRESENT)
563 pvt->channel[i].is_3dimms_present = true;
565 if (data & SINGLE_QUAD_RANK_PRESENT)
566 pvt->channel[i].is_single_4rank = true;
568 if (data & QUAD_RANK_PRESENT)
569 pvt->channel[i].has_4rank = true;
571 if (data & REGISTERED_DIMM)
576 /* Devices 4-6 function 1 */
577 pci_read_config_dword(pvt->pci_ch[i][1],
578 MC_DOD_CH_DIMM0, &dimm_dod[0]);
579 pci_read_config_dword(pvt->pci_ch[i][1],
580 MC_DOD_CH_DIMM1, &dimm_dod[1]);
581 pci_read_config_dword(pvt->pci_ch[i][1],
582 MC_DOD_CH_DIMM2, &dimm_dod[2]);
584 edac_dbg(0, "Ch%d phy rd%d, wr%d (0x%08x): %s%s%s%cDIMMs\n",
586 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
588 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
589 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
590 pvt->channel[i].has_4rank ? "HAS_4R " : "",
591 (data & REGISTERED_DIMM) ? 'R' : 'U');
593 for (j = 0; j < 3; j++) {
594 u32 banks, ranks, rows, cols;
597 if (!DIMM_PRESENT(dimm_dod[j]))
600 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
602 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
603 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
604 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
605 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
607 /* DDR3 has 8 I/O banks */
608 size = (rows * cols * banks * ranks) >> (20 - 3);
610 edac_dbg(0, "\tdimm %d %d Mb offset: %x, bank: %d, rank: %d, row: %#x, col: %#x\n",
612 RANKOFFSET(dimm_dod[j]),
613 banks, ranks, rows, cols);
615 npages = MiB_TO_PAGES(size);
617 dimm->nr_pages = npages;
621 dimm->dtype = DEV_X4;
624 dimm->dtype = DEV_X8;
627 dimm->dtype = DEV_X16;
630 dimm->dtype = DEV_UNKNOWN;
633 snprintf(dimm->label, sizeof(dimm->label),
634 "CPU#%uChannel#%u_DIMM#%u",
635 pvt->i7core_dev->socket, i, j);
637 dimm->edac_mode = mode;
641 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
642 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
643 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
644 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
645 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
646 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
647 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
648 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
649 edac_dbg(1, "\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
650 for (j = 0; j < 8; j++)
651 edac_dbg(1, "\t\t%#x\t%#x\t%#x\n",
652 (value[j] >> 27) & 0x1,
653 (value[j] >> 24) & 0x7,
654 (value[j] & ((1 << 24) - 1)));
660 /****************************************************************************
661 Error insertion routines
662 ****************************************************************************/
664 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
666 /* The i7core has independent error injection features per channel.
667 However, to have a simpler code, we don't allow enabling error injection
668 on more than one channel.
669 Also, since a change at an inject parameter will be applied only at enable,
670 we're disabling error injection on all write calls to the sysfs nodes that
671 controls the error code injection.
673 static int disable_inject(const struct mem_ctl_info *mci)
675 struct i7core_pvt *pvt = mci->pvt_info;
677 pvt->inject.enable = 0;
679 if (!pvt->pci_ch[pvt->inject.channel][0])
682 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
683 MC_CHANNEL_ERROR_INJECT, 0);
689 * i7core inject inject.section
691 * accept and store error injection inject.section value
692 * bit 0 - refers to the lower 32-byte half cacheline
693 * bit 1 - refers to the upper 32-byte half cacheline
695 static ssize_t i7core_inject_section_store(struct device *dev,
696 struct device_attribute *mattr,
697 const char *data, size_t count)
699 struct mem_ctl_info *mci = to_mci(dev);
700 struct i7core_pvt *pvt = mci->pvt_info;
704 if (pvt->inject.enable)
707 rc = kstrtoul(data, 10, &value);
708 if ((rc < 0) || (value > 3))
711 pvt->inject.section = (u32) value;
715 static ssize_t i7core_inject_section_show(struct device *dev,
716 struct device_attribute *mattr,
719 struct mem_ctl_info *mci = to_mci(dev);
720 struct i7core_pvt *pvt = mci->pvt_info;
721 return sprintf(data, "0x%08x\n", pvt->inject.section);
727 * accept and store error injection inject.section value
728 * bit 0 - repeat enable - Enable error repetition
729 * bit 1 - inject ECC error
730 * bit 2 - inject parity error
732 static ssize_t i7core_inject_type_store(struct device *dev,
733 struct device_attribute *mattr,
734 const char *data, size_t count)
736 struct mem_ctl_info *mci = to_mci(dev);
737 struct i7core_pvt *pvt = mci->pvt_info;
741 if (pvt->inject.enable)
744 rc = kstrtoul(data, 10, &value);
745 if ((rc < 0) || (value > 7))
748 pvt->inject.type = (u32) value;
752 static ssize_t i7core_inject_type_show(struct device *dev,
753 struct device_attribute *mattr,
756 struct mem_ctl_info *mci = to_mci(dev);
757 struct i7core_pvt *pvt = mci->pvt_info;
759 return sprintf(data, "0x%08x\n", pvt->inject.type);
763 * i7core_inject_inject.eccmask_store
765 * The type of error (UE/CE) will depend on the inject.eccmask value:
766 * Any bits set to a 1 will flip the corresponding ECC bit
767 * Correctable errors can be injected by flipping 1 bit or the bits within
768 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
769 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
770 * uncorrectable error to be injected.
772 static ssize_t i7core_inject_eccmask_store(struct device *dev,
773 struct device_attribute *mattr,
774 const char *data, size_t count)
776 struct mem_ctl_info *mci = to_mci(dev);
777 struct i7core_pvt *pvt = mci->pvt_info;
781 if (pvt->inject.enable)
784 rc = kstrtoul(data, 10, &value);
788 pvt->inject.eccmask = (u32) value;
792 static ssize_t i7core_inject_eccmask_show(struct device *dev,
793 struct device_attribute *mattr,
796 struct mem_ctl_info *mci = to_mci(dev);
797 struct i7core_pvt *pvt = mci->pvt_info;
799 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
805 * The type of error (UE/CE) will depend on the inject.eccmask value:
806 * Any bits set to a 1 will flip the corresponding ECC bit
807 * Correctable errors can be injected by flipping 1 bit or the bits within
808 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
809 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
810 * uncorrectable error to be injected.
813 #define DECLARE_ADDR_MATCH(param, limit) \
814 static ssize_t i7core_inject_store_##param( \
815 struct device *dev, \
816 struct device_attribute *mattr, \
817 const char *data, size_t count) \
819 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
820 struct i7core_pvt *pvt; \
825 pvt = mci->pvt_info; \
827 if (pvt->inject.enable) \
828 disable_inject(mci); \
830 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
833 rc = kstrtoul(data, 10, &value); \
834 if ((rc < 0) || (value >= limit)) \
838 pvt->inject.param = value; \
843 static ssize_t i7core_inject_show_##param( \
844 struct device *dev, \
845 struct device_attribute *mattr, \
848 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
849 struct i7core_pvt *pvt; \
851 pvt = mci->pvt_info; \
852 edac_dbg(1, "pvt=%p\n", pvt); \
853 if (pvt->inject.param < 0) \
854 return sprintf(data, "any\n"); \
856 return sprintf(data, "%d\n", pvt->inject.param);\
859 #define ATTR_ADDR_MATCH(param) \
860 static DEVICE_ATTR(param, S_IRUGO | S_IWUSR, \
861 i7core_inject_show_##param, \
862 i7core_inject_store_##param)
864 DECLARE_ADDR_MATCH(channel, 3);
865 DECLARE_ADDR_MATCH(dimm, 3);
866 DECLARE_ADDR_MATCH(rank, 4);
867 DECLARE_ADDR_MATCH(bank, 32);
868 DECLARE_ADDR_MATCH(page, 0x10000);
869 DECLARE_ADDR_MATCH(col, 0x4000);
871 ATTR_ADDR_MATCH(channel);
872 ATTR_ADDR_MATCH(dimm);
873 ATTR_ADDR_MATCH(rank);
874 ATTR_ADDR_MATCH(bank);
875 ATTR_ADDR_MATCH(page);
876 ATTR_ADDR_MATCH(col);
878 static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
883 edac_dbg(0, "setting pci %02x:%02x.%x reg=%02x value=%08x\n",
884 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
887 for (count = 0; count < 10; count++) {
890 pci_write_config_dword(dev, where, val);
891 pci_read_config_dword(dev, where, &read);
897 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
898 "write=%08x. Read=%08x\n",
899 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
906 * This routine prepares the Memory Controller for error injection.
907 * The error will be injected when some process tries to write to the
908 * memory that matches the given criteria.
909 * The criteria can be set in terms of a mask where dimm, rank, bank, page
910 * and col can be specified.
911 * A -1 value for any of the mask items will make the MCU to ignore
912 * that matching criteria for error injection.
914 * It should be noticed that the error will only happen after a write operation
915 * on a memory that matches the condition. if REPEAT_EN is not enabled at
916 * inject mask, then it will produce just one error. Otherwise, it will repeat
917 * until the injectmask would be cleaned.
919 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
920 * is reliable enough to check if the MC is using the
921 * three channels. However, this is not clear at the datasheet.
923 static ssize_t i7core_inject_enable_store(struct device *dev,
924 struct device_attribute *mattr,
925 const char *data, size_t count)
927 struct mem_ctl_info *mci = to_mci(dev);
928 struct i7core_pvt *pvt = mci->pvt_info;
934 if (!pvt->pci_ch[pvt->inject.channel][0])
937 rc = kstrtoul(data, 10, &enable);
942 pvt->inject.enable = 1;
948 /* Sets pvt->inject.dimm mask */
949 if (pvt->inject.dimm < 0)
952 if (pvt->channel[pvt->inject.channel].dimms > 2)
953 mask |= (pvt->inject.dimm & 0x3LL) << 35;
955 mask |= (pvt->inject.dimm & 0x1LL) << 36;
958 /* Sets pvt->inject.rank mask */
959 if (pvt->inject.rank < 0)
962 if (pvt->channel[pvt->inject.channel].dimms > 2)
963 mask |= (pvt->inject.rank & 0x1LL) << 34;
965 mask |= (pvt->inject.rank & 0x3LL) << 34;
968 /* Sets pvt->inject.bank mask */
969 if (pvt->inject.bank < 0)
972 mask |= (pvt->inject.bank & 0x15LL) << 30;
974 /* Sets pvt->inject.page mask */
975 if (pvt->inject.page < 0)
978 mask |= (pvt->inject.page & 0xffff) << 14;
980 /* Sets pvt->inject.column mask */
981 if (pvt->inject.col < 0)
984 mask |= (pvt->inject.col & 0x3fff);
988 * bits 1-2: MASK_HALF_CACHELINE
990 * bit 4: INJECT_ADDR_PARITY
993 injectmask = (pvt->inject.type & 1) |
994 (pvt->inject.section & 0x3) << 1 |
995 (pvt->inject.type & 0x6) << (3 - 1);
997 /* Unlock writes to registers - this register is write only */
998 pci_write_config_dword(pvt->pci_noncore,
999 MC_CFG_CONTROL, 0x2);
1001 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1002 MC_CHANNEL_ADDR_MATCH, mask);
1003 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1004 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1006 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1007 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1009 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1010 MC_CHANNEL_ERROR_INJECT, injectmask);
1013 * This is something undocumented, based on my tests
1014 * Without writing 8 to this register, errors aren't injected. Not sure
1017 pci_write_config_dword(pvt->pci_noncore,
1020 edac_dbg(0, "Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",
1021 mask, pvt->inject.eccmask, injectmask);
1027 static ssize_t i7core_inject_enable_show(struct device *dev,
1028 struct device_attribute *mattr,
1031 struct mem_ctl_info *mci = to_mci(dev);
1032 struct i7core_pvt *pvt = mci->pvt_info;
1035 if (!pvt->pci_ch[pvt->inject.channel][0])
1038 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1039 MC_CHANNEL_ERROR_INJECT, &injectmask);
1041 edac_dbg(0, "Inject error read: 0x%018x\n", injectmask);
1043 if (injectmask & 0x0c)
1044 pvt->inject.enable = 1;
1046 return sprintf(data, "%d\n", pvt->inject.enable);
1049 #define DECLARE_COUNTER(param) \
1050 static ssize_t i7core_show_counter_##param( \
1051 struct device *dev, \
1052 struct device_attribute *mattr, \
1055 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
1056 struct i7core_pvt *pvt = mci->pvt_info; \
1058 edac_dbg(1, "\n"); \
1059 if (!pvt->ce_count_available || (pvt->is_registered)) \
1060 return sprintf(data, "data unavailable\n"); \
1061 return sprintf(data, "%lu\n", \
1062 pvt->udimm_ce_count[param]); \
1065 #define ATTR_COUNTER(param) \
1066 static DEVICE_ATTR(udimm##param, S_IRUGO | S_IWUSR, \
1067 i7core_show_counter_##param, \
1079 * inject_addrmatch device sysfs struct
1082 static struct attribute *i7core_addrmatch_attrs[] = {
1083 &dev_attr_channel.attr,
1084 &dev_attr_dimm.attr,
1085 &dev_attr_rank.attr,
1086 &dev_attr_bank.attr,
1087 &dev_attr_page.attr,
1092 static struct attribute_group addrmatch_grp = {
1093 .attrs = i7core_addrmatch_attrs,
1096 static const struct attribute_group *addrmatch_groups[] = {
1101 static void addrmatch_release(struct device *device)
1103 edac_dbg(1, "Releasing device %s\n", dev_name(device));
1107 static struct device_type addrmatch_type = {
1108 .groups = addrmatch_groups,
1109 .release = addrmatch_release,
1113 * all_channel_counts sysfs struct
1116 static struct attribute *i7core_udimm_counters_attrs[] = {
1117 &dev_attr_udimm0.attr,
1118 &dev_attr_udimm1.attr,
1119 &dev_attr_udimm2.attr,
1123 static struct attribute_group all_channel_counts_grp = {
1124 .attrs = i7core_udimm_counters_attrs,
1127 static const struct attribute_group *all_channel_counts_groups[] = {
1128 &all_channel_counts_grp,
1132 static void all_channel_counts_release(struct device *device)
1134 edac_dbg(1, "Releasing device %s\n", dev_name(device));
1138 static struct device_type all_channel_counts_type = {
1139 .groups = all_channel_counts_groups,
1140 .release = all_channel_counts_release,
1144 * inject sysfs attributes
1147 static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
1148 i7core_inject_section_show, i7core_inject_section_store);
1150 static DEVICE_ATTR(inject_type, S_IRUGO | S_IWUSR,
1151 i7core_inject_type_show, i7core_inject_type_store);
1154 static DEVICE_ATTR(inject_eccmask, S_IRUGO | S_IWUSR,
1155 i7core_inject_eccmask_show, i7core_inject_eccmask_store);
1157 static DEVICE_ATTR(inject_enable, S_IRUGO | S_IWUSR,
1158 i7core_inject_enable_show, i7core_inject_enable_store);
1160 static int i7core_create_sysfs_devices(struct mem_ctl_info *mci)
1162 struct i7core_pvt *pvt = mci->pvt_info;
1165 rc = device_create_file(&mci->dev, &dev_attr_inject_section);
1168 rc = device_create_file(&mci->dev, &dev_attr_inject_type);
1171 rc = device_create_file(&mci->dev, &dev_attr_inject_eccmask);
1174 rc = device_create_file(&mci->dev, &dev_attr_inject_enable);
1178 pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL);
1179 if (!pvt->addrmatch_dev)
1182 pvt->addrmatch_dev->type = &addrmatch_type;
1183 pvt->addrmatch_dev->bus = mci->dev.bus;
1184 device_initialize(pvt->addrmatch_dev);
1185 pvt->addrmatch_dev->parent = &mci->dev;
1186 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch");
1187 dev_set_drvdata(pvt->addrmatch_dev, mci);
1189 edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev));
1191 rc = device_add(pvt->addrmatch_dev);
1195 if (!pvt->is_registered) {
1196 pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev),
1198 if (!pvt->chancounts_dev) {
1199 put_device(pvt->addrmatch_dev);
1200 device_del(pvt->addrmatch_dev);
1204 pvt->chancounts_dev->type = &all_channel_counts_type;
1205 pvt->chancounts_dev->bus = mci->dev.bus;
1206 device_initialize(pvt->chancounts_dev);
1207 pvt->chancounts_dev->parent = &mci->dev;
1208 dev_set_name(pvt->chancounts_dev, "all_channel_counts");
1209 dev_set_drvdata(pvt->chancounts_dev, mci);
1211 edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev));
1213 rc = device_add(pvt->chancounts_dev);
1220 static void i7core_delete_sysfs_devices(struct mem_ctl_info *mci)
1222 struct i7core_pvt *pvt = mci->pvt_info;
1226 device_remove_file(&mci->dev, &dev_attr_inject_section);
1227 device_remove_file(&mci->dev, &dev_attr_inject_type);
1228 device_remove_file(&mci->dev, &dev_attr_inject_eccmask);
1229 device_remove_file(&mci->dev, &dev_attr_inject_enable);
1231 if (!pvt->is_registered) {
1232 put_device(pvt->chancounts_dev);
1233 device_del(pvt->chancounts_dev);
1235 put_device(pvt->addrmatch_dev);
1236 device_del(pvt->addrmatch_dev);
1239 /****************************************************************************
1240 Device initialization routines: put/get, init/exit
1241 ****************************************************************************/
1244 * i7core_put_all_devices 'put' all the devices that we have
1245 * reserved via 'get'
1247 static void i7core_put_devices(struct i7core_dev *i7core_dev)
1252 for (i = 0; i < i7core_dev->n_devs; i++) {
1253 struct pci_dev *pdev = i7core_dev->pdev[i];
1256 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1258 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1263 static void i7core_put_all_devices(void)
1265 struct i7core_dev *i7core_dev, *tmp;
1267 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
1268 i7core_put_devices(i7core_dev);
1269 free_i7core_dev(i7core_dev);
1273 static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
1275 struct pci_dev *pdev = NULL;
1279 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
1280 * aren't announced by acpi. So, we need to use a legacy scan probing
1283 while (table && table->descr) {
1284 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1285 if (unlikely(!pdev)) {
1286 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1287 pcibios_scan_specific_bus(255-i);
1294 static unsigned i7core_pci_lastbus(void)
1296 int last_bus = 0, bus;
1297 struct pci_bus *b = NULL;
1299 while ((b = pci_find_next_bus(b)) != NULL) {
1301 edac_dbg(0, "Found bus %d\n", bus);
1306 edac_dbg(0, "Last bus %d\n", last_bus);
1312 * i7core_get_all_devices Find and perform 'get' operation on the MCH's
1313 * device/functions we want to reference for this driver
1315 * Need to 'get' device 16 func 1 and func 2
1317 static int i7core_get_onedevice(struct pci_dev **prev,
1318 const struct pci_id_table *table,
1319 const unsigned devno,
1320 const unsigned last_bus)
1322 struct i7core_dev *i7core_dev;
1323 const struct pci_id_descr *dev_descr = &table->descr[devno];
1325 struct pci_dev *pdev = NULL;
1329 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1330 dev_descr->dev_id, *prev);
1333 * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs
1334 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1335 * to probe for the alternate address in case of failure
1337 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) {
1338 pci_dev_get(*prev); /* pci_get_device will put it */
1339 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1340 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1343 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE &&
1345 pci_dev_get(*prev); /* pci_get_device will put it */
1346 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1347 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1357 if (dev_descr->optional)
1363 i7core_printk(KERN_INFO,
1364 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1365 dev_descr->dev, dev_descr->func,
1366 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1368 /* End of list, leave */
1371 bus = pdev->bus->number;
1373 socket = last_bus - bus;
1375 i7core_dev = get_i7core_dev(socket);
1377 i7core_dev = alloc_i7core_dev(socket, table);
1384 if (i7core_dev->pdev[devno]) {
1385 i7core_printk(KERN_ERR,
1386 "Duplicated device for "
1387 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1388 bus, dev_descr->dev, dev_descr->func,
1389 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1394 i7core_dev->pdev[devno] = pdev;
1397 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1398 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1399 i7core_printk(KERN_ERR,
1400 "Device PCI ID %04x:%04x "
1401 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1402 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1403 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1404 bus, dev_descr->dev, dev_descr->func);
1408 /* Be sure that the device is enabled */
1409 if (unlikely(pci_enable_device(pdev) < 0)) {
1410 i7core_printk(KERN_ERR,
1412 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1413 bus, dev_descr->dev, dev_descr->func,
1414 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1418 edac_dbg(0, "Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1419 socket, bus, dev_descr->dev,
1421 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1424 * As stated on drivers/pci/search.c, the reference count for
1425 * @from is always decremented if it is not %NULL. So, as we need
1426 * to get all devices up to null, we need to do a get for the device
1435 static int i7core_get_all_devices(void)
1437 int i, rc, last_bus;
1438 struct pci_dev *pdev = NULL;
1439 const struct pci_id_table *table = pci_dev_table;
1441 last_bus = i7core_pci_lastbus();
1443 while (table && table->descr) {
1444 for (i = 0; i < table->n_devs; i++) {
1447 rc = i7core_get_onedevice(&pdev, table, i,
1454 i7core_put_all_devices();
1465 static int mci_bind_devs(struct mem_ctl_info *mci,
1466 struct i7core_dev *i7core_dev)
1468 struct i7core_pvt *pvt = mci->pvt_info;
1469 struct pci_dev *pdev;
1473 pvt->is_registered = false;
1474 pvt->enable_scrub = false;
1475 for (i = 0; i < i7core_dev->n_devs; i++) {
1476 pdev = i7core_dev->pdev[i];
1480 func = PCI_FUNC(pdev->devfn);
1481 slot = PCI_SLOT(pdev->devfn);
1483 if (unlikely(func > MAX_MCR_FUNC))
1485 pvt->pci_mcr[func] = pdev;
1486 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1487 if (unlikely(func > MAX_CHAN_FUNC))
1489 pvt->pci_ch[slot - 4][func] = pdev;
1490 } else if (!slot && !func) {
1491 pvt->pci_noncore = pdev;
1493 /* Detect the processor family */
1494 switch (pdev->device) {
1495 case PCI_DEVICE_ID_INTEL_I7_NONCORE:
1496 family = "Xeon 35xx/ i7core";
1497 pvt->enable_scrub = false;
1499 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
1500 family = "i7-800/i5-700";
1501 pvt->enable_scrub = false;
1503 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
1504 family = "Xeon 34xx";
1505 pvt->enable_scrub = false;
1507 case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
1508 family = "Xeon 55xx";
1509 pvt->enable_scrub = true;
1511 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
1512 family = "Xeon 56xx / i7-900";
1513 pvt->enable_scrub = true;
1517 pvt->enable_scrub = false;
1519 edac_dbg(0, "Detected a processor type %s\n", family);
1523 edac_dbg(0, "Associated fn %d.%d, dev = %p, socket %d\n",
1524 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1525 pdev, i7core_dev->socket);
1527 if (PCI_SLOT(pdev->devfn) == 3 &&
1528 PCI_FUNC(pdev->devfn) == 2)
1529 pvt->is_registered = true;
1535 i7core_printk(KERN_ERR, "Device %d, function %d "
1536 "is out of the expected range\n",
1541 /****************************************************************************
1542 Error check routines
1543 ****************************************************************************/
1545 static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
1551 struct i7core_pvt *pvt = mci->pvt_info;
1552 int add0 = 0, add1 = 0, add2 = 0;
1553 /* Updates CE counters if it is not the first time here */
1554 if (pvt->ce_count_available) {
1555 /* Updates CE counters */
1557 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1558 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1559 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1563 pvt->rdimm_ce_count[chan][2] += add2;
1567 pvt->rdimm_ce_count[chan][1] += add1;
1571 pvt->rdimm_ce_count[chan][0] += add0;
1573 pvt->ce_count_available = 1;
1575 /* Store the new values */
1576 pvt->rdimm_last_ce_count[chan][2] = new2;
1577 pvt->rdimm_last_ce_count[chan][1] = new1;
1578 pvt->rdimm_last_ce_count[chan][0] = new0;
1580 /*updated the edac core */
1582 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add0,
1584 chan, 0, -1, "error", "");
1586 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add1,
1588 chan, 1, -1, "error", "");
1590 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add2,
1592 chan, 2, -1, "error", "");
1595 static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1597 struct i7core_pvt *pvt = mci->pvt_info;
1599 int i, new0, new1, new2;
1601 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
1602 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1604 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1606 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1608 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1610 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1612 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1614 for (i = 0 ; i < 3; i++) {
1615 edac_dbg(3, "MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1616 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1617 /*if the channel has 3 dimms*/
1618 if (pvt->channel[i].dimms > 2) {
1619 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1620 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1621 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1623 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1624 DIMM_BOT_COR_ERR(rcv[i][0]);
1625 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1626 DIMM_BOT_COR_ERR(rcv[i][1]);
1630 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
1634 /* This function is based on the device 3 function 4 registers as described on:
1635 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1636 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1637 * also available at:
1638 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1640 static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1642 struct i7core_pvt *pvt = mci->pvt_info;
1644 int new0, new1, new2;
1646 if (!pvt->pci_mcr[4]) {
1647 edac_dbg(0, "MCR registers not found\n");
1651 /* Corrected test errors */
1652 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1653 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1655 /* Store the new values */
1656 new2 = DIMM2_COR_ERR(rcv1);
1657 new1 = DIMM1_COR_ERR(rcv0);
1658 new0 = DIMM0_COR_ERR(rcv0);
1660 /* Updates CE counters if it is not the first time here */
1661 if (pvt->ce_count_available) {
1662 /* Updates CE counters */
1663 int add0, add1, add2;
1665 add2 = new2 - pvt->udimm_last_ce_count[2];
1666 add1 = new1 - pvt->udimm_last_ce_count[1];
1667 add0 = new0 - pvt->udimm_last_ce_count[0];
1671 pvt->udimm_ce_count[2] += add2;
1675 pvt->udimm_ce_count[1] += add1;
1679 pvt->udimm_ce_count[0] += add0;
1681 if (add0 | add1 | add2)
1682 i7core_printk(KERN_ERR, "New Corrected error(s): "
1683 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1686 pvt->ce_count_available = 1;
1688 /* Store the new values */
1689 pvt->udimm_last_ce_count[2] = new2;
1690 pvt->udimm_last_ce_count[1] = new1;
1691 pvt->udimm_last_ce_count[0] = new0;
1695 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1696 * Architectures Software Developer’s Manual Volume 3B.
1697 * Nehalem are defined as family 0x06, model 0x1a
1699 * The MCA registers used here are the following ones:
1700 * struct mce field MCA Register
1701 * m->status MSR_IA32_MC8_STATUS
1702 * m->addr MSR_IA32_MC8_ADDR
1703 * m->misc MSR_IA32_MC8_MISC
1704 * In the case of Nehalem, the error information is masked at .status and .misc
1707 static void i7core_mce_output_error(struct mem_ctl_info *mci,
1708 const struct mce *m)
1710 struct i7core_pvt *pvt = mci->pvt_info;
1711 char *type, *optype, *err;
1712 enum hw_event_mc_err_type tp_event;
1713 unsigned long error = m->status & 0x1ff0000l;
1714 bool uncorrected_error = m->mcgstatus & 1ll << 61;
1715 bool ripv = m->mcgstatus & 1;
1716 u32 optypenum = (m->status >> 4) & 0x07;
1717 u32 core_err_cnt = (m->status >> 38) & 0x7fff;
1718 u32 dimm = (m->misc >> 16) & 0x3;
1719 u32 channel = (m->misc >> 18) & 0x3;
1720 u32 syndrome = m->misc >> 32;
1721 u32 errnum = find_first_bit(&error, 32);
1723 if (uncorrected_error) {
1726 tp_event = HW_EVENT_ERR_FATAL;
1729 tp_event = HW_EVENT_ERR_UNCORRECTED;
1733 tp_event = HW_EVENT_ERR_CORRECTED;
1736 switch (optypenum) {
1738 optype = "generic undef request";
1741 optype = "read error";
1744 optype = "write error";
1747 optype = "addr/cmd error";
1750 optype = "scrubbing error";
1753 optype = "reserved";
1759 err = "read ECC error";
1762 err = "RAS ECC error";
1765 err = "write parity error";
1768 err = "redundacy loss";
1774 err = "memory range error";
1777 err = "RTID out of range";
1780 err = "address parity error";
1783 err = "byte enable parity error";
1790 * Call the helper to output message
1791 * FIXME: what to do if core_err_cnt > 1? Currently, it generates
1794 if (uncorrected_error || !pvt->is_registered)
1795 edac_mc_handle_error(tp_event, mci, core_err_cnt,
1796 m->addr >> PAGE_SHIFT,
1797 m->addr & ~PAGE_MASK,
1804 * i7core_check_error Retrieve and process errors reported by the
1805 * hardware. Called by the Core module.
1807 static void i7core_check_error(struct mem_ctl_info *mci)
1809 struct i7core_pvt *pvt = mci->pvt_info;
1815 * MCE first step: Copy all mce errors into a temporary buffer
1816 * We use a double buffering here, to reduce the risk of
1820 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1823 goto check_ce_error;
1825 m = pvt->mce_outentry;
1826 if (pvt->mce_in + count > MCE_LOG_LEN) {
1827 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1829 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1835 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1837 pvt->mce_in += count;
1840 if (pvt->mce_overrun) {
1841 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1844 pvt->mce_overrun = 0;
1848 * MCE second step: parse errors and display
1850 for (i = 0; i < count; i++)
1851 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
1854 * Now, let's increment CE error counts
1857 if (!pvt->is_registered)
1858 i7core_udimm_check_mc_ecc_err(mci);
1860 i7core_rdimm_check_mc_ecc_err(mci);
1864 * i7core_mce_check_error Replicates mcelog routine to get errors
1865 * This routine simply queues mcelog errors, and
1866 * return. The error itself should be handled later
1867 * by i7core_check_error.
1868 * WARNING: As this routine should be called at NMI time, extra care should
1869 * be taken to avoid deadlocks, and to be as fast as possible.
1871 static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
1874 struct mce *mce = (struct mce *)data;
1875 struct i7core_dev *i7_dev;
1876 struct mem_ctl_info *mci;
1877 struct i7core_pvt *pvt;
1879 i7_dev = get_i7core_dev(mce->socketid);
1884 pvt = mci->pvt_info;
1887 * Just let mcelog handle it if the error is
1888 * outside the memory controller
1890 if (((mce->status & 0xffff) >> 7) != 1)
1893 /* Bank 8 registers are the only ones that we know how to handle */
1898 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1904 /* Copy memory error at the ringbuffer */
1905 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1907 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1909 /* Handle fatal errors immediately */
1910 if (mce->mcgstatus & 1)
1911 i7core_check_error(mci);
1913 /* Advise mcelog that the errors were handled */
1917 static struct notifier_block i7_mce_dec = {
1918 .notifier_call = i7core_mce_check_error,
1921 struct memdev_dmi_entry {
1925 u16 phys_mem_array_handle;
1926 u16 mem_err_info_handle;
1943 u16 conf_mem_clk_speed;
1944 } __attribute__((__packed__));
1948 * Decode the DRAM Clock Frequency, be paranoid, make sure that all
1949 * memory devices show the same speed, and if they don't then consider
1950 * all speeds to be invalid.
1952 static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
1954 int *dclk_freq = _dclk_freq;
1955 u16 dmi_mem_clk_speed;
1957 if (*dclk_freq == -1)
1960 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
1961 struct memdev_dmi_entry *memdev_dmi_entry =
1962 (struct memdev_dmi_entry *)dh;
1963 unsigned long conf_mem_clk_speed_offset =
1964 (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
1965 (unsigned long)&memdev_dmi_entry->type;
1966 unsigned long speed_offset =
1967 (unsigned long)&memdev_dmi_entry->speed -
1968 (unsigned long)&memdev_dmi_entry->type;
1970 /* Check that a DIMM is present */
1971 if (memdev_dmi_entry->size == 0)
1975 * Pick the configured speed if it's available, otherwise
1976 * pick the DIMM speed, or we don't have a speed.
1978 if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
1980 memdev_dmi_entry->conf_mem_clk_speed;
1981 } else if (memdev_dmi_entry->length > speed_offset) {
1982 dmi_mem_clk_speed = memdev_dmi_entry->speed;
1988 if (*dclk_freq == 0) {
1989 /* First pass, speed was 0 */
1990 if (dmi_mem_clk_speed > 0) {
1991 /* Set speed if a valid speed is read */
1992 *dclk_freq = dmi_mem_clk_speed;
1994 /* Otherwise we don't have a valid speed */
1997 } else if (*dclk_freq > 0 &&
1998 *dclk_freq != dmi_mem_clk_speed) {
2000 * If we have a speed, check that all DIMMS are the same
2001 * speed, otherwise set the speed as invalid.
2009 * The default DCLK frequency is used as a fallback if we
2010 * fail to find anything reliable in the DMI. The value
2011 * is taken straight from the datasheet.
2013 #define DEFAULT_DCLK_FREQ 800
2015 static int get_dclk_freq(void)
2019 dmi_walk(decode_dclk, (void *)&dclk_freq);
2022 return DEFAULT_DCLK_FREQ;
2028 * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
2029 * to hardware according to SCRUBINTERVAL formula
2030 * found in datasheet.
2032 static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
2034 struct i7core_pvt *pvt = mci->pvt_info;
2035 struct pci_dev *pdev;
2039 /* Get data from the MC register, function 2 */
2040 pdev = pvt->pci_mcr[2];
2044 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);
2047 /* Prepare to disable petrol scrub */
2048 dw_scrub &= ~STARTSCRUB;
2049 /* Stop the patrol scrub engine */
2050 write_and_test(pdev, MC_SCRUB_CONTROL,
2051 dw_scrub & ~SCRUBINTERVAL_MASK);
2053 /* Get current status of scrub rate and set bit to disable */
2054 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2055 dw_ssr &= ~SSR_MODE_MASK;
2056 dw_ssr |= SSR_MODE_DISABLE;
2058 const int cache_line_size = 64;
2059 const u32 freq_dclk_mhz = pvt->dclk_freq;
2060 unsigned long long scrub_interval;
2062 * Translate the desired scrub rate to a register value and
2063 * program the corresponding register value.
2065 scrub_interval = (unsigned long long)freq_dclk_mhz *
2066 cache_line_size * 1000000;
2067 do_div(scrub_interval, new_bw);
2069 if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
2072 dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
2074 /* Start the patrol scrub engine */
2075 pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
2076 STARTSCRUB | dw_scrub);
2078 /* Get current status of scrub rate and set bit to enable */
2079 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2080 dw_ssr &= ~SSR_MODE_MASK;
2081 dw_ssr |= SSR_MODE_ENABLE;
2083 /* Disable or enable scrubbing */
2084 pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);
2090 * get_sdram_scrub_rate This routine convert current scrub rate value
2091 * into byte/sec bandwidth according to
2092 * SCRUBINTERVAL formula found in datasheet.
2094 static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
2096 struct i7core_pvt *pvt = mci->pvt_info;
2097 struct pci_dev *pdev;
2098 const u32 cache_line_size = 64;
2099 const u32 freq_dclk_mhz = pvt->dclk_freq;
2100 unsigned long long scrub_rate;
2103 /* Get data from the MC register, function 2 */
2104 pdev = pvt->pci_mcr[2];
2108 /* Get current scrub control data */
2109 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
2111 /* Mask highest 8-bits to 0 */
2112 scrubval &= SCRUBINTERVAL_MASK;
2116 /* Calculate scrub rate value into byte/sec bandwidth */
2117 scrub_rate = (unsigned long long)freq_dclk_mhz *
2118 1000000 * cache_line_size;
2119 do_div(scrub_rate, scrubval);
2120 return (int)scrub_rate;
2123 static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
2125 struct i7core_pvt *pvt = mci->pvt_info;
2128 /* Unlock writes to pci registers */
2129 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2131 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2132 pci_lock | MC_CFG_UNLOCK);
2134 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
2135 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
2138 static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
2140 struct i7core_pvt *pvt = mci->pvt_info;
2143 /* Lock writes to pci registers */
2144 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2146 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2147 pci_lock | MC_CFG_LOCK);
2150 static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
2152 pvt->i7core_pci = edac_pci_create_generic_ctl(
2153 &pvt->i7core_dev->pdev[0]->dev,
2155 if (unlikely(!pvt->i7core_pci))
2156 i7core_printk(KERN_WARNING,
2157 "Unable to setup PCI error report via EDAC\n");
2160 static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
2162 if (likely(pvt->i7core_pci))
2163 edac_pci_release_generic_ctl(pvt->i7core_pci);
2165 i7core_printk(KERN_ERR,
2166 "Couldn't find mem_ctl_info for socket %d\n",
2167 pvt->i7core_dev->socket);
2168 pvt->i7core_pci = NULL;
2171 static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2173 struct mem_ctl_info *mci = i7core_dev->mci;
2174 struct i7core_pvt *pvt;
2176 if (unlikely(!mci || !mci->pvt_info)) {
2177 edac_dbg(0, "MC: dev = %p\n", &i7core_dev->pdev[0]->dev);
2179 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
2183 pvt = mci->pvt_info;
2185 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
2187 /* Disable scrubrate setting */
2188 if (pvt->enable_scrub)
2189 disable_sdram_scrub_setting(mci);
2191 /* Disable EDAC polling */
2192 i7core_pci_ctl_release(pvt);
2194 /* Remove MC sysfs nodes */
2195 i7core_delete_sysfs_devices(mci);
2196 edac_mc_del_mc(mci->pdev);
2198 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2199 kfree(mci->ctl_name);
2201 i7core_dev->mci = NULL;
2204 static int i7core_register_mci(struct i7core_dev *i7core_dev)
2206 struct mem_ctl_info *mci;
2207 struct i7core_pvt *pvt;
2209 struct edac_mc_layer layers[2];
2211 /* allocate a new MC control structure */
2213 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2214 layers[0].size = NUM_CHANS;
2215 layers[0].is_virt_csrow = false;
2216 layers[1].type = EDAC_MC_LAYER_SLOT;
2217 layers[1].size = MAX_DIMMS;
2218 layers[1].is_virt_csrow = true;
2219 mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
2224 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
2226 pvt = mci->pvt_info;
2227 memset(pvt, 0, sizeof(*pvt));
2229 /* Associates i7core_dev and mci for future usage */
2230 pvt->i7core_dev = i7core_dev;
2231 i7core_dev->mci = mci;
2234 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
2235 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
2238 mci->mtype_cap = MEM_FLAG_DDR3;
2239 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2240 mci->edac_cap = EDAC_FLAG_NONE;
2241 mci->mod_name = "i7core_edac.c";
2242 mci->mod_ver = I7CORE_REVISION;
2243 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
2244 i7core_dev->socket);
2245 mci->dev_name = pci_name(i7core_dev->pdev[0]);
2246 mci->ctl_page_to_phys = NULL;
2248 /* Store pci devices at mci for faster access */
2249 rc = mci_bind_devs(mci, i7core_dev);
2250 if (unlikely(rc < 0))
2254 /* Get dimm basic config */
2255 get_dimm_config(mci);
2256 /* record ptr to the generic device */
2257 mci->pdev = &i7core_dev->pdev[0]->dev;
2258 /* Set the function pointer to an actual operation function */
2259 mci->edac_check = i7core_check_error;
2261 /* Enable scrubrate setting */
2262 if (pvt->enable_scrub)
2263 enable_sdram_scrub_setting(mci);
2265 /* add this new MC control structure to EDAC's list of MCs */
2266 if (unlikely(edac_mc_add_mc(mci))) {
2267 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2268 /* FIXME: perhaps some code should go here that disables error
2269 * reporting if we just enabled it
2275 if (i7core_create_sysfs_devices(mci)) {
2276 edac_dbg(0, "MC: failed to create sysfs nodes\n");
2277 edac_mc_del_mc(mci->pdev);
2282 /* Default error mask is any memory */
2283 pvt->inject.channel = 0;
2284 pvt->inject.dimm = -1;
2285 pvt->inject.rank = -1;
2286 pvt->inject.bank = -1;
2287 pvt->inject.page = -1;
2288 pvt->inject.col = -1;
2290 /* allocating generic PCI control info */
2291 i7core_pci_ctl_create(pvt);
2293 /* DCLK for scrub rate setting */
2294 pvt->dclk_freq = get_dclk_freq();
2299 kfree(mci->ctl_name);
2301 i7core_dev->mci = NULL;
2306 * i7core_probe Probe for ONE instance of device to see if it is
2309 * 0 for FOUND a device
2310 * < 0 for error code
2313 static int i7core_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2316 struct i7core_dev *i7core_dev;
2318 /* get the pci devices we want to reserve for our use */
2319 mutex_lock(&i7core_edac_lock);
2322 * All memory controllers are allocated at the first pass.
2324 if (unlikely(probed >= 1)) {
2325 mutex_unlock(&i7core_edac_lock);
2330 rc = i7core_get_all_devices();
2331 if (unlikely(rc < 0))
2334 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
2336 rc = i7core_register_mci(i7core_dev);
2337 if (unlikely(rc < 0))
2342 * Nehalem-EX uses a different memory controller. However, as the
2343 * memory controller is not visible on some Nehalem/Nehalem-EP, we
2344 * need to indirectly probe via a X58 PCI device. The same devices
2345 * are found on (some) Nehalem-EX. So, on those machines, the
2346 * probe routine needs to return -ENODEV, as the actual Memory
2347 * Controller registers won't be detected.
2354 i7core_printk(KERN_INFO,
2355 "Driver loaded, %d memory controller(s) found.\n",
2358 mutex_unlock(&i7core_edac_lock);
2362 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2363 i7core_unregister_mci(i7core_dev);
2365 i7core_put_all_devices();
2367 mutex_unlock(&i7core_edac_lock);
2372 * i7core_remove destructor for one instance of device
2375 static void i7core_remove(struct pci_dev *pdev)
2377 struct i7core_dev *i7core_dev;
2382 * we have a trouble here: pdev value for removal will be wrong, since
2383 * it will point to the X58 register used to detect that the machine
2384 * is a Nehalem or upper design. However, due to the way several PCI
2385 * devices are grouped together to provide MC functionality, we need
2386 * to use a different method for releasing the devices
2389 mutex_lock(&i7core_edac_lock);
2391 if (unlikely(!probed)) {
2392 mutex_unlock(&i7core_edac_lock);
2396 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2397 i7core_unregister_mci(i7core_dev);
2399 /* Release PCI resources */
2400 i7core_put_all_devices();
2404 mutex_unlock(&i7core_edac_lock);
2407 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2410 * i7core_driver pci_driver structure for this module
2413 static struct pci_driver i7core_driver = {
2414 .name = "i7core_edac",
2415 .probe = i7core_probe,
2416 .remove = i7core_remove,
2417 .id_table = i7core_pci_tbl,
2421 * i7core_init Module entry function
2422 * Try to initialize this module for its devices
2424 static int __init i7core_init(void)
2430 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2434 i7core_xeon_pci_fixup(pci_dev_table);
2436 pci_rc = pci_register_driver(&i7core_driver);
2439 mce_register_decode_chain(&i7_mce_dec);
2443 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2450 * i7core_exit() Module exit function
2451 * Unregister the driver
2453 static void __exit i7core_exit(void)
2456 pci_unregister_driver(&i7core_driver);
2457 mce_unregister_decode_chain(&i7_mce_dec);
2460 module_init(i7core_init);
2461 module_exit(i7core_exit);
2463 MODULE_LICENSE("GPL");
2464 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2465 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2466 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2469 module_param(edac_op_state, int, 0444);
2470 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");