1 // SPDX-License-Identifier: GPL-2.0-only
3 * GHES/EDAC Linux driver
5 * Copyright (c) 2013 by Mauro Carvalho Chehab
7 * Red Hat Inc. http://www.redhat.com
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <acpi/ghes.h>
13 #include <linux/edac.h>
14 #include <linux/dmi.h>
15 #include "edac_module.h"
16 #include <ras/ras_event.h>
18 struct ghes_edac_pvt {
19 struct list_head list;
21 struct mem_ctl_info *mci;
23 /* Buffers for the error handling routine */
24 char other_detail[400];
28 static refcount_t ghes_refcount = REFCOUNT_INIT(0);
31 * Access to ghes_pvt must be protected by ghes_lock. The spinlock
32 * also provides the necessary (implicit) memory barrier for the SMP
33 * case to make the pointer visible on another CPU.
35 static struct ghes_edac_pvt *ghes_pvt;
37 /* GHES registration mutex */
38 static DEFINE_MUTEX(ghes_reg_mutex);
41 * Sync with other, potentially concurrent callers of
42 * ghes_edac_report_mem_error(). We don't know what the
43 * "inventive" firmware would do.
45 static DEFINE_SPINLOCK(ghes_lock);
47 /* "ghes_edac.force_load=1" skips the platform check */
48 static bool __read_mostly force_load;
49 module_param(force_load, bool, 0);
51 /* Memory Device - Type 17 of SMBIOS spec */
52 struct memdev_dmi_entry {
56 u16 phys_mem_array_handle;
57 u16 mem_err_info_handle;
74 u16 conf_mem_clk_speed;
75 } __attribute__((__packed__));
77 struct ghes_edac_dimm_fill {
78 struct mem_ctl_info *mci;
82 static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
86 if (dh->type == DMI_ENTRY_MEM_DEVICE)
90 static int get_dimm_smbios_index(struct mem_ctl_info *mci, u16 handle)
92 struct dimm_info *dimm;
94 mci_for_each_dimm(mci, dimm) {
95 if (dimm->smbios_handle == handle)
102 static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
104 struct ghes_edac_dimm_fill *dimm_fill = arg;
105 struct mem_ctl_info *mci = dimm_fill->mci;
107 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
108 struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
109 struct dimm_info *dimm = edac_get_dimm(mci, dimm_fill->count, 0, 0);
110 u16 rdr_mask = BIT(7) | BIT(13);
112 if (entry->size == 0xffff) {
113 pr_info("Can't get DIMM%i size\n",
115 dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
116 } else if (entry->size == 0x7fff) {
117 dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
119 if (entry->size & BIT(15))
120 dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
122 dimm->nr_pages = MiB_TO_PAGES(entry->size);
125 switch (entry->memory_type) {
127 if (entry->type_detail & BIT(13))
128 dimm->mtype = MEM_RDDR;
130 dimm->mtype = MEM_DDR;
133 if (entry->type_detail & BIT(13))
134 dimm->mtype = MEM_RDDR2;
136 dimm->mtype = MEM_DDR2;
139 dimm->mtype = MEM_FB_DDR2;
142 if (entry->type_detail & BIT(12))
143 dimm->mtype = MEM_NVDIMM;
144 else if (entry->type_detail & BIT(13))
145 dimm->mtype = MEM_RDDR3;
147 dimm->mtype = MEM_DDR3;
150 if (entry->type_detail & BIT(12))
151 dimm->mtype = MEM_NVDIMM;
152 else if (entry->type_detail & BIT(13))
153 dimm->mtype = MEM_RDDR4;
155 dimm->mtype = MEM_DDR4;
158 if (entry->type_detail & BIT(6))
159 dimm->mtype = MEM_RMBS;
160 else if ((entry->type_detail & rdr_mask) == rdr_mask)
161 dimm->mtype = MEM_RDR;
162 else if (entry->type_detail & BIT(7))
163 dimm->mtype = MEM_SDR;
164 else if (entry->type_detail & BIT(9))
165 dimm->mtype = MEM_EDO;
167 dimm->mtype = MEM_UNKNOWN;
171 * Actually, we can only detect if the memory has bits for
174 if (entry->total_width == entry->data_width)
175 dimm->edac_mode = EDAC_NONE;
177 dimm->edac_mode = EDAC_SECDED;
179 dimm->dtype = DEV_UNKNOWN;
180 dimm->grain = 128; /* Likely, worse case */
183 * FIXME: It shouldn't be hard to also fill the DIMM labels
186 if (dimm->nr_pages) {
187 edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
188 dimm_fill->count, edac_mem_types[dimm->mtype],
189 PAGES_TO_MiB(dimm->nr_pages),
190 (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
191 edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
192 entry->memory_type, entry->type_detail,
193 entry->total_width, entry->data_width);
196 dimm->smbios_handle = entry->handle;
202 void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
204 struct edac_raw_error_desc *e;
205 struct mem_ctl_info *mci;
206 struct ghes_edac_pvt *pvt;
211 * We can do the locking below because GHES defers error processing
212 * from NMI to IRQ context. Whenever that changes, we'd at least
215 if (WARN_ON_ONCE(in_nmi()))
218 spin_lock_irqsave(&ghes_lock, flags);
225 e = &mci->error_desc;
227 /* Cleans the error report buffer */
228 memset(e, 0, sizeof (*e));
231 strcpy(e->label, "unknown label");
233 e->other_detail = pvt->other_detail;
237 *pvt->other_detail = '\0';
241 case GHES_SEV_CORRECTED:
242 e->type = HW_EVENT_ERR_CORRECTED;
244 case GHES_SEV_RECOVERABLE:
245 e->type = HW_EVENT_ERR_UNCORRECTED;
248 e->type = HW_EVENT_ERR_FATAL;
252 e->type = HW_EVENT_ERR_INFO;
255 edac_dbg(1, "error validation_bits: 0x%08llx\n",
256 (long long)mem_err->validation_bits);
258 /* Error type, mapped on e->msg */
259 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
261 switch (mem_err->error_type) {
263 p += sprintf(p, "Unknown");
266 p += sprintf(p, "No error");
269 p += sprintf(p, "Single-bit ECC");
272 p += sprintf(p, "Multi-bit ECC");
275 p += sprintf(p, "Single-symbol ChipKill ECC");
278 p += sprintf(p, "Multi-symbol ChipKill ECC");
281 p += sprintf(p, "Master abort");
284 p += sprintf(p, "Target abort");
287 p += sprintf(p, "Parity Error");
290 p += sprintf(p, "Watchdog timeout");
293 p += sprintf(p, "Invalid address");
296 p += sprintf(p, "Mirror Broken");
299 p += sprintf(p, "Memory Sparing");
302 p += sprintf(p, "Scrub corrected error");
305 p += sprintf(p, "Scrub uncorrected error");
308 p += sprintf(p, "Physical Memory Map-out event");
311 p += sprintf(p, "reserved error (%d)",
312 mem_err->error_type);
315 strcpy(pvt->msg, "unknown error");
319 if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
320 e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
321 e->offset_in_page = offset_in_page(mem_err->physical_addr);
325 if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
326 e->grain = ~mem_err->physical_addr_mask + 1;
328 /* Memory error location, mapped on e->location */
330 if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
331 p += sprintf(p, "node:%d ", mem_err->node);
332 if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
333 p += sprintf(p, "card:%d ", mem_err->card);
334 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
335 p += sprintf(p, "module:%d ", mem_err->module);
336 if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
337 p += sprintf(p, "rank:%d ", mem_err->rank);
338 if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
339 p += sprintf(p, "bank:%d ", mem_err->bank);
340 if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
341 p += sprintf(p, "row:%d ", mem_err->row);
342 if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
343 p += sprintf(p, "col:%d ", mem_err->column);
344 if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
345 p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
346 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
347 const char *bank = NULL, *device = NULL;
350 dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
351 if (bank != NULL && device != NULL)
352 p += sprintf(p, "DIMM location:%s %s ", bank, device);
354 p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
355 mem_err->mem_dev_handle);
357 index = get_dimm_smbios_index(mci, mem_err->mem_dev_handle);
359 e->top_layer = index;
364 /* All other fields are mapped on e->other_detail */
365 p = pvt->other_detail;
366 p += snprintf(p, sizeof(pvt->other_detail),
367 "APEI location: %s ", e->location);
368 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
369 u64 status = mem_err->error_status;
371 p += sprintf(p, "status(0x%016llx): ", (long long)status);
372 switch ((status >> 8) & 0xff) {
374 p += sprintf(p, "Error detected internal to the component ");
377 p += sprintf(p, "Error detected in the bus ");
380 p += sprintf(p, "Storage error in DRAM memory ");
383 p += sprintf(p, "Storage error in TLB ");
386 p += sprintf(p, "Storage error in cache ");
389 p += sprintf(p, "Error in one or more functional units ");
392 p += sprintf(p, "component failed self test ");
395 p += sprintf(p, "Overflow or undervalue of internal queue ");
398 p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
401 p += sprintf(p, "Improper access error ");
404 p += sprintf(p, "Access to a memory address which is not mapped to any component ");
407 p += sprintf(p, "Loss of Lockstep ");
410 p += sprintf(p, "Response not associated with a request ");
413 p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
416 p += sprintf(p, "Detection of a PATH_ERROR ");
419 p += sprintf(p, "Bus operation timeout ");
422 p += sprintf(p, "A read was issued to data that has been poisoned ");
425 p += sprintf(p, "reserved ");
429 if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
430 p += sprintf(p, "requestorID: 0x%016llx ",
431 (long long)mem_err->requestor_id);
432 if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
433 p += sprintf(p, "responderID: 0x%016llx ",
434 (long long)mem_err->responder_id);
435 if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
436 p += sprintf(p, "targetID: 0x%016llx ",
437 (long long)mem_err->responder_id);
438 if (p > pvt->other_detail)
441 edac_raw_mc_handle_error(e);
444 spin_unlock_irqrestore(&ghes_lock, flags);
448 * Known systems that are safe to enable this module.
450 static struct acpi_platform_list plat_list[] = {
451 {"HPE ", "Server ", 0, ACPI_SIG_FADT, all_versions},
455 int ghes_edac_register(struct ghes *ghes, struct device *dev)
458 int rc = 0, num_dimm = 0;
459 struct mem_ctl_info *mci;
460 struct ghes_edac_pvt *pvt;
461 struct edac_mc_layer layers[1];
462 struct ghes_edac_dimm_fill dimm_fill;
466 if (IS_ENABLED(CONFIG_X86)) {
467 /* Check if safe to enable on this system */
468 idx = acpi_match_platform_list(plat_list);
469 if (!force_load && idx < 0)
475 /* finish another registration/unregistration instance first */
476 mutex_lock(&ghes_reg_mutex);
479 * We have only one logical memory controller to which all DIMMs belong.
481 if (refcount_inc_not_zero(&ghes_refcount))
484 /* Get the number of DIMMs */
485 dmi_walk(ghes_edac_count_dimms, &num_dimm);
487 /* Check if we've got a bogus BIOS */
493 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
494 layers[0].size = num_dimm;
495 layers[0].is_virt_csrow = true;
497 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
499 pr_info("Can't allocate memory for EDAC data\n");
509 mci->mtype_cap = MEM_FLAG_EMPTY;
510 mci->edac_ctl_cap = EDAC_FLAG_NONE;
511 mci->edac_cap = EDAC_FLAG_NONE;
512 mci->mod_name = "ghes_edac.c";
513 mci->ctl_name = "ghes_edac";
514 mci->dev_name = "ghes";
517 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
518 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
519 pr_info("work on such system. Use this driver with caution\n");
520 } else if (idx < 0) {
521 pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
522 pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
523 pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
524 pr_info("If you find incorrect reports, please contact your hardware vendor\n");
525 pr_info("to correct its BIOS.\n");
526 pr_info("This system has %d DIMM sockets.\n", num_dimm);
532 dmi_walk(ghes_edac_dmidecode, &dimm_fill);
534 struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
538 dimm->mtype = MEM_UNKNOWN;
539 dimm->dtype = DEV_UNKNOWN;
540 dimm->edac_mode = EDAC_SECDED;
543 rc = edac_mc_add_mc(mci);
545 pr_info("Can't register at EDAC core\n");
551 spin_lock_irqsave(&ghes_lock, flags);
553 spin_unlock_irqrestore(&ghes_lock, flags);
555 /* only set on success */
556 refcount_set(&ghes_refcount, 1);
559 mutex_unlock(&ghes_reg_mutex);
564 void ghes_edac_unregister(struct ghes *ghes)
566 struct mem_ctl_info *mci;
569 mutex_lock(&ghes_reg_mutex);
571 if (!refcount_dec_and_test(&ghes_refcount))
575 * Wait for the irq handler being finished.
577 spin_lock_irqsave(&ghes_lock, flags);
578 mci = ghes_pvt ? ghes_pvt->mci : NULL;
580 spin_unlock_irqrestore(&ghes_lock, flags);
585 mci = edac_mc_del_mc(mci->pdev);
590 mutex_unlock(&ghes_reg_mutex);