drivers/edac/edac_mc.c

   1 /*
   2  * edac_mc kernel module
   3  * (C) 2005, 2006 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Based on work by Dan Hollis <goemon at anime dot net> and others.
   9  *      http://www.anime.net/~goemon/linux-ecc/
  10  *
  11  * Modified by Dave Peterson and Doug Thompson
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/proc_fs.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/smp.h>
  20 #include <linux/init.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/highmem.h>
  23 #include <linux/timer.h>
  24 #include <linux/slab.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/list.h>
  28 #include <linux/ctype.h>
  29 #include <linux/edac.h>
  30 #include <linux/bitops.h>
  31 #include <linux/uaccess.h>
  32 #include <asm/page.h>
  33 #include "edac_mc.h"
  34 #include "edac_module.h"
  35 #include <ras/ras_event.h>
  36
  37 #ifdef CONFIG_EDAC_ATOMIC_SCRUB
  38 #include <asm/edac.h>
  39 #else
  40 #define edac_atomic_scrub(va, size) do { } while (0)
  41 #endif
  42
  43 int edac_op_state = EDAC_OPSTATE_INVAL;
  44 EXPORT_SYMBOL_GPL(edac_op_state);
  45
  46 static int edac_report = EDAC_REPORTING_ENABLED;
  47
  48 /* lock to memory controller's control array */
  49 static DEFINE_MUTEX(mem_ctls_mutex);
  50 static LIST_HEAD(mc_devices);
  51
  52 /*
  53  * Used to lock EDAC MC to just one module, avoiding two drivers e. g.
  54  *      apei/ghes and i7core_edac to be used at the same time.
  55  */
  56 static const char *edac_mc_owner;
  57
  58 static struct bus_type mc_bus[EDAC_MAX_MCS];
  59
  60 int edac_get_report_status(void)
  61 {
  62         return edac_report;
  63 }
  64 EXPORT_SYMBOL_GPL(edac_get_report_status);
  65
  66 void edac_set_report_status(int new)
  67 {
  68         if (new == EDAC_REPORTING_ENABLED ||
  69             new == EDAC_REPORTING_DISABLED ||
  70             new == EDAC_REPORTING_FORCE)
  71                 edac_report = new;
  72 }
  73 EXPORT_SYMBOL_GPL(edac_set_report_status);
  74
  75 static int edac_report_set(const char *str, const struct kernel_param *kp)
  76 {
  77         if (!str)
  78                 return -EINVAL;
  79
  80         if (!strncmp(str, "on", 2))
  81                 edac_report = EDAC_REPORTING_ENABLED;
  82         else if (!strncmp(str, "off", 3))
  83                 edac_report = EDAC_REPORTING_DISABLED;
  84         else if (!strncmp(str, "force", 5))
  85                 edac_report = EDAC_REPORTING_FORCE;
  86
  87         return 0;
  88 }
  89
  90 static int edac_report_get(char *buffer, const struct kernel_param *kp)
  91 {
  92         int ret = 0;
  93
  94         switch (edac_report) {
  95         case EDAC_REPORTING_ENABLED:
  96                 ret = sprintf(buffer, "on");
  97                 break;
  98         case EDAC_REPORTING_DISABLED:
  99                 ret = sprintf(buffer, "off");
 100                 break;
 101         case EDAC_REPORTING_FORCE:
 102                 ret = sprintf(buffer, "force");
 103                 break;
 104         default:
 105                 ret = -EINVAL;
 106                 break;
 107         }
 108
 109         return ret;
 110 }
 111
 112 static const struct kernel_param_ops edac_report_ops = {
 113         .set = edac_report_set,
 114         .get = edac_report_get,
 115 };
 116
 117 module_param_cb(edac_report, &edac_report_ops, &edac_report, 0644);
 118
 119 unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf,
 120                                  unsigned len)
 121 {
 122         struct mem_ctl_info *mci = dimm->mci;
 123         int i, n, count = 0;
 124         char *p = buf;
 125
 126         for (i = 0; i < mci->n_layers; i++) {
 127                 n = snprintf(p, len, "%s %d ",
 128                               edac_layer_name[mci->layers[i].type],
 129                               dimm->location[i]);
 130                 p += n;
 131                 len -= n;
 132                 count += n;
 133                 if (!len)
 134                         break;
 135         }
 136
 137         return count;
 138 }
 139
 140 #ifdef CONFIG_EDAC_DEBUG
 141
 142 static void edac_mc_dump_channel(struct rank_info *chan)
 143 {
 144         edac_dbg(4, "  channel->chan_idx = %d\n", chan->chan_idx);
 145         edac_dbg(4, "    channel = %p\n", chan);
 146         edac_dbg(4, "    channel->csrow = %p\n", chan->csrow);
 147         edac_dbg(4, "    channel->dimm = %p\n", chan->dimm);
 148 }
 149
 150 static void edac_mc_dump_dimm(struct dimm_info *dimm, int number)
 151 {
 152         char location[80];
 153
 154         edac_dimm_info_location(dimm, location, sizeof(location));
 155
 156         edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
 157                  dimm->mci->csbased ? "rank" : "dimm",
 158                  number, location, dimm->csrow, dimm->cschannel);
 159         edac_dbg(4, "  dimm = %p\n", dimm);
 160         edac_dbg(4, "  dimm->label = '%s'\n", dimm->label);
 161         edac_dbg(4, "  dimm->nr_pages = 0x%x\n", dimm->nr_pages);
 162         edac_dbg(4, "  dimm->grain = %d\n", dimm->grain);
 163         edac_dbg(4, "  dimm->nr_pages = 0x%x\n", dimm->nr_pages);
 164 }
 165
 166 static void edac_mc_dump_csrow(struct csrow_info *csrow)
 167 {
 168         edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx);
 169         edac_dbg(4, "  csrow = %p\n", csrow);
 170         edac_dbg(4, "  csrow->first_page = 0x%lx\n", csrow->first_page);
 171         edac_dbg(4, "  csrow->last_page = 0x%lx\n", csrow->last_page);
 172         edac_dbg(4, "  csrow->page_mask = 0x%lx\n", csrow->page_mask);
 173         edac_dbg(4, "  csrow->nr_channels = %d\n", csrow->nr_channels);
 174         edac_dbg(4, "  csrow->channels = %p\n", csrow->channels);
 175         edac_dbg(4, "  csrow->mci = %p\n", csrow->mci);
 176 }
 177
 178 static void edac_mc_dump_mci(struct mem_ctl_info *mci)
 179 {
 180         edac_dbg(3, "\tmci = %p\n", mci);
 181         edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
 182         edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
 183         edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
 184         edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
 185         edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
 186                  mci->nr_csrows, mci->csrows);
 187         edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
 188                  mci->tot_dimms, mci->dimms);
 189         edac_dbg(3, "\tdev = %p\n", mci->pdev);
 190         edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
 191                  mci->mod_name, mci->ctl_name);
 192         edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
 193 }
 194
 195 #endif                          /* CONFIG_EDAC_DEBUG */
 196
 197 const char * const edac_mem_types[] = {
 198         [MEM_EMPTY]     = "Empty",
 199         [MEM_RESERVED]  = "Reserved",
 200         [MEM_UNKNOWN]   = "Unknown",
 201         [MEM_FPM]       = "FPM",
 202         [MEM_EDO]       = "EDO",
 203         [MEM_BEDO]      = "BEDO",
 204         [MEM_SDR]       = "Unbuffered-SDR",
 205         [MEM_RDR]       = "Registered-SDR",
 206         [MEM_DDR]       = "Unbuffered-DDR",
 207         [MEM_RDDR]      = "Registered-DDR",
 208         [MEM_RMBS]      = "RMBS",
 209         [MEM_DDR2]      = "Unbuffered-DDR2",
 210         [MEM_FB_DDR2]   = "FullyBuffered-DDR2",
 211         [MEM_RDDR2]     = "Registered-DDR2",
 212         [MEM_XDR]       = "XDR",
 213         [MEM_DDR3]      = "Unbuffered-DDR3",
 214         [MEM_RDDR3]     = "Registered-DDR3",
 215         [MEM_LRDDR3]    = "Load-Reduced-DDR3-RAM",
 216         [MEM_DDR4]      = "Unbuffered-DDR4",
 217         [MEM_RDDR4]     = "Registered-DDR4",
 218         [MEM_NVDIMM]    = "Non-volatile-RAM",
 219 };
 220 EXPORT_SYMBOL_GPL(edac_mem_types);
 221
 222 /**
 223  * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation
 224  * @p:          pointer to a pointer with the memory offset to be used. At
 225  *              return, this will be incremented to point to the next offset
 226  * @size:       Size of the data structure to be reserved
 227  * @n_elems:    Number of elements that should be reserved
 228  *
 229  * If 'size' is a constant, the compiler will optimize this whole function
 230  * down to either a no-op or the addition of a constant to the value of '*p'.
 231  *
 232  * The 'p' pointer is absolutely needed to keep the proper advancing
 233  * further in memory to the proper offsets when allocating the struct along
 234  * with its embedded structs, as edac_device_alloc_ctl_info() does it
 235  * above, for example.
 236  *
 237  * At return, the pointer 'p' will be incremented to be used on a next call
 238  * to this function.
 239  */
 240 void *edac_align_ptr(void **p, unsigned size, int n_elems)
 241 {
 242         unsigned align, r;
 243         void *ptr = *p;
 244
 245         *p += size * n_elems;
 246
 247         /*
 248          * 'p' can possibly be an unaligned item X such that sizeof(X) is
 249          * 'size'.  Adjust 'p' so that its alignment is at least as
 250          * stringent as what the compiler would provide for X and return
 251          * the aligned result.
 252          * Here we assume that the alignment of a "long long" is the most
 253          * stringent alignment that the compiler will ever provide by default.
 254          * As far as I know, this is a reasonable assumption.
 255          */
 256         if (size > sizeof(long))
 257                 align = sizeof(long long);
 258         else if (size > sizeof(int))
 259                 align = sizeof(long);
 260         else if (size > sizeof(short))
 261                 align = sizeof(int);
 262         else if (size > sizeof(char))
 263                 align = sizeof(short);
 264         else
 265                 return (char *)ptr;
 266
 267         r = (unsigned long)p % align;
 268
 269         if (r == 0)
 270                 return (char *)ptr;
 271
 272         *p += align - r;
 273
 274         return (void *)(((unsigned long)ptr) + align - r);
 275 }
 276
 277 static void _edac_mc_free(struct mem_ctl_info *mci)
 278 {
 279         int i, chn, row;
 280         struct csrow_info *csr;
 281         const unsigned int tot_dimms = mci->tot_dimms;
 282         const unsigned int tot_channels = mci->num_cschannel;
 283         const unsigned int tot_csrows = mci->nr_csrows;
 284
 285         if (mci->dimms) {
 286                 for (i = 0; i < tot_dimms; i++)
 287                         kfree(mci->dimms[i]);
 288                 kfree(mci->dimms);
 289         }
 290         if (mci->csrows) {
 291                 for (row = 0; row < tot_csrows; row++) {
 292                         csr = mci->csrows[row];
 293                         if (csr) {
 294                                 if (csr->channels) {
 295                                         for (chn = 0; chn < tot_channels; chn++)
 296                                                 kfree(csr->channels[chn]);
 297                                         kfree(csr->channels);
 298                                 }
 299                                 kfree(csr);
 300                         }
 301                 }
 302                 kfree(mci->csrows);
 303         }
 304         kfree(mci);
 305 }
 306
 307 struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
 308                                    unsigned n_layers,
 309                                    struct edac_mc_layer *layers,
 310                                    unsigned sz_pvt)
 311 {
 312         struct mem_ctl_info *mci;
 313         struct edac_mc_layer *layer;
 314         struct csrow_info *csr;
 315         struct rank_info *chan;
 316         struct dimm_info *dimm;
 317         u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
 318         unsigned pos[EDAC_MAX_LAYERS];
 319         unsigned size, tot_dimms = 1, count = 1;
 320         unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0;
 321         void *pvt, *p, *ptr = NULL;
 322         int i, j, row, chn, n, len, off;
 323         bool per_rank = false;
 324
 325         BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0);
 326         /*
 327          * Calculate the total amount of dimms and csrows/cschannels while
 328          * in the old API emulation mode
 329          */
 330         for (i = 0; i < n_layers; i++) {
 331                 tot_dimms *= layers[i].size;
 332                 if (layers[i].is_virt_csrow)
 333                         tot_csrows *= layers[i].size;
 334                 else
 335                         tot_channels *= layers[i].size;
 336
 337                 if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT)
 338                         per_rank = true;
 339         }
 340
 341         /* Figure out the offsets of the various items from the start of an mc
 342          * structure.  We want the alignment of each item to be at least as
 343          * stringent as what the compiler would provide if we could simply
 344          * hardcode everything into a single struct.
 345          */
 346         mci = edac_align_ptr(&ptr, sizeof(*mci), 1);
 347         layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers);
 348         for (i = 0; i < n_layers; i++) {
 349                 count *= layers[i].size;
 350                 edac_dbg(4, "errcount layer %d size %d\n", i, count);
 351                 ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
 352                 ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
 353                 tot_errcount += 2 * count;
 354         }
 355
 356         edac_dbg(4, "allocating %d error counters\n", tot_errcount);
 357         pvt = edac_align_ptr(&ptr, sz_pvt, 1);
 358         size = ((unsigned long)pvt) + sz_pvt;
 359
 360         edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n",
 361                  size,
 362                  tot_dimms,
 363                  per_rank ? "ranks" : "dimms",
 364                  tot_csrows * tot_channels);
 365
 366         mci = kzalloc(size, GFP_KERNEL);
 367         if (mci == NULL)
 368                 return NULL;
 369
 370         /* Adjust pointers so they point within the memory we just allocated
 371          * rather than an imaginary chunk of memory located at address 0.
 372          */
 373         layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer));
 374         for (i = 0; i < n_layers; i++) {
 375                 mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i]));
 376                 mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i]));
 377         }
 378         pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL;
 379
 380         /* setup index and various internal pointers */
 381         mci->mc_idx = mc_num;
 382         mci->tot_dimms = tot_dimms;
 383         mci->pvt_info = pvt;
 384         mci->n_layers = n_layers;
 385         mci->layers = layer;
 386         memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
 387         mci->nr_csrows = tot_csrows;
 388         mci->num_cschannel = tot_channels;
 389         mci->csbased = per_rank;
 390
 391         /*
 392          * Alocate and fill the csrow/channels structs
 393          */
 394         mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
 395         if (!mci->csrows)
 396                 goto error;
 397         for (row = 0; row < tot_csrows; row++) {
 398                 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
 399                 if (!csr)
 400                         goto error;
 401                 mci->csrows[row] = csr;
 402                 csr->csrow_idx = row;
 403                 csr->mci = mci;
 404                 csr->nr_channels = tot_channels;
 405                 csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
 406                                         GFP_KERNEL);
 407                 if (!csr->channels)
 408                         goto error;
 409
 410                 for (chn = 0; chn < tot_channels; chn++) {
 411                         chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL);
 412                         if (!chan)
 413                                 goto error;
 414                         csr->channels[chn] = chan;
 415                         chan->chan_idx = chn;
 416                         chan->csrow = csr;
 417                 }
 418         }
 419
 420         /*
 421          * Allocate and fill the dimm structs
 422          */
 423         mci->dimms  = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL);
 424         if (!mci->dimms)
 425                 goto error;
 426
 427         memset(&pos, 0, sizeof(pos));
 428         row = 0;
 429         chn = 0;
 430         for (i = 0; i < tot_dimms; i++) {
 431                 chan = mci->csrows[row]->channels[chn];
 432                 off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]);
 433                 if (off < 0 || off >= tot_dimms) {
 434                         edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n");
 435                         goto error;
 436                 }
 437
 438                 dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL);
 439                 if (!dimm)
 440                         goto error;
 441                 mci->dimms[off] = dimm;
 442                 dimm->mci = mci;
 443
 444                 /*
 445                  * Copy DIMM location and initialize it.
 446                  */
 447                 len = sizeof(dimm->label);
 448                 p = dimm->label;
 449                 n = snprintf(p, len, "mc#%u", mc_num);
 450                 p += n;
 451                 len -= n;
 452                 for (j = 0; j < n_layers; j++) {
 453                         n = snprintf(p, len, "%s#%u",
 454                                      edac_layer_name[layers[j].type],
 455                                      pos[j]);
 456                         p += n;
 457                         len -= n;
 458                         dimm->location[j] = pos[j];
 459
 460                         if (len <= 0)
 461                                 break;
 462                 }
 463
 464                 /* Link it to the csrows old API data */
 465                 chan->dimm = dimm;
 466                 dimm->csrow = row;
 467                 dimm->cschannel = chn;
 468
 469                 /* Increment csrow location */
 470                 if (layers[0].is_virt_csrow) {
 471                         chn++;
 472                         if (chn == tot_channels) {
 473                                 chn = 0;
 474                                 row++;
 475                         }
 476                 } else {
 477                         row++;
 478                         if (row == tot_csrows) {
 479                                 row = 0;
 480                                 chn++;
 481                         }
 482                 }
 483
 484                 /* Increment dimm location */
 485                 for (j = n_layers - 1; j >= 0; j--) {
 486                         pos[j]++;
 487                         if (pos[j] < layers[j].size)
 488                                 break;
 489                         pos[j] = 0;
 490                 }
 491         }
 492
 493         mci->op_state = OP_ALLOC;
 494
 495         return mci;
 496
 497 error:
 498         _edac_mc_free(mci);
 499
 500         return NULL;
 501 }
 502 EXPORT_SYMBOL_GPL(edac_mc_alloc);
 503
 504 void edac_mc_free(struct mem_ctl_info *mci)
 505 {
 506         edac_dbg(1, "\n");
 507
 508         /* If we're not yet registered with sysfs free only what was allocated
 509          * in edac_mc_alloc().
 510          */
 511         if (!device_is_registered(&mci->dev)) {
 512                 _edac_mc_free(mci);
 513                 return;
 514         }
 515
 516         /* the mci instance is freed here, when the sysfs object is dropped */
 517         edac_unregister_sysfs(mci);
 518 }
 519 EXPORT_SYMBOL_GPL(edac_mc_free);
 520
 521 bool edac_has_mcs(void)
 522 {
 523         bool ret;
 524
 525         mutex_lock(&mem_ctls_mutex);
 526
 527         ret = list_empty(&mc_devices);
 528
 529         mutex_unlock(&mem_ctls_mutex);
 530
 531         return !ret;
 532 }
 533 EXPORT_SYMBOL_GPL(edac_has_mcs);
 534
 535 /* Caller must hold mem_ctls_mutex */
 536 static struct mem_ctl_info *__find_mci_by_dev(struct device *dev)
 537 {
 538         struct mem_ctl_info *mci;
 539         struct list_head *item;
 540
 541         edac_dbg(3, "\n");
 542
 543         list_for_each(item, &mc_devices) {
 544                 mci = list_entry(item, struct mem_ctl_info, link);
 545
 546                 if (mci->pdev == dev)
 547                         return mci;
 548         }
 549
 550         return NULL;
 551 }
 552
 553 /**
 554  * find_mci_by_dev
 555  *
 556  *      scan list of controllers looking for the one that manages
 557  *      the 'dev' device
 558  * @dev: pointer to a struct device related with the MCI
 559  */
 560 struct mem_ctl_info *find_mci_by_dev(struct device *dev)
 561 {
 562         struct mem_ctl_info *ret;
 563
 564         mutex_lock(&mem_ctls_mutex);
 565         ret = __find_mci_by_dev(dev);
 566         mutex_unlock(&mem_ctls_mutex);
 567
 568         return ret;
 569 }
 570 EXPORT_SYMBOL_GPL(find_mci_by_dev);
 571
 572 /*
 573  * edac_mc_workq_function
 574  *      performs the operation scheduled by a workq request
 575  */
 576 static void edac_mc_workq_function(struct work_struct *work_req)
 577 {
 578         struct delayed_work *d_work = to_delayed_work(work_req);
 579         struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work);
 580
 581         mutex_lock(&mem_ctls_mutex);
 582
 583         if (mci->op_state != OP_RUNNING_POLL) {
 584                 mutex_unlock(&mem_ctls_mutex);
 585                 return;
 586         }
 587
 588         if (edac_op_state == EDAC_OPSTATE_POLL)
 589                 mci->edac_check(mci);
 590
 591         mutex_unlock(&mem_ctls_mutex);
 592
 593         /* Queue ourselves again. */
 594         edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
 595 }
 596
 597 /*
 598  * edac_mc_reset_delay_period(unsigned long value)
 599  *
 600  *      user space has updated our poll period value, need to
 601  *      reset our workq delays
 602  */
 603 void edac_mc_reset_delay_period(unsigned long value)
 604 {
 605         struct mem_ctl_info *mci;
 606         struct list_head *item;
 607
 608         mutex_lock(&mem_ctls_mutex);
 609
 610         list_for_each(item, &mc_devices) {
 611                 mci = list_entry(item, struct mem_ctl_info, link);
 612
 613                 if (mci->op_state == OP_RUNNING_POLL)
 614                         edac_mod_work(&mci->work, value);
 615         }
 616         mutex_unlock(&mem_ctls_mutex);
 617 }
 618
 619
 620
 621 /* Return 0 on success, 1 on failure.
 622  * Before calling this function, caller must
 623  * assign a unique value to mci->mc_idx.
 624  *
 625  *      locking model:
 626  *
 627  *              called with the mem_ctls_mutex lock held
 628  */
 629 static int add_mc_to_global_list(struct mem_ctl_info *mci)
 630 {
 631         struct list_head *item, *insert_before;
 632         struct mem_ctl_info *p;
 633
 634         insert_before = &mc_devices;
 635
 636         p = __find_mci_by_dev(mci->pdev);
 637         if (unlikely(p != NULL))
 638                 goto fail0;
 639
 640         list_for_each(item, &mc_devices) {
 641                 p = list_entry(item, struct mem_ctl_info, link);
 642
 643                 if (p->mc_idx >= mci->mc_idx) {
 644                         if (unlikely(p->mc_idx == mci->mc_idx))
 645                                 goto fail1;
 646
 647                         insert_before = item;
 648                         break;
 649                 }
 650         }
 651
 652         list_add_tail_rcu(&mci->link, insert_before);
 653         return 0;
 654
 655 fail0:
 656         edac_printk(KERN_WARNING, EDAC_MC,
 657                 "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev),
 658                 edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx);
 659         return 1;
 660
 661 fail1:
 662         edac_printk(KERN_WARNING, EDAC_MC,
 663                 "bug in low-level driver: attempt to assign\n"
 664                 "    duplicate mc_idx %d in %s()\n", p->mc_idx, __func__);
 665         return 1;
 666 }
 667
 668 static int del_mc_from_global_list(struct mem_ctl_info *mci)
 669 {
 670         list_del_rcu(&mci->link);
 671
 672         /* these are for safe removal of devices from global list while
 673          * NMI handlers may be traversing list
 674          */
 675         synchronize_rcu();
 676         INIT_LIST_HEAD(&mci->link);
 677
 678         return list_empty(&mc_devices);
 679 }
 680
 681 struct mem_ctl_info *edac_mc_find(int idx)
 682 {
 683         struct mem_ctl_info *mci = NULL;
 684         struct list_head *item;
 685
 686         mutex_lock(&mem_ctls_mutex);
 687
 688         list_for_each(item, &mc_devices) {
 689                 mci = list_entry(item, struct mem_ctl_info, link);
 690
 691                 if (mci->mc_idx >= idx) {
 692                         if (mci->mc_idx == idx) {
 693                                 goto unlock;
 694                         }
 695                         break;
 696                 }
 697         }
 698
 699 unlock:
 700         mutex_unlock(&mem_ctls_mutex);
 701         return mci;
 702 }
 703 EXPORT_SYMBOL(edac_mc_find);
 704
 705 const char *edac_get_owner(void)
 706 {
 707         return edac_mc_owner;
 708 }
 709 EXPORT_SYMBOL_GPL(edac_get_owner);
 710
 711 /* FIXME - should a warning be printed if no error detection? correction? */
 712 int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
 713                                const struct attribute_group **groups)
 714 {
 715         int ret = -EINVAL;
 716         edac_dbg(0, "\n");
 717
 718         if (mci->mc_idx >= EDAC_MAX_MCS) {
 719                 pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx);
 720                 return -ENODEV;
 721         }
 722
 723 #ifdef CONFIG_EDAC_DEBUG
 724         if (edac_debug_level >= 3)
 725                 edac_mc_dump_mci(mci);
 726
 727         if (edac_debug_level >= 4) {
 728                 int i;
 729
 730                 for (i = 0; i < mci->nr_csrows; i++) {
 731                         struct csrow_info *csrow = mci->csrows[i];
 732                         u32 nr_pages = 0;
 733                         int j;
 734
 735                         for (j = 0; j < csrow->nr_channels; j++)
 736                                 nr_pages += csrow->channels[j]->dimm->nr_pages;
 737                         if (!nr_pages)
 738                                 continue;
 739                         edac_mc_dump_csrow(csrow);
 740                         for (j = 0; j < csrow->nr_channels; j++)
 741                                 if (csrow->channels[j]->dimm->nr_pages)
 742                                         edac_mc_dump_channel(csrow->channels[j]);
 743                 }
 744                 for (i = 0; i < mci->tot_dimms; i++)
 745                         if (mci->dimms[i]->nr_pages)
 746                                 edac_mc_dump_dimm(mci->dimms[i], i);
 747         }
 748 #endif
 749         mutex_lock(&mem_ctls_mutex);
 750
 751         if (edac_mc_owner && edac_mc_owner != mci->mod_name) {
 752                 ret = -EPERM;
 753                 goto fail0;
 754         }
 755
 756         if (add_mc_to_global_list(mci))
 757                 goto fail0;
 758
 759         /* set load time so that error rate can be tracked */
 760         mci->start_time = jiffies;
 761
 762         mci->bus = &mc_bus[mci->mc_idx];
 763
 764         if (edac_create_sysfs_mci_device(mci, groups)) {
 765                 edac_mc_printk(mci, KERN_WARNING,
 766                         "failed to create sysfs device\n");
 767                 goto fail1;
 768         }
 769
 770         if (mci->edac_check) {
 771                 mci->op_state = OP_RUNNING_POLL;
 772
 773                 INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function);
 774                 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
 775
 776         } else {
 777                 mci->op_state = OP_RUNNING_INTERRUPT;
 778         }
 779
 780         /* Report action taken */
 781         edac_mc_printk(mci, KERN_INFO,
 782                 "Giving out device to module %s controller %s: DEV %s (%s)\n",
 783                 mci->mod_name, mci->ctl_name, mci->dev_name,
 784                 edac_op_state_to_string(mci->op_state));
 785
 786         edac_mc_owner = mci->mod_name;
 787
 788         mutex_unlock(&mem_ctls_mutex);
 789         return 0;
 790
 791 fail1:
 792         del_mc_from_global_list(mci);
 793
 794 fail0:
 795         mutex_unlock(&mem_ctls_mutex);
 796         return ret;
 797 }
 798 EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups);
 799
 800 struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
 801 {
 802         struct mem_ctl_info *mci;
 803
 804         edac_dbg(0, "\n");
 805
 806         mutex_lock(&mem_ctls_mutex);
 807
 808         /* find the requested mci struct in the global list */
 809         mci = __find_mci_by_dev(dev);
 810         if (mci == NULL) {
 811                 mutex_unlock(&mem_ctls_mutex);
 812                 return NULL;
 813         }
 814
 815         /* mark MCI offline: */
 816         mci->op_state = OP_OFFLINE;
 817
 818         if (del_mc_from_global_list(mci))
 819                 edac_mc_owner = NULL;
 820
 821         mutex_unlock(&mem_ctls_mutex);
 822
 823         if (mci->edac_check)
 824                 edac_stop_work(&mci->work);
 825
 826         /* remove from sysfs */
 827         edac_remove_sysfs_mci_device(mci);
 828
 829         edac_printk(KERN_INFO, EDAC_MC,
 830                 "Removed device %d for %s %s: DEV %s\n", mci->mc_idx,
 831                 mci->mod_name, mci->ctl_name, edac_dev_name(mci));
 832
 833         return mci;
 834 }
 835 EXPORT_SYMBOL_GPL(edac_mc_del_mc);
 836
 837 static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
 838                                 u32 size)
 839 {
 840         struct page *pg;
 841         void *virt_addr;
 842         unsigned long flags = 0;
 843
 844         edac_dbg(3, "\n");
 845
 846         /* ECC error page was not in our memory. Ignore it. */
 847         if (!pfn_valid(page))
 848                 return;
 849
 850         /* Find the actual page structure then map it and fix */
 851         pg = pfn_to_page(page);
 852
 853         if (PageHighMem(pg))
 854                 local_irq_save(flags);
 855
 856         virt_addr = kmap_atomic(pg);
 857
 858         /* Perform architecture specific atomic scrub operation */
 859         edac_atomic_scrub(virt_addr + offset, size);
 860
 861         /* Unmap and complete */
 862         kunmap_atomic(virt_addr);
 863
 864         if (PageHighMem(pg))
 865                 local_irq_restore(flags);
 866 }
 867
 868 /* FIXME - should return -1 */
 869 int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
 870 {
 871         struct csrow_info **csrows = mci->csrows;
 872         int row, i, j, n;
 873
 874         edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
 875         row = -1;
 876
 877         for (i = 0; i < mci->nr_csrows; i++) {
 878                 struct csrow_info *csrow = csrows[i];
 879                 n = 0;
 880                 for (j = 0; j < csrow->nr_channels; j++) {
 881                         struct dimm_info *dimm = csrow->channels[j]->dimm;
 882                         n += dimm->nr_pages;
 883                 }
 884                 if (n == 0)
 885                         continue;
 886
 887                 edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
 888                          mci->mc_idx,
 889                          csrow->first_page, page, csrow->last_page,
 890                          csrow->page_mask);
 891
 892                 if ((page >= csrow->first_page) &&
 893                     (page <= csrow->last_page) &&
 894                     ((page & csrow->page_mask) ==
 895                      (csrow->first_page & csrow->page_mask))) {
 896                         row = i;
 897                         break;
 898                 }
 899         }
 900
 901         if (row == -1)
 902                 edac_mc_printk(mci, KERN_ERR,
 903                         "could not look up page error address %lx\n",
 904                         (unsigned long)page);
 905
 906         return row;
 907 }
 908 EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
 909
 910 const char *edac_layer_name[] = {
 911         [EDAC_MC_LAYER_BRANCH] = "branch",
 912         [EDAC_MC_LAYER_CHANNEL] = "channel",
 913         [EDAC_MC_LAYER_SLOT] = "slot",
 914         [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
 915         [EDAC_MC_LAYER_ALL_MEM] = "memory",
 916 };
 917 EXPORT_SYMBOL_GPL(edac_layer_name);
 918
 919 static void edac_inc_ce_error(struct mem_ctl_info *mci,
 920                               bool enable_per_layer_report,
 921                               const int pos[EDAC_MAX_LAYERS],
 922                               const u16 count)
 923 {
 924         int i, index = 0;
 925
 926         mci->ce_mc += count;
 927
 928         if (!enable_per_layer_report) {
 929                 mci->ce_noinfo_count += count;
 930                 return;
 931         }
 932
 933         for (i = 0; i < mci->n_layers; i++) {
 934                 if (pos[i] < 0)
 935                         break;
 936                 index += pos[i];
 937                 mci->ce_per_layer[i][index] += count;
 938
 939                 if (i < mci->n_layers - 1)
 940                         index *= mci->layers[i + 1].size;
 941         }
 942 }
 943
 944 static void edac_inc_ue_error(struct mem_ctl_info *mci,
 945                                     bool enable_per_layer_report,
 946                                     const int pos[EDAC_MAX_LAYERS],
 947                                     const u16 count)
 948 {
 949         int i, index = 0;
 950
 951         mci->ue_mc += count;
 952
 953         if (!enable_per_layer_report) {
 954                 mci->ue_noinfo_count += count;
 955                 return;
 956         }
 957
 958         for (i = 0; i < mci->n_layers; i++) {
 959                 if (pos[i] < 0)
 960                         break;
 961                 index += pos[i];
 962                 mci->ue_per_layer[i][index] += count;
 963
 964                 if (i < mci->n_layers - 1)
 965                         index *= mci->layers[i + 1].size;
 966         }
 967 }
 968
 969 static void edac_ce_error(struct mem_ctl_info *mci,
 970                           const u16 error_count,
 971                           const int pos[EDAC_MAX_LAYERS],
 972                           const char *msg,
 973                           const char *location,
 974                           const char *label,
 975                           const char *detail,
 976                           const char *other_detail,
 977                           const bool enable_per_layer_report,
 978                           const unsigned long page_frame_number,
 979                           const unsigned long offset_in_page,
 980                           long grain)
 981 {
 982         unsigned long remapped_page;
 983         char *msg_aux = "";
 984
 985         if (*msg)
 986                 msg_aux = " ";
 987
 988         if (edac_mc_get_log_ce()) {
 989                 if (other_detail && *other_detail)
 990                         edac_mc_printk(mci, KERN_WARNING,
 991                                        "%d CE %s%son %s (%s %s - %s)\n",
 992                                        error_count, msg, msg_aux, label,
 993                                        location, detail, other_detail);
 994                 else
 995                         edac_mc_printk(mci, KERN_WARNING,
 996                                        "%d CE %s%son %s (%s %s)\n",
 997                                        error_count, msg, msg_aux, label,
 998                                        location, detail);
 999         }
1000         edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count);
1001
1002         if (mci->scrub_mode == SCRUB_SW_SRC) {
1003                 /*
1004                         * Some memory controllers (called MCs below) can remap
1005                         * memory so that it is still available at a different
1006                         * address when PCI devices map into memory.
1007                         * MC's that can't do this, lose the memory where PCI
1008                         * devices are mapped. This mapping is MC-dependent
1009                         * and so we call back into the MC driver for it to
1010                         * map the MC page to a physical (CPU) page which can
1011                         * then be mapped to a virtual page - which can then
1012                         * be scrubbed.
1013                         */
1014                 remapped_page = mci->ctl_page_to_phys ?
1015                         mci->ctl_page_to_phys(mci, page_frame_number) :
1016                         page_frame_number;
1017
1018                 edac_mc_scrub_block(remapped_page,
1019                                         offset_in_page, grain);
1020         }
1021 }
1022
1023 static void edac_ue_error(struct mem_ctl_info *mci,
1024                           const u16 error_count,
1025                           const int pos[EDAC_MAX_LAYERS],
1026                           const char *msg,
1027                           const char *location,
1028                           const char *label,
1029                           const char *detail,
1030                           const char *other_detail,
1031                           const bool enable_per_layer_report)
1032 {
1033         char *msg_aux = "";
1034
1035         if (*msg)
1036                 msg_aux = " ";
1037
1038         if (edac_mc_get_log_ue()) {
1039                 if (other_detail && *other_detail)
1040                         edac_mc_printk(mci, KERN_WARNING,
1041                                        "%d UE %s%son %s (%s %s - %s)\n",
1042                                        error_count, msg, msg_aux, label,
1043                                        location, detail, other_detail);
1044                 else
1045                         edac_mc_printk(mci, KERN_WARNING,
1046                                        "%d UE %s%son %s (%s %s)\n",
1047                                        error_count, msg, msg_aux, label,
1048                                        location, detail);
1049         }
1050
1051         if (edac_mc_get_panic_on_ue()) {
1052                 if (other_detail && *other_detail)
1053                         panic("UE %s%son %s (%s%s - %s)\n",
1054                               msg, msg_aux, label, location, detail, other_detail);
1055                 else
1056                         panic("UE %s%son %s (%s%s)\n",
1057                               msg, msg_aux, label, location, detail);
1058         }
1059
1060         edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count);
1061 }
1062
1063 void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type,
1064                               struct mem_ctl_info *mci,
1065                               struct edac_raw_error_desc *e)
1066 {
1067         char detail[80];
1068         int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
1069
1070         /* Memory type dependent details about the error */
1071         if (type == HW_EVENT_ERR_CORRECTED) {
1072                 snprintf(detail, sizeof(detail),
1073                         "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx",
1074                         e->page_frame_number, e->offset_in_page,
1075                         e->grain, e->syndrome);
1076                 edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1077                               detail, e->other_detail, e->enable_per_layer_report,
1078                               e->page_frame_number, e->offset_in_page, e->grain);
1079         } else {
1080                 snprintf(detail, sizeof(detail),
1081                         "page:0x%lx offset:0x%lx grain:%ld",
1082                         e->page_frame_number, e->offset_in_page, e->grain);
1083
1084                 edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1085                               detail, e->other_detail, e->enable_per_layer_report);
1086         }
1087
1088
1089 }
1090 EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error);
1091
1092 void edac_mc_handle_error(const enum hw_event_mc_err_type type,
1093                           struct mem_ctl_info *mci,
1094                           const u16 error_count,
1095                           const unsigned long page_frame_number,
1096                           const unsigned long offset_in_page,
1097                           const unsigned long syndrome,
1098                           const int top_layer,
1099                           const int mid_layer,
1100                           const int low_layer,
1101                           const char *msg,
1102                           const char *other_detail)
1103 {
1104         char *p;
1105         int row = -1, chan = -1;
1106         int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
1107         int i, n_labels = 0;
1108         u8 grain_bits;
1109         struct edac_raw_error_desc *e = &mci->error_desc;
1110
1111         edac_dbg(3, "MC%d\n", mci->mc_idx);
1112
1113         /* Fills the error report buffer */
1114         memset(e, 0, sizeof (*e));
1115         e->error_count = error_count;
1116         e->top_layer = top_layer;
1117         e->mid_layer = mid_layer;
1118         e->low_layer = low_layer;
1119         e->page_frame_number = page_frame_number;
1120         e->offset_in_page = offset_in_page;
1121         e->syndrome = syndrome;
1122         e->msg = msg;
1123         e->other_detail = other_detail;
1124
1125         /*
1126          * Check if the event report is consistent and if the memory
1127          * location is known. If it is known, enable_per_layer_report will be
1128          * true, the DIMM(s) label info will be filled and the per-layer
1129          * error counters will be incremented.
1130          */
1131         for (i = 0; i < mci->n_layers; i++) {
1132                 if (pos[i] >= (int)mci->layers[i].size) {
1133
1134                         edac_mc_printk(mci, KERN_ERR,
1135                                        "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
1136                                        edac_layer_name[mci->layers[i].type],
1137                                        pos[i], mci->layers[i].size);
1138                         /*
1139                          * Instead of just returning it, let's use what's
1140                          * known about the error. The increment routines and
1141                          * the DIMM filter logic will do the right thing by
1142                          * pointing the likely damaged DIMMs.
1143                          */
1144                         pos[i] = -1;
1145                 }
1146                 if (pos[i] >= 0)
1147                         e->enable_per_layer_report = true;
1148         }
1149
1150         /*
1151          * Get the dimm label/grain that applies to the match criteria.
1152          * As the error algorithm may not be able to point to just one memory
1153          * stick, the logic here will get all possible labels that could
1154          * pottentially be affected by the error.
1155          * On FB-DIMM memory controllers, for uncorrected errors, it is common
1156          * to have only the MC channel and the MC dimm (also called "branch")
1157          * but the channel is not known, as the memory is arranged in pairs,
1158          * where each memory belongs to a separate channel within the same
1159          * branch.
1160          */
1161         p = e->label;
1162         *p = '\0';
1163
1164         for (i = 0; i < mci->tot_dimms; i++) {
1165                 struct dimm_info *dimm = mci->dimms[i];
1166
1167                 if (top_layer >= 0 && top_layer != dimm->location[0])
1168                         continue;
1169                 if (mid_layer >= 0 && mid_layer != dimm->location[1])
1170                         continue;
1171                 if (low_layer >= 0 && low_layer != dimm->location[2])
1172                         continue;
1173
1174                 /* get the max grain, over the error match range */
1175                 if (dimm->grain > e->grain)
1176                         e->grain = dimm->grain;
1177
1178                 /*
1179                  * If the error is memory-controller wide, there's no need to
1180                  * seek for the affected DIMMs because the whole
1181                  * channel/memory controller/...  may be affected.
1182                  * Also, don't show errors for empty DIMM slots.
1183                  */
1184                 if (e->enable_per_layer_report && dimm->nr_pages) {
1185                         if (n_labels >= EDAC_MAX_LABELS) {
1186                                 e->enable_per_layer_report = false;
1187                                 break;
1188                         }
1189                         n_labels++;
1190                         if (p != e->label) {
1191                                 strcpy(p, OTHER_LABEL);
1192                                 p += strlen(OTHER_LABEL);
1193                         }
1194                         strcpy(p, dimm->label);
1195                         p += strlen(p);
1196                         *p = '\0';
1197
1198                         /*
1199                          * get csrow/channel of the DIMM, in order to allow
1200                          * incrementing the compat API counters
1201                          */
1202                         edac_dbg(4, "%s csrows map: (%d,%d)\n",
1203                                  mci->csbased ? "rank" : "dimm",
1204                                  dimm->csrow, dimm->cschannel);
1205                         if (row == -1)
1206                                 row = dimm->csrow;
1207                         else if (row >= 0 && row != dimm->csrow)
1208                                 row = -2;
1209
1210                         if (chan == -1)
1211                                 chan = dimm->cschannel;
1212                         else if (chan >= 0 && chan != dimm->cschannel)
1213                                 chan = -2;
1214                 }
1215         }
1216
1217         if (!e->enable_per_layer_report) {
1218                 strcpy(e->label, "any memory");
1219         } else {
1220                 edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
1221                 if (p == e->label)
1222                         strcpy(e->label, "unknown memory");
1223                 if (type == HW_EVENT_ERR_CORRECTED) {
1224                         if (row >= 0) {
1225                                 mci->csrows[row]->ce_count += error_count;
1226                                 if (chan >= 0)
1227                                         mci->csrows[row]->channels[chan]->ce_count += error_count;
1228                         }
1229                 } else
1230                         if (row >= 0)
1231                                 mci->csrows[row]->ue_count += error_count;
1232         }
1233
1234         /* Fill the RAM location data */
1235         p = e->location;
1236
1237         for (i = 0; i < mci->n_layers; i++) {
1238                 if (pos[i] < 0)
1239                         continue;
1240
1241                 p += sprintf(p, "%s:%d ",
1242                              edac_layer_name[mci->layers[i].type],
1243                              pos[i]);
1244         }
1245         if (p > e->location)
1246                 *(p - 1) = '\0';
1247
1248         /* Report the error via the trace interface */
1249         grain_bits = fls_long(e->grain) + 1;
1250
1251         if (IS_ENABLED(CONFIG_RAS))
1252                 trace_mc_event(type, e->msg, e->label, e->error_count,
1253                                mci->mc_idx, e->top_layer, e->mid_layer,
1254                                e->low_layer,
1255                                (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
1256                                grain_bits, e->syndrome, e->other_detail);
1257
1258         edac_raw_mc_handle_error(type, mci, e);
1259 }
1260 EXPORT_SYMBOL_GPL(edac_mc_handle_error);