drivers/dma/ioat/hw.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called COPYING.
  16  */
  17 #ifndef _IOAT_HW_H_
  18 #define _IOAT_HW_H_
  19
  20 /* PCI Configuration Space Values */
  21 #define IOAT_MMIO_BAR           0
  22
  23 /* CB device ID's */
  24 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0   0x0e20
  25 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1   0x0e21
  26 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2   0x0e22
  27 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3   0x0e23
  28 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4   0x0e24
  29 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5   0x0e25
  30 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6   0x0e26
  31 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7   0x0e27
  32 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8   0x0e2e
  33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9   0x0e2f
  34
  35 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0   0x2f20
  36 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1   0x2f21
  37 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2   0x2f22
  38 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3   0x2f23
  39 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4   0x2f24
  40 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5   0x2f25
  41 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6   0x2f26
  42 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7   0x2f27
  43 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8   0x2f2e
  44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9   0x2f2f
  45
  46 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0   0x0C50
  47 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1   0x0C51
  48 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2   0x0C52
  49 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3   0x0C53
  50
  51 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
  52 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
  53 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
  54 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
  55
  56 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
  57 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
  58 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
  59 #define IOAT_VER_3_2            0x32    /* Version 3.2 */
  60 #define IOAT_VER_3_3            0x33    /* Version 3.3 */
  61
  62
  63 int system_has_dca_enabled(struct pci_dev *pdev);
  64
  65 struct ioat_dma_descriptor {
  66         uint32_t        size;
  67         union {
  68                 uint32_t ctl;
  69                 struct {
  70                         unsigned int int_en:1;
  71                         unsigned int src_snoop_dis:1;
  72                         unsigned int dest_snoop_dis:1;
  73                         unsigned int compl_write:1;
  74                         unsigned int fence:1;
  75                         unsigned int null:1;
  76                         unsigned int src_brk:1;
  77                         unsigned int dest_brk:1;
  78                         unsigned int bundle:1;
  79                         unsigned int dest_dca:1;
  80                         unsigned int hint:1;
  81                         unsigned int rsvd2:13;
  82                         #define IOAT_OP_COPY 0x00
  83                         unsigned int op:8;
  84                 } ctl_f;
  85         };
  86         uint64_t        src_addr;
  87         uint64_t        dst_addr;
  88         uint64_t        next;
  89         uint64_t        rsv1;
  90         uint64_t        rsv2;
  91         /* store some driver data in an unused portion of the descriptor */
  92         union {
  93                 uint64_t        user1;
  94                 uint64_t        tx_cnt;
  95         };
  96         uint64_t        user2;
  97 };
  98
  99 struct ioat_xor_descriptor {
 100         uint32_t        size;
 101         union {
 102                 uint32_t ctl;
 103                 struct {
 104                         unsigned int int_en:1;
 105                         unsigned int src_snoop_dis:1;
 106                         unsigned int dest_snoop_dis:1;
 107                         unsigned int compl_write:1;
 108                         unsigned int fence:1;
 109                         unsigned int src_cnt:3;
 110                         unsigned int bundle:1;
 111                         unsigned int dest_dca:1;
 112                         unsigned int hint:1;
 113                         unsigned int rsvd:13;
 114                         #define IOAT_OP_XOR 0x87
 115                         #define IOAT_OP_XOR_VAL 0x88
 116                         unsigned int op:8;
 117                 } ctl_f;
 118         };
 119         uint64_t        src_addr;
 120         uint64_t        dst_addr;
 121         uint64_t        next;
 122         uint64_t        src_addr2;
 123         uint64_t        src_addr3;
 124         uint64_t        src_addr4;
 125         uint64_t        src_addr5;
 126 };
 127
 128 struct ioat_xor_ext_descriptor {
 129         uint64_t        src_addr6;
 130         uint64_t        src_addr7;
 131         uint64_t        src_addr8;
 132         uint64_t        next;
 133         uint64_t        rsvd[4];
 134 };
 135
 136 struct ioat_pq_descriptor {
 137         union {
 138                 uint32_t        size;
 139                 uint32_t        dwbes;
 140                 struct {
 141                         unsigned int rsvd:25;
 142                         unsigned int p_val_err:1;
 143                         unsigned int q_val_err:1;
 144                         unsigned int rsvd1:4;
 145                         unsigned int wbes:1;
 146                 } dwbes_f;
 147         };
 148         union {
 149                 uint32_t ctl;
 150                 struct {
 151                         unsigned int int_en:1;
 152                         unsigned int src_snoop_dis:1;
 153                         unsigned int dest_snoop_dis:1;
 154                         unsigned int compl_write:1;
 155                         unsigned int fence:1;
 156                         unsigned int src_cnt:3;
 157                         unsigned int bundle:1;
 158                         unsigned int dest_dca:1;
 159                         unsigned int hint:1;
 160                         unsigned int p_disable:1;
 161                         unsigned int q_disable:1;
 162                         unsigned int rsvd2:2;
 163                         unsigned int wb_en:1;
 164                         unsigned int prl_en:1;
 165                         unsigned int rsvd3:7;
 166                         #define IOAT_OP_PQ 0x89
 167                         #define IOAT_OP_PQ_VAL 0x8a
 168                         #define IOAT_OP_PQ_16S 0xa0
 169                         #define IOAT_OP_PQ_VAL_16S 0xa1
 170                         unsigned int op:8;
 171                 } ctl_f;
 172         };
 173         uint64_t        src_addr;
 174         uint64_t        p_addr;
 175         uint64_t        next;
 176         uint64_t        src_addr2;
 177         union {
 178                 uint64_t        src_addr3;
 179                 uint64_t        sed_addr;
 180         };
 181         uint8_t         coef[8];
 182         uint64_t        q_addr;
 183 };
 184
 185 struct ioat_pq_ext_descriptor {
 186         uint64_t        src_addr4;
 187         uint64_t        src_addr5;
 188         uint64_t        src_addr6;
 189         uint64_t        next;
 190         uint64_t        src_addr7;
 191         uint64_t        src_addr8;
 192         uint64_t        rsvd[2];
 193 };
 194
 195 struct ioat_pq_update_descriptor {
 196         uint32_t        size;
 197         union {
 198                 uint32_t ctl;
 199                 struct {
 200                         unsigned int int_en:1;
 201                         unsigned int src_snoop_dis:1;
 202                         unsigned int dest_snoop_dis:1;
 203                         unsigned int compl_write:1;
 204                         unsigned int fence:1;
 205                         unsigned int src_cnt:3;
 206                         unsigned int bundle:1;
 207                         unsigned int dest_dca:1;
 208                         unsigned int hint:1;
 209                         unsigned int p_disable:1;
 210                         unsigned int q_disable:1;
 211                         unsigned int rsvd:3;
 212                         unsigned int coef:8;
 213                         #define IOAT_OP_PQ_UP 0x8b
 214                         unsigned int op:8;
 215                 } ctl_f;
 216         };
 217         uint64_t        src_addr;
 218         uint64_t        p_addr;
 219         uint64_t        next;
 220         uint64_t        src_addr2;
 221         uint64_t        p_src;
 222         uint64_t        q_src;
 223         uint64_t        q_addr;
 224 };
 225
 226 struct ioat_raw_descriptor {
 227         uint64_t        field[8];
 228 };
 229
 230 struct ioat_pq16a_descriptor {
 231         uint8_t coef[8];
 232         uint64_t src_addr3;
 233         uint64_t src_addr4;
 234         uint64_t src_addr5;
 235         uint64_t src_addr6;
 236         uint64_t src_addr7;
 237         uint64_t src_addr8;
 238         uint64_t src_addr9;
 239 };
 240
 241 struct ioat_pq16b_descriptor {
 242         uint64_t src_addr10;
 243         uint64_t src_addr11;
 244         uint64_t src_addr12;
 245         uint64_t src_addr13;
 246         uint64_t src_addr14;
 247         uint64_t src_addr15;
 248         uint64_t src_addr16;
 249         uint64_t rsvd;
 250 };
 251
 252 union ioat_sed_pq_descriptor {
 253         struct ioat_pq16a_descriptor a;
 254         struct ioat_pq16b_descriptor b;
 255 };
 256
 257 #define SED_SIZE        64
 258
 259 struct ioat_sed_raw_descriptor {
 260         uint64_t        a[8];
 261         uint64_t        b[8];
 262         uint64_t        c[8];
 263 };
 264
 265 #endif