drivers/clocksource/timer-tegra20.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@google.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/clockchips.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/delay.h>
  23 #include <linux/err.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/percpu.h>
  28 #include <linux/sched_clock.h>
  29 #include <linux/time.h>
  30
  31 #include "timer-of.h"
  32
  33 #ifdef CONFIG_ARM
  34 #include <asm/mach/time.h>
  35 #endif
  36
  37 #define RTC_SECONDS            0x08
  38 #define RTC_SHADOW_SECONDS     0x0c
  39 #define RTC_MILLISECONDS       0x10
  40
  41 #define TIMERUS_CNTR_1US 0x10
  42 #define TIMERUS_USEC_CFG 0x14
  43 #define TIMERUS_CNTR_FREEZE 0x4c
  44
  45 #define TIMER_PTV               0x0
  46 #define TIMER_PTV_EN            BIT(31)
  47 #define TIMER_PTV_PER           BIT(30)
  48 #define TIMER_PCR               0x4
  49 #define TIMER_PCR_INTR_CLR      BIT(30)
  50
  51 #ifdef CONFIG_ARM
  52 #define TIMER_CPU0              0x50 /* TIMER3 */
  53 #else
  54 #define TIMER_CPU0              0x90 /* TIMER10 */
  55 #define TIMER10_IRQ_IDX         10
  56 #define IRQ_IDX_FOR_CPU(cpu)    (TIMER10_IRQ_IDX + cpu)
  57 #endif
  58 #define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
  59
  60 static u32 usec_config;
  61 static void __iomem *timer_reg_base;
  62 #ifdef CONFIG_ARM
  63 static void __iomem *rtc_base;
  64 static struct timespec64 persistent_ts;
  65 static u64 persistent_ms, last_persistent_ms;
  66 static struct delay_timer tegra_delay_timer;
  67 #endif
  68
  69 static int tegra_timer_set_next_event(unsigned long cycles,
  70                                          struct clock_event_device *evt)
  71 {
  72         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  73
  74         writel(TIMER_PTV_EN |
  75                ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
  76                reg_base + TIMER_PTV);
  77
  78         return 0;
  79 }
  80
  81 static int tegra_timer_shutdown(struct clock_event_device *evt)
  82 {
  83         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  84
  85         writel(0, reg_base + TIMER_PTV);
  86
  87         return 0;
  88 }
  89
  90 static int tegra_timer_set_periodic(struct clock_event_device *evt)
  91 {
  92         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  93
  94         writel(TIMER_PTV_EN | TIMER_PTV_PER |
  95                ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
  96                reg_base + TIMER_PTV);
  97
  98         return 0;
  99 }
 100
 101 static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
 102 {
 103         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 104         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
 105
 106         writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
 107         evt->event_handler(evt);
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static void tegra_timer_suspend(struct clock_event_device *evt)
 113 {
 114         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
 115
 116         writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
 117 }
 118
 119 static void tegra_timer_resume(struct clock_event_device *evt)
 120 {
 121         writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
 122 }
 123
 124 #ifdef CONFIG_ARM64
 125 static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
 126         .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
 127
 128         .clkevt = {
 129                 .name = "tegra_timer",
 130                 .rating = 460,
 131                 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 132                 .set_next_event = tegra_timer_set_next_event,
 133                 .set_state_shutdown = tegra_timer_shutdown,
 134                 .set_state_periodic = tegra_timer_set_periodic,
 135                 .set_state_oneshot = tegra_timer_shutdown,
 136                 .tick_resume = tegra_timer_shutdown,
 137                 .suspend = tegra_timer_suspend,
 138                 .resume = tegra_timer_resume,
 139         },
 140 };
 141
 142 static int tegra_timer_setup(unsigned int cpu)
 143 {
 144         struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
 145
 146         irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
 147         enable_irq(to->clkevt.irq);
 148
 149         clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
 150                                         1, /* min */
 151                                         0x1fffffff); /* 29 bits */
 152
 153         return 0;
 154 }
 155
 156 static int tegra_timer_stop(unsigned int cpu)
 157 {
 158         struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
 159
 160         to->clkevt.set_state_shutdown(&to->clkevt);
 161         disable_irq_nosync(to->clkevt.irq);
 162
 163         return 0;
 164 }
 165 #else /* CONFIG_ARM */
 166 static struct timer_of tegra_to = {
 167         .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
 168
 169         .clkevt = {
 170                 .name = "tegra_timer",
 171                 .rating = 300,
 172                 .features = CLOCK_EVT_FEAT_ONESHOT |
 173                             CLOCK_EVT_FEAT_PERIODIC |
 174                             CLOCK_EVT_FEAT_DYNIRQ,
 175                 .set_next_event = tegra_timer_set_next_event,
 176                 .set_state_shutdown = tegra_timer_shutdown,
 177                 .set_state_periodic = tegra_timer_set_periodic,
 178                 .set_state_oneshot = tegra_timer_shutdown,
 179                 .tick_resume = tegra_timer_shutdown,
 180                 .suspend = tegra_timer_suspend,
 181                 .resume = tegra_timer_resume,
 182                 .cpumask = cpu_possible_mask,
 183         },
 184
 185         .of_irq = {
 186                 .index = 2,
 187                 .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
 188                 .handler = tegra_timer_isr,
 189         },
 190 };
 191
 192 static u64 notrace tegra_read_sched_clock(void)
 193 {
 194         return readl(timer_reg_base + TIMERUS_CNTR_1US);
 195 }
 196
 197 static unsigned long tegra_delay_timer_read_counter_long(void)
 198 {
 199         return readl(timer_reg_base + TIMERUS_CNTR_1US);
 200 }
 201
 202 /*
 203  * tegra_rtc_read - Reads the Tegra RTC registers
 204  * Care must be taken that this funciton is not called while the
 205  * tegra_rtc driver could be executing to avoid race conditions
 206  * on the RTC shadow register
 207  */
 208 static u64 tegra_rtc_read_ms(void)
 209 {
 210         u32 ms = readl(rtc_base + RTC_MILLISECONDS);
 211         u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
 212         return (u64)s * MSEC_PER_SEC + ms;
 213 }
 214
 215 /*
 216  * tegra_read_persistent_clock64 -  Return time from a persistent clock.
 217  *
 218  * Reads the time from a source which isn't disabled during PM, the
 219  * 32k sync timer.  Convert the cycles elapsed since last read into
 220  * nsecs and adds to a monotonically increasing timespec64.
 221  * Care must be taken that this funciton is not called while the
 222  * tegra_rtc driver could be executing to avoid race conditions
 223  * on the RTC shadow register
 224  */
 225 static void tegra_read_persistent_clock64(struct timespec64 *ts)
 226 {
 227         u64 delta;
 228
 229         last_persistent_ms = persistent_ms;
 230         persistent_ms = tegra_rtc_read_ms();
 231         delta = persistent_ms - last_persistent_ms;
 232
 233         timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
 234         *ts = persistent_ts;
 235 }
 236 #endif
 237
 238 static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
 239 {
 240         int ret = 0;
 241
 242         ret = timer_of_init(np, to);
 243         if (ret < 0)
 244                 goto out;
 245
 246         timer_reg_base = timer_of_base(to);
 247
 248         /*
 249          * Configure microsecond timers to have 1MHz clock
 250          * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
 251          * Uses n+1 scheme
 252          */
 253         switch (timer_of_rate(to)) {
 254         case 12000000:
 255                 usec_config = 0x000b; /* (11+1)/(0+1) */
 256                 break;
 257         case 12800000:
 258                 usec_config = 0x043f; /* (63+1)/(4+1) */
 259                 break;
 260         case 13000000:
 261                 usec_config = 0x000c; /* (12+1)/(0+1) */
 262                 break;
 263         case 16800000:
 264                 usec_config = 0x0453; /* (83+1)/(4+1) */
 265                 break;
 266         case 19200000:
 267                 usec_config = 0x045f; /* (95+1)/(4+1) */
 268                 break;
 269         case 26000000:
 270                 usec_config = 0x0019; /* (25+1)/(0+1) */
 271                 break;
 272         case 38400000:
 273                 usec_config = 0x04bf; /* (191+1)/(4+1) */
 274                 break;
 275         case 48000000:
 276                 usec_config = 0x002f; /* (47+1)/(0+1) */
 277                 break;
 278         default:
 279                 ret = -EINVAL;
 280                 goto out;
 281         }
 282
 283         writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
 284
 285 out:
 286         return ret;
 287 }
 288
 289 #ifdef CONFIG_ARM64
 290 static int __init tegra_init_timer(struct device_node *np)
 291 {
 292         int cpu, ret = 0;
 293         struct timer_of *to;
 294
 295         to = this_cpu_ptr(&tegra_to);
 296         ret = tegra_timer_common_init(np, to);
 297         if (ret < 0)
 298                 goto out;
 299
 300         for_each_possible_cpu(cpu) {
 301                 struct timer_of *cpu_to;
 302
 303                 cpu_to = per_cpu_ptr(&tegra_to, cpu);
 304                 cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
 305                 cpu_to->of_clk.rate = timer_of_rate(to);
 306                 cpu_to->clkevt.cpumask = cpumask_of(cpu);
 307                 cpu_to->clkevt.irq =
 308                         irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
 309                 if (!cpu_to->clkevt.irq) {
 310                         pr_err("%s: can't map IRQ for CPU%d\n",
 311                                __func__, cpu);
 312                         ret = -EINVAL;
 313                         goto out;
 314                 }
 315
 316                 irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
 317                 ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
 318                                   IRQF_TIMER | IRQF_NOBALANCING,
 319                                   cpu_to->clkevt.name, &cpu_to->clkevt);
 320                 if (ret) {
 321                         pr_err("%s: cannot setup irq %d for CPU%d\n",
 322                                 __func__, cpu_to->clkevt.irq, cpu);
 323                         ret = -EINVAL;
 324                         goto out_irq;
 325                 }
 326         }
 327
 328         cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
 329                           "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
 330                           tegra_timer_stop);
 331
 332         return ret;
 333 out_irq:
 334         for_each_possible_cpu(cpu) {
 335                 struct timer_of *cpu_to;
 336
 337                 cpu_to = per_cpu_ptr(&tegra_to, cpu);
 338                 if (cpu_to->clkevt.irq) {
 339                         free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
 340                         irq_dispose_mapping(cpu_to->clkevt.irq);
 341                 }
 342         }
 343 out:
 344         timer_of_cleanup(to);
 345         return ret;
 346 }
 347 #else /* CONFIG_ARM */
 348 static int __init tegra_init_timer(struct device_node *np)
 349 {
 350         int ret = 0;
 351
 352         ret = tegra_timer_common_init(np, &tegra_to);
 353         if (ret < 0)
 354                 goto out;
 355
 356         tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
 357         tegra_to.of_clk.rate = 1000000; /* microsecond timer */
 358
 359         sched_clock_register(tegra_read_sched_clock, 32,
 360                              timer_of_rate(&tegra_to));
 361         ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
 362                                     "timer_us", timer_of_rate(&tegra_to),
 363                                     300, 32, clocksource_mmio_readl_up);
 364         if (ret) {
 365                 pr_err("Failed to register clocksource\n");
 366                 goto out;
 367         }
 368
 369         tegra_delay_timer.read_current_timer =
 370                         tegra_delay_timer_read_counter_long;
 371         tegra_delay_timer.freq = timer_of_rate(&tegra_to);
 372         register_current_timer_delay(&tegra_delay_timer);
 373
 374         clockevents_config_and_register(&tegra_to.clkevt,
 375                                         timer_of_rate(&tegra_to),
 376                                         0x1,
 377                                         0x1fffffff);
 378
 379         return ret;
 380 out:
 381         timer_of_cleanup(&tegra_to);
 382
 383         return ret;
 384 }
 385
 386 static int __init tegra20_init_rtc(struct device_node *np)
 387 {
 388         struct clk *clk;
 389
 390         rtc_base = of_iomap(np, 0);
 391         if (!rtc_base) {
 392                 pr_err("Can't map RTC registers\n");
 393                 return -ENXIO;
 394         }
 395
 396         /*
 397          * rtc registers are used by read_persistent_clock, keep the rtc clock
 398          * enabled
 399          */
 400         clk = of_clk_get(np, 0);
 401         if (IS_ERR(clk))
 402                 pr_warn("Unable to get rtc-tegra clock\n");
 403         else
 404                 clk_prepare_enable(clk);
 405
 406         return register_persistent_clock(tegra_read_persistent_clock64);
 407 }
 408 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
 409 #endif
 410 TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
 411 TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);