drivers/clk/ti/clk-7xx.c

   1 /*
   2  * DRA7 Clock init
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo (t-kristo@ti.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/list.h>
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/clk/ti.h>
  18 #include <dt-bindings/clock/dra7.h>
  19
  20 #include "clock.h"
  21
  22 #define DRA7_DPLL_GMAC_DEFFREQ                          1000000000
  23 #define DRA7_DPLL_USB_DEFFREQ                           960000000
  24
  25 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
  26         { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
  27         { 0 },
  28 };
  29
  30 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
  31         "per_abe_x1_gfclk2_div",
  32         "video1_clk2_div",
  33         "video2_clk2_div",
  34         "hdmi_clk2_div",
  35         NULL,
  36 };
  37
  38 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
  39         "abe_24m_fclk",
  40         "abe_sys_clk_div",
  41         "func_24m_clk",
  42         "atl_clkin3_ck",
  43         "atl_clkin2_ck",
  44         "atl_clkin1_ck",
  45         "atl_clkin0_ck",
  46         "sys_clkin2",
  47         "ref_clkin0_ck",
  48         "ref_clkin1_ck",
  49         "ref_clkin2_ck",
  50         "ref_clkin3_ck",
  51         "mlb_clk",
  52         "mlbp_clk",
  53         NULL,
  54 };
  55
  56 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
  57         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  58         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  59         { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  60         { 0 },
  61 };
  62
  63 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
  64         "timer_sys_clk_div",
  65         "sys_32k_ck",
  66         "sys_clkin2",
  67         "ref_clkin0_ck",
  68         "ref_clkin1_ck",
  69         "ref_clkin2_ck",
  70         "ref_clkin3_ck",
  71         "abe_giclk_div",
  72         "video1_div_clk",
  73         "video2_div_clk",
  74         "hdmi_div_clk",
  75         "clkoutmux0_clk_mux",
  76         NULL,
  77 };
  78
  79 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
  80         { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  81         { 0 },
  82 };
  83
  84 static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
  85         { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  86         { 0 },
  87 };
  88
  89 static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
  90         { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  91         { 0 },
  92 };
  93
  94 static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
  95         { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  96         { 0 },
  97 };
  98
  99 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
 100         "func_48m_fclk",
 101         "dpll_per_m2x2_ck",
 102         NULL,
 103 };
 104
 105 static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
 106         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 107         { 0 },
 108 };
 109
 110 static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
 111         { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
 112         { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
 113         { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
 114         { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
 115         { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
 116         { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 117         { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
 118         { 0 },
 119 };
 120
 121 static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
 122         { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 123         { 0 },
 124 };
 125
 126 static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
 127         { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
 128         { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
 129         { 0 },
 130 };
 131
 132 static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
 133         { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 134         { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 135         { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
 136         { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 137         { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 138         { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 139         { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
 140         { 0 },
 141 };
 142
 143 static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
 144         { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 145         { 0 },
 146 };
 147
 148 static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
 149         { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 150         { 0 },
 151 };
 152
 153 static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
 154         "sys_32k_ck",
 155         "video1_clkin_ck",
 156         "video2_clkin_ck",
 157         "hdmi_clkin_ck",
 158         NULL,
 159 };
 160
 161 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
 162         "l3_iclk_div",
 163         "dpll_abe_m2_ck",
 164         "atl_cm:clk:0000:24",
 165         NULL,
 166 };
 167
 168 static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
 169         { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
 170         { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
 171         { 0 },
 172 };
 173
 174 static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
 175         { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
 176         { 0 },
 177 };
 178
 179 static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
 180         { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
 181         { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
 182         { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 183         { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
 184         { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
 185         { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
 186         { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
 187         { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
 188         { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
 189         { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
 190         { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
 191         { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
 192         { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
 193         { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
 194         { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
 195         { 0 },
 196 };
 197
 198 static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
 199         { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 200         { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 201         { 0 },
 202 };
 203
 204 static const char * const dra7_dss_dss_clk_parents[] __initconst = {
 205         "dpll_per_h12x2_ck",
 206         NULL,
 207 };
 208
 209 static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
 210         "func_48m_fclk",
 211         NULL,
 212 };
 213
 214 static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
 215         "hdmi_dpll_clk_mux",
 216         NULL,
 217 };
 218
 219 static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
 220         "sys_32k_ck",
 221         NULL,
 222 };
 223
 224 static const char * const dra7_dss_video1_clk_parents[] __initconst = {
 225         "video1_dpll_clk_mux",
 226         NULL,
 227 };
 228
 229 static const char * const dra7_dss_video2_clk_parents[] __initconst = {
 230         "video2_dpll_clk_mux",
 231         NULL,
 232 };
 233
 234 static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
 235         { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
 236         { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
 237         { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
 238         { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 239         { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
 240         { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
 241         { 0 },
 242 };
 243
 244 static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
 245         { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
 246         { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
 247         { 0 },
 248 };
 249
 250 static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
 251         "func_128m_clk",
 252         "dpll_per_m2x2_ck",
 253         NULL,
 254 };
 255
 256 static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
 257         "l3init_cm:clk:0008:24",
 258         NULL,
 259 };
 260
 261 static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
 262         .max_div = 4,
 263         .flags = CLK_DIVIDER_POWER_OF_TWO,
 264 };
 265
 266 static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
 267         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 268         { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
 269         { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
 270         { 0 },
 271 };
 272
 273 static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
 274         "l3init_cm:clk:0010:24",
 275         NULL,
 276 };
 277
 278 static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
 279         .max_div = 4,
 280         .flags = CLK_DIVIDER_POWER_OF_TWO,
 281 };
 282
 283 static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
 284         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 285         { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
 286         { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
 287         { 0 },
 288 };
 289
 290 static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
 291         "l3init_960m_gfclk",
 292         NULL,
 293 };
 294
 295 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
 296         { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
 297         { 0 },
 298 };
 299
 300 static const char * const dra7_sata_ref_clk_parents[] __initconst = {
 301         "sys_clkin1",
 302         NULL,
 303 };
 304
 305 static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
 306         { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
 307         { 0 },
 308 };
 309
 310 static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
 311         "apll_pcie_ck",
 312         NULL,
 313 };
 314
 315 static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
 316         "optfclk_pciephy_div",
 317         NULL,
 318 };
 319
 320 static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
 321         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 322         { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
 323         { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
 324         { 0 },
 325 };
 326
 327 static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
 328         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 329         { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
 330         { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
 331         { 0 },
 332 };
 333
 334 static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
 335         "dpll_gmac_h11x2_ck",
 336         "rmii_clk_ck",
 337         NULL,
 338 };
 339
 340 static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
 341         "video1_clkin_ck",
 342         "video2_clkin_ck",
 343         "dpll_abe_m2_ck",
 344         "hdmi_clkin_ck",
 345         "l3_iclk_div",
 346         NULL,
 347 };
 348
 349 static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
 350         { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
 351         { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
 352         { 0 },
 353 };
 354
 355 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
 356         { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
 357         { 0 },
 358 };
 359
 360 static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
 361         { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
 362         { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
 363         { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 364         { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 365         { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 366         { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
 367         { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
 368         { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
 369         { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
 370         { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 371         { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 372         { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 373         { 0 },
 374 };
 375
 376 static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
 377         "timer_sys_clk_div",
 378         "sys_32k_ck",
 379         "sys_clkin2",
 380         "ref_clkin0_ck",
 381         "ref_clkin1_ck",
 382         "ref_clkin2_ck",
 383         "ref_clkin3_ck",
 384         "abe_giclk_div",
 385         "video1_div_clk",
 386         "video2_div_clk",
 387         "hdmi_div_clk",
 388         NULL,
 389 };
 390
 391 static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
 392         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 393         { 0 },
 394 };
 395
 396 static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
 397         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 398         { 0 },
 399 };
 400
 401 static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
 402         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 403         { 0 },
 404 };
 405
 406 static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
 407         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 408         { 0 },
 409 };
 410
 411 static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
 412         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 413         { 0 },
 414 };
 415
 416 static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
 417         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 418         { 0 },
 419 };
 420
 421 static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
 422         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 423         { 0 },
 424 };
 425
 426 static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
 427         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 428         { 0 },
 429 };
 430
 431 static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
 432         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 433         { 0 },
 434 };
 435
 436 static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
 437         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 438         { 0 },
 439 };
 440
 441 static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
 442         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 443         { 0 },
 444 };
 445
 446 static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
 447         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 448         { 0 },
 449 };
 450
 451 static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
 452         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 453         { 0 },
 454 };
 455
 456 static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
 457         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 458         { 0 },
 459 };
 460
 461 static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
 462         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 463         { 0 },
 464 };
 465
 466 static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
 467         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 468         { 0 },
 469 };
 470
 471 static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
 472         "l4per_cm:clk:0120:24",
 473         NULL,
 474 };
 475
 476 static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
 477         .max_div = 4,
 478         .flags = CLK_DIVIDER_POWER_OF_TWO,
 479 };
 480
 481 static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
 482         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 483         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 484         { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
 485         { 0 },
 486 };
 487
 488 static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
 489         "l4per_cm:clk:0128:24",
 490         NULL,
 491 };
 492
 493 static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
 494         .max_div = 4,
 495         .flags = CLK_DIVIDER_POWER_OF_TWO,
 496 };
 497
 498 static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
 499         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 500         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 501         { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
 502         { 0 },
 503 };
 504
 505 static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
 506         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 507         { 0 },
 508 };
 509
 510 static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
 511         "func_128m_clk",
 512         "dpll_per_h13x2_ck",
 513         NULL,
 514 };
 515
 516 static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
 517         "l4per_cm:clk:0138:24",
 518         NULL,
 519 };
 520
 521 static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
 522         .max_div = 4,
 523         .flags = CLK_DIVIDER_POWER_OF_TWO,
 524 };
 525
 526 static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
 527         { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
 528         { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
 529         { 0 },
 530 };
 531
 532 static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
 533         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 534         { 0 },
 535 };
 536
 537 static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
 538         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 539         { 0 },
 540 };
 541
 542 static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
 543         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 544         { 0 },
 545 };
 546
 547 static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
 548         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 549         { 0 },
 550 };
 551
 552 static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
 553         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 554         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 555         { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 556         { 0 },
 557 };
 558
 559 static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
 560         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 561         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 562         { 0 },
 563 };
 564
 565 static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
 566         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 567         { 0 },
 568 };
 569
 570 static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
 571         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 572         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 573         { 0 },
 574 };
 575
 576 static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
 577         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 578         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 579         { 0 },
 580 };
 581
 582 static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
 583         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 584         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 585         { 0 },
 586 };
 587
 588 static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
 589         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 590         { 0 },
 591 };
 592
 593 static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
 594         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 595         { 0 },
 596 };
 597
 598 static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
 599         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 600         { 0 },
 601 };
 602
 603 static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
 604         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 605         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 606         { 0 },
 607 };
 608
 609 static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
 610         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 611         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 612         { 0 },
 613 };
 614
 615 static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
 616         { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
 617         { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
 618         { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
 619         { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
 620         { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
 621         { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
 622         { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
 623         { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
 624         { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 625         { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 626         { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 627         { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 628         { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 629         { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 630         { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
 631         { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
 632         { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
 633         { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 634         { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 635         { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 636         { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 637         { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 638         { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
 639         { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
 640         { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
 641         { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
 642         { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 643         { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 644         { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 645         { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 646         { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 647         { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 648         { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
 649         { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
 650         { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
 651         { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
 652         { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
 653         { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
 654         { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
 655         { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
 656         { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
 657         { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
 658         { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
 659         { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
 660         { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
 661         { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
 662         { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
 663         { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
 664         { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
 665         { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
 666         { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
 667         { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
 668         { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
 669         { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
 670         { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
 671         { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
 672         { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
 673         { 0 },
 674 };
 675
 676 static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
 677         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 678         { 0 },
 679 };
 680
 681 static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
 682         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 683         { 0 },
 684 };
 685
 686 static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
 687         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 688         { 0 },
 689 };
 690
 691 static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
 692         "sys_clkin1",
 693         "sys_clkin2",
 694         NULL,
 695 };
 696
 697 static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
 698         { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
 699         { 0 },
 700 };
 701
 702 static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
 703         { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 704         { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 705         { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
 706         { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
 707         { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
 708         { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 709         { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
 710         { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
 711         { 0 },
 712 };
 713
 714 const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
 715         { 0x4a005320, dra7_mpu_clkctrl_regs },
 716         { 0x4a005540, dra7_ipu_clkctrl_regs },
 717         { 0x4a005740, dra7_rtc_clkctrl_regs },
 718         { 0x4a008620, dra7_coreaon_clkctrl_regs },
 719         { 0x4a008720, dra7_l3main1_clkctrl_regs },
 720         { 0x4a008a20, dra7_dma_clkctrl_regs },
 721         { 0x4a008b20, dra7_emif_clkctrl_regs },
 722         { 0x4a008c00, dra7_atl_clkctrl_regs },
 723         { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
 724         { 0x4a008e20, dra7_l3instr_clkctrl_regs },
 725         { 0x4a009120, dra7_dss_clkctrl_regs },
 726         { 0x4a009320, dra7_l3init_clkctrl_regs },
 727         { 0x4a009700, dra7_l4per_clkctrl_regs },
 728         { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
 729         { 0 },
 730 };
 731
 732 static struct ti_dt_clk dra7xx_clks[] = {
 733         DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
 734         DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
 735         DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
 736         DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
 737         DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
 738         DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
 739         DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
 740         DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
 741         DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
 742         DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
 743         DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
 744         DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
 745         DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
 746         DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
 747         DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
 748         DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
 749         DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
 750         DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
 751         DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
 752         DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
 753         DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
 754         DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
 755         DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
 756         DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
 757         DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
 758         DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
 759         DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
 760         DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
 761         DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
 762         DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
 763         DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
 764         DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
 765         DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
 766         DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
 767         DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
 768         DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
 769         DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
 770         DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
 771         DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
 772         DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
 773         DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
 774         DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
 775         DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
 776         DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
 777         DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
 778         DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
 779         DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
 780         DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
 781         DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
 782         DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
 783         DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
 784         DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
 785         DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
 786         DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
 787         DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
 788         DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
 789         DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
 790         DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
 791         DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
 792         DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
 793         DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
 794         DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
 795         DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
 796         DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
 797         DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
 798         DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
 799         DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
 800         DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
 801         DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
 802         DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
 803         DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
 804         DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
 805         DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
 806         DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
 807         DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
 808         DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
 809         DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
 810         DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
 811         DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
 812         DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
 813         DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
 814         DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
 815         DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
 816         DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
 817         DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
 818         DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
 819         DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
 820         DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
 821         { .node_name = NULL },
 822 };
 823
 824 int __init dra7xx_dt_clk_init(void)
 825 {
 826         int rc;
 827         struct clk *dpll_ck, *hdcp_ck;
 828
 829         ti_dt_clocks_register(dra7xx_clks);
 830
 831         omap2_clk_disable_autoidle_all();
 832
 833         ti_clk_add_aliases();
 834
 835         dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
 836         rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
 837         if (rc)
 838                 pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
 839
 840         dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
 841         rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
 842         if (rc)
 843                 pr_err("%s: failed to configure USB DPLL!\n", __func__);
 844
 845         dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
 846         rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
 847         if (rc)
 848                 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 849
 850         hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
 851         rc = clk_prepare_enable(hdcp_ck);
 852         if (rc)
 853                 pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
 854
 855         return rc;
 856 }