drivers/clk/qcom/lcc-msm8960.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14
  15 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
  16
  17 #include "common.h"
  18 #include "clk-regmap.h"
  19 #include "clk-pll.h"
  20 #include "clk-rcg.h"
  21 #include "clk-branch.h"
  22 #include "clk-regmap-divider.h"
  23 #include "clk-regmap-mux.h"
  24
  25 static struct clk_parent_data pxo_parent_data = {
  26         .fw_name = "pxo", .name = "pxo_board",
  27 };
  28
  29 static struct clk_pll pll4 = {
  30         .l_reg = 0x4,
  31         .m_reg = 0x8,
  32         .n_reg = 0xc,
  33         .config_reg = 0x14,
  34         .mode_reg = 0x0,
  35         .status_reg = 0x18,
  36         .status_bit = 16,
  37         .clkr.hw.init = &(struct clk_init_data){
  38                 .name = "pll4",
  39                 .parent_data = &pxo_parent_data,
  40                 .num_parents = 1,
  41                 .ops = &clk_pll_ops,
  42         },
  43 };
  44
  45 enum {
  46         P_PXO,
  47         P_PLL4,
  48 };
  49
  50 static const struct parent_map lcc_pxo_pll4_map[] = {
  51         { P_PXO, 0 },
  52         { P_PLL4, 2 }
  53 };
  54
  55 static struct clk_parent_data lcc_pxo_pll4[] = {
  56         { .fw_name = "pxo", .name = "pxo_board" },
  57         { .fw_name = "pll4_vote", .name = "pll4_vote" },
  58 };
  59
  60 static struct freq_tbl clk_tbl_aif_osr_492[] = {
  61         {   512000, P_PLL4, 4, 1, 240 },
  62         {   768000, P_PLL4, 4, 1, 160 },
  63         {  1024000, P_PLL4, 4, 1, 120 },
  64         {  1536000, P_PLL4, 4, 1,  80 },
  65         {  2048000, P_PLL4, 4, 1,  60 },
  66         {  3072000, P_PLL4, 4, 1,  40 },
  67         {  4096000, P_PLL4, 4, 1,  30 },
  68         {  6144000, P_PLL4, 4, 1,  20 },
  69         {  8192000, P_PLL4, 4, 1,  15 },
  70         { 12288000, P_PLL4, 4, 1,  10 },
  71         { 24576000, P_PLL4, 4, 1,   5 },
  72         { 27000000, P_PXO,  1, 0,   0 },
  73         { }
  74 };
  75
  76 static struct freq_tbl clk_tbl_aif_osr_393[] = {
  77         {   512000, P_PLL4, 4, 1, 192 },
  78         {   768000, P_PLL4, 4, 1, 128 },
  79         {  1024000, P_PLL4, 4, 1,  96 },
  80         {  1536000, P_PLL4, 4, 1,  64 },
  81         {  2048000, P_PLL4, 4, 1,  48 },
  82         {  3072000, P_PLL4, 4, 1,  32 },
  83         {  4096000, P_PLL4, 4, 1,  24 },
  84         {  6144000, P_PLL4, 4, 1,  16 },
  85         {  8192000, P_PLL4, 4, 1,  12 },
  86         { 12288000, P_PLL4, 4, 1,   8 },
  87         { 24576000, P_PLL4, 4, 1,   4 },
  88         { 27000000, P_PXO,  1, 0,   0 },
  89         { }
  90 };
  91
  92 #define CLK_AIF_OSR_SRC(prefix, _ns, _md)                       \
  93 static struct clk_rcg prefix##_osr_src = {                      \
  94         .ns_reg = _ns,                                          \
  95         .md_reg = _md,                                          \
  96         .mn = {                                                 \
  97                 .mnctr_en_bit = 8,                              \
  98                 .mnctr_reset_bit = 7,                           \
  99                 .mnctr_mode_shift = 5,                          \
 100                 .n_val_shift = 24,                              \
 101                 .m_val_shift = 8,                               \
 102                 .width = 8,                                     \
 103         },                                                      \
 104         .p = {                                                  \
 105                 .pre_div_shift = 3,                             \
 106                 .pre_div_width = 2,                             \
 107         },                                                      \
 108         .s = {                                                  \
 109                 .src_sel_shift = 0,                             \
 110                 .parent_map = lcc_pxo_pll4_map,                 \
 111         },                                                      \
 112         .freq_tbl = clk_tbl_aif_osr_393,                        \
 113         .clkr = {                                               \
 114                 .enable_reg = _ns,                              \
 115                 .enable_mask = BIT(9),                          \
 116                 .hw.init = &(struct clk_init_data){             \
 117                         .name = #prefix "_osr_src",             \
 118                         .parent_data = lcc_pxo_pll4,            \
 119                         .num_parents = ARRAY_SIZE(lcc_pxo_pll4), \
 120                         .ops = &clk_rcg_ops,                    \
 121                         .flags = CLK_SET_RATE_GATE,             \
 122                 },                                              \
 123         },                                                      \
 124 };                                                              \
 125
 126 #define CLK_AIF_OSR_CLK(prefix, _ns, hr, en_bit)                \
 127 static struct clk_branch prefix##_osr_clk = {                   \
 128         .halt_reg = hr,                                         \
 129         .halt_bit = 1,                                          \
 130         .halt_check = BRANCH_HALT_ENABLE,                       \
 131         .clkr = {                                               \
 132                 .enable_reg = _ns,                              \
 133                 .enable_mask = BIT(en_bit),                     \
 134                 .hw.init = &(struct clk_init_data){             \
 135                         .name = #prefix "_osr_clk",             \
 136                         .parent_hws = (const struct clk_hw*[]){ \
 137                                 &prefix##_osr_src.clkr.hw,      \
 138                         },                                      \
 139                         .num_parents = 1,                       \
 140                         .ops = &clk_branch_ops,                 \
 141                         .flags = CLK_SET_RATE_PARENT,           \
 142                 },                                              \
 143         },                                                      \
 144 };                                                              \
 145
 146 #define CLK_AIF_OSR_DIV_CLK(prefix, _ns, _width)                \
 147 static struct clk_regmap_div prefix##_div_clk = {               \
 148         .reg = _ns,                                             \
 149         .shift = 10,                                            \
 150         .width = _width,                                        \
 151         .clkr = {                                               \
 152                 .hw.init = &(struct clk_init_data){             \
 153                         .name = #prefix "_div_clk",             \
 154                         .parent_hws = (const struct clk_hw*[]){ \
 155                                 &prefix##_osr_src.clkr.hw,      \
 156                         },                                      \
 157                         .num_parents = 1,                       \
 158                         .ops = &clk_regmap_div_ops,             \
 159                 },                                              \
 160         },                                                      \
 161 };                                                              \
 162
 163 #define CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, en_bit)        \
 164 static struct clk_branch prefix##_bit_div_clk = {               \
 165         .halt_reg = hr,                                         \
 166         .halt_bit = 0,                                          \
 167         .halt_check = BRANCH_HALT_ENABLE,                       \
 168         .clkr = {                                               \
 169                 .enable_reg = _ns,                              \
 170                 .enable_mask = BIT(en_bit),                     \
 171                 .hw.init = &(struct clk_init_data){             \
 172                         .name = #prefix "_bit_div_clk",         \
 173                         .parent_hws = (const struct clk_hw*[]){ \
 174                                 &prefix##_div_clk.clkr.hw,      \
 175                         },                                      \
 176                         .num_parents = 1,                       \
 177                         .ops = &clk_branch_ops,                 \
 178                         .flags = CLK_SET_RATE_PARENT,           \
 179                 },                                              \
 180         },                                                      \
 181 };                                                              \
 182
 183 #define CLK_AIF_OSR_BIT_CLK(prefix, _ns, _shift)                \
 184 static struct clk_regmap_mux prefix##_bit_clk = {               \
 185         .reg = _ns,                                             \
 186         .shift = _shift,                                        \
 187         .width = 1,                                             \
 188         .clkr = {                                               \
 189                 .hw.init = &(struct clk_init_data){             \
 190                         .name = #prefix "_bit_clk",             \
 191                         .parent_data = (const struct clk_parent_data[]){ \
 192                                 { .hw = &prefix##_bit_div_clk.clkr.hw, }, \
 193                                 { .fw_name = #prefix "_codec_clk", \
 194                                   .name = #prefix "_codec_clk", }, \
 195                         },                                      \
 196                         .num_parents = 2,                       \
 197                         .ops = &clk_regmap_mux_closest_ops,     \
 198                         .flags = CLK_SET_RATE_PARENT,           \
 199                 },                                              \
 200         },                                                      \
 201 };
 202
 203 CLK_AIF_OSR_SRC(mi2s, 0x48, 0x4c)
 204 CLK_AIF_OSR_CLK(mi2s, 0x48, 0x50, 17)
 205 CLK_AIF_OSR_DIV_CLK(mi2s, 0x48, 4)
 206 CLK_AIF_OSR_BIT_DIV_CLK(mi2s, 0x48, 0x50, 15)
 207 CLK_AIF_OSR_BIT_CLK(mi2s, 0x48, 14)
 208
 209 #define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr)                   \
 210         CLK_AIF_OSR_SRC(prefix, _ns, _md)                       \
 211         CLK_AIF_OSR_CLK(prefix, _ns, hr, 21)                    \
 212         CLK_AIF_OSR_DIV_CLK(prefix, _ns, 8)                     \
 213         CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, 19)            \
 214         CLK_AIF_OSR_BIT_CLK(prefix, _ns, 18)
 215
 216 CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
 217 CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
 218 CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
 219 CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
 220
 221 static struct freq_tbl clk_tbl_pcm_492[] = {
 222         {   256000, P_PLL4, 4, 1, 480 },
 223         {   512000, P_PLL4, 4, 1, 240 },
 224         {   768000, P_PLL4, 4, 1, 160 },
 225         {  1024000, P_PLL4, 4, 1, 120 },
 226         {  1536000, P_PLL4, 4, 1,  80 },
 227         {  2048000, P_PLL4, 4, 1,  60 },
 228         {  3072000, P_PLL4, 4, 1,  40 },
 229         {  4096000, P_PLL4, 4, 1,  30 },
 230         {  6144000, P_PLL4, 4, 1,  20 },
 231         {  8192000, P_PLL4, 4, 1,  15 },
 232         { 12288000, P_PLL4, 4, 1,  10 },
 233         { 24576000, P_PLL4, 4, 1,   5 },
 234         { 27000000, P_PXO,  1, 0,   0 },
 235         { }
 236 };
 237
 238 static struct freq_tbl clk_tbl_pcm_393[] = {
 239         {   256000, P_PLL4, 4, 1, 384 },
 240         {   512000, P_PLL4, 4, 1, 192 },
 241         {   768000, P_PLL4, 4, 1, 128 },
 242         {  1024000, P_PLL4, 4, 1,  96 },
 243         {  1536000, P_PLL4, 4, 1,  64 },
 244         {  2048000, P_PLL4, 4, 1,  48 },
 245         {  3072000, P_PLL4, 4, 1,  32 },
 246         {  4096000, P_PLL4, 4, 1,  24 },
 247         {  6144000, P_PLL4, 4, 1,  16 },
 248         {  8192000, P_PLL4, 4, 1,  12 },
 249         { 12288000, P_PLL4, 4, 1,   8 },
 250         { 24576000, P_PLL4, 4, 1,   4 },
 251         { 27000000, P_PXO,  1, 0,   0 },
 252         { }
 253 };
 254
 255 static struct clk_rcg pcm_src = {
 256         .ns_reg = 0x54,
 257         .md_reg = 0x58,
 258         .mn = {
 259                 .mnctr_en_bit = 8,
 260                 .mnctr_reset_bit = 7,
 261                 .mnctr_mode_shift = 5,
 262                 .n_val_shift = 16,
 263                 .m_val_shift = 16,
 264                 .width = 16,
 265         },
 266         .p = {
 267                 .pre_div_shift = 3,
 268                 .pre_div_width = 2,
 269         },
 270         .s = {
 271                 .src_sel_shift = 0,
 272                 .parent_map = lcc_pxo_pll4_map,
 273         },
 274         .freq_tbl = clk_tbl_pcm_393,
 275         .clkr = {
 276                 .enable_reg = 0x54,
 277                 .enable_mask = BIT(9),
 278                 .hw.init = &(struct clk_init_data){
 279                         .name = "pcm_src",
 280                         .parent_data = lcc_pxo_pll4,
 281                         .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
 282                         .ops = &clk_rcg_ops,
 283                         .flags = CLK_SET_RATE_GATE,
 284                 },
 285         },
 286 };
 287
 288 static struct clk_branch pcm_clk_out = {
 289         .halt_reg = 0x5c,
 290         .halt_bit = 0,
 291         .halt_check = BRANCH_HALT_ENABLE,
 292         .clkr = {
 293                 .enable_reg = 0x54,
 294                 .enable_mask = BIT(11),
 295                 .hw.init = &(struct clk_init_data){
 296                         .name = "pcm_clk_out",
 297                         .parent_hws = (const struct clk_hw*[]){
 298                                 &pcm_src.clkr.hw
 299                         },
 300                         .num_parents = 1,
 301                         .ops = &clk_branch_ops,
 302                         .flags = CLK_SET_RATE_PARENT,
 303                 },
 304         },
 305 };
 306
 307 static struct clk_regmap_mux pcm_clk = {
 308         .reg = 0x54,
 309         .shift = 10,
 310         .width = 1,
 311         .clkr = {
 312                 .hw.init = &(struct clk_init_data){
 313                         .name = "pcm_clk",
 314                         .parent_data = (const struct clk_parent_data[]){
 315                                 { .hw = &pcm_clk_out.clkr.hw },
 316                                 { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
 317                         },
 318                         .num_parents = 2,
 319                         .ops = &clk_regmap_mux_closest_ops,
 320                         .flags = CLK_SET_RATE_PARENT,
 321                 },
 322         },
 323 };
 324
 325 static struct clk_rcg slimbus_src = {
 326         .ns_reg = 0xcc,
 327         .md_reg = 0xd0,
 328         .mn = {
 329                 .mnctr_en_bit = 8,
 330                 .mnctr_reset_bit = 7,
 331                 .mnctr_mode_shift = 5,
 332                 .n_val_shift = 24,
 333                 .m_val_shift = 8,
 334                 .width = 8,
 335         },
 336         .p = {
 337                 .pre_div_shift = 3,
 338                 .pre_div_width = 2,
 339         },
 340         .s = {
 341                 .src_sel_shift = 0,
 342                 .parent_map = lcc_pxo_pll4_map,
 343         },
 344         .freq_tbl = clk_tbl_aif_osr_393,
 345         .clkr = {
 346                 .enable_reg = 0xcc,
 347                 .enable_mask = BIT(9),
 348                 .hw.init = &(struct clk_init_data){
 349                         .name = "slimbus_src",
 350                         .parent_data = lcc_pxo_pll4,
 351                         .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
 352                         .ops = &clk_rcg_ops,
 353                         .flags = CLK_SET_RATE_GATE,
 354                 },
 355         },
 356 };
 357
 358 static struct clk_branch audio_slimbus_clk = {
 359         .halt_reg = 0xd4,
 360         .halt_bit = 0,
 361         .halt_check = BRANCH_HALT_ENABLE,
 362         .clkr = {
 363                 .enable_reg = 0xcc,
 364                 .enable_mask = BIT(10),
 365                 .hw.init = &(struct clk_init_data){
 366                         .name = "audio_slimbus_clk",
 367                         .parent_hws = (const struct clk_hw*[]){
 368                                 &slimbus_src.clkr.hw,
 369                         },
 370                         .num_parents = 1,
 371                         .ops = &clk_branch_ops,
 372                         .flags = CLK_SET_RATE_PARENT,
 373                 },
 374         },
 375 };
 376
 377 static struct clk_branch sps_slimbus_clk = {
 378         .halt_reg = 0xd4,
 379         .halt_bit = 1,
 380         .halt_check = BRANCH_HALT_ENABLE,
 381         .clkr = {
 382                 .enable_reg = 0xcc,
 383                 .enable_mask = BIT(12),
 384                 .hw.init = &(struct clk_init_data){
 385                         .name = "sps_slimbus_clk",
 386                         .parent_hws = (const struct clk_hw*[]){
 387                                 &slimbus_src.clkr.hw,
 388                         },
 389                         .num_parents = 1,
 390                         .ops = &clk_branch_ops,
 391                         .flags = CLK_SET_RATE_PARENT,
 392                 },
 393         },
 394 };
 395
 396 static struct clk_regmap *lcc_msm8960_clks[] = {
 397         [PLL4] = &pll4.clkr,
 398         [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
 399         [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
 400         [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
 401         [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
 402         [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
 403         [PCM_SRC] = &pcm_src.clkr,
 404         [PCM_CLK_OUT] = &pcm_clk_out.clkr,
 405         [PCM_CLK] = &pcm_clk.clkr,
 406         [SLIMBUS_SRC] = &slimbus_src.clkr,
 407         [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
 408         [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
 409         [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
 410         [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
 411         [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
 412         [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
 413         [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
 414         [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
 415         [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
 416         [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
 417         [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
 418         [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
 419         [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
 420         [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
 421         [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
 422         [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
 423         [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
 424         [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
 425         [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
 426         [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
 427         [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
 428         [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
 429 };
 430
 431 static const struct regmap_config lcc_msm8960_regmap_config = {
 432         .reg_bits       = 32,
 433         .reg_stride     = 4,
 434         .val_bits       = 32,
 435         .max_register   = 0xfc,
 436         .fast_io        = true,
 437 };
 438
 439 static const struct qcom_cc_desc lcc_msm8960_desc = {
 440         .config = &lcc_msm8960_regmap_config,
 441         .clks = lcc_msm8960_clks,
 442         .num_clks = ARRAY_SIZE(lcc_msm8960_clks),
 443 };
 444
 445 static const struct of_device_id lcc_msm8960_match_table[] = {
 446         { .compatible = "qcom,lcc-msm8960" },
 447         { .compatible = "qcom,lcc-apq8064" },
 448         { .compatible = "qcom,lcc-mdm9615" },
 449         { }
 450 };
 451 MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
 452
 453 static int lcc_msm8960_probe(struct platform_device *pdev)
 454 {
 455         u32 val;
 456         struct regmap *regmap;
 457
 458         /* patch for the cxo <-> pxo difference */
 459         if (of_device_is_compatible(pdev->dev.of_node, "qcom,lcc-mdm9615")) {
 460                 pxo_parent_data.fw_name = "cxo";
 461                 pxo_parent_data.name = "cxo_board";
 462                 lcc_pxo_pll4[0].fw_name = "cxo";
 463                 lcc_pxo_pll4[0].name = "cxo_board";
 464         }
 465
 466         regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
 467         if (IS_ERR(regmap))
 468                 return PTR_ERR(regmap);
 469
 470         /* Use the correct frequency plan depending on speed of PLL4 */
 471         regmap_read(regmap, 0x4, &val);
 472         if (val == 0x12) {
 473                 slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
 474                 mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
 475                 codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
 476                 spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
 477                 codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
 478                 spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
 479                 pcm_src.freq_tbl = clk_tbl_pcm_492;
 480         }
 481         /* Enable PLL4 source on the LPASS Primary PLL Mux */
 482         regmap_write(regmap, 0xc4, 0x1);
 483
 484         return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
 485 }
 486
 487 static struct platform_driver lcc_msm8960_driver = {
 488         .probe          = lcc_msm8960_probe,
 489         .driver         = {
 490                 .name   = "lcc-msm8960",
 491                 .of_match_table = lcc_msm8960_match_table,
 492         },
 493 };
 494 module_platform_driver(lcc_msm8960_driver);
 495
 496 MODULE_DESCRIPTION("QCOM LCC MSM8960 Driver");
 497 MODULE_LICENSE("GPL v2");
 498 MODULE_ALIAS("platform:lcc-msm8960");