drivers/clk/qcom/gcc-msm8996.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  26
  27 #include "common.h"
  28 #include "clk-regmap.h"
  29 #include "clk-alpha-pll.h"
  30 #include "clk-rcg.h"
  31 #include "clk-branch.h"
  32 #include "reset.h"
  33 #include "gdsc.h"
  34
  35 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  36
  37 enum {
  38         P_XO,
  39         P_GPLL0,
  40         P_GPLL2,
  41         P_GPLL3,
  42         P_GPLL1,
  43         P_GPLL2_EARLY,
  44         P_GPLL0_EARLY_DIV,
  45         P_SLEEP_CLK,
  46         P_GPLL4,
  47         P_AUD_REF_CLK,
  48         P_GPLL1_EARLY_DIV
  49 };
  50
  51 static const struct parent_map gcc_sleep_clk_map[] = {
  52         { P_SLEEP_CLK, 5 }
  53 };
  54
  55 static const char * const gcc_sleep_clk[] = {
  56         "sleep_clk"
  57 };
  58
  59 static const struct parent_map gcc_xo_gpll0_map[] = {
  60         { P_XO, 0 },
  61         { P_GPLL0, 1 }
  62 };
  63
  64 static const char * const gcc_xo_gpll0[] = {
  65         "xo",
  66         "gpll0"
  67 };
  68
  69 static const struct parent_map gcc_xo_sleep_clk_map[] = {
  70         { P_XO, 0 },
  71         { P_SLEEP_CLK, 5 }
  72 };
  73
  74 static const char * const gcc_xo_sleep_clk[] = {
  75         "xo",
  76         "sleep_clk"
  77 };
  78
  79 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  80         { P_XO, 0 },
  81         { P_GPLL0, 1 },
  82         { P_GPLL0_EARLY_DIV, 6 }
  83 };
  84
  85 static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
  86         "xo",
  87         "gpll0",
  88         "gpll0_early_div"
  89 };
  90
  91 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  92         { P_XO, 0 },
  93         { P_GPLL0, 1 },
  94         { P_GPLL4, 5 }
  95 };
  96
  97 static const char * const gcc_xo_gpll0_gpll4[] = {
  98         "xo",
  99         "gpll0",
 100         "gpll4"
 101 };
 102
 103 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
 104         { P_XO, 0 },
 105         { P_GPLL0, 1 },
 106         { P_AUD_REF_CLK, 2 }
 107 };
 108
 109 static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
 110         "xo",
 111         "gpll0",
 112         "aud_ref_clk"
 113 };
 114
 115 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 116         { P_XO, 0 },
 117         { P_GPLL0, 1 },
 118         { P_SLEEP_CLK, 5 },
 119         { P_GPLL0_EARLY_DIV, 6 }
 120 };
 121
 122 static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
 123         "xo",
 124         "gpll0",
 125         "sleep_clk",
 126         "gpll0_early_div"
 127 };
 128
 129 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 130         { P_XO, 0 },
 131         { P_GPLL0, 1 },
 132         { P_GPLL4, 5 },
 133         { P_GPLL0_EARLY_DIV, 6 }
 134 };
 135
 136 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 137         "xo",
 138         "gpll0",
 139         "gpll4",
 140         "gpll0_early_div"
 141 };
 142
 143 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = {
 144         { P_XO, 0 },
 145         { P_GPLL0, 1 },
 146         { P_GPLL2, 2 },
 147         { P_GPLL3, 3 },
 148         { P_GPLL0_EARLY_DIV, 6 }
 149 };
 150
 151 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = {
 152         "xo",
 153         "gpll0",
 154         "gpll2",
 155         "gpll3",
 156         "gpll0_early_div"
 157 };
 158
 159 static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
 160         { P_XO, 0 },
 161         { P_GPLL0, 1 },
 162         { P_GPLL1_EARLY_DIV, 3 },
 163         { P_GPLL1, 4 },
 164         { P_GPLL4, 5 },
 165         { P_GPLL0_EARLY_DIV, 6 }
 166 };
 167
 168 static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
 169         "xo",
 170         "gpll0",
 171         "gpll1_early_div",
 172         "gpll1",
 173         "gpll4",
 174         "gpll0_early_div"
 175 };
 176
 177 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
 178         { P_XO, 0 },
 179         { P_GPLL0, 1 },
 180         { P_GPLL2, 2 },
 181         { P_GPLL3, 3 },
 182         { P_GPLL1, 4 },
 183         { P_GPLL2_EARLY, 5 },
 184         { P_GPLL0_EARLY_DIV, 6 }
 185 };
 186
 187 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
 188         "xo",
 189         "gpll0",
 190         "gpll2",
 191         "gpll3",
 192         "gpll1",
 193         "gpll2_early",
 194         "gpll0_early_div"
 195 };
 196
 197 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = {
 198         { P_XO, 0 },
 199         { P_GPLL0, 1 },
 200         { P_GPLL2, 2 },
 201         { P_GPLL3, 3 },
 202         { P_GPLL1, 4 },
 203         { P_GPLL4, 5 },
 204         { P_GPLL0_EARLY_DIV, 6 }
 205 };
 206
 207 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
 208         "xo",
 209         "gpll0",
 210         "gpll2",
 211         "gpll3",
 212         "gpll1",
 213         "gpll4",
 214         "gpll0_early_div"
 215 };
 216
 217 static struct clk_fixed_factor xo = {
 218         .mult = 1,
 219         .div = 1,
 220         .hw.init = &(struct clk_init_data){
 221                 .name = "xo",
 222                 .parent_names = (const char *[]){ "xo_board" },
 223                 .num_parents = 1,
 224                 .ops = &clk_fixed_factor_ops,
 225         },
 226 };
 227
 228 static struct clk_alpha_pll gpll0_early = {
 229         .offset = 0x00000,
 230         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 231         .clkr = {
 232                 .enable_reg = 0x52000,
 233                 .enable_mask = BIT(0),
 234                 .hw.init = &(struct clk_init_data){
 235                         .name = "gpll0_early",
 236                         .parent_names = (const char *[]){ "xo" },
 237                         .num_parents = 1,
 238                         .ops = &clk_alpha_pll_ops,
 239                 },
 240         },
 241 };
 242
 243 static struct clk_fixed_factor gpll0_early_div = {
 244         .mult = 1,
 245         .div = 2,
 246         .hw.init = &(struct clk_init_data){
 247                 .name = "gpll0_early_div",
 248                 .parent_names = (const char *[]){ "gpll0_early" },
 249                 .num_parents = 1,
 250                 .ops = &clk_fixed_factor_ops,
 251         },
 252 };
 253
 254 static struct clk_alpha_pll_postdiv gpll0 = {
 255         .offset = 0x00000,
 256         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 257         .clkr.hw.init = &(struct clk_init_data){
 258                 .name = "gpll0",
 259                 .parent_names = (const char *[]){ "gpll0_early" },
 260                 .num_parents = 1,
 261                 .ops = &clk_alpha_pll_postdiv_ops,
 262         },
 263 };
 264
 265 static struct clk_alpha_pll gpll4_early = {
 266         .offset = 0x77000,
 267         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 268         .clkr = {
 269                 .enable_reg = 0x52000,
 270                 .enable_mask = BIT(4),
 271                 .hw.init = &(struct clk_init_data){
 272                         .name = "gpll4_early",
 273                         .parent_names = (const char *[]){ "xo" },
 274                         .num_parents = 1,
 275                         .ops = &clk_alpha_pll_ops,
 276                 },
 277         },
 278 };
 279
 280 static struct clk_alpha_pll_postdiv gpll4 = {
 281         .offset = 0x77000,
 282         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 283         .clkr.hw.init = &(struct clk_init_data){
 284                 .name = "gpll4",
 285                 .parent_names = (const char *[]){ "gpll4_early" },
 286                 .num_parents = 1,
 287                 .ops = &clk_alpha_pll_postdiv_ops,
 288         },
 289 };
 290
 291 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 292         F(19200000, P_XO, 1, 0, 0),
 293         F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
 294         F(100000000, P_GPLL0, 6, 0, 0),
 295         F(150000000, P_GPLL0, 4, 0, 0),
 296         F(200000000, P_GPLL0, 3, 0, 0),
 297         F(240000000, P_GPLL0, 2.5, 0, 0),
 298         { }
 299 };
 300
 301 static struct clk_rcg2 system_noc_clk_src = {
 302         .cmd_rcgr = 0x0401c,
 303         .hid_width = 5,
 304         .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
 305         .freq_tbl = ftbl_system_noc_clk_src,
 306         .clkr.hw.init = &(struct clk_init_data){
 307                 .name = "system_noc_clk_src",
 308                 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
 309                 .num_parents = 7,
 310                 .ops = &clk_rcg2_ops,
 311         },
 312 };
 313
 314 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
 315         F(19200000, P_XO, 1, 0, 0),
 316         F(37500000, P_GPLL0, 16, 0, 0),
 317         F(75000000, P_GPLL0, 8, 0, 0),
 318         { }
 319 };
 320
 321 static struct clk_rcg2 config_noc_clk_src = {
 322         .cmd_rcgr = 0x0500c,
 323         .hid_width = 5,
 324         .parent_map = gcc_xo_gpll0_map,
 325         .freq_tbl = ftbl_config_noc_clk_src,
 326         .clkr.hw.init = &(struct clk_init_data){
 327                 .name = "config_noc_clk_src",
 328                 .parent_names = gcc_xo_gpll0,
 329                 .num_parents = 2,
 330                 .ops = &clk_rcg2_ops,
 331         },
 332 };
 333
 334 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
 335         F(19200000, P_XO, 1, 0, 0),
 336         F(37500000, P_GPLL0, 16, 0, 0),
 337         F(50000000, P_GPLL0, 12, 0, 0),
 338         F(75000000, P_GPLL0, 8, 0, 0),
 339         F(100000000, P_GPLL0, 6, 0, 0),
 340         { }
 341 };
 342
 343 static struct clk_rcg2 periph_noc_clk_src = {
 344         .cmd_rcgr = 0x06014,
 345         .hid_width = 5,
 346         .parent_map = gcc_xo_gpll0_map,
 347         .freq_tbl = ftbl_periph_noc_clk_src,
 348         .clkr.hw.init = &(struct clk_init_data){
 349                 .name = "periph_noc_clk_src",
 350                 .parent_names = gcc_xo_gpll0,
 351                 .num_parents = 2,
 352                 .ops = &clk_rcg2_ops,
 353         },
 354 };
 355
 356 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
 357         F(19200000, P_XO, 1, 0, 0),
 358         F(120000000, P_GPLL0, 5, 0, 0),
 359         F(150000000, P_GPLL0, 4, 0, 0),
 360         { }
 361 };
 362
 363 static struct clk_rcg2 usb30_master_clk_src = {
 364         .cmd_rcgr = 0x0f014,
 365         .mnd_width = 8,
 366         .hid_width = 5,
 367         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 368         .freq_tbl = ftbl_usb30_master_clk_src,
 369         .clkr.hw.init = &(struct clk_init_data){
 370                 .name = "usb30_master_clk_src",
 371                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 372                 .num_parents = 3,
 373                 .ops = &clk_rcg2_ops,
 374         },
 375 };
 376
 377 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 378         F(19200000, P_XO, 1, 0, 0),
 379         { }
 380 };
 381
 382 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 383         .cmd_rcgr = 0x0f028,
 384         .hid_width = 5,
 385         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 386         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 387         .clkr.hw.init = &(struct clk_init_data){
 388                 .name = "usb30_mock_utmi_clk_src",
 389                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 390                 .num_parents = 3,
 391                 .ops = &clk_rcg2_ops,
 392         },
 393 };
 394
 395 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
 396         F(1200000, P_XO, 16, 0, 0),
 397         { }
 398 };
 399
 400 static struct clk_rcg2 usb3_phy_aux_clk_src = {
 401         .cmd_rcgr = 0x5000c,
 402         .hid_width = 5,
 403         .parent_map = gcc_xo_sleep_clk_map,
 404         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
 405         .clkr.hw.init = &(struct clk_init_data){
 406                 .name = "usb3_phy_aux_clk_src",
 407                 .parent_names = gcc_xo_sleep_clk,
 408                 .num_parents = 2,
 409                 .ops = &clk_rcg2_ops,
 410         },
 411 };
 412
 413 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
 414         F(120000000, P_GPLL0, 5, 0, 0),
 415         { }
 416 };
 417
 418 static struct clk_rcg2 usb20_master_clk_src = {
 419         .cmd_rcgr = 0x12010,
 420         .mnd_width = 8,
 421         .hid_width = 5,
 422         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 423         .freq_tbl = ftbl_usb20_master_clk_src,
 424         .clkr.hw.init = &(struct clk_init_data){
 425                 .name = "usb20_master_clk_src",
 426                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 427                 .num_parents = 3,
 428                 .ops = &clk_rcg2_ops,
 429         },
 430 };
 431
 432 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 433         .cmd_rcgr = 0x12024,
 434         .hid_width = 5,
 435         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 436         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 437         .clkr.hw.init = &(struct clk_init_data){
 438                 .name = "usb20_mock_utmi_clk_src",
 439                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 440                 .num_parents = 3,
 441                 .ops = &clk_rcg2_ops,
 442         },
 443 };
 444
 445 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 446         F(144000, P_XO, 16, 3, 25),
 447         F(400000, P_XO, 12, 1, 4),
 448         F(20000000, P_GPLL0, 15, 1, 2),
 449         F(25000000, P_GPLL0, 12, 1, 2),
 450         F(50000000, P_GPLL0, 12, 0, 0),
 451         F(96000000, P_GPLL4, 4, 0, 0),
 452         F(192000000, P_GPLL4, 2, 0, 0),
 453         F(384000000, P_GPLL4, 1, 0, 0),
 454         { }
 455 };
 456
 457 static struct clk_rcg2 sdcc1_apps_clk_src = {
 458         .cmd_rcgr = 0x13010,
 459         .mnd_width = 8,
 460         .hid_width = 5,
 461         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 462         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 463         .clkr.hw.init = &(struct clk_init_data){
 464                 .name = "sdcc1_apps_clk_src",
 465                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 466                 .num_parents = 4,
 467                 .ops = &clk_rcg2_floor_ops,
 468         },
 469 };
 470
 471 static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
 472         F(19200000, P_XO, 1, 0, 0),
 473         F(150000000, P_GPLL0, 4, 0, 0),
 474         F(300000000, P_GPLL0, 2, 0, 0),
 475         { }
 476 };
 477
 478 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 479         .cmd_rcgr = 0x13024,
 480         .hid_width = 5,
 481         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 482         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 483         .clkr.hw.init = &(struct clk_init_data){
 484                 .name = "sdcc1_ice_core_clk_src",
 485                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 486                 .num_parents = 4,
 487                 .ops = &clk_rcg2_ops,
 488         },
 489 };
 490
 491 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
 492         F(144000, P_XO, 16, 3, 25),
 493         F(400000, P_XO, 12, 1, 4),
 494         F(20000000, P_GPLL0, 15, 1, 2),
 495         F(25000000, P_GPLL0, 12, 1, 2),
 496         F(50000000, P_GPLL0, 12, 0, 0),
 497         F(100000000, P_GPLL0, 6, 0, 0),
 498         F(200000000, P_GPLL0, 3, 0, 0),
 499         { }
 500 };
 501
 502 static struct clk_rcg2 sdcc2_apps_clk_src = {
 503         .cmd_rcgr = 0x14010,
 504         .mnd_width = 8,
 505         .hid_width = 5,
 506         .parent_map = gcc_xo_gpll0_gpll4_map,
 507         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 508         .clkr.hw.init = &(struct clk_init_data){
 509                 .name = "sdcc2_apps_clk_src",
 510                 .parent_names = gcc_xo_gpll0_gpll4,
 511                 .num_parents = 3,
 512                 .ops = &clk_rcg2_floor_ops,
 513         },
 514 };
 515
 516 static struct clk_rcg2 sdcc3_apps_clk_src = {
 517         .cmd_rcgr = 0x15010,
 518         .mnd_width = 8,
 519         .hid_width = 5,
 520         .parent_map = gcc_xo_gpll0_gpll4_map,
 521         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 522         .clkr.hw.init = &(struct clk_init_data){
 523                 .name = "sdcc3_apps_clk_src",
 524                 .parent_names = gcc_xo_gpll0_gpll4,
 525                 .num_parents = 3,
 526                 .ops = &clk_rcg2_floor_ops,
 527         },
 528 };
 529
 530 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
 531         F(144000, P_XO, 16, 3, 25),
 532         F(400000, P_XO, 12, 1, 4),
 533         F(20000000, P_GPLL0, 15, 1, 2),
 534         F(25000000, P_GPLL0, 12, 1, 2),
 535         F(50000000, P_GPLL0, 12, 0, 0),
 536         F(100000000, P_GPLL0, 6, 0, 0),
 537         { }
 538 };
 539
 540 static struct clk_rcg2 sdcc4_apps_clk_src = {
 541         .cmd_rcgr = 0x16010,
 542         .mnd_width = 8,
 543         .hid_width = 5,
 544         .parent_map = gcc_xo_gpll0_map,
 545         .freq_tbl = ftbl_sdcc4_apps_clk_src,
 546         .clkr.hw.init = &(struct clk_init_data){
 547                 .name = "sdcc4_apps_clk_src",
 548                 .parent_names = gcc_xo_gpll0,
 549                 .num_parents = 2,
 550                 .ops = &clk_rcg2_floor_ops,
 551         },
 552 };
 553
 554 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 555         F(960000, P_XO, 10, 1, 2),
 556         F(4800000, P_XO, 4, 0, 0),
 557         F(9600000, P_XO, 2, 0, 0),
 558         F(15000000, P_GPLL0, 10, 1, 4),
 559         F(19200000, P_XO, 1, 0, 0),
 560         F(25000000, P_GPLL0, 12, 1, 2),
 561         F(50000000, P_GPLL0, 12, 0, 0),
 562         { }
 563 };
 564
 565 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 566         .cmd_rcgr = 0x1900c,
 567         .mnd_width = 8,
 568         .hid_width = 5,
 569         .parent_map = gcc_xo_gpll0_map,
 570         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 571         .clkr.hw.init = &(struct clk_init_data){
 572                 .name = "blsp1_qup1_spi_apps_clk_src",
 573                 .parent_names = gcc_xo_gpll0,
 574                 .num_parents = 2,
 575                 .ops = &clk_rcg2_ops,
 576         },
 577 };
 578
 579 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 580         F(19200000, P_XO, 1, 0, 0),
 581         F(50000000, P_GPLL0, 12, 0, 0),
 582         { }
 583 };
 584
 585 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 586         .cmd_rcgr = 0x19020,
 587         .hid_width = 5,
 588         .parent_map = gcc_xo_gpll0_map,
 589         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 590         .clkr.hw.init = &(struct clk_init_data){
 591                 .name = "blsp1_qup1_i2c_apps_clk_src",
 592                 .parent_names = gcc_xo_gpll0,
 593                 .num_parents = 2,
 594                 .ops = &clk_rcg2_ops,
 595         },
 596 };
 597
 598 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 599         F(3686400, P_GPLL0, 1, 96, 15625),
 600         F(7372800, P_GPLL0, 1, 192, 15625),
 601         F(14745600, P_GPLL0, 1, 384, 15625),
 602         F(16000000, P_GPLL0, 5, 2, 15),
 603         F(19200000, P_XO, 1, 0, 0),
 604         F(24000000, P_GPLL0, 5, 1, 5),
 605         F(32000000, P_GPLL0, 1, 4, 75),
 606         F(40000000, P_GPLL0, 15, 0, 0),
 607         F(46400000, P_GPLL0, 1, 29, 375),
 608         F(48000000, P_GPLL0, 12.5, 0, 0),
 609         F(51200000, P_GPLL0, 1, 32, 375),
 610         F(56000000, P_GPLL0, 1, 7, 75),
 611         F(58982400, P_GPLL0, 1, 1536, 15625),
 612         F(60000000, P_GPLL0, 10, 0, 0),
 613         F(63157895, P_GPLL0, 9.5, 0, 0),
 614         { }
 615 };
 616
 617 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 618         .cmd_rcgr = 0x1a00c,
 619         .mnd_width = 16,
 620         .hid_width = 5,
 621         .parent_map = gcc_xo_gpll0_map,
 622         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 623         .clkr.hw.init = &(struct clk_init_data){
 624                 .name = "blsp1_uart1_apps_clk_src",
 625                 .parent_names = gcc_xo_gpll0,
 626                 .num_parents = 2,
 627                 .ops = &clk_rcg2_ops,
 628         },
 629 };
 630
 631 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 632         .cmd_rcgr = 0x1b00c,
 633         .mnd_width = 8,
 634         .hid_width = 5,
 635         .parent_map = gcc_xo_gpll0_map,
 636         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 637         .clkr.hw.init = &(struct clk_init_data){
 638                 .name = "blsp1_qup2_spi_apps_clk_src",
 639                 .parent_names = gcc_xo_gpll0,
 640                 .num_parents = 2,
 641                 .ops = &clk_rcg2_ops,
 642         },
 643 };
 644
 645 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 646         .cmd_rcgr = 0x1b020,
 647         .hid_width = 5,
 648         .parent_map = gcc_xo_gpll0_map,
 649         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 650         .clkr.hw.init = &(struct clk_init_data){
 651                 .name = "blsp1_qup2_i2c_apps_clk_src",
 652                 .parent_names = gcc_xo_gpll0,
 653                 .num_parents = 2,
 654                 .ops = &clk_rcg2_ops,
 655         },
 656 };
 657
 658 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 659         .cmd_rcgr = 0x1c00c,
 660         .mnd_width = 16,
 661         .hid_width = 5,
 662         .parent_map = gcc_xo_gpll0_map,
 663         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 664         .clkr.hw.init = &(struct clk_init_data){
 665                 .name = "blsp1_uart2_apps_clk_src",
 666                 .parent_names = gcc_xo_gpll0,
 667                 .num_parents = 2,
 668                 .ops = &clk_rcg2_ops,
 669         },
 670 };
 671
 672 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 673         .cmd_rcgr = 0x1d00c,
 674         .mnd_width = 8,
 675         .hid_width = 5,
 676         .parent_map = gcc_xo_gpll0_map,
 677         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 678         .clkr.hw.init = &(struct clk_init_data){
 679                 .name = "blsp1_qup3_spi_apps_clk_src",
 680                 .parent_names = gcc_xo_gpll0,
 681                 .num_parents = 2,
 682                 .ops = &clk_rcg2_ops,
 683         },
 684 };
 685
 686 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 687         .cmd_rcgr = 0x1d020,
 688         .hid_width = 5,
 689         .parent_map = gcc_xo_gpll0_map,
 690         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 691         .clkr.hw.init = &(struct clk_init_data){
 692                 .name = "blsp1_qup3_i2c_apps_clk_src",
 693                 .parent_names = gcc_xo_gpll0,
 694                 .num_parents = 2,
 695                 .ops = &clk_rcg2_ops,
 696         },
 697 };
 698
 699 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 700         .cmd_rcgr = 0x1e00c,
 701         .mnd_width = 16,
 702         .hid_width = 5,
 703         .parent_map = gcc_xo_gpll0_map,
 704         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 705         .clkr.hw.init = &(struct clk_init_data){
 706                 .name = "blsp1_uart3_apps_clk_src",
 707                 .parent_names = gcc_xo_gpll0,
 708                 .num_parents = 2,
 709                 .ops = &clk_rcg2_ops,
 710         },
 711 };
 712
 713 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 714         .cmd_rcgr = 0x1f00c,
 715         .mnd_width = 8,
 716         .hid_width = 5,
 717         .parent_map = gcc_xo_gpll0_map,
 718         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 719         .clkr.hw.init = &(struct clk_init_data){
 720                 .name = "blsp1_qup4_spi_apps_clk_src",
 721                 .parent_names = gcc_xo_gpll0,
 722                 .num_parents = 2,
 723                 .ops = &clk_rcg2_ops,
 724         },
 725 };
 726
 727 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 728         .cmd_rcgr = 0x1f020,
 729         .hid_width = 5,
 730         .parent_map = gcc_xo_gpll0_map,
 731         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 732         .clkr.hw.init = &(struct clk_init_data){
 733                 .name = "blsp1_qup4_i2c_apps_clk_src",
 734                 .parent_names = gcc_xo_gpll0,
 735                 .num_parents = 2,
 736                 .ops = &clk_rcg2_ops,
 737         },
 738 };
 739
 740 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 741         .cmd_rcgr = 0x2000c,
 742         .mnd_width = 16,
 743         .hid_width = 5,
 744         .parent_map = gcc_xo_gpll0_map,
 745         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 746         .clkr.hw.init = &(struct clk_init_data){
 747                 .name = "blsp1_uart4_apps_clk_src",
 748                 .parent_names = gcc_xo_gpll0,
 749                 .num_parents = 2,
 750                 .ops = &clk_rcg2_ops,
 751         },
 752 };
 753
 754 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 755         .cmd_rcgr = 0x2100c,
 756         .mnd_width = 8,
 757         .hid_width = 5,
 758         .parent_map = gcc_xo_gpll0_map,
 759         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 760         .clkr.hw.init = &(struct clk_init_data){
 761                 .name = "blsp1_qup5_spi_apps_clk_src",
 762                 .parent_names = gcc_xo_gpll0,
 763                 .num_parents = 2,
 764                 .ops = &clk_rcg2_ops,
 765         },
 766 };
 767
 768 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 769         .cmd_rcgr = 0x21020,
 770         .hid_width = 5,
 771         .parent_map = gcc_xo_gpll0_map,
 772         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 773         .clkr.hw.init = &(struct clk_init_data){
 774                 .name = "blsp1_qup5_i2c_apps_clk_src",
 775                 .parent_names = gcc_xo_gpll0,
 776                 .num_parents = 2,
 777                 .ops = &clk_rcg2_ops,
 778         },
 779 };
 780
 781 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 782         .cmd_rcgr = 0x2200c,
 783         .mnd_width = 16,
 784         .hid_width = 5,
 785         .parent_map = gcc_xo_gpll0_map,
 786         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 787         .clkr.hw.init = &(struct clk_init_data){
 788                 .name = "blsp1_uart5_apps_clk_src",
 789                 .parent_names = gcc_xo_gpll0,
 790                 .num_parents = 2,
 791                 .ops = &clk_rcg2_ops,
 792         },
 793 };
 794
 795 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 796         .cmd_rcgr = 0x2300c,
 797         .mnd_width = 8,
 798         .hid_width = 5,
 799         .parent_map = gcc_xo_gpll0_map,
 800         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "blsp1_qup6_spi_apps_clk_src",
 803                 .parent_names = gcc_xo_gpll0,
 804                 .num_parents = 2,
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 810         .cmd_rcgr = 0x23020,
 811         .hid_width = 5,
 812         .parent_map = gcc_xo_gpll0_map,
 813         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 814         .clkr.hw.init = &(struct clk_init_data){
 815                 .name = "blsp1_qup6_i2c_apps_clk_src",
 816                 .parent_names = gcc_xo_gpll0,
 817                 .num_parents = 2,
 818                 .ops = &clk_rcg2_ops,
 819         },
 820 };
 821
 822 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 823         .cmd_rcgr = 0x2400c,
 824         .mnd_width = 16,
 825         .hid_width = 5,
 826         .parent_map = gcc_xo_gpll0_map,
 827         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 828         .clkr.hw.init = &(struct clk_init_data){
 829                 .name = "blsp1_uart6_apps_clk_src",
 830                 .parent_names = gcc_xo_gpll0,
 831                 .num_parents = 2,
 832                 .ops = &clk_rcg2_ops,
 833         },
 834 };
 835
 836 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 837         .cmd_rcgr = 0x2600c,
 838         .mnd_width = 8,
 839         .hid_width = 5,
 840         .parent_map = gcc_xo_gpll0_map,
 841         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 842         .clkr.hw.init = &(struct clk_init_data){
 843                 .name = "blsp2_qup1_spi_apps_clk_src",
 844                 .parent_names = gcc_xo_gpll0,
 845                 .num_parents = 2,
 846                 .ops = &clk_rcg2_ops,
 847         },
 848 };
 849
 850 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 851         .cmd_rcgr = 0x26020,
 852         .hid_width = 5,
 853         .parent_map = gcc_xo_gpll0_map,
 854         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 855         .clkr.hw.init = &(struct clk_init_data){
 856                 .name = "blsp2_qup1_i2c_apps_clk_src",
 857                 .parent_names = gcc_xo_gpll0,
 858                 .num_parents = 2,
 859                 .ops = &clk_rcg2_ops,
 860         },
 861 };
 862
 863 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 864         .cmd_rcgr = 0x2700c,
 865         .mnd_width = 16,
 866         .hid_width = 5,
 867         .parent_map = gcc_xo_gpll0_map,
 868         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 869         .clkr.hw.init = &(struct clk_init_data){
 870                 .name = "blsp2_uart1_apps_clk_src",
 871                 .parent_names = gcc_xo_gpll0,
 872                 .num_parents = 2,
 873                 .ops = &clk_rcg2_ops,
 874         },
 875 };
 876
 877 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 878         .cmd_rcgr = 0x2800c,
 879         .mnd_width = 8,
 880         .hid_width = 5,
 881         .parent_map = gcc_xo_gpll0_map,
 882         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 883         .clkr.hw.init = &(struct clk_init_data){
 884                 .name = "blsp2_qup2_spi_apps_clk_src",
 885                 .parent_names = gcc_xo_gpll0,
 886                 .num_parents = 2,
 887                 .ops = &clk_rcg2_ops,
 888         },
 889 };
 890
 891 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 892         .cmd_rcgr = 0x28020,
 893         .hid_width = 5,
 894         .parent_map = gcc_xo_gpll0_map,
 895         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 896         .clkr.hw.init = &(struct clk_init_data){
 897                 .name = "blsp2_qup2_i2c_apps_clk_src",
 898                 .parent_names = gcc_xo_gpll0,
 899                 .num_parents = 2,
 900                 .ops = &clk_rcg2_ops,
 901         },
 902 };
 903
 904 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 905         .cmd_rcgr = 0x2900c,
 906         .mnd_width = 16,
 907         .hid_width = 5,
 908         .parent_map = gcc_xo_gpll0_map,
 909         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 910         .clkr.hw.init = &(struct clk_init_data){
 911                 .name = "blsp2_uart2_apps_clk_src",
 912                 .parent_names = gcc_xo_gpll0,
 913                 .num_parents = 2,
 914                 .ops = &clk_rcg2_ops,
 915         },
 916 };
 917
 918 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 919         .cmd_rcgr = 0x2a00c,
 920         .mnd_width = 8,
 921         .hid_width = 5,
 922         .parent_map = gcc_xo_gpll0_map,
 923         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 924         .clkr.hw.init = &(struct clk_init_data){
 925                 .name = "blsp2_qup3_spi_apps_clk_src",
 926                 .parent_names = gcc_xo_gpll0,
 927                 .num_parents = 2,
 928                 .ops = &clk_rcg2_ops,
 929         },
 930 };
 931
 932 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 933         .cmd_rcgr = 0x2a020,
 934         .hid_width = 5,
 935         .parent_map = gcc_xo_gpll0_map,
 936         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 937         .clkr.hw.init = &(struct clk_init_data){
 938                 .name = "blsp2_qup3_i2c_apps_clk_src",
 939                 .parent_names = gcc_xo_gpll0,
 940                 .num_parents = 2,
 941                 .ops = &clk_rcg2_ops,
 942         },
 943 };
 944
 945 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 946         .cmd_rcgr = 0x2b00c,
 947         .mnd_width = 16,
 948         .hid_width = 5,
 949         .parent_map = gcc_xo_gpll0_map,
 950         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 951         .clkr.hw.init = &(struct clk_init_data){
 952                 .name = "blsp2_uart3_apps_clk_src",
 953                 .parent_names = gcc_xo_gpll0,
 954                 .num_parents = 2,
 955                 .ops = &clk_rcg2_ops,
 956         },
 957 };
 958
 959 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 960         .cmd_rcgr = 0x2c00c,
 961         .mnd_width = 8,
 962         .hid_width = 5,
 963         .parent_map = gcc_xo_gpll0_map,
 964         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 965         .clkr.hw.init = &(struct clk_init_data){
 966                 .name = "blsp2_qup4_spi_apps_clk_src",
 967                 .parent_names = gcc_xo_gpll0,
 968                 .num_parents = 2,
 969                 .ops = &clk_rcg2_ops,
 970         },
 971 };
 972
 973 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 974         .cmd_rcgr = 0x2c020,
 975         .hid_width = 5,
 976         .parent_map = gcc_xo_gpll0_map,
 977         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 978         .clkr.hw.init = &(struct clk_init_data){
 979                 .name = "blsp2_qup4_i2c_apps_clk_src",
 980                 .parent_names = gcc_xo_gpll0,
 981                 .num_parents = 2,
 982                 .ops = &clk_rcg2_ops,
 983         },
 984 };
 985
 986 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 987         .cmd_rcgr = 0x2d00c,
 988         .mnd_width = 16,
 989         .hid_width = 5,
 990         .parent_map = gcc_xo_gpll0_map,
 991         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 992         .clkr.hw.init = &(struct clk_init_data){
 993                 .name = "blsp2_uart4_apps_clk_src",
 994                 .parent_names = gcc_xo_gpll0,
 995                 .num_parents = 2,
 996                 .ops = &clk_rcg2_ops,
 997         },
 998 };
 999
1000 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
1001         .cmd_rcgr = 0x2e00c,
1002         .mnd_width = 8,
1003         .hid_width = 5,
1004         .parent_map = gcc_xo_gpll0_map,
1005         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1006         .clkr.hw.init = &(struct clk_init_data){
1007                 .name = "blsp2_qup5_spi_apps_clk_src",
1008                 .parent_names = gcc_xo_gpll0,
1009                 .num_parents = 2,
1010                 .ops = &clk_rcg2_ops,
1011         },
1012 };
1013
1014 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
1015         .cmd_rcgr = 0x2e020,
1016         .hid_width = 5,
1017         .parent_map = gcc_xo_gpll0_map,
1018         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1019         .clkr.hw.init = &(struct clk_init_data){
1020                 .name = "blsp2_qup5_i2c_apps_clk_src",
1021                 .parent_names = gcc_xo_gpll0,
1022                 .num_parents = 2,
1023                 .ops = &clk_rcg2_ops,
1024         },
1025 };
1026
1027 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
1028         .cmd_rcgr = 0x2f00c,
1029         .mnd_width = 16,
1030         .hid_width = 5,
1031         .parent_map = gcc_xo_gpll0_map,
1032         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1033         .clkr.hw.init = &(struct clk_init_data){
1034                 .name = "blsp2_uart5_apps_clk_src",
1035                 .parent_names = gcc_xo_gpll0,
1036                 .num_parents = 2,
1037                 .ops = &clk_rcg2_ops,
1038         },
1039 };
1040
1041 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1042         .cmd_rcgr = 0x3000c,
1043         .mnd_width = 8,
1044         .hid_width = 5,
1045         .parent_map = gcc_xo_gpll0_map,
1046         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1047         .clkr.hw.init = &(struct clk_init_data){
1048                 .name = "blsp2_qup6_spi_apps_clk_src",
1049                 .parent_names = gcc_xo_gpll0,
1050                 .num_parents = 2,
1051                 .ops = &clk_rcg2_ops,
1052         },
1053 };
1054
1055 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1056         .cmd_rcgr = 0x30020,
1057         .hid_width = 5,
1058         .parent_map = gcc_xo_gpll0_map,
1059         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1060         .clkr.hw.init = &(struct clk_init_data){
1061                 .name = "blsp2_qup6_i2c_apps_clk_src",
1062                 .parent_names = gcc_xo_gpll0,
1063                 .num_parents = 2,
1064                 .ops = &clk_rcg2_ops,
1065         },
1066 };
1067
1068 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1069         .cmd_rcgr = 0x3100c,
1070         .mnd_width = 16,
1071         .hid_width = 5,
1072         .parent_map = gcc_xo_gpll0_map,
1073         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1074         .clkr.hw.init = &(struct clk_init_data){
1075                 .name = "blsp2_uart6_apps_clk_src",
1076                 .parent_names = gcc_xo_gpll0,
1077                 .num_parents = 2,
1078                 .ops = &clk_rcg2_ops,
1079         },
1080 };
1081
1082 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1083         F(60000000, P_GPLL0, 10, 0, 0),
1084         { }
1085 };
1086
1087 static struct clk_rcg2 pdm2_clk_src = {
1088         .cmd_rcgr = 0x33010,
1089         .hid_width = 5,
1090         .parent_map = gcc_xo_gpll0_map,
1091         .freq_tbl = ftbl_pdm2_clk_src,
1092         .clkr.hw.init = &(struct clk_init_data){
1093                 .name = "pdm2_clk_src",
1094                 .parent_names = gcc_xo_gpll0,
1095                 .num_parents = 2,
1096                 .ops = &clk_rcg2_ops,
1097         },
1098 };
1099
1100 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1101         F(105495, P_XO, 1, 1, 182),
1102         { }
1103 };
1104
1105 static struct clk_rcg2 tsif_ref_clk_src = {
1106         .cmd_rcgr = 0x36010,
1107         .mnd_width = 8,
1108         .hid_width = 5,
1109         .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1110         .freq_tbl = ftbl_tsif_ref_clk_src,
1111         .clkr.hw.init = &(struct clk_init_data){
1112                 .name = "tsif_ref_clk_src",
1113                 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1114                 .num_parents = 3,
1115                 .ops = &clk_rcg2_ops,
1116         },
1117 };
1118
1119 static struct clk_rcg2 gcc_sleep_clk_src = {
1120         .cmd_rcgr = 0x43014,
1121         .hid_width = 5,
1122         .parent_map = gcc_sleep_clk_map,
1123         .clkr.hw.init = &(struct clk_init_data){
1124                 .name = "gcc_sleep_clk_src",
1125                 .parent_names = gcc_sleep_clk,
1126                 .num_parents = 1,
1127                 .ops = &clk_rcg2_ops,
1128         },
1129 };
1130
1131 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1132         .cmd_rcgr = 0x48040,
1133         .hid_width = 5,
1134         .parent_map = gcc_xo_gpll0_map,
1135         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1136         .clkr.hw.init = &(struct clk_init_data){
1137                 .name = "hmss_rbcpr_clk_src",
1138                 .parent_names = gcc_xo_gpll0,
1139                 .num_parents = 2,
1140                 .ops = &clk_rcg2_ops,
1141         },
1142 };
1143
1144 static struct clk_rcg2 hmss_gpll0_clk_src = {
1145         .cmd_rcgr = 0x48058,
1146         .hid_width = 5,
1147         .parent_map = gcc_xo_gpll0_map,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "hmss_gpll0_clk_src",
1150                 .parent_names = gcc_xo_gpll0,
1151                 .num_parents = 2,
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1157         F(19200000, P_XO, 1, 0, 0),
1158         F(100000000, P_GPLL0, 6, 0, 0),
1159         F(200000000, P_GPLL0, 3, 0, 0),
1160         { }
1161 };
1162
1163 static struct clk_rcg2 gp1_clk_src = {
1164         .cmd_rcgr = 0x64004,
1165         .mnd_width = 8,
1166         .hid_width = 5,
1167         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1168         .freq_tbl = ftbl_gp1_clk_src,
1169         .clkr.hw.init = &(struct clk_init_data){
1170                 .name = "gp1_clk_src",
1171                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1172                 .num_parents = 4,
1173                 .ops = &clk_rcg2_ops,
1174         },
1175 };
1176
1177 static struct clk_rcg2 gp2_clk_src = {
1178         .cmd_rcgr = 0x65004,
1179         .mnd_width = 8,
1180         .hid_width = 5,
1181         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1182         .freq_tbl = ftbl_gp1_clk_src,
1183         .clkr.hw.init = &(struct clk_init_data){
1184                 .name = "gp2_clk_src",
1185                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1186                 .num_parents = 4,
1187                 .ops = &clk_rcg2_ops,
1188         },
1189 };
1190
1191 static struct clk_rcg2 gp3_clk_src = {
1192         .cmd_rcgr = 0x66004,
1193         .mnd_width = 8,
1194         .hid_width = 5,
1195         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1196         .freq_tbl = ftbl_gp1_clk_src,
1197         .clkr.hw.init = &(struct clk_init_data){
1198                 .name = "gp3_clk_src",
1199                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1200                 .num_parents = 4,
1201                 .ops = &clk_rcg2_ops,
1202         },
1203 };
1204
1205 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1206         F(1010526, P_XO, 1, 1, 19),
1207         { }
1208 };
1209
1210 static struct clk_rcg2 pcie_aux_clk_src = {
1211         .cmd_rcgr = 0x6c000,
1212         .mnd_width = 16,
1213         .hid_width = 5,
1214         .parent_map = gcc_xo_sleep_clk_map,
1215         .freq_tbl = ftbl_pcie_aux_clk_src,
1216         .clkr.hw.init = &(struct clk_init_data){
1217                 .name = "pcie_aux_clk_src",
1218                 .parent_names = gcc_xo_sleep_clk,
1219                 .num_parents = 2,
1220                 .ops = &clk_rcg2_ops,
1221         },
1222 };
1223
1224 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1225         F(100000000, P_GPLL0, 6, 0, 0),
1226         F(200000000, P_GPLL0, 3, 0, 0),
1227         F(240000000, P_GPLL0, 2.5, 0, 0),
1228         { }
1229 };
1230
1231 static struct clk_rcg2 ufs_axi_clk_src = {
1232         .cmd_rcgr = 0x75024,
1233         .mnd_width = 8,
1234         .hid_width = 5,
1235         .parent_map = gcc_xo_gpll0_map,
1236         .freq_tbl = ftbl_ufs_axi_clk_src,
1237         .clkr.hw.init = &(struct clk_init_data){
1238                 .name = "ufs_axi_clk_src",
1239                 .parent_names = gcc_xo_gpll0,
1240                 .num_parents = 2,
1241                 .ops = &clk_rcg2_ops,
1242         },
1243 };
1244
1245 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1246         F(19200000, P_XO, 1, 0, 0),
1247         F(150000000, P_GPLL0, 4, 0, 0),
1248         F(300000000, P_GPLL0, 2, 0, 0),
1249         { }
1250 };
1251
1252 static struct clk_rcg2 ufs_ice_core_clk_src = {
1253         .cmd_rcgr = 0x76014,
1254         .hid_width = 5,
1255         .parent_map = gcc_xo_gpll0_map,
1256         .freq_tbl = ftbl_ufs_ice_core_clk_src,
1257         .clkr.hw.init = &(struct clk_init_data){
1258                 .name = "ufs_ice_core_clk_src",
1259                 .parent_names = gcc_xo_gpll0,
1260                 .num_parents = 2,
1261                 .ops = &clk_rcg2_ops,
1262         },
1263 };
1264
1265 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1266         F(75000000, P_GPLL0, 8, 0, 0),
1267         F(150000000, P_GPLL0, 4, 0, 0),
1268         F(256000000, P_GPLL4, 1.5, 0, 0),
1269         F(300000000, P_GPLL0, 2, 0, 0),
1270         { }
1271 };
1272
1273 static struct clk_rcg2 qspi_ser_clk_src = {
1274         .cmd_rcgr = 0x8b00c,
1275         .hid_width = 5,
1276         .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1277         .freq_tbl = ftbl_qspi_ser_clk_src,
1278         .clkr.hw.init = &(struct clk_init_data){
1279                 .name = "qspi_ser_clk_src",
1280                 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1281                 .num_parents = 6,
1282                 .ops = &clk_rcg2_ops,
1283         },
1284 };
1285
1286 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1287         .halt_reg = 0x0f03c,
1288         .clkr = {
1289                 .enable_reg = 0x0f03c,
1290                 .enable_mask = BIT(0),
1291                 .hw.init = &(struct clk_init_data){
1292                         .name = "gcc_sys_noc_usb3_axi_clk",
1293                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1294                         .num_parents = 1,
1295                         .flags = CLK_SET_RATE_PARENT,
1296                         .ops = &clk_branch2_ops,
1297                 },
1298         },
1299 };
1300
1301 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1302         .halt_reg = 0x75038,
1303         .clkr = {
1304                 .enable_reg = 0x75038,
1305                 .enable_mask = BIT(0),
1306                 .hw.init = &(struct clk_init_data){
1307                         .name = "gcc_sys_noc_ufs_axi_clk",
1308                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1309                         .num_parents = 1,
1310                         .flags = CLK_SET_RATE_PARENT,
1311                         .ops = &clk_branch2_ops,
1312                 },
1313         },
1314 };
1315
1316 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1317         .halt_reg = 0x6010,
1318         .clkr = {
1319                 .enable_reg = 0x6010,
1320                 .enable_mask = BIT(0),
1321                 .hw.init = &(struct clk_init_data){
1322                         .name = "gcc_periph_noc_usb20_ahb_clk",
1323                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1324                         .num_parents = 1,
1325                         .flags = CLK_SET_RATE_PARENT,
1326                         .ops = &clk_branch2_ops,
1327                 },
1328         },
1329 };
1330
1331 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1332         .halt_reg = 0x9008,
1333         .clkr = {
1334                 .enable_reg = 0x9008,
1335                 .enable_mask = BIT(0),
1336                 .hw.init = &(struct clk_init_data){
1337                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1338                         .parent_names = (const char *[]){ "config_noc_clk_src" },
1339                         .num_parents = 1,
1340                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1341                         .ops = &clk_branch2_ops,
1342                 },
1343         },
1344 };
1345
1346 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1347         .halt_reg = 0x9010,
1348         .clkr = {
1349                 .enable_reg = 0x9010,
1350                 .enable_mask = BIT(0),
1351                 .hw.init = &(struct clk_init_data){
1352                         .name = "gcc_mmss_bimc_gfx_clk",
1353                         .flags = CLK_SET_RATE_PARENT,
1354                         .ops = &clk_branch2_ops,
1355                 },
1356         },
1357 };
1358
1359 static struct clk_branch gcc_usb30_master_clk = {
1360         .halt_reg = 0x0f008,
1361         .clkr = {
1362                 .enable_reg = 0x0f008,
1363                 .enable_mask = BIT(0),
1364                 .hw.init = &(struct clk_init_data){
1365                         .name = "gcc_usb30_master_clk",
1366                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1367                         .num_parents = 1,
1368                         .flags = CLK_SET_RATE_PARENT,
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_usb30_sleep_clk = {
1375         .halt_reg = 0x0f00c,
1376         .clkr = {
1377                 .enable_reg = 0x0f00c,
1378                 .enable_mask = BIT(0),
1379                 .hw.init = &(struct clk_init_data){
1380                         .name = "gcc_usb30_sleep_clk",
1381                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1382                         .num_parents = 1,
1383                         .flags = CLK_SET_RATE_PARENT,
1384                         .ops = &clk_branch2_ops,
1385                 },
1386         },
1387 };
1388
1389 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1390         .halt_reg = 0x0f010,
1391         .clkr = {
1392                 .enable_reg = 0x0f010,
1393                 .enable_mask = BIT(0),
1394                 .hw.init = &(struct clk_init_data){
1395                         .name = "gcc_usb30_mock_utmi_clk",
1396                         .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1397                         .num_parents = 1,
1398                         .flags = CLK_SET_RATE_PARENT,
1399                         .ops = &clk_branch2_ops,
1400                 },
1401         },
1402 };
1403
1404 static struct clk_branch gcc_usb3_phy_aux_clk = {
1405         .halt_reg = 0x50000,
1406         .clkr = {
1407                 .enable_reg = 0x50000,
1408                 .enable_mask = BIT(0),
1409                 .hw.init = &(struct clk_init_data){
1410                         .name = "gcc_usb3_phy_aux_clk",
1411                         .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1412                         .num_parents = 1,
1413                         .flags = CLK_SET_RATE_PARENT,
1414                         .ops = &clk_branch2_ops,
1415                 },
1416         },
1417 };
1418
1419 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1420         .halt_reg = 0x50004,
1421         .clkr = {
1422                 .enable_reg = 0x50004,
1423                 .enable_mask = BIT(0),
1424                 .hw.init = &(struct clk_init_data){
1425                         .name = "gcc_usb3_phy_pipe_clk",
1426                         .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1427                         .num_parents = 1,
1428                         .flags = CLK_SET_RATE_PARENT,
1429                         .ops = &clk_branch2_ops,
1430                 },
1431         },
1432 };
1433
1434 static struct clk_branch gcc_usb20_master_clk = {
1435         .halt_reg = 0x12004,
1436         .clkr = {
1437                 .enable_reg = 0x12004,
1438                 .enable_mask = BIT(0),
1439                 .hw.init = &(struct clk_init_data){
1440                         .name = "gcc_usb20_master_clk",
1441                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1442                         .num_parents = 1,
1443                         .flags = CLK_SET_RATE_PARENT,
1444                         .ops = &clk_branch2_ops,
1445                 },
1446         },
1447 };
1448
1449 static struct clk_branch gcc_usb20_sleep_clk = {
1450         .halt_reg = 0x12008,
1451         .clkr = {
1452                 .enable_reg = 0x12008,
1453                 .enable_mask = BIT(0),
1454                 .hw.init = &(struct clk_init_data){
1455                         .name = "gcc_usb20_sleep_clk",
1456                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1457                         .num_parents = 1,
1458                         .flags = CLK_SET_RATE_PARENT,
1459                         .ops = &clk_branch2_ops,
1460                 },
1461         },
1462 };
1463
1464 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1465         .halt_reg = 0x1200c,
1466         .clkr = {
1467                 .enable_reg = 0x1200c,
1468                 .enable_mask = BIT(0),
1469                 .hw.init = &(struct clk_init_data){
1470                         .name = "gcc_usb20_mock_utmi_clk",
1471                         .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1472                         .num_parents = 1,
1473                         .flags = CLK_SET_RATE_PARENT,
1474                         .ops = &clk_branch2_ops,
1475                 },
1476         },
1477 };
1478
1479 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1480         .halt_reg = 0x6a004,
1481         .clkr = {
1482                 .enable_reg = 0x6a004,
1483                 .enable_mask = BIT(0),
1484                 .hw.init = &(struct clk_init_data){
1485                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1486                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1487                         .num_parents = 1,
1488                         .flags = CLK_SET_RATE_PARENT,
1489                         .ops = &clk_branch2_ops,
1490                 },
1491         },
1492 };
1493
1494 static struct clk_branch gcc_sdcc1_apps_clk = {
1495         .halt_reg = 0x13004,
1496         .clkr = {
1497                 .enable_reg = 0x13004,
1498                 .enable_mask = BIT(0),
1499                 .hw.init = &(struct clk_init_data){
1500                         .name = "gcc_sdcc1_apps_clk",
1501                         .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1502                         .num_parents = 1,
1503                         .flags = CLK_SET_RATE_PARENT,
1504                         .ops = &clk_branch2_ops,
1505                 },
1506         },
1507 };
1508
1509 static struct clk_branch gcc_sdcc1_ahb_clk = {
1510         .halt_reg = 0x13008,
1511         .clkr = {
1512                 .enable_reg = 0x13008,
1513                 .enable_mask = BIT(0),
1514                 .hw.init = &(struct clk_init_data){
1515                         .name = "gcc_sdcc1_ahb_clk",
1516                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1517                         .num_parents = 1,
1518                         .flags = CLK_SET_RATE_PARENT,
1519                         .ops = &clk_branch2_ops,
1520                 },
1521         },
1522 };
1523
1524 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1525         .halt_reg = 0x13038,
1526         .clkr = {
1527                 .enable_reg = 0x13038,
1528                 .enable_mask = BIT(0),
1529                 .hw.init = &(struct clk_init_data){
1530                         .name = "gcc_sdcc1_ice_core_clk",
1531                         .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1532                         .num_parents = 1,
1533                         .flags = CLK_SET_RATE_PARENT,
1534                         .ops = &clk_branch2_ops,
1535                 },
1536         },
1537 };
1538
1539 static struct clk_branch gcc_sdcc2_apps_clk = {
1540         .halt_reg = 0x14004,
1541         .clkr = {
1542                 .enable_reg = 0x14004,
1543                 .enable_mask = BIT(0),
1544                 .hw.init = &(struct clk_init_data){
1545                         .name = "gcc_sdcc2_apps_clk",
1546                         .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1547                         .num_parents = 1,
1548                         .flags = CLK_SET_RATE_PARENT,
1549                         .ops = &clk_branch2_ops,
1550                 },
1551         },
1552 };
1553
1554 static struct clk_branch gcc_sdcc2_ahb_clk = {
1555         .halt_reg = 0x14008,
1556         .clkr = {
1557                 .enable_reg = 0x14008,
1558                 .enable_mask = BIT(0),
1559                 .hw.init = &(struct clk_init_data){
1560                         .name = "gcc_sdcc2_ahb_clk",
1561                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1562                         .num_parents = 1,
1563                         .flags = CLK_SET_RATE_PARENT,
1564                         .ops = &clk_branch2_ops,
1565                 },
1566         },
1567 };
1568
1569 static struct clk_branch gcc_sdcc3_apps_clk = {
1570         .halt_reg = 0x15004,
1571         .clkr = {
1572                 .enable_reg = 0x15004,
1573                 .enable_mask = BIT(0),
1574                 .hw.init = &(struct clk_init_data){
1575                         .name = "gcc_sdcc3_apps_clk",
1576                         .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1577                         .num_parents = 1,
1578                         .flags = CLK_SET_RATE_PARENT,
1579                         .ops = &clk_branch2_ops,
1580                 },
1581         },
1582 };
1583
1584 static struct clk_branch gcc_sdcc3_ahb_clk = {
1585         .halt_reg = 0x15008,
1586         .clkr = {
1587                 .enable_reg = 0x15008,
1588                 .enable_mask = BIT(0),
1589                 .hw.init = &(struct clk_init_data){
1590                         .name = "gcc_sdcc3_ahb_clk",
1591                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1592                         .num_parents = 1,
1593                         .flags = CLK_SET_RATE_PARENT,
1594                         .ops = &clk_branch2_ops,
1595                 },
1596         },
1597 };
1598
1599 static struct clk_branch gcc_sdcc4_apps_clk = {
1600         .halt_reg = 0x16004,
1601         .clkr = {
1602                 .enable_reg = 0x16004,
1603                 .enable_mask = BIT(0),
1604                 .hw.init = &(struct clk_init_data){
1605                         .name = "gcc_sdcc4_apps_clk",
1606                         .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1607                         .num_parents = 1,
1608                         .flags = CLK_SET_RATE_PARENT,
1609                         .ops = &clk_branch2_ops,
1610                 },
1611         },
1612 };
1613
1614 static struct clk_branch gcc_sdcc4_ahb_clk = {
1615         .halt_reg = 0x16008,
1616         .clkr = {
1617                 .enable_reg = 0x16008,
1618                 .enable_mask = BIT(0),
1619                 .hw.init = &(struct clk_init_data){
1620                         .name = "gcc_sdcc4_ahb_clk",
1621                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1622                         .num_parents = 1,
1623                         .flags = CLK_SET_RATE_PARENT,
1624                         .ops = &clk_branch2_ops,
1625                 },
1626         },
1627 };
1628
1629 static struct clk_branch gcc_blsp1_ahb_clk = {
1630         .halt_reg = 0x17004,
1631         .halt_check = BRANCH_HALT_VOTED,
1632         .clkr = {
1633                 .enable_reg = 0x52004,
1634                 .enable_mask = BIT(17),
1635                 .hw.init = &(struct clk_init_data){
1636                         .name = "gcc_blsp1_ahb_clk",
1637                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1638                         .num_parents = 1,
1639                         .flags = CLK_SET_RATE_PARENT,
1640                         .ops = &clk_branch2_ops,
1641                 },
1642         },
1643 };
1644
1645 static struct clk_branch gcc_blsp1_sleep_clk = {
1646         .halt_reg = 0x17008,
1647         .halt_check = BRANCH_HALT_VOTED,
1648         .clkr = {
1649                 .enable_reg = 0x52004,
1650                 .enable_mask = BIT(16),
1651                 .hw.init = &(struct clk_init_data){
1652                         .name = "gcc_blsp1_sleep_clk",
1653                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1654                         .num_parents = 1,
1655                         .flags = CLK_SET_RATE_PARENT,
1656                         .ops = &clk_branch2_ops,
1657                 },
1658         },
1659 };
1660
1661 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1662         .halt_reg = 0x19004,
1663         .clkr = {
1664                 .enable_reg = 0x19004,
1665                 .enable_mask = BIT(0),
1666                 .hw.init = &(struct clk_init_data){
1667                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1668                         .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1669                         .num_parents = 1,
1670                         .flags = CLK_SET_RATE_PARENT,
1671                         .ops = &clk_branch2_ops,
1672                 },
1673         },
1674 };
1675
1676 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1677         .halt_reg = 0x19008,
1678         .clkr = {
1679                 .enable_reg = 0x19008,
1680                 .enable_mask = BIT(0),
1681                 .hw.init = &(struct clk_init_data){
1682                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1683                         .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1684                         .num_parents = 1,
1685                         .flags = CLK_SET_RATE_PARENT,
1686                         .ops = &clk_branch2_ops,
1687                 },
1688         },
1689 };
1690
1691 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1692         .halt_reg = 0x1a004,
1693         .clkr = {
1694                 .enable_reg = 0x1a004,
1695                 .enable_mask = BIT(0),
1696                 .hw.init = &(struct clk_init_data){
1697                         .name = "gcc_blsp1_uart1_apps_clk",
1698                         .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1699                         .num_parents = 1,
1700                         .flags = CLK_SET_RATE_PARENT,
1701                         .ops = &clk_branch2_ops,
1702                 },
1703         },
1704 };
1705
1706 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1707         .halt_reg = 0x1b004,
1708         .clkr = {
1709                 .enable_reg = 0x1b004,
1710                 .enable_mask = BIT(0),
1711                 .hw.init = &(struct clk_init_data){
1712                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1713                         .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1714                         .num_parents = 1,
1715                         .flags = CLK_SET_RATE_PARENT,
1716                         .ops = &clk_branch2_ops,
1717                 },
1718         },
1719 };
1720
1721 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1722         .halt_reg = 0x1b008,
1723         .clkr = {
1724                 .enable_reg = 0x1b008,
1725                 .enable_mask = BIT(0),
1726                 .hw.init = &(struct clk_init_data){
1727                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1728                         .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1729                         .num_parents = 1,
1730                         .flags = CLK_SET_RATE_PARENT,
1731                         .ops = &clk_branch2_ops,
1732                 },
1733         },
1734 };
1735
1736 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1737         .halt_reg = 0x1c004,
1738         .clkr = {
1739                 .enable_reg = 0x1c004,
1740                 .enable_mask = BIT(0),
1741                 .hw.init = &(struct clk_init_data){
1742                         .name = "gcc_blsp1_uart2_apps_clk",
1743                         .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1744                         .num_parents = 1,
1745                         .flags = CLK_SET_RATE_PARENT,
1746                         .ops = &clk_branch2_ops,
1747                 },
1748         },
1749 };
1750
1751 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1752         .halt_reg = 0x1d004,
1753         .clkr = {
1754                 .enable_reg = 0x1d004,
1755                 .enable_mask = BIT(0),
1756                 .hw.init = &(struct clk_init_data){
1757                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1758                         .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1759                         .num_parents = 1,
1760                         .flags = CLK_SET_RATE_PARENT,
1761                         .ops = &clk_branch2_ops,
1762                 },
1763         },
1764 };
1765
1766 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1767         .halt_reg = 0x1d008,
1768         .clkr = {
1769                 .enable_reg = 0x1d008,
1770                 .enable_mask = BIT(0),
1771                 .hw.init = &(struct clk_init_data){
1772                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1773                         .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1774                         .num_parents = 1,
1775                         .flags = CLK_SET_RATE_PARENT,
1776                         .ops = &clk_branch2_ops,
1777                 },
1778         },
1779 };
1780
1781 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1782         .halt_reg = 0x1e004,
1783         .clkr = {
1784                 .enable_reg = 0x1e004,
1785                 .enable_mask = BIT(0),
1786                 .hw.init = &(struct clk_init_data){
1787                         .name = "gcc_blsp1_uart3_apps_clk",
1788                         .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1789                         .num_parents = 1,
1790                         .flags = CLK_SET_RATE_PARENT,
1791                         .ops = &clk_branch2_ops,
1792                 },
1793         },
1794 };
1795
1796 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1797         .halt_reg = 0x1f004,
1798         .clkr = {
1799                 .enable_reg = 0x1f004,
1800                 .enable_mask = BIT(0),
1801                 .hw.init = &(struct clk_init_data){
1802                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1803                         .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1804                         .num_parents = 1,
1805                         .flags = CLK_SET_RATE_PARENT,
1806                         .ops = &clk_branch2_ops,
1807                 },
1808         },
1809 };
1810
1811 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1812         .halt_reg = 0x1f008,
1813         .clkr = {
1814                 .enable_reg = 0x1f008,
1815                 .enable_mask = BIT(0),
1816                 .hw.init = &(struct clk_init_data){
1817                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1818                         .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1819                         .num_parents = 1,
1820                         .flags = CLK_SET_RATE_PARENT,
1821                         .ops = &clk_branch2_ops,
1822                 },
1823         },
1824 };
1825
1826 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1827         .halt_reg = 0x20004,
1828         .clkr = {
1829                 .enable_reg = 0x20004,
1830                 .enable_mask = BIT(0),
1831                 .hw.init = &(struct clk_init_data){
1832                         .name = "gcc_blsp1_uart4_apps_clk",
1833                         .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1834                         .num_parents = 1,
1835                         .flags = CLK_SET_RATE_PARENT,
1836                         .ops = &clk_branch2_ops,
1837                 },
1838         },
1839 };
1840
1841 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1842         .halt_reg = 0x21004,
1843         .clkr = {
1844                 .enable_reg = 0x21004,
1845                 .enable_mask = BIT(0),
1846                 .hw.init = &(struct clk_init_data){
1847                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1848                         .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1849                         .num_parents = 1,
1850                         .flags = CLK_SET_RATE_PARENT,
1851                         .ops = &clk_branch2_ops,
1852                 },
1853         },
1854 };
1855
1856 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1857         .halt_reg = 0x21008,
1858         .clkr = {
1859                 .enable_reg = 0x21008,
1860                 .enable_mask = BIT(0),
1861                 .hw.init = &(struct clk_init_data){
1862                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1863                         .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1864                         .num_parents = 1,
1865                         .flags = CLK_SET_RATE_PARENT,
1866                         .ops = &clk_branch2_ops,
1867                 },
1868         },
1869 };
1870
1871 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1872         .halt_reg = 0x22004,
1873         .clkr = {
1874                 .enable_reg = 0x22004,
1875                 .enable_mask = BIT(0),
1876                 .hw.init = &(struct clk_init_data){
1877                         .name = "gcc_blsp1_uart5_apps_clk",
1878                         .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1879                         .num_parents = 1,
1880                         .flags = CLK_SET_RATE_PARENT,
1881                         .ops = &clk_branch2_ops,
1882                 },
1883         },
1884 };
1885
1886 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1887         .halt_reg = 0x23004,
1888         .clkr = {
1889                 .enable_reg = 0x23004,
1890                 .enable_mask = BIT(0),
1891                 .hw.init = &(struct clk_init_data){
1892                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1893                         .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1894                         .num_parents = 1,
1895                         .flags = CLK_SET_RATE_PARENT,
1896                         .ops = &clk_branch2_ops,
1897                 },
1898         },
1899 };
1900
1901 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1902         .halt_reg = 0x23008,
1903         .clkr = {
1904                 .enable_reg = 0x23008,
1905                 .enable_mask = BIT(0),
1906                 .hw.init = &(struct clk_init_data){
1907                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1908                         .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1909                         .num_parents = 1,
1910                         .flags = CLK_SET_RATE_PARENT,
1911                         .ops = &clk_branch2_ops,
1912                 },
1913         },
1914 };
1915
1916 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1917         .halt_reg = 0x24004,
1918         .clkr = {
1919                 .enable_reg = 0x24004,
1920                 .enable_mask = BIT(0),
1921                 .hw.init = &(struct clk_init_data){
1922                         .name = "gcc_blsp1_uart6_apps_clk",
1923                         .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1924                         .num_parents = 1,
1925                         .flags = CLK_SET_RATE_PARENT,
1926                         .ops = &clk_branch2_ops,
1927                 },
1928         },
1929 };
1930
1931 static struct clk_branch gcc_blsp2_ahb_clk = {
1932         .halt_reg = 0x25004,
1933         .halt_check = BRANCH_HALT_VOTED,
1934         .clkr = {
1935                 .enable_reg = 0x52004,
1936                 .enable_mask = BIT(15),
1937                 .hw.init = &(struct clk_init_data){
1938                         .name = "gcc_blsp2_ahb_clk",
1939                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1940                         .num_parents = 1,
1941                         .flags = CLK_SET_RATE_PARENT,
1942                         .ops = &clk_branch2_ops,
1943                 },
1944         },
1945 };
1946
1947 static struct clk_branch gcc_blsp2_sleep_clk = {
1948         .halt_reg = 0x25008,
1949         .halt_check = BRANCH_HALT_VOTED,
1950         .clkr = {
1951                 .enable_reg = 0x52004,
1952                 .enable_mask = BIT(14),
1953                 .hw.init = &(struct clk_init_data){
1954                         .name = "gcc_blsp2_sleep_clk",
1955                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1956                         .num_parents = 1,
1957                         .flags = CLK_SET_RATE_PARENT,
1958                         .ops = &clk_branch2_ops,
1959                 },
1960         },
1961 };
1962
1963 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1964         .halt_reg = 0x26004,
1965         .clkr = {
1966                 .enable_reg = 0x26004,
1967                 .enable_mask = BIT(0),
1968                 .hw.init = &(struct clk_init_data){
1969                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1970                         .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1971                         .num_parents = 1,
1972                         .flags = CLK_SET_RATE_PARENT,
1973                         .ops = &clk_branch2_ops,
1974                 },
1975         },
1976 };
1977
1978 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1979         .halt_reg = 0x26008,
1980         .clkr = {
1981                 .enable_reg = 0x26008,
1982                 .enable_mask = BIT(0),
1983                 .hw.init = &(struct clk_init_data){
1984                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1985                         .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1986                         .num_parents = 1,
1987                         .flags = CLK_SET_RATE_PARENT,
1988                         .ops = &clk_branch2_ops,
1989                 },
1990         },
1991 };
1992
1993 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1994         .halt_reg = 0x27004,
1995         .clkr = {
1996                 .enable_reg = 0x27004,
1997                 .enable_mask = BIT(0),
1998                 .hw.init = &(struct clk_init_data){
1999                         .name = "gcc_blsp2_uart1_apps_clk",
2000                         .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
2001                         .num_parents = 1,
2002                         .flags = CLK_SET_RATE_PARENT,
2003                         .ops = &clk_branch2_ops,
2004                 },
2005         },
2006 };
2007
2008 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
2009         .halt_reg = 0x28004,
2010         .clkr = {
2011                 .enable_reg = 0x28004,
2012                 .enable_mask = BIT(0),
2013                 .hw.init = &(struct clk_init_data){
2014                         .name = "gcc_blsp2_qup2_spi_apps_clk",
2015                         .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
2016                         .num_parents = 1,
2017                         .flags = CLK_SET_RATE_PARENT,
2018                         .ops = &clk_branch2_ops,
2019                 },
2020         },
2021 };
2022
2023 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
2024         .halt_reg = 0x28008,
2025         .clkr = {
2026                 .enable_reg = 0x28008,
2027                 .enable_mask = BIT(0),
2028                 .hw.init = &(struct clk_init_data){
2029                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
2030                         .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
2031                         .num_parents = 1,
2032                         .flags = CLK_SET_RATE_PARENT,
2033                         .ops = &clk_branch2_ops,
2034                 },
2035         },
2036 };
2037
2038 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2039         .halt_reg = 0x29004,
2040         .clkr = {
2041                 .enable_reg = 0x29004,
2042                 .enable_mask = BIT(0),
2043                 .hw.init = &(struct clk_init_data){
2044                         .name = "gcc_blsp2_uart2_apps_clk",
2045                         .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2046                         .num_parents = 1,
2047                         .flags = CLK_SET_RATE_PARENT,
2048                         .ops = &clk_branch2_ops,
2049                 },
2050         },
2051 };
2052
2053 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2054         .halt_reg = 0x2a004,
2055         .clkr = {
2056                 .enable_reg = 0x2a004,
2057                 .enable_mask = BIT(0),
2058                 .hw.init = &(struct clk_init_data){
2059                         .name = "gcc_blsp2_qup3_spi_apps_clk",
2060                         .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2061                         .num_parents = 1,
2062                         .flags = CLK_SET_RATE_PARENT,
2063                         .ops = &clk_branch2_ops,
2064                 },
2065         },
2066 };
2067
2068 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2069         .halt_reg = 0x2a008,
2070         .clkr = {
2071                 .enable_reg = 0x2a008,
2072                 .enable_mask = BIT(0),
2073                 .hw.init = &(struct clk_init_data){
2074                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
2075                         .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2076                         .num_parents = 1,
2077                         .flags = CLK_SET_RATE_PARENT,
2078                         .ops = &clk_branch2_ops,
2079                 },
2080         },
2081 };
2082
2083 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2084         .halt_reg = 0x2b004,
2085         .clkr = {
2086                 .enable_reg = 0x2b004,
2087                 .enable_mask = BIT(0),
2088                 .hw.init = &(struct clk_init_data){
2089                         .name = "gcc_blsp2_uart3_apps_clk",
2090                         .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2091                         .num_parents = 1,
2092                         .flags = CLK_SET_RATE_PARENT,
2093                         .ops = &clk_branch2_ops,
2094                 },
2095         },
2096 };
2097
2098 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2099         .halt_reg = 0x2c004,
2100         .clkr = {
2101                 .enable_reg = 0x2c004,
2102                 .enable_mask = BIT(0),
2103                 .hw.init = &(struct clk_init_data){
2104                         .name = "gcc_blsp2_qup4_spi_apps_clk",
2105                         .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2106                         .num_parents = 1,
2107                         .flags = CLK_SET_RATE_PARENT,
2108                         .ops = &clk_branch2_ops,
2109                 },
2110         },
2111 };
2112
2113 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2114         .halt_reg = 0x2c008,
2115         .clkr = {
2116                 .enable_reg = 0x2c008,
2117                 .enable_mask = BIT(0),
2118                 .hw.init = &(struct clk_init_data){
2119                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
2120                         .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2121                         .num_parents = 1,
2122                         .flags = CLK_SET_RATE_PARENT,
2123                         .ops = &clk_branch2_ops,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2129         .halt_reg = 0x2d004,
2130         .clkr = {
2131                 .enable_reg = 0x2d004,
2132                 .enable_mask = BIT(0),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "gcc_blsp2_uart4_apps_clk",
2135                         .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2136                         .num_parents = 1,
2137                         .flags = CLK_SET_RATE_PARENT,
2138                         .ops = &clk_branch2_ops,
2139                 },
2140         },
2141 };
2142
2143 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2144         .halt_reg = 0x2e004,
2145         .clkr = {
2146                 .enable_reg = 0x2e004,
2147                 .enable_mask = BIT(0),
2148                 .hw.init = &(struct clk_init_data){
2149                         .name = "gcc_blsp2_qup5_spi_apps_clk",
2150                         .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2151                         .num_parents = 1,
2152                         .flags = CLK_SET_RATE_PARENT,
2153                         .ops = &clk_branch2_ops,
2154                 },
2155         },
2156 };
2157
2158 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2159         .halt_reg = 0x2e008,
2160         .clkr = {
2161                 .enable_reg = 0x2e008,
2162                 .enable_mask = BIT(0),
2163                 .hw.init = &(struct clk_init_data){
2164                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
2165                         .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2166                         .num_parents = 1,
2167                         .flags = CLK_SET_RATE_PARENT,
2168                         .ops = &clk_branch2_ops,
2169                 },
2170         },
2171 };
2172
2173 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2174         .halt_reg = 0x2f004,
2175         .clkr = {
2176                 .enable_reg = 0x2f004,
2177                 .enable_mask = BIT(0),
2178                 .hw.init = &(struct clk_init_data){
2179                         .name = "gcc_blsp2_uart5_apps_clk",
2180                         .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2181                         .num_parents = 1,
2182                         .flags = CLK_SET_RATE_PARENT,
2183                         .ops = &clk_branch2_ops,
2184                 },
2185         },
2186 };
2187
2188 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2189         .halt_reg = 0x30004,
2190         .clkr = {
2191                 .enable_reg = 0x30004,
2192                 .enable_mask = BIT(0),
2193                 .hw.init = &(struct clk_init_data){
2194                         .name = "gcc_blsp2_qup6_spi_apps_clk",
2195                         .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2196                         .num_parents = 1,
2197                         .flags = CLK_SET_RATE_PARENT,
2198                         .ops = &clk_branch2_ops,
2199                 },
2200         },
2201 };
2202
2203 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2204         .halt_reg = 0x30008,
2205         .clkr = {
2206                 .enable_reg = 0x30008,
2207                 .enable_mask = BIT(0),
2208                 .hw.init = &(struct clk_init_data){
2209                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
2210                         .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2211                         .num_parents = 1,
2212                         .flags = CLK_SET_RATE_PARENT,
2213                         .ops = &clk_branch2_ops,
2214                 },
2215         },
2216 };
2217
2218 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2219         .halt_reg = 0x31004,
2220         .clkr = {
2221                 .enable_reg = 0x31004,
2222                 .enable_mask = BIT(0),
2223                 .hw.init = &(struct clk_init_data){
2224                         .name = "gcc_blsp2_uart6_apps_clk",
2225                         .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2226                         .num_parents = 1,
2227                         .flags = CLK_SET_RATE_PARENT,
2228                         .ops = &clk_branch2_ops,
2229                 },
2230         },
2231 };
2232
2233 static struct clk_branch gcc_pdm_ahb_clk = {
2234         .halt_reg = 0x33004,
2235         .clkr = {
2236                 .enable_reg = 0x33004,
2237                 .enable_mask = BIT(0),
2238                 .hw.init = &(struct clk_init_data){
2239                         .name = "gcc_pdm_ahb_clk",
2240                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2241                         .num_parents = 1,
2242                         .flags = CLK_SET_RATE_PARENT,
2243                         .ops = &clk_branch2_ops,
2244                 },
2245         },
2246 };
2247
2248 static struct clk_branch gcc_pdm2_clk = {
2249         .halt_reg = 0x3300c,
2250         .clkr = {
2251                 .enable_reg = 0x3300c,
2252                 .enable_mask = BIT(0),
2253                 .hw.init = &(struct clk_init_data){
2254                         .name = "gcc_pdm2_clk",
2255                         .parent_names = (const char *[]){ "pdm2_clk_src" },
2256                         .num_parents = 1,
2257                         .flags = CLK_SET_RATE_PARENT,
2258                         .ops = &clk_branch2_ops,
2259                 },
2260         },
2261 };
2262
2263 static struct clk_branch gcc_prng_ahb_clk = {
2264         .halt_reg = 0x34004,
2265         .halt_check = BRANCH_HALT_VOTED,
2266         .clkr = {
2267                 .enable_reg = 0x52004,
2268                 .enable_mask = BIT(13),
2269                 .hw.init = &(struct clk_init_data){
2270                         .name = "gcc_prng_ahb_clk",
2271                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2272                         .num_parents = 1,
2273                         .flags = CLK_SET_RATE_PARENT,
2274                         .ops = &clk_branch2_ops,
2275                 },
2276         },
2277 };
2278
2279 static struct clk_branch gcc_tsif_ahb_clk = {
2280         .halt_reg = 0x36004,
2281         .clkr = {
2282                 .enable_reg = 0x36004,
2283                 .enable_mask = BIT(0),
2284                 .hw.init = &(struct clk_init_data){
2285                         .name = "gcc_tsif_ahb_clk",
2286                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2287                         .num_parents = 1,
2288                         .flags = CLK_SET_RATE_PARENT,
2289                         .ops = &clk_branch2_ops,
2290                 },
2291         },
2292 };
2293
2294 static struct clk_branch gcc_tsif_ref_clk = {
2295         .halt_reg = 0x36008,
2296         .clkr = {
2297                 .enable_reg = 0x36008,
2298                 .enable_mask = BIT(0),
2299                 .hw.init = &(struct clk_init_data){
2300                         .name = "gcc_tsif_ref_clk",
2301                         .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2302                         .num_parents = 1,
2303                         .flags = CLK_SET_RATE_PARENT,
2304                         .ops = &clk_branch2_ops,
2305                 },
2306         },
2307 };
2308
2309 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2310         .halt_reg = 0x3600c,
2311         .clkr = {
2312                 .enable_reg = 0x3600c,
2313                 .enable_mask = BIT(0),
2314                 .hw.init = &(struct clk_init_data){
2315                         .name = "gcc_tsif_inactivity_timers_clk",
2316                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2317                         .num_parents = 1,
2318                         .flags = CLK_SET_RATE_PARENT,
2319                         .ops = &clk_branch2_ops,
2320                 },
2321         },
2322 };
2323
2324 static struct clk_branch gcc_boot_rom_ahb_clk = {
2325         .halt_reg = 0x38004,
2326         .halt_check = BRANCH_HALT_VOTED,
2327         .clkr = {
2328                 .enable_reg = 0x52004,
2329                 .enable_mask = BIT(10),
2330                 .hw.init = &(struct clk_init_data){
2331                         .name = "gcc_boot_rom_ahb_clk",
2332                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2333                         .num_parents = 1,
2334                         .flags = CLK_SET_RATE_PARENT,
2335                         .ops = &clk_branch2_ops,
2336                 },
2337         },
2338 };
2339
2340 static struct clk_branch gcc_bimc_gfx_clk = {
2341         .halt_reg = 0x46018,
2342         .clkr = {
2343                 .enable_reg = 0x46018,
2344                 .enable_mask = BIT(0),
2345                 .hw.init = &(struct clk_init_data){
2346                         .name = "gcc_bimc_gfx_clk",
2347                         .flags = CLK_SET_RATE_PARENT,
2348                         .ops = &clk_branch2_ops,
2349                 },
2350         },
2351 };
2352
2353 static struct clk_branch gcc_hmss_rbcpr_clk = {
2354         .halt_reg = 0x4800c,
2355         .clkr = {
2356                 .enable_reg = 0x4800c,
2357                 .enable_mask = BIT(0),
2358                 .hw.init = &(struct clk_init_data){
2359                         .name = "gcc_hmss_rbcpr_clk",
2360                         .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2361                         .num_parents = 1,
2362                         .flags = CLK_SET_RATE_PARENT,
2363                         .ops = &clk_branch2_ops,
2364                 },
2365         },
2366 };
2367
2368 static struct clk_branch gcc_gp1_clk = {
2369         .halt_reg = 0x64000,
2370         .clkr = {
2371                 .enable_reg = 0x64000,
2372                 .enable_mask = BIT(0),
2373                 .hw.init = &(struct clk_init_data){
2374                         .name = "gcc_gp1_clk",
2375                         .parent_names = (const char *[]){ "gp1_clk_src" },
2376                         .num_parents = 1,
2377                         .flags = CLK_SET_RATE_PARENT,
2378                         .ops = &clk_branch2_ops,
2379                 },
2380         },
2381 };
2382
2383 static struct clk_branch gcc_gp2_clk = {
2384         .halt_reg = 0x65000,
2385         .clkr = {
2386                 .enable_reg = 0x65000,
2387                 .enable_mask = BIT(0),
2388                 .hw.init = &(struct clk_init_data){
2389                         .name = "gcc_gp2_clk",
2390                         .parent_names = (const char *[]){ "gp2_clk_src" },
2391                         .num_parents = 1,
2392                         .flags = CLK_SET_RATE_PARENT,
2393                         .ops = &clk_branch2_ops,
2394                 },
2395         },
2396 };
2397
2398 static struct clk_branch gcc_gp3_clk = {
2399         .halt_reg = 0x66000,
2400         .clkr = {
2401                 .enable_reg = 0x66000,
2402                 .enable_mask = BIT(0),
2403                 .hw.init = &(struct clk_init_data){
2404                         .name = "gcc_gp3_clk",
2405                         .parent_names = (const char *[]){ "gp3_clk_src" },
2406                         .num_parents = 1,
2407                         .flags = CLK_SET_RATE_PARENT,
2408                         .ops = &clk_branch2_ops,
2409                 },
2410         },
2411 };
2412
2413 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2414         .halt_reg = 0x6b008,
2415         .clkr = {
2416                 .enable_reg = 0x6b008,
2417                 .enable_mask = BIT(0),
2418                 .hw.init = &(struct clk_init_data){
2419                         .name = "gcc_pcie_0_slv_axi_clk",
2420                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2421                         .num_parents = 1,
2422                         .flags = CLK_SET_RATE_PARENT,
2423                         .ops = &clk_branch2_ops,
2424                 },
2425         },
2426 };
2427
2428 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2429         .halt_reg = 0x6b00c,
2430         .clkr = {
2431                 .enable_reg = 0x6b00c,
2432                 .enable_mask = BIT(0),
2433                 .hw.init = &(struct clk_init_data){
2434                         .name = "gcc_pcie_0_mstr_axi_clk",
2435                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2436                         .num_parents = 1,
2437                         .flags = CLK_SET_RATE_PARENT,
2438                         .ops = &clk_branch2_ops,
2439                 },
2440         },
2441 };
2442
2443 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2444         .halt_reg = 0x6b010,
2445         .clkr = {
2446                 .enable_reg = 0x6b010,
2447                 .enable_mask = BIT(0),
2448                 .hw.init = &(struct clk_init_data){
2449                         .name = "gcc_pcie_0_cfg_ahb_clk",
2450                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2451                         .num_parents = 1,
2452                         .flags = CLK_SET_RATE_PARENT,
2453                         .ops = &clk_branch2_ops,
2454                 },
2455         },
2456 };
2457
2458 static struct clk_branch gcc_pcie_0_aux_clk = {
2459         .halt_reg = 0x6b014,
2460         .clkr = {
2461                 .enable_reg = 0x6b014,
2462                 .enable_mask = BIT(0),
2463                 .hw.init = &(struct clk_init_data){
2464                         .name = "gcc_pcie_0_aux_clk",
2465                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2466                         .num_parents = 1,
2467                         .flags = CLK_SET_RATE_PARENT,
2468                         .ops = &clk_branch2_ops,
2469                 },
2470         },
2471 };
2472
2473 static struct clk_branch gcc_pcie_0_pipe_clk = {
2474         .halt_reg = 0x6b018,
2475         .clkr = {
2476                 .enable_reg = 0x6b018,
2477                 .enable_mask = BIT(0),
2478                 .hw.init = &(struct clk_init_data){
2479                         .name = "gcc_pcie_0_pipe_clk",
2480                         .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2481                         .num_parents = 1,
2482                         .flags = CLK_SET_RATE_PARENT,
2483                         .ops = &clk_branch2_ops,
2484                 },
2485         },
2486 };
2487
2488 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2489         .halt_reg = 0x6d008,
2490         .clkr = {
2491                 .enable_reg = 0x6d008,
2492                 .enable_mask = BIT(0),
2493                 .hw.init = &(struct clk_init_data){
2494                         .name = "gcc_pcie_1_slv_axi_clk",
2495                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2496                         .num_parents = 1,
2497                         .flags = CLK_SET_RATE_PARENT,
2498                         .ops = &clk_branch2_ops,
2499                 },
2500         },
2501 };
2502
2503 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2504         .halt_reg = 0x6d00c,
2505         .clkr = {
2506                 .enable_reg = 0x6d00c,
2507                 .enable_mask = BIT(0),
2508                 .hw.init = &(struct clk_init_data){
2509                         .name = "gcc_pcie_1_mstr_axi_clk",
2510                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2511                         .num_parents = 1,
2512                         .flags = CLK_SET_RATE_PARENT,
2513                         .ops = &clk_branch2_ops,
2514                 },
2515         },
2516 };
2517
2518 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2519         .halt_reg = 0x6d010,
2520         .clkr = {
2521                 .enable_reg = 0x6d010,
2522                 .enable_mask = BIT(0),
2523                 .hw.init = &(struct clk_init_data){
2524                         .name = "gcc_pcie_1_cfg_ahb_clk",
2525                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2526                         .num_parents = 1,
2527                         .flags = CLK_SET_RATE_PARENT,
2528                         .ops = &clk_branch2_ops,
2529                 },
2530         },
2531 };
2532
2533 static struct clk_branch gcc_pcie_1_aux_clk = {
2534         .halt_reg = 0x6d014,
2535         .clkr = {
2536                 .enable_reg = 0x6d014,
2537                 .enable_mask = BIT(0),
2538                 .hw.init = &(struct clk_init_data){
2539                         .name = "gcc_pcie_1_aux_clk",
2540                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2541                         .num_parents = 1,
2542                         .flags = CLK_SET_RATE_PARENT,
2543                         .ops = &clk_branch2_ops,
2544                 },
2545         },
2546 };
2547
2548 static struct clk_branch gcc_pcie_1_pipe_clk = {
2549         .halt_reg = 0x6d018,
2550         .clkr = {
2551                 .enable_reg = 0x6d018,
2552                 .enable_mask = BIT(0),
2553                 .hw.init = &(struct clk_init_data){
2554                         .name = "gcc_pcie_1_pipe_clk",
2555                         .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2556                         .num_parents = 1,
2557                         .flags = CLK_SET_RATE_PARENT,
2558                         .ops = &clk_branch2_ops,
2559                 },
2560         },
2561 };
2562
2563 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2564         .halt_reg = 0x6e008,
2565         .clkr = {
2566                 .enable_reg = 0x6e008,
2567                 .enable_mask = BIT(0),
2568                 .hw.init = &(struct clk_init_data){
2569                         .name = "gcc_pcie_2_slv_axi_clk",
2570                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2571                         .num_parents = 1,
2572                         .flags = CLK_SET_RATE_PARENT,
2573                         .ops = &clk_branch2_ops,
2574                 },
2575         },
2576 };
2577
2578 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2579         .halt_reg = 0x6e00c,
2580         .clkr = {
2581                 .enable_reg = 0x6e00c,
2582                 .enable_mask = BIT(0),
2583                 .hw.init = &(struct clk_init_data){
2584                         .name = "gcc_pcie_2_mstr_axi_clk",
2585                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2586                         .num_parents = 1,
2587                         .flags = CLK_SET_RATE_PARENT,
2588                         .ops = &clk_branch2_ops,
2589                 },
2590         },
2591 };
2592
2593 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2594         .halt_reg = 0x6e010,
2595         .clkr = {
2596                 .enable_reg = 0x6e010,
2597                 .enable_mask = BIT(0),
2598                 .hw.init = &(struct clk_init_data){
2599                         .name = "gcc_pcie_2_cfg_ahb_clk",
2600                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2601                         .num_parents = 1,
2602                         .flags = CLK_SET_RATE_PARENT,
2603                         .ops = &clk_branch2_ops,
2604                 },
2605         },
2606 };
2607
2608 static struct clk_branch gcc_pcie_2_aux_clk = {
2609         .halt_reg = 0x6e014,
2610         .clkr = {
2611                 .enable_reg = 0x6e014,
2612                 .enable_mask = BIT(0),
2613                 .hw.init = &(struct clk_init_data){
2614                         .name = "gcc_pcie_2_aux_clk",
2615                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2616                         .num_parents = 1,
2617                         .flags = CLK_SET_RATE_PARENT,
2618                         .ops = &clk_branch2_ops,
2619                 },
2620         },
2621 };
2622
2623 static struct clk_branch gcc_pcie_2_pipe_clk = {
2624         .halt_reg = 0x6e018,
2625         .clkr = {
2626                 .enable_reg = 0x6e018,
2627                 .enable_mask = BIT(0),
2628                 .hw.init = &(struct clk_init_data){
2629                         .name = "gcc_pcie_2_pipe_clk",
2630                         .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2631                         .num_parents = 1,
2632                         .flags = CLK_SET_RATE_PARENT,
2633                         .ops = &clk_branch2_ops,
2634                 },
2635         },
2636 };
2637
2638 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2639         .halt_reg = 0x6f004,
2640         .clkr = {
2641                 .enable_reg = 0x6f004,
2642                 .enable_mask = BIT(0),
2643                 .hw.init = &(struct clk_init_data){
2644                         .name = "gcc_pcie_phy_cfg_ahb_clk",
2645                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2646                         .num_parents = 1,
2647                         .flags = CLK_SET_RATE_PARENT,
2648                         .ops = &clk_branch2_ops,
2649                 },
2650         },
2651 };
2652
2653 static struct clk_branch gcc_pcie_phy_aux_clk = {
2654         .halt_reg = 0x6f008,
2655         .clkr = {
2656                 .enable_reg = 0x6f008,
2657                 .enable_mask = BIT(0),
2658                 .hw.init = &(struct clk_init_data){
2659                         .name = "gcc_pcie_phy_aux_clk",
2660                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2661                         .num_parents = 1,
2662                         .flags = CLK_SET_RATE_PARENT,
2663                         .ops = &clk_branch2_ops,
2664                 },
2665         },
2666 };
2667
2668 static struct clk_branch gcc_ufs_axi_clk = {
2669         .halt_reg = 0x75008,
2670         .clkr = {
2671                 .enable_reg = 0x75008,
2672                 .enable_mask = BIT(0),
2673                 .hw.init = &(struct clk_init_data){
2674                         .name = "gcc_ufs_axi_clk",
2675                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2676                         .num_parents = 1,
2677                         .flags = CLK_SET_RATE_PARENT,
2678                         .ops = &clk_branch2_ops,
2679                 },
2680         },
2681 };
2682
2683 static struct clk_branch gcc_ufs_ahb_clk = {
2684         .halt_reg = 0x7500c,
2685         .clkr = {
2686                 .enable_reg = 0x7500c,
2687                 .enable_mask = BIT(0),
2688                 .hw.init = &(struct clk_init_data){
2689                         .name = "gcc_ufs_ahb_clk",
2690                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2691                         .num_parents = 1,
2692                         .flags = CLK_SET_RATE_PARENT,
2693                         .ops = &clk_branch2_ops,
2694                 },
2695         },
2696 };
2697
2698 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2699         .mult = 1,
2700         .div = 16,
2701         .hw.init = &(struct clk_init_data){
2702                 .name = "ufs_tx_cfg_clk_src",
2703                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2704                 .num_parents = 1,
2705                 .flags = CLK_SET_RATE_PARENT,
2706                 .ops = &clk_fixed_factor_ops,
2707         },
2708 };
2709
2710 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2711         .halt_reg = 0x75010,
2712         .clkr = {
2713                 .enable_reg = 0x75010,
2714                 .enable_mask = BIT(0),
2715                 .hw.init = &(struct clk_init_data){
2716                         .name = "gcc_ufs_tx_cfg_clk",
2717                         .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2718                         .num_parents = 1,
2719                         .flags = CLK_SET_RATE_PARENT,
2720                         .ops = &clk_branch2_ops,
2721                 },
2722         },
2723 };
2724
2725 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2726         .mult = 1,
2727         .div = 16,
2728         .hw.init = &(struct clk_init_data){
2729                 .name = "ufs_rx_cfg_clk_src",
2730                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2731                 .num_parents = 1,
2732                 .flags = CLK_SET_RATE_PARENT,
2733                 .ops = &clk_fixed_factor_ops,
2734         },
2735 };
2736
2737 static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2738         .halt_reg = 0x7d010,
2739         .halt_check = BRANCH_HALT_VOTED,
2740         .clkr = {
2741                 .enable_reg = 0x7d010,
2742                 .enable_mask = BIT(0),
2743                 .hw.init = &(struct clk_init_data){
2744                         .name = "hlos1_vote_lpass_core_smmu_clk",
2745                         .ops = &clk_branch2_ops,
2746                 },
2747         },
2748 };
2749
2750 static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2751         .halt_reg = 0x7d014,
2752         .halt_check = BRANCH_HALT_VOTED,
2753         .clkr = {
2754                 .enable_reg = 0x7d014,
2755                 .enable_mask = BIT(0),
2756                 .hw.init = &(struct clk_init_data){
2757                         .name = "hlos1_vote_lpass_adsp_smmu_clk",
2758                         .ops = &clk_branch2_ops,
2759                 },
2760         },
2761 };
2762
2763 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2764         .halt_reg = 0x75014,
2765         .clkr = {
2766                 .enable_reg = 0x75014,
2767                 .enable_mask = BIT(0),
2768                 .hw.init = &(struct clk_init_data){
2769                         .name = "gcc_ufs_rx_cfg_clk",
2770                         .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2771                         .num_parents = 1,
2772                         .flags = CLK_SET_RATE_PARENT,
2773                         .ops = &clk_branch2_ops,
2774                 },
2775         },
2776 };
2777
2778 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2779         .halt_reg = 0x75018,
2780         .clkr = {
2781                 .enable_reg = 0x75018,
2782                 .enable_mask = BIT(0),
2783                 .hw.init = &(struct clk_init_data){
2784                         .name = "gcc_ufs_tx_symbol_0_clk",
2785                         .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2786                         .num_parents = 1,
2787                         .flags = CLK_SET_RATE_PARENT,
2788                         .ops = &clk_branch2_ops,
2789                 },
2790         },
2791 };
2792
2793 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2794         .halt_reg = 0x7501c,
2795         .clkr = {
2796                 .enable_reg = 0x7501c,
2797                 .enable_mask = BIT(0),
2798                 .hw.init = &(struct clk_init_data){
2799                         .name = "gcc_ufs_rx_symbol_0_clk",
2800                         .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2801                         .num_parents = 1,
2802                         .flags = CLK_SET_RATE_PARENT,
2803                         .ops = &clk_branch2_ops,
2804                 },
2805         },
2806 };
2807
2808 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2809         .halt_reg = 0x75020,
2810         .clkr = {
2811                 .enable_reg = 0x75020,
2812                 .enable_mask = BIT(0),
2813                 .hw.init = &(struct clk_init_data){
2814                         .name = "gcc_ufs_rx_symbol_1_clk",
2815                         .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2816                         .num_parents = 1,
2817                         .flags = CLK_SET_RATE_PARENT,
2818                         .ops = &clk_branch2_ops,
2819                 },
2820         },
2821 };
2822
2823 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2824         .mult = 1,
2825         .div = 2,
2826         .hw.init = &(struct clk_init_data){
2827                 .name = "ufs_ice_core_postdiv_clk_src",
2828                 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2829                 .num_parents = 1,
2830                 .flags = CLK_SET_RATE_PARENT,
2831                 .ops = &clk_fixed_factor_ops,
2832         },
2833 };
2834
2835 static struct clk_branch gcc_ufs_unipro_core_clk = {
2836         .halt_reg = 0x7600c,
2837         .clkr = {
2838                 .enable_reg = 0x7600c,
2839                 .enable_mask = BIT(0),
2840                 .hw.init = &(struct clk_init_data){
2841                         .name = "gcc_ufs_unipro_core_clk",
2842                         .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2843                         .num_parents = 1,
2844                         .flags = CLK_SET_RATE_PARENT,
2845                         .ops = &clk_branch2_ops,
2846                 },
2847         },
2848 };
2849
2850 static struct clk_branch gcc_ufs_ice_core_clk = {
2851         .halt_reg = 0x76010,
2852         .clkr = {
2853                 .enable_reg = 0x76010,
2854                 .enable_mask = BIT(0),
2855                 .hw.init = &(struct clk_init_data){
2856                         .name = "gcc_ufs_ice_core_clk",
2857                         .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2858                         .num_parents = 1,
2859                         .flags = CLK_SET_RATE_PARENT,
2860                         .ops = &clk_branch2_ops,
2861                 },
2862         },
2863 };
2864
2865 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2866         .halt_check = BRANCH_HALT_DELAY,
2867         .clkr = {
2868                 .enable_reg = 0x76030,
2869                 .enable_mask = BIT(0),
2870                 .hw.init = &(struct clk_init_data){
2871                         .name = "gcc_ufs_sys_clk_core_clk",
2872                         .ops = &clk_branch2_ops,
2873                 },
2874         },
2875 };
2876
2877 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2878         .halt_check = BRANCH_HALT_DELAY,
2879         .clkr = {
2880                 .enable_reg = 0x76034,
2881                 .enable_mask = BIT(0),
2882                 .hw.init = &(struct clk_init_data){
2883                         .name = "gcc_ufs_tx_symbol_clk_core_clk",
2884                         .ops = &clk_branch2_ops,
2885                 },
2886         },
2887 };
2888
2889 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2890         .halt_reg = 0x81008,
2891         .clkr = {
2892                 .enable_reg = 0x81008,
2893                 .enable_mask = BIT(0),
2894                 .hw.init = &(struct clk_init_data){
2895                         .name = "gcc_aggre0_snoc_axi_clk",
2896                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2897                         .num_parents = 1,
2898                         .flags = CLK_SET_RATE_PARENT,
2899                         .ops = &clk_branch2_ops,
2900                 },
2901         },
2902 };
2903
2904 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2905         .halt_reg = 0x8100c,
2906         .clkr = {
2907                 .enable_reg = 0x8100c,
2908                 .enable_mask = BIT(0),
2909                 .hw.init = &(struct clk_init_data){
2910                         .name = "gcc_aggre0_cnoc_ahb_clk",
2911                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2912                         .num_parents = 1,
2913                         .flags = CLK_SET_RATE_PARENT,
2914                         .ops = &clk_branch2_ops,
2915                 },
2916         },
2917 };
2918
2919 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2920         .halt_reg = 0x81014,
2921         .clkr = {
2922                 .enable_reg = 0x81014,
2923                 .enable_mask = BIT(0),
2924                 .hw.init = &(struct clk_init_data){
2925                         .name = "gcc_smmu_aggre0_axi_clk",
2926                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2927                         .num_parents = 1,
2928                         .flags = CLK_SET_RATE_PARENT,
2929                         .ops = &clk_branch2_ops,
2930                 },
2931         },
2932 };
2933
2934 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2935         .halt_reg = 0x81018,
2936         .clkr = {
2937                 .enable_reg = 0x81018,
2938                 .enable_mask = BIT(0),
2939                 .hw.init = &(struct clk_init_data){
2940                         .name = "gcc_smmu_aggre0_ahb_clk",
2941                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2942                         .num_parents = 1,
2943                         .flags = CLK_SET_RATE_PARENT,
2944                         .ops = &clk_branch2_ops,
2945                 },
2946         },
2947 };
2948
2949 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2950         .halt_reg = 0x83014,
2951         .clkr = {
2952                 .enable_reg = 0x83014,
2953                 .enable_mask = BIT(0),
2954                 .hw.init = &(struct clk_init_data){
2955                         .name = "gcc_aggre2_ufs_axi_clk",
2956                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2957                         .num_parents = 1,
2958                         .flags = CLK_SET_RATE_PARENT,
2959                         .ops = &clk_branch2_ops,
2960                 },
2961         },
2962 };
2963
2964 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2965         .halt_reg = 0x83018,
2966         .clkr = {
2967                 .enable_reg = 0x83018,
2968                 .enable_mask = BIT(0),
2969                 .hw.init = &(struct clk_init_data){
2970                         .name = "gcc_aggre2_usb3_axi_clk",
2971                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
2972                         .num_parents = 1,
2973                         .flags = CLK_SET_RATE_PARENT,
2974                         .ops = &clk_branch2_ops,
2975                 },
2976         },
2977 };
2978
2979 static struct clk_branch gcc_qspi_ahb_clk = {
2980         .halt_reg = 0x8b004,
2981         .clkr = {
2982                 .enable_reg = 0x8b004,
2983                 .enable_mask = BIT(0),
2984                 .hw.init = &(struct clk_init_data){
2985                         .name = "gcc_qspi_ahb_clk",
2986                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2987                         .num_parents = 1,
2988                         .flags = CLK_SET_RATE_PARENT,
2989                         .ops = &clk_branch2_ops,
2990                 },
2991         },
2992 };
2993
2994 static struct clk_branch gcc_qspi_ser_clk = {
2995         .halt_reg = 0x8b008,
2996         .clkr = {
2997                 .enable_reg = 0x8b008,
2998                 .enable_mask = BIT(0),
2999                 .hw.init = &(struct clk_init_data){
3000                         .name = "gcc_qspi_ser_clk",
3001                         .parent_names = (const char *[]){ "qspi_ser_clk_src" },
3002                         .num_parents = 1,
3003                         .flags = CLK_SET_RATE_PARENT,
3004                         .ops = &clk_branch2_ops,
3005                 },
3006         },
3007 };
3008
3009 static struct clk_branch gcc_usb3_clkref_clk = {
3010         .halt_reg = 0x8800C,
3011         .clkr = {
3012                 .enable_reg = 0x8800C,
3013                 .enable_mask = BIT(0),
3014                 .hw.init = &(struct clk_init_data){
3015                         .name = "gcc_usb3_clkref_clk",
3016                         .parent_names = (const char *[]){ "xo" },
3017                         .num_parents = 1,
3018                         .ops = &clk_branch2_ops,
3019                 },
3020         },
3021 };
3022
3023 static struct clk_branch gcc_hdmi_clkref_clk = {
3024         .halt_reg = 0x88000,
3025         .clkr = {
3026                 .enable_reg = 0x88000,
3027                 .enable_mask = BIT(0),
3028                 .hw.init = &(struct clk_init_data){
3029                         .name = "gcc_hdmi_clkref_clk",
3030                         .parent_names = (const char *[]){ "xo" },
3031                         .num_parents = 1,
3032                         .ops = &clk_branch2_ops,
3033                 },
3034         },
3035 };
3036
3037 static struct clk_branch gcc_ufs_clkref_clk = {
3038         .halt_reg = 0x88008,
3039         .clkr = {
3040                 .enable_reg = 0x88008,
3041                 .enable_mask = BIT(0),
3042                 .hw.init = &(struct clk_init_data){
3043                         .name = "gcc_ufs_clkref_clk",
3044                         .parent_names = (const char *[]){ "xo" },
3045                         .num_parents = 1,
3046                         .ops = &clk_branch2_ops,
3047                 },
3048         },
3049 };
3050
3051 static struct clk_branch gcc_pcie_clkref_clk = {
3052         .halt_reg = 0x88010,
3053         .clkr = {
3054                 .enable_reg = 0x88010,
3055                 .enable_mask = BIT(0),
3056                 .hw.init = &(struct clk_init_data){
3057                         .name = "gcc_pcie_clkref_clk",
3058                         .parent_names = (const char *[]){ "xo" },
3059                         .num_parents = 1,
3060                         .ops = &clk_branch2_ops,
3061                 },
3062         },
3063 };
3064
3065 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3066         .halt_reg = 0x88014,
3067         .clkr = {
3068                 .enable_reg = 0x88014,
3069                 .enable_mask = BIT(0),
3070                 .hw.init = &(struct clk_init_data){
3071                         .name = "gcc_rx2_usb2_clkref_clk",
3072                         .parent_names = (const char *[]){ "xo" },
3073                         .num_parents = 1,
3074                         .ops = &clk_branch2_ops,
3075                 },
3076         },
3077 };
3078
3079 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3080         .halt_reg = 0x88018,
3081         .clkr = {
3082                 .enable_reg = 0x88018,
3083                 .enable_mask = BIT(0),
3084                 .hw.init = &(struct clk_init_data){
3085                         .name = "gcc_rx1_usb2_clkref_clk",
3086                         .parent_names = (const char *[]){ "xo" },
3087                         .num_parents = 1,
3088                         .ops = &clk_branch2_ops,
3089                 },
3090         },
3091 };
3092
3093 static struct clk_hw *gcc_msm8996_hws[] = {
3094         &xo.hw,
3095         &gpll0_early_div.hw,
3096         &ufs_tx_cfg_clk_src.hw,
3097         &ufs_rx_cfg_clk_src.hw,
3098         &ufs_ice_core_postdiv_clk_src.hw,
3099 };
3100
3101 static struct gdsc aggre0_noc_gdsc = {
3102         .gdscr = 0x81004,
3103         .gds_hw_ctrl = 0x81028,
3104         .pd = {
3105                 .name = "aggre0_noc",
3106         },
3107         .pwrsts = PWRSTS_OFF_ON,
3108         .flags = VOTABLE,
3109 };
3110
3111 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3112         .gdscr = 0x7d024,
3113         .pd = {
3114                 .name = "hlos1_vote_aggre0_noc",
3115         },
3116         .pwrsts = PWRSTS_OFF_ON,
3117         .flags = VOTABLE,
3118 };
3119
3120 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3121         .gdscr = 0x7d034,
3122         .pd = {
3123                 .name = "hlos1_vote_lpass_adsp",
3124         },
3125         .pwrsts = PWRSTS_OFF_ON,
3126         .flags = VOTABLE,
3127 };
3128
3129 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3130         .gdscr = 0x7d038,
3131         .pd = {
3132                 .name = "hlos1_vote_lpass_core",
3133         },
3134         .pwrsts = PWRSTS_OFF_ON,
3135         .flags = VOTABLE,
3136 };
3137
3138 static struct gdsc usb30_gdsc = {
3139         .gdscr = 0xf004,
3140         .pd = {
3141                 .name = "usb30",
3142         },
3143         .pwrsts = PWRSTS_OFF_ON,
3144 };
3145
3146 static struct gdsc pcie0_gdsc = {
3147         .gdscr = 0x6b004,
3148         .pd = {
3149                 .name = "pcie0",
3150         },
3151         .pwrsts = PWRSTS_OFF_ON,
3152 };
3153
3154 static struct gdsc pcie1_gdsc = {
3155         .gdscr = 0x6d004,
3156         .pd = {
3157                 .name = "pcie1",
3158         },
3159         .pwrsts = PWRSTS_OFF_ON,
3160 };
3161
3162 static struct gdsc pcie2_gdsc = {
3163         .gdscr = 0x6e004,
3164         .pd = {
3165                 .name = "pcie2",
3166         },
3167         .pwrsts = PWRSTS_OFF_ON,
3168 };
3169
3170 static struct gdsc ufs_gdsc = {
3171         .gdscr = 0x75004,
3172         .pd = {
3173                 .name = "ufs",
3174         },
3175         .pwrsts = PWRSTS_OFF_ON,
3176 };
3177
3178 static struct clk_regmap *gcc_msm8996_clocks[] = {
3179         [GPLL0_EARLY] = &gpll0_early.clkr,
3180         [GPLL0] = &gpll0.clkr,
3181         [GPLL4_EARLY] = &gpll4_early.clkr,
3182         [GPLL4] = &gpll4.clkr,
3183         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3184         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3185         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3186         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3187         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3188         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3189         [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3190         [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3191         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3192         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3193         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3194         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3195         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3196         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3197         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3198         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3199         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3200         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3201         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3202         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3203         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3204         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3205         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3206         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3207         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3208         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3209         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3210         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3211         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3212         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3213         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3214         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3215         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3216         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3217         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3218         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3219         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3220         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3221         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3222         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3223         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3224         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3225         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3226         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3227         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3228         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3229         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3230         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3231         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3232         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3233         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3234         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3235         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3236         [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3237         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3238         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3239         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3240         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3241         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3242         [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3243         [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3244         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3245         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3246         [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3247         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3248         [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3249         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3250         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3251         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3252         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3253         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3254         [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3255         [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3256         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3257         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3258         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3259         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3260         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3261         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3262         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3263         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3264         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3265         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3266         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3267         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3268         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3269         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3270         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3271         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3272         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3273         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3274         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3275         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3276         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3277         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3278         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3279         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3280         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3281         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3282         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3283         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3284         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3285         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3286         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3287         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3288         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3289         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3290         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3291         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3292         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3293         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3294         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3295         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3296         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3297         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3298         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3299         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3300         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3301         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3302         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3303         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3304         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3305         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3306         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3307         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3308         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3309         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3310         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3311         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3312         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3313         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3314         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3315         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3316         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3317         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3318         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3319         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3320         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3321         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3322         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3323         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3324         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3325         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3326         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3327         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3328         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3329         [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3330         [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3331         [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3332         [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3333         [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3334         [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3335         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3336         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3337         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3338         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3339         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3340         [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3341         [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3342         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3343         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3344         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3345         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3346         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3347         [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3348         [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3349         [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3350         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3351         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3352         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3353         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3354         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3355         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3356         [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3357         [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3358         [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3359         [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3360         [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3361         [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3362         [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3363 };
3364
3365 static struct gdsc *gcc_msm8996_gdscs[] = {
3366         [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3367         [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3368         [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3369         [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3370         [USB30_GDSC] = &usb30_gdsc,
3371         [PCIE0_GDSC] = &pcie0_gdsc,
3372         [PCIE1_GDSC] = &pcie1_gdsc,
3373         [PCIE2_GDSC] = &pcie2_gdsc,
3374         [UFS_GDSC] = &ufs_gdsc,
3375 };
3376
3377 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3378         [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3379         [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3380         [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3381         [GCC_IMEM_BCR] = { 0x8000 },
3382         [GCC_MMSS_BCR] = { 0x9000 },
3383         [GCC_PIMEM_BCR] = { 0x0a000 },
3384         [GCC_QDSS_BCR] = { 0x0c000 },
3385         [GCC_USB_30_BCR] = { 0x0f000 },
3386         [GCC_USB_20_BCR] = { 0x12000 },
3387         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3388         [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3389         [GCC_USB3_PHY_BCR] = { 0x50020 },
3390         [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3391         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3392         [GCC_SDCC1_BCR] = { 0x13000 },
3393         [GCC_SDCC2_BCR] = { 0x14000 },
3394         [GCC_SDCC3_BCR] = { 0x15000 },
3395         [GCC_SDCC4_BCR] = { 0x16000 },
3396         [GCC_BLSP1_BCR] = { 0x17000 },
3397         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3398         [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3399         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3400         [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3401         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3402         [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3403         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3404         [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3405         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3406         [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3407         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3408         [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3409         [GCC_BLSP2_BCR] = { 0x25000 },
3410         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3411         [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3412         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3413         [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3414         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3415         [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3416         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3417         [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3418         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3419         [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3420         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3421         [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3422         [GCC_PDM_BCR] = { 0x33000 },
3423         [GCC_PRNG_BCR] = { 0x34000 },
3424         [GCC_TSIF_BCR] = { 0x36000 },
3425         [GCC_TCSR_BCR] = { 0x37000 },
3426         [GCC_BOOT_ROM_BCR] = { 0x38000 },
3427         [GCC_MSG_RAM_BCR] = { 0x39000 },
3428         [GCC_TLMM_BCR] = { 0x3a000 },
3429         [GCC_MPM_BCR] = { 0x3b000 },
3430         [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3431         [GCC_SPMI_BCR] = { 0x3f000 },
3432         [GCC_SPDM_BCR] = { 0x40000 },
3433         [GCC_CE1_BCR] = { 0x41000 },
3434         [GCC_BIMC_BCR] = { 0x44000 },
3435         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3436         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3437         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3438         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3439         [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3440         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3441         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3442         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3443         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3444         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3445         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3446         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3447         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3448         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3449         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3450         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3451         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3452         [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3453         [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3454         [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3455         [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3456         [GCC_APB2JTAG_BCR] = { 0x4c000 },
3457         [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3458         [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3459         [GCC_PCIE_0_BCR] = { 0x6b000 },
3460         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3461         [GCC_PCIE_1_BCR] = { 0x6d000 },
3462         [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3463         [GCC_PCIE_2_BCR] = { 0x6e000 },
3464         [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3465         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3466         [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3467         [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3468         [GCC_DCD_BCR] = { 0x70000 },
3469         [GCC_OBT_ODT_BCR] = { 0x73000 },
3470         [GCC_UFS_BCR] = { 0x75000 },
3471         [GCC_SSC_BCR] = { 0x63000 },
3472         [GCC_VS_BCR] = { 0x7a000 },
3473         [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3474         [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3475         [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3476         [GCC_DCC_BCR] = { 0x84000 },
3477         [GCC_IPA_BCR] = { 0x89000 },
3478         [GCC_QSPI_BCR] = { 0x8b000 },
3479         [GCC_SKL_BCR] = { 0x8c000 },
3480         [GCC_MSMPU_BCR] = { 0x8d000 },
3481         [GCC_MSS_Q6_BCR] = { 0x8e000 },
3482         [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3483         [GCC_MSS_RESTART] = { 0x8f008 },
3484 };
3485
3486 static const struct regmap_config gcc_msm8996_regmap_config = {
3487         .reg_bits       = 32,
3488         .reg_stride     = 4,
3489         .val_bits       = 32,
3490         .max_register   = 0x8f010,
3491         .fast_io        = true,
3492 };
3493
3494 static const struct qcom_cc_desc gcc_msm8996_desc = {
3495         .config = &gcc_msm8996_regmap_config,
3496         .clks = gcc_msm8996_clocks,
3497         .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3498         .resets = gcc_msm8996_resets,
3499         .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3500         .gdscs = gcc_msm8996_gdscs,
3501         .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3502 };
3503
3504 static const struct of_device_id gcc_msm8996_match_table[] = {
3505         { .compatible = "qcom,gcc-msm8996" },
3506         { }
3507 };
3508 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3509
3510 static int gcc_msm8996_probe(struct platform_device *pdev)
3511 {
3512         struct device *dev = &pdev->dev;
3513         int i, ret;
3514         struct regmap *regmap;
3515
3516         regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3517         if (IS_ERR(regmap))
3518                 return PTR_ERR(regmap);
3519
3520         /*
3521          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3522          * turned off by hardware during certain apps low power modes.
3523          */
3524         regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3525
3526         for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3527                 ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
3528                 if (ret)
3529                         return ret;
3530         }
3531
3532         return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3533 }
3534
3535 static struct platform_driver gcc_msm8996_driver = {
3536         .probe          = gcc_msm8996_probe,
3537         .driver         = {
3538                 .name   = "gcc-msm8996",
3539                 .of_match_table = gcc_msm8996_match_table,
3540         },
3541 };
3542
3543 static int __init gcc_msm8996_init(void)
3544 {
3545         return platform_driver_register(&gcc_msm8996_driver);
3546 }
3547 core_initcall(gcc_msm8996_init);
3548
3549 static void __exit gcc_msm8996_exit(void)
3550 {
3551         platform_driver_unregister(&gcc_msm8996_driver);
3552 }
3553 module_exit(gcc_msm8996_exit);
3554
3555 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3556 MODULE_LICENSE("GPL v2");
3557 MODULE_ALIAS("platform:gcc-msm8996");