drivers/clk/qcom/gcc-ipq8074.c

   1 /*
   2  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/regmap.h>
  22
  23 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  24
  25 #include "common.h"
  26 #include "clk-regmap.h"
  27 #include "clk-pll.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "clk-alpha-pll.h"
  31 #include "clk-regmap-divider.h"
  32 #include "clk-regmap-mux.h"
  33 #include "reset.h"
  34
  35 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  36
  37 enum {
  38         P_XO,
  39         P_GPLL0,
  40         P_GPLL0_DIV2,
  41         P_GPLL2,
  42         P_GPLL4,
  43         P_GPLL6,
  44         P_SLEEP_CLK,
  45         P_PCIE20_PHY0_PIPE,
  46         P_PCIE20_PHY1_PIPE,
  47         P_USB3PHY_0_PIPE,
  48         P_USB3PHY_1_PIPE,
  49         P_UBI32_PLL,
  50         P_NSS_CRYPTO_PLL,
  51         P_BIAS_PLL,
  52         P_BIAS_PLL_NSS_NOC,
  53         P_UNIPHY0_RX,
  54         P_UNIPHY0_TX,
  55         P_UNIPHY1_RX,
  56         P_UNIPHY1_TX,
  57         P_UNIPHY2_RX,
  58         P_UNIPHY2_TX,
  59 };
  60
  61 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
  62         "xo",
  63         "gpll0",
  64         "gpll0_out_main_div2",
  65 };
  66
  67 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  68         { P_XO, 0 },
  69         { P_GPLL0, 1 },
  70         { P_GPLL0_DIV2, 4 },
  71 };
  72
  73 static const char * const gcc_xo_gpll0[] = {
  74         "xo",
  75         "gpll0",
  76 };
  77
  78 static const struct parent_map gcc_xo_gpll0_map[] = {
  79         { P_XO, 0 },
  80         { P_GPLL0, 1 },
  81 };
  82
  83 static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
  84         "xo",
  85         "gpll0",
  86         "gpll2",
  87         "gpll0_out_main_div2",
  88 };
  89
  90 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
  91         { P_XO, 0 },
  92         { P_GPLL0, 1 },
  93         { P_GPLL2, 2 },
  94         { P_GPLL0_DIV2, 4 },
  95 };
  96
  97 static const char * const gcc_xo_gpll0_sleep_clk[] = {
  98         "xo",
  99         "gpll0",
 100         "sleep_clk",
 101 };
 102
 103 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
 104         { P_XO, 0 },
 105         { P_GPLL0, 2 },
 106         { P_SLEEP_CLK, 6 },
 107 };
 108
 109 static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
 110         "xo",
 111         "gpll6",
 112         "gpll0",
 113         "gpll0_out_main_div2",
 114 };
 115
 116 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 117         { P_XO, 0 },
 118         { P_GPLL6, 1 },
 119         { P_GPLL0, 3 },
 120         { P_GPLL0_DIV2, 4 },
 121 };
 122
 123 static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
 124         "xo",
 125         "gpll0_out_main_div2",
 126         "gpll0",
 127 };
 128
 129 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 130         { P_XO, 0 },
 131         { P_GPLL0_DIV2, 2 },
 132         { P_GPLL0, 1 },
 133 };
 134
 135 static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 136         "usb3phy_0_cc_pipe_clk",
 137         "xo",
 138 };
 139
 140 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 141         { P_USB3PHY_0_PIPE, 0 },
 142         { P_XO, 2 },
 143 };
 144
 145 static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
 146         "usb3phy_1_cc_pipe_clk",
 147         "xo",
 148 };
 149
 150 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
 151         { P_USB3PHY_1_PIPE, 0 },
 152         { P_XO, 2 },
 153 };
 154
 155 static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
 156         "pcie20_phy0_pipe_clk",
 157         "xo",
 158 };
 159
 160 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 161         { P_PCIE20_PHY0_PIPE, 0 },
 162         { P_XO, 2 },
 163 };
 164
 165 static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
 166         "pcie20_phy1_pipe_clk",
 167         "xo",
 168 };
 169
 170 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 171         { P_PCIE20_PHY1_PIPE, 0 },
 172         { P_XO, 2 },
 173 };
 174
 175 static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 176         "xo",
 177         "gpll0",
 178         "gpll6",
 179         "gpll0_out_main_div2",
 180 };
 181
 182 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 183         { P_XO, 0 },
 184         { P_GPLL0, 1 },
 185         { P_GPLL6, 2 },
 186         { P_GPLL0_DIV2, 4 },
 187 };
 188
 189 static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 190         "xo",
 191         "gpll0",
 192         "gpll6",
 193         "gpll0_out_main_div2",
 194 };
 195
 196 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 197         { P_XO, 0 },
 198         { P_GPLL0, 1 },
 199         { P_GPLL6, 2 },
 200         { P_GPLL0_DIV2, 3 },
 201 };
 202
 203 static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
 204         "xo",
 205         "bias_pll_nss_noc_clk",
 206         "gpll0",
 207         "gpll2",
 208 };
 209
 210 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
 211         { P_XO, 0 },
 212         { P_BIAS_PLL_NSS_NOC, 1 },
 213         { P_GPLL0, 2 },
 214         { P_GPLL2, 3 },
 215 };
 216
 217 static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
 218         "xo",
 219         "nss_crypto_pll",
 220         "gpll0",
 221 };
 222
 223 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 224         { P_XO, 0 },
 225         { P_NSS_CRYPTO_PLL, 1 },
 226         { P_GPLL0, 2 },
 227 };
 228
 229 static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
 230         "xo",
 231         "ubi32_pll",
 232         "gpll0",
 233         "gpll2",
 234         "gpll4",
 235         "gpll6",
 236 };
 237
 238 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
 239         { P_XO, 0 },
 240         { P_UBI32_PLL, 1 },
 241         { P_GPLL0, 2 },
 242         { P_GPLL2, 3 },
 243         { P_GPLL4, 4 },
 244         { P_GPLL6, 5 },
 245 };
 246
 247 static const char * const gcc_xo_gpll0_out_main_div2[] = {
 248         "xo",
 249         "gpll0_out_main_div2",
 250 };
 251
 252 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
 253         { P_XO, 0 },
 254         { P_GPLL0_DIV2, 1 },
 255 };
 256
 257 static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 258         "xo",
 259         "bias_pll_cc_clk",
 260         "gpll0",
 261         "gpll4",
 262         "nss_crypto_pll",
 263         "ubi32_pll",
 264 };
 265
 266 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 267         { P_XO, 0 },
 268         { P_BIAS_PLL, 1 },
 269         { P_GPLL0, 2 },
 270         { P_GPLL4, 3 },
 271         { P_NSS_CRYPTO_PLL, 4 },
 272         { P_UBI32_PLL, 5 },
 273 };
 274
 275 static const char * const gcc_xo_gpll0_gpll4[] = {
 276         "xo",
 277         "gpll0",
 278         "gpll4",
 279 };
 280
 281 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 282         { P_XO, 0 },
 283         { P_GPLL0, 1 },
 284         { P_GPLL4, 2 },
 285 };
 286
 287 static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 288         "xo",
 289         "uniphy0_gcc_rx_clk",
 290         "uniphy0_gcc_tx_clk",
 291         "ubi32_pll",
 292         "bias_pll_cc_clk",
 293 };
 294
 295 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 296         { P_XO, 0 },
 297         { P_UNIPHY0_RX, 1 },
 298         { P_UNIPHY0_TX, 2 },
 299         { P_UBI32_PLL, 5 },
 300         { P_BIAS_PLL, 6 },
 301 };
 302
 303 static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 304         "xo",
 305         "uniphy0_gcc_tx_clk",
 306         "uniphy0_gcc_rx_clk",
 307         "ubi32_pll",
 308         "bias_pll_cc_clk",
 309 };
 310
 311 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 312         { P_XO, 0 },
 313         { P_UNIPHY0_TX, 1 },
 314         { P_UNIPHY0_RX, 2 },
 315         { P_UBI32_PLL, 5 },
 316         { P_BIAS_PLL, 6 },
 317 };
 318
 319 static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 320         "xo",
 321         "uniphy0_gcc_rx_clk",
 322         "uniphy0_gcc_tx_clk",
 323         "uniphy1_gcc_rx_clk",
 324         "uniphy1_gcc_tx_clk",
 325         "ubi32_pll",
 326         "bias_pll_cc_clk",
 327 };
 328
 329 static const struct parent_map
 330 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 331         { P_XO, 0 },
 332         { P_UNIPHY0_RX, 1 },
 333         { P_UNIPHY0_TX, 2 },
 334         { P_UNIPHY1_RX, 3 },
 335         { P_UNIPHY1_TX, 4 },
 336         { P_UBI32_PLL, 5 },
 337         { P_BIAS_PLL, 6 },
 338 };
 339
 340 static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 341         "xo",
 342         "uniphy0_gcc_tx_clk",
 343         "uniphy0_gcc_rx_clk",
 344         "uniphy1_gcc_tx_clk",
 345         "uniphy1_gcc_rx_clk",
 346         "ubi32_pll",
 347         "bias_pll_cc_clk",
 348 };
 349
 350 static const struct parent_map
 351 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 352         { P_XO, 0 },
 353         { P_UNIPHY0_TX, 1 },
 354         { P_UNIPHY0_RX, 2 },
 355         { P_UNIPHY1_TX, 3 },
 356         { P_UNIPHY1_RX, 4 },
 357         { P_UBI32_PLL, 5 },
 358         { P_BIAS_PLL, 6 },
 359 };
 360
 361 static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
 362         "xo",
 363         "uniphy2_gcc_rx_clk",
 364         "uniphy2_gcc_tx_clk",
 365         "ubi32_pll",
 366         "bias_pll_cc_clk",
 367 };
 368
 369 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
 370         { P_XO, 0 },
 371         { P_UNIPHY2_RX, 1 },
 372         { P_UNIPHY2_TX, 2 },
 373         { P_UBI32_PLL, 5 },
 374         { P_BIAS_PLL, 6 },
 375 };
 376
 377 static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
 378         "xo",
 379         "uniphy2_gcc_tx_clk",
 380         "uniphy2_gcc_rx_clk",
 381         "ubi32_pll",
 382         "bias_pll_cc_clk",
 383 };
 384
 385 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
 386         { P_XO, 0 },
 387         { P_UNIPHY2_TX, 1 },
 388         { P_UNIPHY2_RX, 2 },
 389         { P_UBI32_PLL, 5 },
 390         { P_BIAS_PLL, 6 },
 391 };
 392
 393 static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
 394         "xo",
 395         "gpll0",
 396         "gpll6",
 397         "gpll0_out_main_div2",
 398         "sleep_clk",
 399 };
 400
 401 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
 402         { P_XO, 0 },
 403         { P_GPLL0, 1 },
 404         { P_GPLL6, 2 },
 405         { P_GPLL0_DIV2, 4 },
 406         { P_SLEEP_CLK, 6 },
 407 };
 408
 409 static struct clk_alpha_pll gpll0_main = {
 410         .offset = 0x21000,
 411         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 412         .clkr = {
 413                 .enable_reg = 0x0b000,
 414                 .enable_mask = BIT(0),
 415                 .hw.init = &(struct clk_init_data){
 416                         .name = "gpll0_main",
 417                         .parent_names = (const char *[]){
 418                                 "xo"
 419                         },
 420                         .num_parents = 1,
 421                         .ops = &clk_alpha_pll_ops,
 422                 },
 423         },
 424 };
 425
 426 static struct clk_fixed_factor gpll0_out_main_div2 = {
 427         .mult = 1,
 428         .div = 2,
 429         .hw.init = &(struct clk_init_data){
 430                 .name = "gpll0_out_main_div2",
 431                 .parent_names = (const char *[]){
 432                         "gpll0_main"
 433                 },
 434                 .num_parents = 1,
 435                 .ops = &clk_fixed_factor_ops,
 436                 .flags = CLK_SET_RATE_PARENT,
 437         },
 438 };
 439
 440 static struct clk_alpha_pll_postdiv gpll0 = {
 441         .offset = 0x21000,
 442         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 443         .width = 4,
 444         .clkr.hw.init = &(struct clk_init_data){
 445                 .name = "gpll0",
 446                 .parent_names = (const char *[]){
 447                         "gpll0_main"
 448                 },
 449                 .num_parents = 1,
 450                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 451         },
 452 };
 453
 454 static struct clk_alpha_pll gpll2_main = {
 455         .offset = 0x4a000,
 456         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 457         .clkr = {
 458                 .enable_reg = 0x0b000,
 459                 .enable_mask = BIT(2),
 460                 .hw.init = &(struct clk_init_data){
 461                         .name = "gpll2_main",
 462                         .parent_names = (const char *[]){
 463                                 "xo"
 464                         },
 465                         .num_parents = 1,
 466                         .ops = &clk_alpha_pll_ops,
 467                         .flags = CLK_IS_CRITICAL,
 468                 },
 469         },
 470 };
 471
 472 static struct clk_alpha_pll_postdiv gpll2 = {
 473         .offset = 0x4a000,
 474         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 475         .width = 4,
 476         .clkr.hw.init = &(struct clk_init_data){
 477                 .name = "gpll2",
 478                 .parent_names = (const char *[]){
 479                         "gpll2_main"
 480                 },
 481                 .num_parents = 1,
 482                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 483                 .flags = CLK_SET_RATE_PARENT,
 484         },
 485 };
 486
 487 static struct clk_alpha_pll gpll4_main = {
 488         .offset = 0x24000,
 489         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 490         .clkr = {
 491                 .enable_reg = 0x0b000,
 492                 .enable_mask = BIT(5),
 493                 .hw.init = &(struct clk_init_data){
 494                         .name = "gpll4_main",
 495                         .parent_names = (const char *[]){
 496                                 "xo"
 497                         },
 498                         .num_parents = 1,
 499                         .ops = &clk_alpha_pll_ops,
 500                         .flags = CLK_IS_CRITICAL,
 501                 },
 502         },
 503 };
 504
 505 static struct clk_alpha_pll_postdiv gpll4 = {
 506         .offset = 0x24000,
 507         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 508         .width = 4,
 509         .clkr.hw.init = &(struct clk_init_data){
 510                 .name = "gpll4",
 511                 .parent_names = (const char *[]){
 512                         "gpll4_main"
 513                 },
 514                 .num_parents = 1,
 515                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 516                 .flags = CLK_SET_RATE_PARENT,
 517         },
 518 };
 519
 520 static struct clk_alpha_pll gpll6_main = {
 521         .offset = 0x37000,
 522         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 523         .flags = SUPPORTS_DYNAMIC_UPDATE,
 524         .clkr = {
 525                 .enable_reg = 0x0b000,
 526                 .enable_mask = BIT(7),
 527                 .hw.init = &(struct clk_init_data){
 528                         .name = "gpll6_main",
 529                         .parent_names = (const char *[]){
 530                                 "xo"
 531                         },
 532                         .num_parents = 1,
 533                         .ops = &clk_alpha_pll_ops,
 534                         .flags = CLK_IS_CRITICAL,
 535                 },
 536         },
 537 };
 538
 539 static struct clk_alpha_pll_postdiv gpll6 = {
 540         .offset = 0x37000,
 541         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 542         .width = 2,
 543         .clkr.hw.init = &(struct clk_init_data){
 544                 .name = "gpll6",
 545                 .parent_names = (const char *[]){
 546                         "gpll6_main"
 547                 },
 548                 .num_parents = 1,
 549                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 550                 .flags = CLK_SET_RATE_PARENT,
 551         },
 552 };
 553
 554 static struct clk_fixed_factor gpll6_out_main_div2 = {
 555         .mult = 1,
 556         .div = 2,
 557         .hw.init = &(struct clk_init_data){
 558                 .name = "gpll6_out_main_div2",
 559                 .parent_names = (const char *[]){
 560                         "gpll6_main"
 561                 },
 562                 .num_parents = 1,
 563                 .ops = &clk_fixed_factor_ops,
 564                 .flags = CLK_SET_RATE_PARENT,
 565         },
 566 };
 567
 568 static struct clk_alpha_pll ubi32_pll_main = {
 569         .offset = 0x25000,
 570         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 571         .flags = SUPPORTS_DYNAMIC_UPDATE,
 572         .clkr = {
 573                 .enable_reg = 0x0b000,
 574                 .enable_mask = BIT(6),
 575                 .hw.init = &(struct clk_init_data){
 576                         .name = "ubi32_pll_main",
 577                         .parent_names = (const char *[]){
 578                                 "xo"
 579                         },
 580                         .num_parents = 1,
 581                         .ops = &clk_alpha_pll_huayra_ops,
 582                 },
 583         },
 584 };
 585
 586 static struct clk_alpha_pll_postdiv ubi32_pll = {
 587         .offset = 0x25000,
 588         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 589         .width = 2,
 590         .clkr.hw.init = &(struct clk_init_data){
 591                 .name = "ubi32_pll",
 592                 .parent_names = (const char *[]){
 593                         "ubi32_pll_main"
 594                 },
 595                 .num_parents = 1,
 596                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 597                 .flags = CLK_SET_RATE_PARENT,
 598         },
 599 };
 600
 601 static struct clk_alpha_pll nss_crypto_pll_main = {
 602         .offset = 0x22000,
 603         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 604         .clkr = {
 605                 .enable_reg = 0x0b000,
 606                 .enable_mask = BIT(4),
 607                 .hw.init = &(struct clk_init_data){
 608                         .name = "nss_crypto_pll_main",
 609                         .parent_names = (const char *[]){
 610                                 "xo"
 611                         },
 612                         .num_parents = 1,
 613                         .ops = &clk_alpha_pll_ops,
 614                 },
 615         },
 616 };
 617
 618 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 619         .offset = 0x22000,
 620         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 621         .width = 4,
 622         .clkr.hw.init = &(struct clk_init_data){
 623                 .name = "nss_crypto_pll",
 624                 .parent_names = (const char *[]){
 625                         "nss_crypto_pll_main"
 626                 },
 627                 .num_parents = 1,
 628                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 629                 .flags = CLK_SET_RATE_PARENT,
 630         },
 631 };
 632
 633 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 634         F(19200000, P_XO, 1, 0, 0),
 635         F(50000000, P_GPLL0, 16, 0, 0),
 636         F(100000000, P_GPLL0, 8, 0, 0),
 637         { }
 638 };
 639
 640 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 641         .cmd_rcgr = 0x27000,
 642         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 643         .hid_width = 5,
 644         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 645         .clkr.hw.init = &(struct clk_init_data){
 646                 .name = "pcnoc_bfdcd_clk_src",
 647                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 648                 .num_parents = 3,
 649                 .ops = &clk_rcg2_ops,
 650                 .flags = CLK_IS_CRITICAL,
 651         },
 652 };
 653
 654 static struct clk_fixed_factor pcnoc_clk_src = {
 655         .mult = 1,
 656         .div = 1,
 657         .hw.init = &(struct clk_init_data){
 658                 .name = "pcnoc_clk_src",
 659                 .parent_names = (const char *[]){
 660                         "pcnoc_bfdcd_clk_src"
 661                 },
 662                 .num_parents = 1,
 663                 .ops = &clk_fixed_factor_ops,
 664                 .flags = CLK_SET_RATE_PARENT,
 665         },
 666 };
 667
 668 static struct clk_branch gcc_sleep_clk_src = {
 669         .halt_reg = 0x30000,
 670         .clkr = {
 671                 .enable_reg = 0x30000,
 672                 .enable_mask = BIT(1),
 673                 .hw.init = &(struct clk_init_data){
 674                         .name = "gcc_sleep_clk_src",
 675                         .parent_names = (const char *[]){
 676                                 "sleep_clk"
 677                         },
 678                         .num_parents = 1,
 679                         .ops = &clk_branch2_ops,
 680                 },
 681         },
 682 };
 683
 684 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 685         F(19200000, P_XO, 1, 0, 0),
 686         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 687         F(50000000, P_GPLL0, 16, 0, 0),
 688         { }
 689 };
 690
 691 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 692         .cmd_rcgr = 0x0200c,
 693         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 694         .hid_width = 5,
 695         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 696         .clkr.hw.init = &(struct clk_init_data){
 697                 .name = "blsp1_qup1_i2c_apps_clk_src",
 698                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 699                 .num_parents = 3,
 700                 .ops = &clk_rcg2_ops,
 701         },
 702 };
 703
 704 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 705         F(960000, P_XO, 10, 1, 2),
 706         F(4800000, P_XO, 4, 0, 0),
 707         F(9600000, P_XO, 2, 0, 0),
 708         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 709         F(16000000, P_GPLL0, 10, 1, 5),
 710         F(19200000, P_XO, 1, 0, 0),
 711         F(25000000, P_GPLL0, 16, 1, 2),
 712         F(50000000, P_GPLL0, 16, 0, 0),
 713         { }
 714 };
 715
 716 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 717         .cmd_rcgr = 0x02024,
 718         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 719         .mnd_width = 8,
 720         .hid_width = 5,
 721         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 722         .clkr.hw.init = &(struct clk_init_data){
 723                 .name = "blsp1_qup1_spi_apps_clk_src",
 724                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 725                 .num_parents = 3,
 726                 .ops = &clk_rcg2_ops,
 727         },
 728 };
 729
 730 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 731         .cmd_rcgr = 0x03000,
 732         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 733         .hid_width = 5,
 734         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 735         .clkr.hw.init = &(struct clk_init_data){
 736                 .name = "blsp1_qup2_i2c_apps_clk_src",
 737                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 738                 .num_parents = 3,
 739                 .ops = &clk_rcg2_ops,
 740         },
 741 };
 742
 743 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 744         .cmd_rcgr = 0x03014,
 745         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 746         .mnd_width = 8,
 747         .hid_width = 5,
 748         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 749         .clkr.hw.init = &(struct clk_init_data){
 750                 .name = "blsp1_qup2_spi_apps_clk_src",
 751                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 752                 .num_parents = 3,
 753                 .ops = &clk_rcg2_ops,
 754         },
 755 };
 756
 757 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 758         .cmd_rcgr = 0x04000,
 759         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 760         .hid_width = 5,
 761         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 762         .clkr.hw.init = &(struct clk_init_data){
 763                 .name = "blsp1_qup3_i2c_apps_clk_src",
 764                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 765                 .num_parents = 3,
 766                 .ops = &clk_rcg2_ops,
 767         },
 768 };
 769
 770 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 771         .cmd_rcgr = 0x04014,
 772         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 773         .mnd_width = 8,
 774         .hid_width = 5,
 775         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 776         .clkr.hw.init = &(struct clk_init_data){
 777                 .name = "blsp1_qup3_spi_apps_clk_src",
 778                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 779                 .num_parents = 3,
 780                 .ops = &clk_rcg2_ops,
 781         },
 782 };
 783
 784 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 785         .cmd_rcgr = 0x05000,
 786         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 787         .hid_width = 5,
 788         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 789         .clkr.hw.init = &(struct clk_init_data){
 790                 .name = "blsp1_qup4_i2c_apps_clk_src",
 791                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 792                 .num_parents = 3,
 793                 .ops = &clk_rcg2_ops,
 794         },
 795 };
 796
 797 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 798         .cmd_rcgr = 0x05014,
 799         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 800         .mnd_width = 8,
 801         .hid_width = 5,
 802         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 803         .clkr.hw.init = &(struct clk_init_data){
 804                 .name = "blsp1_qup4_spi_apps_clk_src",
 805                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 806                 .num_parents = 3,
 807                 .ops = &clk_rcg2_ops,
 808         },
 809 };
 810
 811 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 812         .cmd_rcgr = 0x06000,
 813         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 814         .hid_width = 5,
 815         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 816         .clkr.hw.init = &(struct clk_init_data){
 817                 .name = "blsp1_qup5_i2c_apps_clk_src",
 818                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 819                 .num_parents = 3,
 820                 .ops = &clk_rcg2_ops,
 821         },
 822 };
 823
 824 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 825         .cmd_rcgr = 0x06014,
 826         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 827         .mnd_width = 8,
 828         .hid_width = 5,
 829         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 830         .clkr.hw.init = &(struct clk_init_data){
 831                 .name = "blsp1_qup5_spi_apps_clk_src",
 832                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 833                 .num_parents = 3,
 834                 .ops = &clk_rcg2_ops,
 835         },
 836 };
 837
 838 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 839         .cmd_rcgr = 0x07000,
 840         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 841         .hid_width = 5,
 842         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 843         .clkr.hw.init = &(struct clk_init_data){
 844                 .name = "blsp1_qup6_i2c_apps_clk_src",
 845                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 846                 .num_parents = 3,
 847                 .ops = &clk_rcg2_ops,
 848         },
 849 };
 850
 851 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 852         .cmd_rcgr = 0x07014,
 853         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 854         .mnd_width = 8,
 855         .hid_width = 5,
 856         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 857         .clkr.hw.init = &(struct clk_init_data){
 858                 .name = "blsp1_qup6_spi_apps_clk_src",
 859                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 860                 .num_parents = 3,
 861                 .ops = &clk_rcg2_ops,
 862         },
 863 };
 864
 865 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 866         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 867         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 868         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 869         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 870         F(19200000, P_XO, 1, 0, 0),
 871         F(24000000, P_GPLL0, 1, 3, 100),
 872         F(25000000, P_GPLL0, 16, 1, 2),
 873         F(32000000, P_GPLL0, 1, 1, 25),
 874         F(40000000, P_GPLL0, 1, 1, 20),
 875         F(46400000, P_GPLL0, 1, 29, 500),
 876         F(48000000, P_GPLL0, 1, 3, 50),
 877         F(51200000, P_GPLL0, 1, 8, 125),
 878         F(56000000, P_GPLL0, 1, 7, 100),
 879         F(58982400, P_GPLL0, 1, 1152, 15625),
 880         F(60000000, P_GPLL0, 1, 3, 40),
 881         F(64000000, P_GPLL0, 12.5, 1, 1),
 882         { }
 883 };
 884
 885 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 886         .cmd_rcgr = 0x02044,
 887         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 888         .mnd_width = 16,
 889         .hid_width = 5,
 890         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 891         .clkr.hw.init = &(struct clk_init_data){
 892                 .name = "blsp1_uart1_apps_clk_src",
 893                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 894                 .num_parents = 3,
 895                 .ops = &clk_rcg2_ops,
 896         },
 897 };
 898
 899 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 900         .cmd_rcgr = 0x03034,
 901         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 902         .mnd_width = 16,
 903         .hid_width = 5,
 904         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 905         .clkr.hw.init = &(struct clk_init_data){
 906                 .name = "blsp1_uart2_apps_clk_src",
 907                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 908                 .num_parents = 3,
 909                 .ops = &clk_rcg2_ops,
 910         },
 911 };
 912
 913 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 914         .cmd_rcgr = 0x04034,
 915         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 916         .mnd_width = 16,
 917         .hid_width = 5,
 918         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 919         .clkr.hw.init = &(struct clk_init_data){
 920                 .name = "blsp1_uart3_apps_clk_src",
 921                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 922                 .num_parents = 3,
 923                 .ops = &clk_rcg2_ops,
 924         },
 925 };
 926
 927 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 928         .cmd_rcgr = 0x05034,
 929         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 930         .mnd_width = 16,
 931         .hid_width = 5,
 932         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 933         .clkr.hw.init = &(struct clk_init_data){
 934                 .name = "blsp1_uart4_apps_clk_src",
 935                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 936                 .num_parents = 3,
 937                 .ops = &clk_rcg2_ops,
 938         },
 939 };
 940
 941 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 942         .cmd_rcgr = 0x06034,
 943         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 944         .mnd_width = 16,
 945         .hid_width = 5,
 946         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 947         .clkr.hw.init = &(struct clk_init_data){
 948                 .name = "blsp1_uart5_apps_clk_src",
 949                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 950                 .num_parents = 3,
 951                 .ops = &clk_rcg2_ops,
 952         },
 953 };
 954
 955 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 956         .cmd_rcgr = 0x07034,
 957         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 958         .mnd_width = 16,
 959         .hid_width = 5,
 960         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 961         .clkr.hw.init = &(struct clk_init_data){
 962                 .name = "blsp1_uart6_apps_clk_src",
 963                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 964                 .num_parents = 3,
 965                 .ops = &clk_rcg2_ops,
 966         },
 967 };
 968
 969 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 970         F(19200000, P_XO, 1, 0, 0),
 971         F(200000000, P_GPLL0, 4, 0, 0),
 972         { }
 973 };
 974
 975 static struct clk_rcg2 pcie0_axi_clk_src = {
 976         .cmd_rcgr = 0x75054,
 977         .freq_tbl = ftbl_pcie_axi_clk_src,
 978         .hid_width = 5,
 979         .parent_map = gcc_xo_gpll0_map,
 980         .clkr.hw.init = &(struct clk_init_data){
 981                 .name = "pcie0_axi_clk_src",
 982                 .parent_names = gcc_xo_gpll0,
 983                 .num_parents = 2,
 984                 .ops = &clk_rcg2_ops,
 985         },
 986 };
 987
 988 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 989         F(19200000, P_XO, 1, 0, 0),
 990 };
 991
 992 static struct clk_rcg2 pcie0_aux_clk_src = {
 993         .cmd_rcgr = 0x75024,
 994         .freq_tbl = ftbl_pcie_aux_clk_src,
 995         .mnd_width = 16,
 996         .hid_width = 5,
 997         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 998         .clkr.hw.init = &(struct clk_init_data){
 999                 .name = "pcie0_aux_clk_src",
1000                 .parent_names = gcc_xo_gpll0_sleep_clk,
1001                 .num_parents = 3,
1002                 .ops = &clk_rcg2_ops,
1003         },
1004 };
1005
1006 static struct clk_regmap_mux pcie0_pipe_clk_src = {
1007         .reg = 0x7501c,
1008         .shift = 8,
1009         .width = 2,
1010         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1011         .clkr = {
1012                 .hw.init = &(struct clk_init_data){
1013                         .name = "pcie0_pipe_clk_src",
1014                         .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
1015                         .num_parents = 2,
1016                         .ops = &clk_regmap_mux_closest_ops,
1017                         .flags = CLK_SET_RATE_PARENT,
1018                 },
1019         },
1020 };
1021
1022 static struct clk_rcg2 pcie1_axi_clk_src = {
1023         .cmd_rcgr = 0x76054,
1024         .freq_tbl = ftbl_pcie_axi_clk_src,
1025         .hid_width = 5,
1026         .parent_map = gcc_xo_gpll0_map,
1027         .clkr.hw.init = &(struct clk_init_data){
1028                 .name = "pcie1_axi_clk_src",
1029                 .parent_names = gcc_xo_gpll0,
1030                 .num_parents = 2,
1031                 .ops = &clk_rcg2_ops,
1032         },
1033 };
1034
1035 static struct clk_rcg2 pcie1_aux_clk_src = {
1036         .cmd_rcgr = 0x76024,
1037         .freq_tbl = ftbl_pcie_aux_clk_src,
1038         .mnd_width = 16,
1039         .hid_width = 5,
1040         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1041         .clkr.hw.init = &(struct clk_init_data){
1042                 .name = "pcie1_aux_clk_src",
1043                 .parent_names = gcc_xo_gpll0_sleep_clk,
1044                 .num_parents = 3,
1045                 .ops = &clk_rcg2_ops,
1046         },
1047 };
1048
1049 static struct clk_regmap_mux pcie1_pipe_clk_src = {
1050         .reg = 0x7601c,
1051         .shift = 8,
1052         .width = 2,
1053         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
1054         .clkr = {
1055                 .hw.init = &(struct clk_init_data){
1056                         .name = "pcie1_pipe_clk_src",
1057                         .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
1058                         .num_parents = 2,
1059                         .ops = &clk_regmap_mux_closest_ops,
1060                         .flags = CLK_SET_RATE_PARENT,
1061                 },
1062         },
1063 };
1064
1065 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1066         F(144000, P_XO, 16, 3, 25),
1067         F(400000, P_XO, 12, 1, 4),
1068         F(24000000, P_GPLL2, 12, 1, 4),
1069         F(48000000, P_GPLL2, 12, 1, 2),
1070         F(96000000, P_GPLL2, 12, 0, 0),
1071         F(177777778, P_GPLL0, 4.5, 0, 0),
1072         F(192000000, P_GPLL2, 6, 0, 0),
1073         F(384000000, P_GPLL2, 3, 0, 0),
1074         { }
1075 };
1076
1077 static struct clk_rcg2 sdcc1_apps_clk_src = {
1078         .cmd_rcgr = 0x42004,
1079         .freq_tbl = ftbl_sdcc_apps_clk_src,
1080         .mnd_width = 8,
1081         .hid_width = 5,
1082         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1083         .clkr.hw.init = &(struct clk_init_data){
1084                 .name = "sdcc1_apps_clk_src",
1085                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1086                 .num_parents = 4,
1087                 .ops = &clk_rcg2_ops,
1088         },
1089 };
1090
1091 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1092         F(19200000, P_XO, 1, 0, 0),
1093         F(160000000, P_GPLL0, 5, 0, 0),
1094         F(308570000, P_GPLL6, 3.5, 0, 0),
1095 };
1096
1097 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1098         .cmd_rcgr = 0x5d000,
1099         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
1100         .mnd_width = 8,
1101         .hid_width = 5,
1102         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1103         .clkr.hw.init = &(struct clk_init_data){
1104                 .name = "sdcc1_ice_core_clk_src",
1105                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
1106                 .num_parents = 4,
1107                 .ops = &clk_rcg2_ops,
1108         },
1109 };
1110
1111 static struct clk_rcg2 sdcc2_apps_clk_src = {
1112         .cmd_rcgr = 0x43004,
1113         .freq_tbl = ftbl_sdcc_apps_clk_src,
1114         .mnd_width = 8,
1115         .hid_width = 5,
1116         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1117         .clkr.hw.init = &(struct clk_init_data){
1118                 .name = "sdcc2_apps_clk_src",
1119                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1120                 .num_parents = 4,
1121                 .ops = &clk_rcg2_ops,
1122         },
1123 };
1124
1125 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
1126         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1127         F(100000000, P_GPLL0, 8, 0, 0),
1128         F(133330000, P_GPLL0, 6, 0, 0),
1129         { }
1130 };
1131
1132 static struct clk_rcg2 usb0_master_clk_src = {
1133         .cmd_rcgr = 0x3e00c,
1134         .freq_tbl = ftbl_usb_master_clk_src,
1135         .mnd_width = 8,
1136         .hid_width = 5,
1137         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1138         .clkr.hw.init = &(struct clk_init_data){
1139                 .name = "usb0_master_clk_src",
1140                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1141                 .num_parents = 3,
1142                 .ops = &clk_rcg2_ops,
1143         },
1144 };
1145
1146 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1147         F(19200000, P_XO, 1, 0, 0),
1148         { }
1149 };
1150
1151 static struct clk_rcg2 usb0_aux_clk_src = {
1152         .cmd_rcgr = 0x3e05c,
1153         .freq_tbl = ftbl_usb_aux_clk_src,
1154         .mnd_width = 16,
1155         .hid_width = 5,
1156         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1157         .clkr.hw.init = &(struct clk_init_data){
1158                 .name = "usb0_aux_clk_src",
1159                 .parent_names = gcc_xo_gpll0_sleep_clk,
1160                 .num_parents = 3,
1161                 .ops = &clk_rcg2_ops,
1162         },
1163 };
1164
1165 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1166         F(19200000, P_XO, 1, 0, 0),
1167         F(20000000, P_GPLL6, 6, 1, 9),
1168         F(60000000, P_GPLL6, 6, 1, 3),
1169         { }
1170 };
1171
1172 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1173         .cmd_rcgr = 0x3e020,
1174         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1175         .mnd_width = 8,
1176         .hid_width = 5,
1177         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1178         .clkr.hw.init = &(struct clk_init_data){
1179                 .name = "usb0_mock_utmi_clk_src",
1180                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1181                 .num_parents = 4,
1182                 .ops = &clk_rcg2_ops,
1183         },
1184 };
1185
1186 static struct clk_regmap_mux usb0_pipe_clk_src = {
1187         .reg = 0x3e048,
1188         .shift = 8,
1189         .width = 2,
1190         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1191         .clkr = {
1192                 .hw.init = &(struct clk_init_data){
1193                         .name = "usb0_pipe_clk_src",
1194                         .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
1195                         .num_parents = 2,
1196                         .ops = &clk_regmap_mux_closest_ops,
1197                         .flags = CLK_SET_RATE_PARENT,
1198                 },
1199         },
1200 };
1201
1202 static struct clk_rcg2 usb1_master_clk_src = {
1203         .cmd_rcgr = 0x3f00c,
1204         .freq_tbl = ftbl_usb_master_clk_src,
1205         .mnd_width = 8,
1206         .hid_width = 5,
1207         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1208         .clkr.hw.init = &(struct clk_init_data){
1209                 .name = "usb1_master_clk_src",
1210                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1211                 .num_parents = 3,
1212                 .ops = &clk_rcg2_ops,
1213         },
1214 };
1215
1216 static struct clk_rcg2 usb1_aux_clk_src = {
1217         .cmd_rcgr = 0x3f05c,
1218         .freq_tbl = ftbl_usb_aux_clk_src,
1219         .mnd_width = 16,
1220         .hid_width = 5,
1221         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1222         .clkr.hw.init = &(struct clk_init_data){
1223                 .name = "usb1_aux_clk_src",
1224                 .parent_names = gcc_xo_gpll0_sleep_clk,
1225                 .num_parents = 3,
1226                 .ops = &clk_rcg2_ops,
1227         },
1228 };
1229
1230 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1231         .cmd_rcgr = 0x3f020,
1232         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1233         .mnd_width = 8,
1234         .hid_width = 5,
1235         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1236         .clkr.hw.init = &(struct clk_init_data){
1237                 .name = "usb1_mock_utmi_clk_src",
1238                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1239                 .num_parents = 4,
1240                 .ops = &clk_rcg2_ops,
1241         },
1242 };
1243
1244 static struct clk_regmap_mux usb1_pipe_clk_src = {
1245         .reg = 0x3f048,
1246         .shift = 8,
1247         .width = 2,
1248         .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1249         .clkr = {
1250                 .hw.init = &(struct clk_init_data){
1251                         .name = "usb1_pipe_clk_src",
1252                         .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1253                         .num_parents = 2,
1254                         .ops = &clk_regmap_mux_closest_ops,
1255                         .flags = CLK_SET_RATE_PARENT,
1256                 },
1257         },
1258 };
1259
1260 static struct clk_branch gcc_xo_clk_src = {
1261         .halt_reg = 0x30018,
1262         .clkr = {
1263                 .enable_reg = 0x30018,
1264                 .enable_mask = BIT(1),
1265                 .hw.init = &(struct clk_init_data){
1266                         .name = "gcc_xo_clk_src",
1267                         .parent_names = (const char *[]){
1268                                 "xo"
1269                         },
1270                         .num_parents = 1,
1271                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1272                         .ops = &clk_branch2_ops,
1273                 },
1274         },
1275 };
1276
1277 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1278         .mult = 1,
1279         .div = 4,
1280         .hw.init = &(struct clk_init_data){
1281                 .name = "gcc_xo_div4_clk_src",
1282                 .parent_names = (const char *[]){
1283                         "gcc_xo_clk_src"
1284                 },
1285                 .num_parents = 1,
1286                 .ops = &clk_fixed_factor_ops,
1287                 .flags = CLK_SET_RATE_PARENT,
1288         },
1289 };
1290
1291 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1292         F(19200000, P_XO, 1, 0, 0),
1293         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1294         F(100000000, P_GPLL0, 8, 0, 0),
1295         F(133333333, P_GPLL0, 6, 0, 0),
1296         F(160000000, P_GPLL0, 5, 0, 0),
1297         F(200000000, P_GPLL0, 4, 0, 0),
1298         F(266666667, P_GPLL0, 3, 0, 0),
1299         { }
1300 };
1301
1302 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1303         .cmd_rcgr = 0x26004,
1304         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1305         .hid_width = 5,
1306         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1307         .clkr.hw.init = &(struct clk_init_data){
1308                 .name = "system_noc_bfdcd_clk_src",
1309                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1310                 .num_parents = 4,
1311                 .ops = &clk_rcg2_ops,
1312                 .flags = CLK_IS_CRITICAL,
1313         },
1314 };
1315
1316 static struct clk_fixed_factor system_noc_clk_src = {
1317         .mult = 1,
1318         .div = 1,
1319         .hw.init = &(struct clk_init_data){
1320                 .name = "system_noc_clk_src",
1321                 .parent_names = (const char *[]){
1322                         "system_noc_bfdcd_clk_src"
1323                 },
1324                 .num_parents = 1,
1325                 .ops = &clk_fixed_factor_ops,
1326                 .flags = CLK_SET_RATE_PARENT,
1327         },
1328 };
1329
1330 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1331         F(19200000, P_XO, 1, 0, 0),
1332         F(200000000, P_GPLL0, 4, 0, 0),
1333         { }
1334 };
1335
1336 static struct clk_rcg2 nss_ce_clk_src = {
1337         .cmd_rcgr = 0x68098,
1338         .freq_tbl = ftbl_nss_ce_clk_src,
1339         .hid_width = 5,
1340         .parent_map = gcc_xo_gpll0_map,
1341         .clkr.hw.init = &(struct clk_init_data){
1342                 .name = "nss_ce_clk_src",
1343                 .parent_names = gcc_xo_gpll0,
1344                 .num_parents = 2,
1345                 .ops = &clk_rcg2_ops,
1346         },
1347 };
1348
1349 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1350         F(19200000, P_XO, 1, 0, 0),
1351         F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1352         { }
1353 };
1354
1355 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1356         .cmd_rcgr = 0x68088,
1357         .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1358         .hid_width = 5,
1359         .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1360         .clkr.hw.init = &(struct clk_init_data){
1361                 .name = "nss_noc_bfdcd_clk_src",
1362                 .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1363                 .num_parents = 4,
1364                 .ops = &clk_rcg2_ops,
1365         },
1366 };
1367
1368 static struct clk_fixed_factor nss_noc_clk_src = {
1369         .mult = 1,
1370         .div = 1,
1371         .hw.init = &(struct clk_init_data){
1372                 .name = "nss_noc_clk_src",
1373                 .parent_names = (const char *[]){
1374                         "nss_noc_bfdcd_clk_src"
1375                 },
1376                 .num_parents = 1,
1377                 .ops = &clk_fixed_factor_ops,
1378                 .flags = CLK_SET_RATE_PARENT,
1379         },
1380 };
1381
1382 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1383         F(19200000, P_XO, 1, 0, 0),
1384         F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1385         { }
1386 };
1387
1388 static struct clk_rcg2 nss_crypto_clk_src = {
1389         .cmd_rcgr = 0x68144,
1390         .freq_tbl = ftbl_nss_crypto_clk_src,
1391         .mnd_width = 16,
1392         .hid_width = 5,
1393         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1394         .clkr.hw.init = &(struct clk_init_data){
1395                 .name = "nss_crypto_clk_src",
1396                 .parent_names = gcc_xo_nss_crypto_pll_gpll0,
1397                 .num_parents = 3,
1398                 .ops = &clk_rcg2_ops,
1399         },
1400 };
1401
1402 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1403         F(19200000, P_XO, 1, 0, 0),
1404         F(187200000, P_UBI32_PLL, 8, 0, 0),
1405         F(748800000, P_UBI32_PLL, 2, 0, 0),
1406         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1407         F(1689600000, P_UBI32_PLL, 1, 0, 0),
1408         { }
1409 };
1410
1411 static struct clk_rcg2 nss_ubi0_clk_src = {
1412         .cmd_rcgr = 0x68104,
1413         .freq_tbl = ftbl_nss_ubi_clk_src,
1414         .hid_width = 5,
1415         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1416         .clkr.hw.init = &(struct clk_init_data){
1417                 .name = "nss_ubi0_clk_src",
1418                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1419                 .num_parents = 6,
1420                 .ops = &clk_rcg2_ops,
1421                 .flags = CLK_SET_RATE_PARENT,
1422         },
1423 };
1424
1425 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1426         .reg = 0x68118,
1427         .shift = 0,
1428         .width = 4,
1429         .clkr = {
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "nss_ubi0_div_clk_src",
1432                         .parent_names = (const char *[]){
1433                                 "nss_ubi0_clk_src"
1434                         },
1435                         .num_parents = 1,
1436                         .ops = &clk_regmap_div_ro_ops,
1437                         .flags = CLK_SET_RATE_PARENT,
1438                 },
1439         },
1440 };
1441
1442 static struct clk_rcg2 nss_ubi1_clk_src = {
1443         .cmd_rcgr = 0x68124,
1444         .freq_tbl = ftbl_nss_ubi_clk_src,
1445         .hid_width = 5,
1446         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1447         .clkr.hw.init = &(struct clk_init_data){
1448                 .name = "nss_ubi1_clk_src",
1449                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1450                 .num_parents = 6,
1451                 .ops = &clk_rcg2_ops,
1452                 .flags = CLK_SET_RATE_PARENT,
1453         },
1454 };
1455
1456 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1457         .reg = 0x68138,
1458         .shift = 0,
1459         .width = 4,
1460         .clkr = {
1461                 .hw.init = &(struct clk_init_data){
1462                         .name = "nss_ubi1_div_clk_src",
1463                         .parent_names = (const char *[]){
1464                                 "nss_ubi1_clk_src"
1465                         },
1466                         .num_parents = 1,
1467                         .ops = &clk_regmap_div_ro_ops,
1468                         .flags = CLK_SET_RATE_PARENT,
1469                 },
1470         },
1471 };
1472
1473 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1474         F(19200000, P_XO, 1, 0, 0),
1475         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1476         { }
1477 };
1478
1479 static struct clk_rcg2 ubi_mpt_clk_src = {
1480         .cmd_rcgr = 0x68090,
1481         .freq_tbl = ftbl_ubi_mpt_clk_src,
1482         .hid_width = 5,
1483         .parent_map = gcc_xo_gpll0_out_main_div2_map,
1484         .clkr.hw.init = &(struct clk_init_data){
1485                 .name = "ubi_mpt_clk_src",
1486                 .parent_names = gcc_xo_gpll0_out_main_div2,
1487                 .num_parents = 2,
1488                 .ops = &clk_rcg2_ops,
1489         },
1490 };
1491
1492 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1493         F(19200000, P_XO, 1, 0, 0),
1494         F(400000000, P_GPLL0, 2, 0, 0),
1495         { }
1496 };
1497
1498 static struct clk_rcg2 nss_imem_clk_src = {
1499         .cmd_rcgr = 0x68158,
1500         .freq_tbl = ftbl_nss_imem_clk_src,
1501         .hid_width = 5,
1502         .parent_map = gcc_xo_gpll0_gpll4_map,
1503         .clkr.hw.init = &(struct clk_init_data){
1504                 .name = "nss_imem_clk_src",
1505                 .parent_names = gcc_xo_gpll0_gpll4,
1506                 .num_parents = 3,
1507                 .ops = &clk_rcg2_ops,
1508         },
1509 };
1510
1511 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1512         F(19200000, P_XO, 1, 0, 0),
1513         F(300000000, P_BIAS_PLL, 1, 0, 0),
1514         { }
1515 };
1516
1517 static struct clk_rcg2 nss_ppe_clk_src = {
1518         .cmd_rcgr = 0x68080,
1519         .freq_tbl = ftbl_nss_ppe_clk_src,
1520         .hid_width = 5,
1521         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1522         .clkr.hw.init = &(struct clk_init_data){
1523                 .name = "nss_ppe_clk_src",
1524                 .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1525                 .num_parents = 6,
1526                 .ops = &clk_rcg2_ops,
1527         },
1528 };
1529
1530 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1531         .mult = 1,
1532         .div = 4,
1533         .hw.init = &(struct clk_init_data){
1534                 .name = "nss_ppe_cdiv_clk_src",
1535                 .parent_names = (const char *[]){
1536                         "nss_ppe_clk_src"
1537                 },
1538                 .num_parents = 1,
1539                 .ops = &clk_fixed_factor_ops,
1540                 .flags = CLK_SET_RATE_PARENT,
1541         },
1542 };
1543
1544 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1545         F(19200000, P_XO, 1, 0, 0),
1546         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1547         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1548         { }
1549 };
1550
1551 static struct clk_rcg2 nss_port1_rx_clk_src = {
1552         .cmd_rcgr = 0x68020,
1553         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1554         .hid_width = 5,
1555         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1556         .clkr.hw.init = &(struct clk_init_data){
1557                 .name = "nss_port1_rx_clk_src",
1558                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1559                 .num_parents = 5,
1560                 .ops = &clk_rcg2_ops,
1561         },
1562 };
1563
1564 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1565         .reg = 0x68400,
1566         .shift = 0,
1567         .width = 4,
1568         .clkr = {
1569                 .hw.init = &(struct clk_init_data){
1570                         .name = "nss_port1_rx_div_clk_src",
1571                         .parent_names = (const char *[]){
1572                                 "nss_port1_rx_clk_src"
1573                         },
1574                         .num_parents = 1,
1575                         .ops = &clk_regmap_div_ops,
1576                         .flags = CLK_SET_RATE_PARENT,
1577                 },
1578         },
1579 };
1580
1581 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1582         F(19200000, P_XO, 1, 0, 0),
1583         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1584         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1585         { }
1586 };
1587
1588 static struct clk_rcg2 nss_port1_tx_clk_src = {
1589         .cmd_rcgr = 0x68028,
1590         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1591         .hid_width = 5,
1592         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1593         .clkr.hw.init = &(struct clk_init_data){
1594                 .name = "nss_port1_tx_clk_src",
1595                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1596                 .num_parents = 5,
1597                 .ops = &clk_rcg2_ops,
1598         },
1599 };
1600
1601 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1602         .reg = 0x68404,
1603         .shift = 0,
1604         .width = 4,
1605         .clkr = {
1606                 .hw.init = &(struct clk_init_data){
1607                         .name = "nss_port1_tx_div_clk_src",
1608                         .parent_names = (const char *[]){
1609                                 "nss_port1_tx_clk_src"
1610                         },
1611                         .num_parents = 1,
1612                         .ops = &clk_regmap_div_ops,
1613                         .flags = CLK_SET_RATE_PARENT,
1614                 },
1615         },
1616 };
1617
1618 static struct clk_rcg2 nss_port2_rx_clk_src = {
1619         .cmd_rcgr = 0x68030,
1620         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1621         .hid_width = 5,
1622         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1623         .clkr.hw.init = &(struct clk_init_data){
1624                 .name = "nss_port2_rx_clk_src",
1625                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1626                 .num_parents = 5,
1627                 .ops = &clk_rcg2_ops,
1628         },
1629 };
1630
1631 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1632         .reg = 0x68410,
1633         .shift = 0,
1634         .width = 4,
1635         .clkr = {
1636                 .hw.init = &(struct clk_init_data){
1637                         .name = "nss_port2_rx_div_clk_src",
1638                         .parent_names = (const char *[]){
1639                                 "nss_port2_rx_clk_src"
1640                         },
1641                         .num_parents = 1,
1642                         .ops = &clk_regmap_div_ops,
1643                         .flags = CLK_SET_RATE_PARENT,
1644                 },
1645         },
1646 };
1647
1648 static struct clk_rcg2 nss_port2_tx_clk_src = {
1649         .cmd_rcgr = 0x68038,
1650         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1651         .hid_width = 5,
1652         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1653         .clkr.hw.init = &(struct clk_init_data){
1654                 .name = "nss_port2_tx_clk_src",
1655                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1656                 .num_parents = 5,
1657                 .ops = &clk_rcg2_ops,
1658         },
1659 };
1660
1661 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1662         .reg = 0x68414,
1663         .shift = 0,
1664         .width = 4,
1665         .clkr = {
1666                 .hw.init = &(struct clk_init_data){
1667                         .name = "nss_port2_tx_div_clk_src",
1668                         .parent_names = (const char *[]){
1669                                 "nss_port2_tx_clk_src"
1670                         },
1671                         .num_parents = 1,
1672                         .ops = &clk_regmap_div_ops,
1673                         .flags = CLK_SET_RATE_PARENT,
1674                 },
1675         },
1676 };
1677
1678 static struct clk_rcg2 nss_port3_rx_clk_src = {
1679         .cmd_rcgr = 0x68040,
1680         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1681         .hid_width = 5,
1682         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1683         .clkr.hw.init = &(struct clk_init_data){
1684                 .name = "nss_port3_rx_clk_src",
1685                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1686                 .num_parents = 5,
1687                 .ops = &clk_rcg2_ops,
1688         },
1689 };
1690
1691 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1692         .reg = 0x68420,
1693         .shift = 0,
1694         .width = 4,
1695         .clkr = {
1696                 .hw.init = &(struct clk_init_data){
1697                         .name = "nss_port3_rx_div_clk_src",
1698                         .parent_names = (const char *[]){
1699                                 "nss_port3_rx_clk_src"
1700                         },
1701                         .num_parents = 1,
1702                         .ops = &clk_regmap_div_ops,
1703                         .flags = CLK_SET_RATE_PARENT,
1704                 },
1705         },
1706 };
1707
1708 static struct clk_rcg2 nss_port3_tx_clk_src = {
1709         .cmd_rcgr = 0x68048,
1710         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1711         .hid_width = 5,
1712         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1713         .clkr.hw.init = &(struct clk_init_data){
1714                 .name = "nss_port3_tx_clk_src",
1715                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1716                 .num_parents = 5,
1717                 .ops = &clk_rcg2_ops,
1718         },
1719 };
1720
1721 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1722         .reg = 0x68424,
1723         .shift = 0,
1724         .width = 4,
1725         .clkr = {
1726                 .hw.init = &(struct clk_init_data){
1727                         .name = "nss_port3_tx_div_clk_src",
1728                         .parent_names = (const char *[]){
1729                                 "nss_port3_tx_clk_src"
1730                         },
1731                         .num_parents = 1,
1732                         .ops = &clk_regmap_div_ops,
1733                         .flags = CLK_SET_RATE_PARENT,
1734                 },
1735         },
1736 };
1737
1738 static struct clk_rcg2 nss_port4_rx_clk_src = {
1739         .cmd_rcgr = 0x68050,
1740         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1741         .hid_width = 5,
1742         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1743         .clkr.hw.init = &(struct clk_init_data){
1744                 .name = "nss_port4_rx_clk_src",
1745                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1746                 .num_parents = 5,
1747                 .ops = &clk_rcg2_ops,
1748         },
1749 };
1750
1751 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1752         .reg = 0x68430,
1753         .shift = 0,
1754         .width = 4,
1755         .clkr = {
1756                 .hw.init = &(struct clk_init_data){
1757                         .name = "nss_port4_rx_div_clk_src",
1758                         .parent_names = (const char *[]){
1759                                 "nss_port4_rx_clk_src"
1760                         },
1761                         .num_parents = 1,
1762                         .ops = &clk_regmap_div_ops,
1763                         .flags = CLK_SET_RATE_PARENT,
1764                 },
1765         },
1766 };
1767
1768 static struct clk_rcg2 nss_port4_tx_clk_src = {
1769         .cmd_rcgr = 0x68058,
1770         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1771         .hid_width = 5,
1772         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1773         .clkr.hw.init = &(struct clk_init_data){
1774                 .name = "nss_port4_tx_clk_src",
1775                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1776                 .num_parents = 5,
1777                 .ops = &clk_rcg2_ops,
1778         },
1779 };
1780
1781 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1782         .reg = 0x68434,
1783         .shift = 0,
1784         .width = 4,
1785         .clkr = {
1786                 .hw.init = &(struct clk_init_data){
1787                         .name = "nss_port4_tx_div_clk_src",
1788                         .parent_names = (const char *[]){
1789                                 "nss_port4_tx_clk_src"
1790                         },
1791                         .num_parents = 1,
1792                         .ops = &clk_regmap_div_ops,
1793                         .flags = CLK_SET_RATE_PARENT,
1794                 },
1795         },
1796 };
1797
1798 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1799         F(19200000, P_XO, 1, 0, 0),
1800         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1801         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1802         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1803         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1804         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1805         { }
1806 };
1807
1808 static struct clk_rcg2 nss_port5_rx_clk_src = {
1809         .cmd_rcgr = 0x68060,
1810         .freq_tbl = ftbl_nss_port5_rx_clk_src,
1811         .hid_width = 5,
1812         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1813         .clkr.hw.init = &(struct clk_init_data){
1814                 .name = "nss_port5_rx_clk_src",
1815                 .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1816                 .num_parents = 7,
1817                 .ops = &clk_rcg2_ops,
1818         },
1819 };
1820
1821 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1822         .reg = 0x68440,
1823         .shift = 0,
1824         .width = 4,
1825         .clkr = {
1826                 .hw.init = &(struct clk_init_data){
1827                         .name = "nss_port5_rx_div_clk_src",
1828                         .parent_names = (const char *[]){
1829                                 "nss_port5_rx_clk_src"
1830                         },
1831                         .num_parents = 1,
1832                         .ops = &clk_regmap_div_ops,
1833                         .flags = CLK_SET_RATE_PARENT,
1834                 },
1835         },
1836 };
1837
1838 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1839         F(19200000, P_XO, 1, 0, 0),
1840         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1841         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1842         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1843         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1844         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1845         { }
1846 };
1847
1848 static struct clk_rcg2 nss_port5_tx_clk_src = {
1849         .cmd_rcgr = 0x68068,
1850         .freq_tbl = ftbl_nss_port5_tx_clk_src,
1851         .hid_width = 5,
1852         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1853         .clkr.hw.init = &(struct clk_init_data){
1854                 .name = "nss_port5_tx_clk_src",
1855                 .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1856                 .num_parents = 7,
1857                 .ops = &clk_rcg2_ops,
1858         },
1859 };
1860
1861 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1862         .reg = 0x68444,
1863         .shift = 0,
1864         .width = 4,
1865         .clkr = {
1866                 .hw.init = &(struct clk_init_data){
1867                         .name = "nss_port5_tx_div_clk_src",
1868                         .parent_names = (const char *[]){
1869                                 "nss_port5_tx_clk_src"
1870                         },
1871                         .num_parents = 1,
1872                         .ops = &clk_regmap_div_ops,
1873                         .flags = CLK_SET_RATE_PARENT,
1874                 },
1875         },
1876 };
1877
1878 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1879         F(19200000, P_XO, 1, 0, 0),
1880         F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1881         F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1882         F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1883         F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1884         F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1885         { }
1886 };
1887
1888 static struct clk_rcg2 nss_port6_rx_clk_src = {
1889         .cmd_rcgr = 0x68070,
1890         .freq_tbl = ftbl_nss_port6_rx_clk_src,
1891         .hid_width = 5,
1892         .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1893         .clkr.hw.init = &(struct clk_init_data){
1894                 .name = "nss_port6_rx_clk_src",
1895                 .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1896                 .num_parents = 5,
1897                 .ops = &clk_rcg2_ops,
1898         },
1899 };
1900
1901 static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1902         .reg = 0x68450,
1903         .shift = 0,
1904         .width = 4,
1905         .clkr = {
1906                 .hw.init = &(struct clk_init_data){
1907                         .name = "nss_port6_rx_div_clk_src",
1908                         .parent_names = (const char *[]){
1909                                 "nss_port6_rx_clk_src"
1910                         },
1911                         .num_parents = 1,
1912                         .ops = &clk_regmap_div_ops,
1913                         .flags = CLK_SET_RATE_PARENT,
1914                 },
1915         },
1916 };
1917
1918 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1919         F(19200000, P_XO, 1, 0, 0),
1920         F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1921         F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1922         F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1923         F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1924         F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1925         { }
1926 };
1927
1928 static struct clk_rcg2 nss_port6_tx_clk_src = {
1929         .cmd_rcgr = 0x68078,
1930         .freq_tbl = ftbl_nss_port6_tx_clk_src,
1931         .hid_width = 5,
1932         .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1933         .clkr.hw.init = &(struct clk_init_data){
1934                 .name = "nss_port6_tx_clk_src",
1935                 .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1936                 .num_parents = 5,
1937                 .ops = &clk_rcg2_ops,
1938         },
1939 };
1940
1941 static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1942         .reg = 0x68454,
1943         .shift = 0,
1944         .width = 4,
1945         .clkr = {
1946                 .hw.init = &(struct clk_init_data){
1947                         .name = "nss_port6_tx_div_clk_src",
1948                         .parent_names = (const char *[]){
1949                                 "nss_port6_tx_clk_src"
1950                         },
1951                         .num_parents = 1,
1952                         .ops = &clk_regmap_div_ops,
1953                         .flags = CLK_SET_RATE_PARENT,
1954                 },
1955         },
1956 };
1957
1958 static struct freq_tbl ftbl_crypto_clk_src[] = {
1959         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1960         F(80000000, P_GPLL0, 10, 0, 0),
1961         F(100000000, P_GPLL0, 8, 0, 0),
1962         F(160000000, P_GPLL0, 5, 0, 0),
1963         { }
1964 };
1965
1966 static struct clk_rcg2 crypto_clk_src = {
1967         .cmd_rcgr = 0x16004,
1968         .freq_tbl = ftbl_crypto_clk_src,
1969         .hid_width = 5,
1970         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1971         .clkr.hw.init = &(struct clk_init_data){
1972                 .name = "crypto_clk_src",
1973                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
1974                 .num_parents = 3,
1975                 .ops = &clk_rcg2_ops,
1976         },
1977 };
1978
1979 static struct freq_tbl ftbl_gp_clk_src[] = {
1980         F(19200000, P_XO, 1, 0, 0),
1981         { }
1982 };
1983
1984 static struct clk_rcg2 gp1_clk_src = {
1985         .cmd_rcgr = 0x08004,
1986         .freq_tbl = ftbl_gp_clk_src,
1987         .mnd_width = 8,
1988         .hid_width = 5,
1989         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1990         .clkr.hw.init = &(struct clk_init_data){
1991                 .name = "gp1_clk_src",
1992                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1993                 .num_parents = 5,
1994                 .ops = &clk_rcg2_ops,
1995         },
1996 };
1997
1998 static struct clk_rcg2 gp2_clk_src = {
1999         .cmd_rcgr = 0x09004,
2000         .freq_tbl = ftbl_gp_clk_src,
2001         .mnd_width = 8,
2002         .hid_width = 5,
2003         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2004         .clkr.hw.init = &(struct clk_init_data){
2005                 .name = "gp2_clk_src",
2006                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2007                 .num_parents = 5,
2008                 .ops = &clk_rcg2_ops,
2009         },
2010 };
2011
2012 static struct clk_rcg2 gp3_clk_src = {
2013         .cmd_rcgr = 0x0a004,
2014         .freq_tbl = ftbl_gp_clk_src,
2015         .mnd_width = 8,
2016         .hid_width = 5,
2017         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2018         .clkr.hw.init = &(struct clk_init_data){
2019                 .name = "gp3_clk_src",
2020                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2021                 .num_parents = 5,
2022                 .ops = &clk_rcg2_ops,
2023         },
2024 };
2025
2026 static struct clk_branch gcc_blsp1_ahb_clk = {
2027         .halt_reg = 0x01008,
2028         .clkr = {
2029                 .enable_reg = 0x01008,
2030                 .enable_mask = BIT(0),
2031                 .hw.init = &(struct clk_init_data){
2032                         .name = "gcc_blsp1_ahb_clk",
2033                         .parent_names = (const char *[]){
2034                                 "pcnoc_clk_src"
2035                         },
2036                         .num_parents = 1,
2037                         .flags = CLK_SET_RATE_PARENT,
2038                         .ops = &clk_branch2_ops,
2039                 },
2040         },
2041 };
2042
2043 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2044         .halt_reg = 0x02008,
2045         .clkr = {
2046                 .enable_reg = 0x02008,
2047                 .enable_mask = BIT(0),
2048                 .hw.init = &(struct clk_init_data){
2049                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
2050                         .parent_names = (const char *[]){
2051                                 "blsp1_qup1_i2c_apps_clk_src"
2052                         },
2053                         .num_parents = 1,
2054                         .flags = CLK_SET_RATE_PARENT,
2055                         .ops = &clk_branch2_ops,
2056                 },
2057         },
2058 };
2059
2060 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2061         .halt_reg = 0x02004,
2062         .clkr = {
2063                 .enable_reg = 0x02004,
2064                 .enable_mask = BIT(0),
2065                 .hw.init = &(struct clk_init_data){
2066                         .name = "gcc_blsp1_qup1_spi_apps_clk",
2067                         .parent_names = (const char *[]){
2068                                 "blsp1_qup1_spi_apps_clk_src"
2069                         },
2070                         .num_parents = 1,
2071                         .flags = CLK_SET_RATE_PARENT,
2072                         .ops = &clk_branch2_ops,
2073                 },
2074         },
2075 };
2076
2077 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2078         .halt_reg = 0x03010,
2079         .clkr = {
2080                 .enable_reg = 0x03010,
2081                 .enable_mask = BIT(0),
2082                 .hw.init = &(struct clk_init_data){
2083                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2084                         .parent_names = (const char *[]){
2085                                 "blsp1_qup2_i2c_apps_clk_src"
2086                         },
2087                         .num_parents = 1,
2088                         .flags = CLK_SET_RATE_PARENT,
2089                         .ops = &clk_branch2_ops,
2090                 },
2091         },
2092 };
2093
2094 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2095         .halt_reg = 0x0300c,
2096         .clkr = {
2097                 .enable_reg = 0x0300c,
2098                 .enable_mask = BIT(0),
2099                 .hw.init = &(struct clk_init_data){
2100                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2101                         .parent_names = (const char *[]){
2102                                 "blsp1_qup2_spi_apps_clk_src"
2103                         },
2104                         .num_parents = 1,
2105                         .flags = CLK_SET_RATE_PARENT,
2106                         .ops = &clk_branch2_ops,
2107                 },
2108         },
2109 };
2110
2111 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2112         .halt_reg = 0x04010,
2113         .clkr = {
2114                 .enable_reg = 0x04010,
2115                 .enable_mask = BIT(0),
2116                 .hw.init = &(struct clk_init_data){
2117                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2118                         .parent_names = (const char *[]){
2119                                 "blsp1_qup3_i2c_apps_clk_src"
2120                         },
2121                         .num_parents = 1,
2122                         .flags = CLK_SET_RATE_PARENT,
2123                         .ops = &clk_branch2_ops,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2129         .halt_reg = 0x0400c,
2130         .clkr = {
2131                 .enable_reg = 0x0400c,
2132                 .enable_mask = BIT(0),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2135                         .parent_names = (const char *[]){
2136                                 "blsp1_qup3_spi_apps_clk_src"
2137                         },
2138                         .num_parents = 1,
2139                         .flags = CLK_SET_RATE_PARENT,
2140                         .ops = &clk_branch2_ops,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2146         .halt_reg = 0x05010,
2147         .clkr = {
2148                 .enable_reg = 0x05010,
2149                 .enable_mask = BIT(0),
2150                 .hw.init = &(struct clk_init_data){
2151                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2152                         .parent_names = (const char *[]){
2153                                 "blsp1_qup4_i2c_apps_clk_src"
2154                         },
2155                         .num_parents = 1,
2156                         .flags = CLK_SET_RATE_PARENT,
2157                         .ops = &clk_branch2_ops,
2158                 },
2159         },
2160 };
2161
2162 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2163         .halt_reg = 0x0500c,
2164         .clkr = {
2165                 .enable_reg = 0x0500c,
2166                 .enable_mask = BIT(0),
2167                 .hw.init = &(struct clk_init_data){
2168                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2169                         .parent_names = (const char *[]){
2170                                 "blsp1_qup4_spi_apps_clk_src"
2171                         },
2172                         .num_parents = 1,
2173                         .flags = CLK_SET_RATE_PARENT,
2174                         .ops = &clk_branch2_ops,
2175                 },
2176         },
2177 };
2178
2179 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2180         .halt_reg = 0x06010,
2181         .clkr = {
2182                 .enable_reg = 0x06010,
2183                 .enable_mask = BIT(0),
2184                 .hw.init = &(struct clk_init_data){
2185                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2186                         .parent_names = (const char *[]){
2187                                 "blsp1_qup5_i2c_apps_clk_src"
2188                         },
2189                         .num_parents = 1,
2190                         .flags = CLK_SET_RATE_PARENT,
2191                         .ops = &clk_branch2_ops,
2192                 },
2193         },
2194 };
2195
2196 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2197         .halt_reg = 0x0600c,
2198         .clkr = {
2199                 .enable_reg = 0x0600c,
2200                 .enable_mask = BIT(0),
2201                 .hw.init = &(struct clk_init_data){
2202                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2203                         .parent_names = (const char *[]){
2204                                 "blsp1_qup5_spi_apps_clk_src"
2205                         },
2206                         .num_parents = 1,
2207                         .flags = CLK_SET_RATE_PARENT,
2208                         .ops = &clk_branch2_ops,
2209                 },
2210         },
2211 };
2212
2213 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2214         .halt_reg = 0x07010,
2215         .clkr = {
2216                 .enable_reg = 0x07010,
2217                 .enable_mask = BIT(0),
2218                 .hw.init = &(struct clk_init_data){
2219                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2220                         .parent_names = (const char *[]){
2221                                 "blsp1_qup6_i2c_apps_clk_src"
2222                         },
2223                         .num_parents = 1,
2224                         .flags = CLK_SET_RATE_PARENT,
2225                         .ops = &clk_branch2_ops,
2226                 },
2227         },
2228 };
2229
2230 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2231         .halt_reg = 0x0700c,
2232         .clkr = {
2233                 .enable_reg = 0x0700c,
2234                 .enable_mask = BIT(0),
2235                 .hw.init = &(struct clk_init_data){
2236                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2237                         .parent_names = (const char *[]){
2238                                 "blsp1_qup6_spi_apps_clk_src"
2239                         },
2240                         .num_parents = 1,
2241                         .flags = CLK_SET_RATE_PARENT,
2242                         .ops = &clk_branch2_ops,
2243                 },
2244         },
2245 };
2246
2247 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2248         .halt_reg = 0x0203c,
2249         .clkr = {
2250                 .enable_reg = 0x0203c,
2251                 .enable_mask = BIT(0),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "gcc_blsp1_uart1_apps_clk",
2254                         .parent_names = (const char *[]){
2255                                 "blsp1_uart1_apps_clk_src"
2256                         },
2257                         .num_parents = 1,
2258                         .flags = CLK_SET_RATE_PARENT,
2259                         .ops = &clk_branch2_ops,
2260                 },
2261         },
2262 };
2263
2264 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2265         .halt_reg = 0x0302c,
2266         .clkr = {
2267                 .enable_reg = 0x0302c,
2268                 .enable_mask = BIT(0),
2269                 .hw.init = &(struct clk_init_data){
2270                         .name = "gcc_blsp1_uart2_apps_clk",
2271                         .parent_names = (const char *[]){
2272                                 "blsp1_uart2_apps_clk_src"
2273                         },
2274                         .num_parents = 1,
2275                         .flags = CLK_SET_RATE_PARENT,
2276                         .ops = &clk_branch2_ops,
2277                 },
2278         },
2279 };
2280
2281 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2282         .halt_reg = 0x0402c,
2283         .clkr = {
2284                 .enable_reg = 0x0402c,
2285                 .enable_mask = BIT(0),
2286                 .hw.init = &(struct clk_init_data){
2287                         .name = "gcc_blsp1_uart3_apps_clk",
2288                         .parent_names = (const char *[]){
2289                                 "blsp1_uart3_apps_clk_src"
2290                         },
2291                         .num_parents = 1,
2292                         .flags = CLK_SET_RATE_PARENT,
2293                         .ops = &clk_branch2_ops,
2294                 },
2295         },
2296 };
2297
2298 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2299         .halt_reg = 0x0502c,
2300         .clkr = {
2301                 .enable_reg = 0x0502c,
2302                 .enable_mask = BIT(0),
2303                 .hw.init = &(struct clk_init_data){
2304                         .name = "gcc_blsp1_uart4_apps_clk",
2305                         .parent_names = (const char *[]){
2306                                 "blsp1_uart4_apps_clk_src"
2307                         },
2308                         .num_parents = 1,
2309                         .flags = CLK_SET_RATE_PARENT,
2310                         .ops = &clk_branch2_ops,
2311                 },
2312         },
2313 };
2314
2315 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2316         .halt_reg = 0x0602c,
2317         .clkr = {
2318                 .enable_reg = 0x0602c,
2319                 .enable_mask = BIT(0),
2320                 .hw.init = &(struct clk_init_data){
2321                         .name = "gcc_blsp1_uart5_apps_clk",
2322                         .parent_names = (const char *[]){
2323                                 "blsp1_uart5_apps_clk_src"
2324                         },
2325                         .num_parents = 1,
2326                         .flags = CLK_SET_RATE_PARENT,
2327                         .ops = &clk_branch2_ops,
2328                 },
2329         },
2330 };
2331
2332 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2333         .halt_reg = 0x0702c,
2334         .clkr = {
2335                 .enable_reg = 0x0702c,
2336                 .enable_mask = BIT(0),
2337                 .hw.init = &(struct clk_init_data){
2338                         .name = "gcc_blsp1_uart6_apps_clk",
2339                         .parent_names = (const char *[]){
2340                                 "blsp1_uart6_apps_clk_src"
2341                         },
2342                         .num_parents = 1,
2343                         .flags = CLK_SET_RATE_PARENT,
2344                         .ops = &clk_branch2_ops,
2345                 },
2346         },
2347 };
2348
2349 static struct clk_branch gcc_prng_ahb_clk = {
2350         .halt_reg = 0x13004,
2351         .halt_check = BRANCH_HALT_VOTED,
2352         .clkr = {
2353                 .enable_reg = 0x0b004,
2354                 .enable_mask = BIT(8),
2355                 .hw.init = &(struct clk_init_data){
2356                         .name = "gcc_prng_ahb_clk",
2357                         .parent_names = (const char *[]){
2358                                 "pcnoc_clk_src"
2359                         },
2360                         .num_parents = 1,
2361                         .flags = CLK_SET_RATE_PARENT,
2362                         .ops = &clk_branch2_ops,
2363                 },
2364         },
2365 };
2366
2367 static struct clk_branch gcc_qpic_ahb_clk = {
2368         .halt_reg = 0x57024,
2369         .clkr = {
2370                 .enable_reg = 0x57024,
2371                 .enable_mask = BIT(0),
2372                 .hw.init = &(struct clk_init_data){
2373                         .name = "gcc_qpic_ahb_clk",
2374                         .parent_names = (const char *[]){
2375                                 "pcnoc_clk_src"
2376                         },
2377                         .num_parents = 1,
2378                         .flags = CLK_SET_RATE_PARENT,
2379                         .ops = &clk_branch2_ops,
2380                 },
2381         },
2382 };
2383
2384 static struct clk_branch gcc_qpic_clk = {
2385         .halt_reg = 0x57020,
2386         .clkr = {
2387                 .enable_reg = 0x57020,
2388                 .enable_mask = BIT(0),
2389                 .hw.init = &(struct clk_init_data){
2390                         .name = "gcc_qpic_clk",
2391                         .parent_names = (const char *[]){
2392                                 "pcnoc_clk_src"
2393                         },
2394                         .num_parents = 1,
2395                         .flags = CLK_SET_RATE_PARENT,
2396                         .ops = &clk_branch2_ops,
2397                 },
2398         },
2399 };
2400
2401 static struct clk_branch gcc_pcie0_ahb_clk = {
2402         .halt_reg = 0x75010,
2403         .clkr = {
2404                 .enable_reg = 0x75010,
2405                 .enable_mask = BIT(0),
2406                 .hw.init = &(struct clk_init_data){
2407                         .name = "gcc_pcie0_ahb_clk",
2408                         .parent_names = (const char *[]){
2409                                 "pcnoc_clk_src"
2410                         },
2411                         .num_parents = 1,
2412                         .flags = CLK_SET_RATE_PARENT,
2413                         .ops = &clk_branch2_ops,
2414                 },
2415         },
2416 };
2417
2418 static struct clk_branch gcc_pcie0_aux_clk = {
2419         .halt_reg = 0x75014,
2420         .clkr = {
2421                 .enable_reg = 0x75014,
2422                 .enable_mask = BIT(0),
2423                 .hw.init = &(struct clk_init_data){
2424                         .name = "gcc_pcie0_aux_clk",
2425                         .parent_names = (const char *[]){
2426                                 "pcie0_aux_clk_src"
2427                         },
2428                         .num_parents = 1,
2429                         .flags = CLK_SET_RATE_PARENT,
2430                         .ops = &clk_branch2_ops,
2431                 },
2432         },
2433 };
2434
2435 static struct clk_branch gcc_pcie0_axi_m_clk = {
2436         .halt_reg = 0x75008,
2437         .clkr = {
2438                 .enable_reg = 0x75008,
2439                 .enable_mask = BIT(0),
2440                 .hw.init = &(struct clk_init_data){
2441                         .name = "gcc_pcie0_axi_m_clk",
2442                         .parent_names = (const char *[]){
2443                                 "pcie0_axi_clk_src"
2444                         },
2445                         .num_parents = 1,
2446                         .flags = CLK_SET_RATE_PARENT,
2447                         .ops = &clk_branch2_ops,
2448                 },
2449         },
2450 };
2451
2452 static struct clk_branch gcc_pcie0_axi_s_clk = {
2453         .halt_reg = 0x7500c,
2454         .clkr = {
2455                 .enable_reg = 0x7500c,
2456                 .enable_mask = BIT(0),
2457                 .hw.init = &(struct clk_init_data){
2458                         .name = "gcc_pcie0_axi_s_clk",
2459                         .parent_names = (const char *[]){
2460                                 "pcie0_axi_clk_src"
2461                         },
2462                         .num_parents = 1,
2463                         .flags = CLK_SET_RATE_PARENT,
2464                         .ops = &clk_branch2_ops,
2465                 },
2466         },
2467 };
2468
2469 static struct clk_branch gcc_pcie0_pipe_clk = {
2470         .halt_reg = 0x75018,
2471         .halt_check = BRANCH_HALT_DELAY,
2472         .clkr = {
2473                 .enable_reg = 0x75018,
2474                 .enable_mask = BIT(0),
2475                 .hw.init = &(struct clk_init_data){
2476                         .name = "gcc_pcie0_pipe_clk",
2477                         .parent_names = (const char *[]){
2478                                 "pcie0_pipe_clk_src"
2479                         },
2480                         .num_parents = 1,
2481                         .flags = CLK_SET_RATE_PARENT,
2482                         .ops = &clk_branch2_ops,
2483                 },
2484         },
2485 };
2486
2487 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2488         .halt_reg = 0x26048,
2489         .clkr = {
2490                 .enable_reg = 0x26048,
2491                 .enable_mask = BIT(0),
2492                 .hw.init = &(struct clk_init_data){
2493                         .name = "gcc_sys_noc_pcie0_axi_clk",
2494                         .parent_names = (const char *[]){
2495                                 "pcie0_axi_clk_src"
2496                         },
2497                         .num_parents = 1,
2498                         .flags = CLK_SET_RATE_PARENT,
2499                         .ops = &clk_branch2_ops,
2500                 },
2501         },
2502 };
2503
2504 static struct clk_branch gcc_pcie1_ahb_clk = {
2505         .halt_reg = 0x76010,
2506         .clkr = {
2507                 .enable_reg = 0x76010,
2508                 .enable_mask = BIT(0),
2509                 .hw.init = &(struct clk_init_data){
2510                         .name = "gcc_pcie1_ahb_clk",
2511                         .parent_names = (const char *[]){
2512                                 "pcnoc_clk_src"
2513                         },
2514                         .num_parents = 1,
2515                         .flags = CLK_SET_RATE_PARENT,
2516                         .ops = &clk_branch2_ops,
2517                 },
2518         },
2519 };
2520
2521 static struct clk_branch gcc_pcie1_aux_clk = {
2522         .halt_reg = 0x76014,
2523         .clkr = {
2524                 .enable_reg = 0x76014,
2525                 .enable_mask = BIT(0),
2526                 .hw.init = &(struct clk_init_data){
2527                         .name = "gcc_pcie1_aux_clk",
2528                         .parent_names = (const char *[]){
2529                                 "pcie1_aux_clk_src"
2530                         },
2531                         .num_parents = 1,
2532                         .flags = CLK_SET_RATE_PARENT,
2533                         .ops = &clk_branch2_ops,
2534                 },
2535         },
2536 };
2537
2538 static struct clk_branch gcc_pcie1_axi_m_clk = {
2539         .halt_reg = 0x76008,
2540         .clkr = {
2541                 .enable_reg = 0x76008,
2542                 .enable_mask = BIT(0),
2543                 .hw.init = &(struct clk_init_data){
2544                         .name = "gcc_pcie1_axi_m_clk",
2545                         .parent_names = (const char *[]){
2546                                 "pcie1_axi_clk_src"
2547                         },
2548                         .num_parents = 1,
2549                         .flags = CLK_SET_RATE_PARENT,
2550                         .ops = &clk_branch2_ops,
2551                 },
2552         },
2553 };
2554
2555 static struct clk_branch gcc_pcie1_axi_s_clk = {
2556         .halt_reg = 0x7600c,
2557         .clkr = {
2558                 .enable_reg = 0x7600c,
2559                 .enable_mask = BIT(0),
2560                 .hw.init = &(struct clk_init_data){
2561                         .name = "gcc_pcie1_axi_s_clk",
2562                         .parent_names = (const char *[]){
2563                                 "pcie1_axi_clk_src"
2564                         },
2565                         .num_parents = 1,
2566                         .flags = CLK_SET_RATE_PARENT,
2567                         .ops = &clk_branch2_ops,
2568                 },
2569         },
2570 };
2571
2572 static struct clk_branch gcc_pcie1_pipe_clk = {
2573         .halt_reg = 0x76018,
2574         .halt_check = BRANCH_HALT_DELAY,
2575         .clkr = {
2576                 .enable_reg = 0x76018,
2577                 .enable_mask = BIT(0),
2578                 .hw.init = &(struct clk_init_data){
2579                         .name = "gcc_pcie1_pipe_clk",
2580                         .parent_names = (const char *[]){
2581                                 "pcie1_pipe_clk_src"
2582                         },
2583                         .num_parents = 1,
2584                         .flags = CLK_SET_RATE_PARENT,
2585                         .ops = &clk_branch2_ops,
2586                 },
2587         },
2588 };
2589
2590 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2591         .halt_reg = 0x2604c,
2592         .clkr = {
2593                 .enable_reg = 0x2604c,
2594                 .enable_mask = BIT(0),
2595                 .hw.init = &(struct clk_init_data){
2596                         .name = "gcc_sys_noc_pcie1_axi_clk",
2597                         .parent_names = (const char *[]){
2598                                 "pcie1_axi_clk_src"
2599                         },
2600                         .num_parents = 1,
2601                         .flags = CLK_SET_RATE_PARENT,
2602                         .ops = &clk_branch2_ops,
2603                 },
2604         },
2605 };
2606
2607 static struct clk_branch gcc_usb0_aux_clk = {
2608         .halt_reg = 0x3e044,
2609         .clkr = {
2610                 .enable_reg = 0x3e044,
2611                 .enable_mask = BIT(0),
2612                 .hw.init = &(struct clk_init_data){
2613                         .name = "gcc_usb0_aux_clk",
2614                         .parent_names = (const char *[]){
2615                                 "usb0_aux_clk_src"
2616                         },
2617                         .num_parents = 1,
2618                         .flags = CLK_SET_RATE_PARENT,
2619                         .ops = &clk_branch2_ops,
2620                 },
2621         },
2622 };
2623
2624 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2625         .halt_reg = 0x26040,
2626         .clkr = {
2627                 .enable_reg = 0x26040,
2628                 .enable_mask = BIT(0),
2629                 .hw.init = &(struct clk_init_data){
2630                         .name = "gcc_sys_noc_usb0_axi_clk",
2631                         .parent_names = (const char *[]){
2632                                 "usb0_master_clk_src"
2633                         },
2634                         .num_parents = 1,
2635                         .flags = CLK_SET_RATE_PARENT,
2636                         .ops = &clk_branch2_ops,
2637                 },
2638         },
2639 };
2640
2641 static struct clk_branch gcc_usb0_master_clk = {
2642         .halt_reg = 0x3e000,
2643         .clkr = {
2644                 .enable_reg = 0x3e000,
2645                 .enable_mask = BIT(0),
2646                 .hw.init = &(struct clk_init_data){
2647                         .name = "gcc_usb0_master_clk",
2648                         .parent_names = (const char *[]){
2649                                 "usb0_master_clk_src"
2650                         },
2651                         .num_parents = 1,
2652                         .flags = CLK_SET_RATE_PARENT,
2653                         .ops = &clk_branch2_ops,
2654                 },
2655         },
2656 };
2657
2658 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2659         .halt_reg = 0x3e008,
2660         .clkr = {
2661                 .enable_reg = 0x3e008,
2662                 .enable_mask = BIT(0),
2663                 .hw.init = &(struct clk_init_data){
2664                         .name = "gcc_usb0_mock_utmi_clk",
2665                         .parent_names = (const char *[]){
2666                                 "usb0_mock_utmi_clk_src"
2667                         },
2668                         .num_parents = 1,
2669                         .flags = CLK_SET_RATE_PARENT,
2670                         .ops = &clk_branch2_ops,
2671                 },
2672         },
2673 };
2674
2675 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2676         .halt_reg = 0x3e080,
2677         .clkr = {
2678                 .enable_reg = 0x3e080,
2679                 .enable_mask = BIT(0),
2680                 .hw.init = &(struct clk_init_data){
2681                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2682                         .parent_names = (const char *[]){
2683                                 "pcnoc_clk_src"
2684                         },
2685                         .num_parents = 1,
2686                         .flags = CLK_SET_RATE_PARENT,
2687                         .ops = &clk_branch2_ops,
2688                 },
2689         },
2690 };
2691
2692 static struct clk_branch gcc_usb0_pipe_clk = {
2693         .halt_reg = 0x3e040,
2694         .halt_check = BRANCH_HALT_DELAY,
2695         .clkr = {
2696                 .enable_reg = 0x3e040,
2697                 .enable_mask = BIT(0),
2698                 .hw.init = &(struct clk_init_data){
2699                         .name = "gcc_usb0_pipe_clk",
2700                         .parent_names = (const char *[]){
2701                                 "usb0_pipe_clk_src"
2702                         },
2703                         .num_parents = 1,
2704                         .flags = CLK_SET_RATE_PARENT,
2705                         .ops = &clk_branch2_ops,
2706                 },
2707         },
2708 };
2709
2710 static struct clk_branch gcc_usb0_sleep_clk = {
2711         .halt_reg = 0x3e004,
2712         .clkr = {
2713                 .enable_reg = 0x3e004,
2714                 .enable_mask = BIT(0),
2715                 .hw.init = &(struct clk_init_data){
2716                         .name = "gcc_usb0_sleep_clk",
2717                         .parent_names = (const char *[]){
2718                                 "gcc_sleep_clk_src"
2719                         },
2720                         .num_parents = 1,
2721                         .flags = CLK_SET_RATE_PARENT,
2722                         .ops = &clk_branch2_ops,
2723                 },
2724         },
2725 };
2726
2727 static struct clk_branch gcc_usb1_aux_clk = {
2728         .halt_reg = 0x3f044,
2729         .clkr = {
2730                 .enable_reg = 0x3f044,
2731                 .enable_mask = BIT(0),
2732                 .hw.init = &(struct clk_init_data){
2733                         .name = "gcc_usb1_aux_clk",
2734                         .parent_names = (const char *[]){
2735                                 "usb1_aux_clk_src"
2736                         },
2737                         .num_parents = 1,
2738                         .flags = CLK_SET_RATE_PARENT,
2739                         .ops = &clk_branch2_ops,
2740                 },
2741         },
2742 };
2743
2744 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2745         .halt_reg = 0x26044,
2746         .clkr = {
2747                 .enable_reg = 0x26044,
2748                 .enable_mask = BIT(0),
2749                 .hw.init = &(struct clk_init_data){
2750                         .name = "gcc_sys_noc_usb1_axi_clk",
2751                         .parent_names = (const char *[]){
2752                                 "usb1_master_clk_src"
2753                         },
2754                         .num_parents = 1,
2755                         .flags = CLK_SET_RATE_PARENT,
2756                         .ops = &clk_branch2_ops,
2757                 },
2758         },
2759 };
2760
2761 static struct clk_branch gcc_usb1_master_clk = {
2762         .halt_reg = 0x3f000,
2763         .clkr = {
2764                 .enable_reg = 0x3f000,
2765                 .enable_mask = BIT(0),
2766                 .hw.init = &(struct clk_init_data){
2767                         .name = "gcc_usb1_master_clk",
2768                         .parent_names = (const char *[]){
2769                                 "usb1_master_clk_src"
2770                         },
2771                         .num_parents = 1,
2772                         .flags = CLK_SET_RATE_PARENT,
2773                         .ops = &clk_branch2_ops,
2774                 },
2775         },
2776 };
2777
2778 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2779         .halt_reg = 0x3f008,
2780         .clkr = {
2781                 .enable_reg = 0x3f008,
2782                 .enable_mask = BIT(0),
2783                 .hw.init = &(struct clk_init_data){
2784                         .name = "gcc_usb1_mock_utmi_clk",
2785                         .parent_names = (const char *[]){
2786                                 "usb1_mock_utmi_clk_src"
2787                         },
2788                         .num_parents = 1,
2789                         .flags = CLK_SET_RATE_PARENT,
2790                         .ops = &clk_branch2_ops,
2791                 },
2792         },
2793 };
2794
2795 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2796         .halt_reg = 0x3f080,
2797         .clkr = {
2798                 .enable_reg = 0x3f080,
2799                 .enable_mask = BIT(0),
2800                 .hw.init = &(struct clk_init_data){
2801                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2802                         .parent_names = (const char *[]){
2803                                 "pcnoc_clk_src"
2804                         },
2805                         .num_parents = 1,
2806                         .flags = CLK_SET_RATE_PARENT,
2807                         .ops = &clk_branch2_ops,
2808                 },
2809         },
2810 };
2811
2812 static struct clk_branch gcc_usb1_pipe_clk = {
2813         .halt_reg = 0x3f040,
2814         .halt_check = BRANCH_HALT_DELAY,
2815         .clkr = {
2816                 .enable_reg = 0x3f040,
2817                 .enable_mask = BIT(0),
2818                 .hw.init = &(struct clk_init_data){
2819                         .name = "gcc_usb1_pipe_clk",
2820                         .parent_names = (const char *[]){
2821                                 "usb1_pipe_clk_src"
2822                         },
2823                         .num_parents = 1,
2824                         .flags = CLK_SET_RATE_PARENT,
2825                         .ops = &clk_branch2_ops,
2826                 },
2827         },
2828 };
2829
2830 static struct clk_branch gcc_usb1_sleep_clk = {
2831         .halt_reg = 0x3f004,
2832         .clkr = {
2833                 .enable_reg = 0x3f004,
2834                 .enable_mask = BIT(0),
2835                 .hw.init = &(struct clk_init_data){
2836                         .name = "gcc_usb1_sleep_clk",
2837                         .parent_names = (const char *[]){
2838                                 "gcc_sleep_clk_src"
2839                         },
2840                         .num_parents = 1,
2841                         .flags = CLK_SET_RATE_PARENT,
2842                         .ops = &clk_branch2_ops,
2843                 },
2844         },
2845 };
2846
2847 static struct clk_branch gcc_sdcc1_ahb_clk = {
2848         .halt_reg = 0x4201c,
2849         .clkr = {
2850                 .enable_reg = 0x4201c,
2851                 .enable_mask = BIT(0),
2852                 .hw.init = &(struct clk_init_data){
2853                         .name = "gcc_sdcc1_ahb_clk",
2854                         .parent_names = (const char *[]){
2855                                 "pcnoc_clk_src"
2856                         },
2857                         .num_parents = 1,
2858                         .flags = CLK_SET_RATE_PARENT,
2859                         .ops = &clk_branch2_ops,
2860                 },
2861         },
2862 };
2863
2864 static struct clk_branch gcc_sdcc1_apps_clk = {
2865         .halt_reg = 0x42018,
2866         .clkr = {
2867                 .enable_reg = 0x42018,
2868                 .enable_mask = BIT(0),
2869                 .hw.init = &(struct clk_init_data){
2870                         .name = "gcc_sdcc1_apps_clk",
2871                         .parent_names = (const char *[]){
2872                                 "sdcc1_apps_clk_src"
2873                         },
2874                         .num_parents = 1,
2875                         .flags = CLK_SET_RATE_PARENT,
2876                         .ops = &clk_branch2_ops,
2877                 },
2878         },
2879 };
2880
2881 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2882         .halt_reg = 0x5d014,
2883         .clkr = {
2884                 .enable_reg = 0x5d014,
2885                 .enable_mask = BIT(0),
2886                 .hw.init = &(struct clk_init_data){
2887                         .name = "gcc_sdcc1_ice_core_clk",
2888                         .parent_names = (const char *[]){
2889                                 "sdcc1_ice_core_clk_src"
2890                         },
2891                         .num_parents = 1,
2892                         .flags = CLK_SET_RATE_PARENT,
2893                         .ops = &clk_branch2_ops,
2894                 },
2895         },
2896 };
2897
2898 static struct clk_branch gcc_sdcc2_ahb_clk = {
2899         .halt_reg = 0x4301c,
2900         .clkr = {
2901                 .enable_reg = 0x4301c,
2902                 .enable_mask = BIT(0),
2903                 .hw.init = &(struct clk_init_data){
2904                         .name = "gcc_sdcc2_ahb_clk",
2905                         .parent_names = (const char *[]){
2906                                 "pcnoc_clk_src"
2907                         },
2908                         .num_parents = 1,
2909                         .flags = CLK_SET_RATE_PARENT,
2910                         .ops = &clk_branch2_ops,
2911                 },
2912         },
2913 };
2914
2915 static struct clk_branch gcc_sdcc2_apps_clk = {
2916         .halt_reg = 0x43018,
2917         .clkr = {
2918                 .enable_reg = 0x43018,
2919                 .enable_mask = BIT(0),
2920                 .hw.init = &(struct clk_init_data){
2921                         .name = "gcc_sdcc2_apps_clk",
2922                         .parent_names = (const char *[]){
2923                                 "sdcc2_apps_clk_src"
2924                         },
2925                         .num_parents = 1,
2926                         .flags = CLK_SET_RATE_PARENT,
2927                         .ops = &clk_branch2_ops,
2928                 },
2929         },
2930 };
2931
2932 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2933         .halt_reg = 0x1d03c,
2934         .clkr = {
2935                 .enable_reg = 0x1d03c,
2936                 .enable_mask = BIT(0),
2937                 .hw.init = &(struct clk_init_data){
2938                         .name = "gcc_mem_noc_nss_axi_clk",
2939                         .parent_names = (const char *[]){
2940                                 "nss_noc_clk_src"
2941                         },
2942                         .num_parents = 1,
2943                         .flags = CLK_SET_RATE_PARENT,
2944                         .ops = &clk_branch2_ops,
2945                 },
2946         },
2947 };
2948
2949 static struct clk_branch gcc_nss_ce_apb_clk = {
2950         .halt_reg = 0x68174,
2951         .clkr = {
2952                 .enable_reg = 0x68174,
2953                 .enable_mask = BIT(0),
2954                 .hw.init = &(struct clk_init_data){
2955                         .name = "gcc_nss_ce_apb_clk",
2956                         .parent_names = (const char *[]){
2957                                 "nss_ce_clk_src"
2958                         },
2959                         .num_parents = 1,
2960                         .flags = CLK_SET_RATE_PARENT,
2961                         .ops = &clk_branch2_ops,
2962                 },
2963         },
2964 };
2965
2966 static struct clk_branch gcc_nss_ce_axi_clk = {
2967         .halt_reg = 0x68170,
2968         .clkr = {
2969                 .enable_reg = 0x68170,
2970                 .enable_mask = BIT(0),
2971                 .hw.init = &(struct clk_init_data){
2972                         .name = "gcc_nss_ce_axi_clk",
2973                         .parent_names = (const char *[]){
2974                                 "nss_ce_clk_src"
2975                         },
2976                         .num_parents = 1,
2977                         .flags = CLK_SET_RATE_PARENT,
2978                         .ops = &clk_branch2_ops,
2979                 },
2980         },
2981 };
2982
2983 static struct clk_branch gcc_nss_cfg_clk = {
2984         .halt_reg = 0x68160,
2985         .clkr = {
2986                 .enable_reg = 0x68160,
2987                 .enable_mask = BIT(0),
2988                 .hw.init = &(struct clk_init_data){
2989                         .name = "gcc_nss_cfg_clk",
2990                         .parent_names = (const char *[]){
2991                                 "pcnoc_clk_src"
2992                         },
2993                         .num_parents = 1,
2994                         .flags = CLK_SET_RATE_PARENT,
2995                         .ops = &clk_branch2_ops,
2996                 },
2997         },
2998 };
2999
3000 static struct clk_branch gcc_nss_crypto_clk = {
3001         .halt_reg = 0x68164,
3002         .clkr = {
3003                 .enable_reg = 0x68164,
3004                 .enable_mask = BIT(0),
3005                 .hw.init = &(struct clk_init_data){
3006                         .name = "gcc_nss_crypto_clk",
3007                         .parent_names = (const char *[]){
3008                                 "nss_crypto_clk_src"
3009                         },
3010                         .num_parents = 1,
3011                         .flags = CLK_SET_RATE_PARENT,
3012                         .ops = &clk_branch2_ops,
3013                 },
3014         },
3015 };
3016
3017 static struct clk_branch gcc_nss_csr_clk = {
3018         .halt_reg = 0x68318,
3019         .clkr = {
3020                 .enable_reg = 0x68318,
3021                 .enable_mask = BIT(0),
3022                 .hw.init = &(struct clk_init_data){
3023                         .name = "gcc_nss_csr_clk",
3024                         .parent_names = (const char *[]){
3025                                 "nss_ce_clk_src"
3026                         },
3027                         .num_parents = 1,
3028                         .flags = CLK_SET_RATE_PARENT,
3029                         .ops = &clk_branch2_ops,
3030                 },
3031         },
3032 };
3033
3034 static struct clk_branch gcc_nss_edma_cfg_clk = {
3035         .halt_reg = 0x6819c,
3036         .clkr = {
3037                 .enable_reg = 0x6819c,
3038                 .enable_mask = BIT(0),
3039                 .hw.init = &(struct clk_init_data){
3040                         .name = "gcc_nss_edma_cfg_clk",
3041                         .parent_names = (const char *[]){
3042                                 "nss_ppe_clk_src"
3043                         },
3044                         .num_parents = 1,
3045                         .flags = CLK_SET_RATE_PARENT,
3046                         .ops = &clk_branch2_ops,
3047                 },
3048         },
3049 };
3050
3051 static struct clk_branch gcc_nss_edma_clk = {
3052         .halt_reg = 0x68198,
3053         .clkr = {
3054                 .enable_reg = 0x68198,
3055                 .enable_mask = BIT(0),
3056                 .hw.init = &(struct clk_init_data){
3057                         .name = "gcc_nss_edma_clk",
3058                         .parent_names = (const char *[]){
3059                                 "nss_ppe_clk_src"
3060                         },
3061                         .num_parents = 1,
3062                         .flags = CLK_SET_RATE_PARENT,
3063                         .ops = &clk_branch2_ops,
3064                 },
3065         },
3066 };
3067
3068 static struct clk_branch gcc_nss_imem_clk = {
3069         .halt_reg = 0x68178,
3070         .clkr = {
3071                 .enable_reg = 0x68178,
3072                 .enable_mask = BIT(0),
3073                 .hw.init = &(struct clk_init_data){
3074                         .name = "gcc_nss_imem_clk",
3075                         .parent_names = (const char *[]){
3076                                 "nss_imem_clk_src"
3077                         },
3078                         .num_parents = 1,
3079                         .flags = CLK_SET_RATE_PARENT,
3080                         .ops = &clk_branch2_ops,
3081                 },
3082         },
3083 };
3084
3085 static struct clk_branch gcc_nss_noc_clk = {
3086         .halt_reg = 0x68168,
3087         .clkr = {
3088                 .enable_reg = 0x68168,
3089                 .enable_mask = BIT(0),
3090                 .hw.init = &(struct clk_init_data){
3091                         .name = "gcc_nss_noc_clk",
3092                         .parent_names = (const char *[]){
3093                                 "nss_noc_clk_src"
3094                         },
3095                         .num_parents = 1,
3096                         .flags = CLK_SET_RATE_PARENT,
3097                         .ops = &clk_branch2_ops,
3098                 },
3099         },
3100 };
3101
3102 static struct clk_branch gcc_nss_ppe_btq_clk = {
3103         .halt_reg = 0x6833c,
3104         .clkr = {
3105                 .enable_reg = 0x6833c,
3106                 .enable_mask = BIT(0),
3107                 .hw.init = &(struct clk_init_data){
3108                         .name = "gcc_nss_ppe_btq_clk",
3109                         .parent_names = (const char *[]){
3110                                 "nss_ppe_clk_src"
3111                         },
3112                         .num_parents = 1,
3113                         .flags = CLK_SET_RATE_PARENT,
3114                         .ops = &clk_branch2_ops,
3115                 },
3116         },
3117 };
3118
3119 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3120         .halt_reg = 0x68194,
3121         .clkr = {
3122                 .enable_reg = 0x68194,
3123                 .enable_mask = BIT(0),
3124                 .hw.init = &(struct clk_init_data){
3125                         .name = "gcc_nss_ppe_cfg_clk",
3126                         .parent_names = (const char *[]){
3127                                 "nss_ppe_clk_src"
3128                         },
3129                         .num_parents = 1,
3130                         .flags = CLK_SET_RATE_PARENT,
3131                         .ops = &clk_branch2_ops,
3132                 },
3133         },
3134 };
3135
3136 static struct clk_branch gcc_nss_ppe_clk = {
3137         .halt_reg = 0x68190,
3138         .clkr = {
3139                 .enable_reg = 0x68190,
3140                 .enable_mask = BIT(0),
3141                 .hw.init = &(struct clk_init_data){
3142                         .name = "gcc_nss_ppe_clk",
3143                         .parent_names = (const char *[]){
3144                                 "nss_ppe_clk_src"
3145                         },
3146                         .num_parents = 1,
3147                         .flags = CLK_SET_RATE_PARENT,
3148                         .ops = &clk_branch2_ops,
3149                 },
3150         },
3151 };
3152
3153 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3154         .halt_reg = 0x68338,
3155         .clkr = {
3156                 .enable_reg = 0x68338,
3157                 .enable_mask = BIT(0),
3158                 .hw.init = &(struct clk_init_data){
3159                         .name = "gcc_nss_ppe_ipe_clk",
3160                         .parent_names = (const char *[]){
3161                                 "nss_ppe_clk_src"
3162                         },
3163                         .num_parents = 1,
3164                         .flags = CLK_SET_RATE_PARENT,
3165                         .ops = &clk_branch2_ops,
3166                 },
3167         },
3168 };
3169
3170 static struct clk_branch gcc_nss_ptp_ref_clk = {
3171         .halt_reg = 0x6816c,
3172         .clkr = {
3173                 .enable_reg = 0x6816c,
3174                 .enable_mask = BIT(0),
3175                 .hw.init = &(struct clk_init_data){
3176                         .name = "gcc_nss_ptp_ref_clk",
3177                         .parent_names = (const char *[]){
3178                                 "nss_ppe_cdiv_clk_src"
3179                         },
3180                         .num_parents = 1,
3181                         .flags = CLK_SET_RATE_PARENT,
3182                         .ops = &clk_branch2_ops,
3183                 },
3184         },
3185 };
3186
3187 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3188         .halt_reg = 0x6830c,
3189         .clkr = {
3190                 .enable_reg = 0x6830c,
3191                 .enable_mask = BIT(0),
3192                 .hw.init = &(struct clk_init_data){
3193                         .name = "gcc_nssnoc_ce_apb_clk",
3194                         .parent_names = (const char *[]){
3195                                 "nss_ce_clk_src"
3196                         },
3197                         .num_parents = 1,
3198                         .flags = CLK_SET_RATE_PARENT,
3199                         .ops = &clk_branch2_ops,
3200                 },
3201         },
3202 };
3203
3204 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3205         .halt_reg = 0x68308,
3206         .clkr = {
3207                 .enable_reg = 0x68308,
3208                 .enable_mask = BIT(0),
3209                 .hw.init = &(struct clk_init_data){
3210                         .name = "gcc_nssnoc_ce_axi_clk",
3211                         .parent_names = (const char *[]){
3212                                 "nss_ce_clk_src"
3213                         },
3214                         .num_parents = 1,
3215                         .flags = CLK_SET_RATE_PARENT,
3216                         .ops = &clk_branch2_ops,
3217                 },
3218         },
3219 };
3220
3221 static struct clk_branch gcc_nssnoc_crypto_clk = {
3222         .halt_reg = 0x68314,
3223         .clkr = {
3224                 .enable_reg = 0x68314,
3225                 .enable_mask = BIT(0),
3226                 .hw.init = &(struct clk_init_data){
3227                         .name = "gcc_nssnoc_crypto_clk",
3228                         .parent_names = (const char *[]){
3229                                 "nss_crypto_clk_src"
3230                         },
3231                         .num_parents = 1,
3232                         .flags = CLK_SET_RATE_PARENT,
3233                         .ops = &clk_branch2_ops,
3234                 },
3235         },
3236 };
3237
3238 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3239         .halt_reg = 0x68304,
3240         .clkr = {
3241                 .enable_reg = 0x68304,
3242                 .enable_mask = BIT(0),
3243                 .hw.init = &(struct clk_init_data){
3244                         .name = "gcc_nssnoc_ppe_cfg_clk",
3245                         .parent_names = (const char *[]){
3246                                 "nss_ppe_clk_src"
3247                         },
3248                         .num_parents = 1,
3249                         .flags = CLK_SET_RATE_PARENT,
3250                         .ops = &clk_branch2_ops,
3251                 },
3252         },
3253 };
3254
3255 static struct clk_branch gcc_nssnoc_ppe_clk = {
3256         .halt_reg = 0x68300,
3257         .clkr = {
3258                 .enable_reg = 0x68300,
3259                 .enable_mask = BIT(0),
3260                 .hw.init = &(struct clk_init_data){
3261                         .name = "gcc_nssnoc_ppe_clk",
3262                         .parent_names = (const char *[]){
3263                                 "nss_ppe_clk_src"
3264                         },
3265                         .num_parents = 1,
3266                         .flags = CLK_SET_RATE_PARENT,
3267                         .ops = &clk_branch2_ops,
3268                 },
3269         },
3270 };
3271
3272 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3273         .halt_reg = 0x68180,
3274         .clkr = {
3275                 .enable_reg = 0x68180,
3276                 .enable_mask = BIT(0),
3277                 .hw.init = &(struct clk_init_data){
3278                         .name = "gcc_nssnoc_qosgen_ref_clk",
3279                         .parent_names = (const char *[]){
3280                                 "gcc_xo_clk_src"
3281                         },
3282                         .num_parents = 1,
3283                         .flags = CLK_SET_RATE_PARENT,
3284                         .ops = &clk_branch2_ops,
3285                 },
3286         },
3287 };
3288
3289 static struct clk_branch gcc_nssnoc_snoc_clk = {
3290         .halt_reg = 0x68188,
3291         .clkr = {
3292                 .enable_reg = 0x68188,
3293                 .enable_mask = BIT(0),
3294                 .hw.init = &(struct clk_init_data){
3295                         .name = "gcc_nssnoc_snoc_clk",
3296                         .parent_names = (const char *[]){
3297                                 "system_noc_clk_src"
3298                         },
3299                         .num_parents = 1,
3300                         .flags = CLK_SET_RATE_PARENT,
3301                         .ops = &clk_branch2_ops,
3302                 },
3303         },
3304 };
3305
3306 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3307         .halt_reg = 0x68184,
3308         .clkr = {
3309                 .enable_reg = 0x68184,
3310                 .enable_mask = BIT(0),
3311                 .hw.init = &(struct clk_init_data){
3312                         .name = "gcc_nssnoc_timeout_ref_clk",
3313                         .parent_names = (const char *[]){
3314                                 "gcc_xo_div4_clk_src"
3315                         },
3316                         .num_parents = 1,
3317                         .flags = CLK_SET_RATE_PARENT,
3318                         .ops = &clk_branch2_ops,
3319                 },
3320         },
3321 };
3322
3323 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3324         .halt_reg = 0x68270,
3325         .clkr = {
3326                 .enable_reg = 0x68270,
3327                 .enable_mask = BIT(0),
3328                 .hw.init = &(struct clk_init_data){
3329                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3330                         .parent_names = (const char *[]){
3331                                 "nss_ce_clk_src"
3332                         },
3333                         .num_parents = 1,
3334                         .flags = CLK_SET_RATE_PARENT,
3335                         .ops = &clk_branch2_ops,
3336                 },
3337         },
3338 };
3339
3340 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3341         .halt_reg = 0x68274,
3342         .clkr = {
3343                 .enable_reg = 0x68274,
3344                 .enable_mask = BIT(0),
3345                 .hw.init = &(struct clk_init_data){
3346                         .name = "gcc_nssnoc_ubi1_ahb_clk",
3347                         .parent_names = (const char *[]){
3348                                 "nss_ce_clk_src"
3349                         },
3350                         .num_parents = 1,
3351                         .flags = CLK_SET_RATE_PARENT,
3352                         .ops = &clk_branch2_ops,
3353                 },
3354         },
3355 };
3356
3357 static struct clk_branch gcc_ubi0_ahb_clk = {
3358         .halt_reg = 0x6820c,
3359         .clkr = {
3360                 .enable_reg = 0x6820c,
3361                 .enable_mask = BIT(0),
3362                 .hw.init = &(struct clk_init_data){
3363                         .name = "gcc_ubi0_ahb_clk",
3364                         .parent_names = (const char *[]){
3365                                 "nss_ce_clk_src"
3366                         },
3367                         .num_parents = 1,
3368                         .flags = CLK_SET_RATE_PARENT,
3369                         .ops = &clk_branch2_ops,
3370                 },
3371         },
3372 };
3373
3374 static struct clk_branch gcc_ubi0_axi_clk = {
3375         .halt_reg = 0x68200,
3376         .clkr = {
3377                 .enable_reg = 0x68200,
3378                 .enable_mask = BIT(0),
3379                 .hw.init = &(struct clk_init_data){
3380                         .name = "gcc_ubi0_axi_clk",
3381                         .parent_names = (const char *[]){
3382                                 "nss_noc_clk_src"
3383                         },
3384                         .num_parents = 1,
3385                         .flags = CLK_SET_RATE_PARENT,
3386                         .ops = &clk_branch2_ops,
3387                 },
3388         },
3389 };
3390
3391 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3392         .halt_reg = 0x68204,
3393         .clkr = {
3394                 .enable_reg = 0x68204,
3395                 .enable_mask = BIT(0),
3396                 .hw.init = &(struct clk_init_data){
3397                         .name = "gcc_ubi0_nc_axi_clk",
3398                         .parent_names = (const char *[]){
3399                                 "nss_noc_clk_src"
3400                         },
3401                         .num_parents = 1,
3402                         .flags = CLK_SET_RATE_PARENT,
3403                         .ops = &clk_branch2_ops,
3404                 },
3405         },
3406 };
3407
3408 static struct clk_branch gcc_ubi0_core_clk = {
3409         .halt_reg = 0x68210,
3410         .clkr = {
3411                 .enable_reg = 0x68210,
3412                 .enable_mask = BIT(0),
3413                 .hw.init = &(struct clk_init_data){
3414                         .name = "gcc_ubi0_core_clk",
3415                         .parent_names = (const char *[]){
3416                                 "nss_ubi0_div_clk_src"
3417                         },
3418                         .num_parents = 1,
3419                         .flags = CLK_SET_RATE_PARENT,
3420                         .ops = &clk_branch2_ops,
3421                 },
3422         },
3423 };
3424
3425 static struct clk_branch gcc_ubi0_mpt_clk = {
3426         .halt_reg = 0x68208,
3427         .clkr = {
3428                 .enable_reg = 0x68208,
3429                 .enable_mask = BIT(0),
3430                 .hw.init = &(struct clk_init_data){
3431                         .name = "gcc_ubi0_mpt_clk",
3432                         .parent_names = (const char *[]){
3433                                 "ubi_mpt_clk_src"
3434                         },
3435                         .num_parents = 1,
3436                         .flags = CLK_SET_RATE_PARENT,
3437                         .ops = &clk_branch2_ops,
3438                 },
3439         },
3440 };
3441
3442 static struct clk_branch gcc_ubi1_ahb_clk = {
3443         .halt_reg = 0x6822c,
3444         .clkr = {
3445                 .enable_reg = 0x6822c,
3446                 .enable_mask = BIT(0),
3447                 .hw.init = &(struct clk_init_data){
3448                         .name = "gcc_ubi1_ahb_clk",
3449                         .parent_names = (const char *[]){
3450                                 "nss_ce_clk_src"
3451                         },
3452                         .num_parents = 1,
3453                         .flags = CLK_SET_RATE_PARENT,
3454                         .ops = &clk_branch2_ops,
3455                 },
3456         },
3457 };
3458
3459 static struct clk_branch gcc_ubi1_axi_clk = {
3460         .halt_reg = 0x68220,
3461         .clkr = {
3462                 .enable_reg = 0x68220,
3463                 .enable_mask = BIT(0),
3464                 .hw.init = &(struct clk_init_data){
3465                         .name = "gcc_ubi1_axi_clk",
3466                         .parent_names = (const char *[]){
3467                                 "nss_noc_clk_src"
3468                         },
3469                         .num_parents = 1,
3470                         .flags = CLK_SET_RATE_PARENT,
3471                         .ops = &clk_branch2_ops,
3472                 },
3473         },
3474 };
3475
3476 static struct clk_branch gcc_ubi1_nc_axi_clk = {
3477         .halt_reg = 0x68224,
3478         .clkr = {
3479                 .enable_reg = 0x68224,
3480                 .enable_mask = BIT(0),
3481                 .hw.init = &(struct clk_init_data){
3482                         .name = "gcc_ubi1_nc_axi_clk",
3483                         .parent_names = (const char *[]){
3484                                 "nss_noc_clk_src"
3485                         },
3486                         .num_parents = 1,
3487                         .flags = CLK_SET_RATE_PARENT,
3488                         .ops = &clk_branch2_ops,
3489                 },
3490         },
3491 };
3492
3493 static struct clk_branch gcc_ubi1_core_clk = {
3494         .halt_reg = 0x68230,
3495         .clkr = {
3496                 .enable_reg = 0x68230,
3497                 .enable_mask = BIT(0),
3498                 .hw.init = &(struct clk_init_data){
3499                         .name = "gcc_ubi1_core_clk",
3500                         .parent_names = (const char *[]){
3501                                 "nss_ubi1_div_clk_src"
3502                         },
3503                         .num_parents = 1,
3504                         .flags = CLK_SET_RATE_PARENT,
3505                         .ops = &clk_branch2_ops,
3506                 },
3507         },
3508 };
3509
3510 static struct clk_branch gcc_ubi1_mpt_clk = {
3511         .halt_reg = 0x68228,
3512         .clkr = {
3513                 .enable_reg = 0x68228,
3514                 .enable_mask = BIT(0),
3515                 .hw.init = &(struct clk_init_data){
3516                         .name = "gcc_ubi1_mpt_clk",
3517                         .parent_names = (const char *[]){
3518                                 "ubi_mpt_clk_src"
3519                         },
3520                         .num_parents = 1,
3521                         .flags = CLK_SET_RATE_PARENT,
3522                         .ops = &clk_branch2_ops,
3523                 },
3524         },
3525 };
3526
3527 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3528         .halt_reg = 0x56308,
3529         .clkr = {
3530                 .enable_reg = 0x56308,
3531                 .enable_mask = BIT(0),
3532                 .hw.init = &(struct clk_init_data){
3533                         .name = "gcc_cmn_12gpll_ahb_clk",
3534                         .parent_names = (const char *[]){
3535                                 "pcnoc_clk_src"
3536                         },
3537                         .num_parents = 1,
3538                         .flags = CLK_SET_RATE_PARENT,
3539                         .ops = &clk_branch2_ops,
3540                 },
3541         },
3542 };
3543
3544 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3545         .halt_reg = 0x5630c,
3546         .clkr = {
3547                 .enable_reg = 0x5630c,
3548                 .enable_mask = BIT(0),
3549                 .hw.init = &(struct clk_init_data){
3550                         .name = "gcc_cmn_12gpll_sys_clk",
3551                         .parent_names = (const char *[]){
3552                                 "gcc_xo_clk_src"
3553                         },
3554                         .num_parents = 1,
3555                         .flags = CLK_SET_RATE_PARENT,
3556                         .ops = &clk_branch2_ops,
3557                 },
3558         },
3559 };
3560
3561 static struct clk_branch gcc_mdio_ahb_clk = {
3562         .halt_reg = 0x58004,
3563         .clkr = {
3564                 .enable_reg = 0x58004,
3565                 .enable_mask = BIT(0),
3566                 .hw.init = &(struct clk_init_data){
3567                         .name = "gcc_mdio_ahb_clk",
3568                         .parent_names = (const char *[]){
3569                                 "pcnoc_clk_src"
3570                         },
3571                         .num_parents = 1,
3572                         .flags = CLK_SET_RATE_PARENT,
3573                         .ops = &clk_branch2_ops,
3574                 },
3575         },
3576 };
3577
3578 static struct clk_branch gcc_uniphy0_ahb_clk = {
3579         .halt_reg = 0x56008,
3580         .clkr = {
3581                 .enable_reg = 0x56008,
3582                 .enable_mask = BIT(0),
3583                 .hw.init = &(struct clk_init_data){
3584                         .name = "gcc_uniphy0_ahb_clk",
3585                         .parent_names = (const char *[]){
3586                                 "pcnoc_clk_src"
3587                         },
3588                         .num_parents = 1,
3589                         .flags = CLK_SET_RATE_PARENT,
3590                         .ops = &clk_branch2_ops,
3591                 },
3592         },
3593 };
3594
3595 static struct clk_branch gcc_uniphy0_sys_clk = {
3596         .halt_reg = 0x5600c,
3597         .clkr = {
3598                 .enable_reg = 0x5600c,
3599                 .enable_mask = BIT(0),
3600                 .hw.init = &(struct clk_init_data){
3601                         .name = "gcc_uniphy0_sys_clk",
3602                         .parent_names = (const char *[]){
3603                                 "gcc_xo_clk_src"
3604                         },
3605                         .num_parents = 1,
3606                         .flags = CLK_SET_RATE_PARENT,
3607                         .ops = &clk_branch2_ops,
3608                 },
3609         },
3610 };
3611
3612 static struct clk_branch gcc_uniphy1_ahb_clk = {
3613         .halt_reg = 0x56108,
3614         .clkr = {
3615                 .enable_reg = 0x56108,
3616                 .enable_mask = BIT(0),
3617                 .hw.init = &(struct clk_init_data){
3618                         .name = "gcc_uniphy1_ahb_clk",
3619                         .parent_names = (const char *[]){
3620                                 "pcnoc_clk_src"
3621                         },
3622                         .num_parents = 1,
3623                         .flags = CLK_SET_RATE_PARENT,
3624                         .ops = &clk_branch2_ops,
3625                 },
3626         },
3627 };
3628
3629 static struct clk_branch gcc_uniphy1_sys_clk = {
3630         .halt_reg = 0x5610c,
3631         .clkr = {
3632                 .enable_reg = 0x5610c,
3633                 .enable_mask = BIT(0),
3634                 .hw.init = &(struct clk_init_data){
3635                         .name = "gcc_uniphy1_sys_clk",
3636                         .parent_names = (const char *[]){
3637                                 "gcc_xo_clk_src"
3638                         },
3639                         .num_parents = 1,
3640                         .flags = CLK_SET_RATE_PARENT,
3641                         .ops = &clk_branch2_ops,
3642                 },
3643         },
3644 };
3645
3646 static struct clk_branch gcc_uniphy2_ahb_clk = {
3647         .halt_reg = 0x56208,
3648         .clkr = {
3649                 .enable_reg = 0x56208,
3650                 .enable_mask = BIT(0),
3651                 .hw.init = &(struct clk_init_data){
3652                         .name = "gcc_uniphy2_ahb_clk",
3653                         .parent_names = (const char *[]){
3654                                 "pcnoc_clk_src"
3655                         },
3656                         .num_parents = 1,
3657                         .flags = CLK_SET_RATE_PARENT,
3658                         .ops = &clk_branch2_ops,
3659                 },
3660         },
3661 };
3662
3663 static struct clk_branch gcc_uniphy2_sys_clk = {
3664         .halt_reg = 0x5620c,
3665         .clkr = {
3666                 .enable_reg = 0x5620c,
3667                 .enable_mask = BIT(0),
3668                 .hw.init = &(struct clk_init_data){
3669                         .name = "gcc_uniphy2_sys_clk",
3670                         .parent_names = (const char *[]){
3671                                 "gcc_xo_clk_src"
3672                         },
3673                         .num_parents = 1,
3674                         .flags = CLK_SET_RATE_PARENT,
3675                         .ops = &clk_branch2_ops,
3676                 },
3677         },
3678 };
3679
3680 static struct clk_branch gcc_nss_port1_rx_clk = {
3681         .halt_reg = 0x68240,
3682         .clkr = {
3683                 .enable_reg = 0x68240,
3684                 .enable_mask = BIT(0),
3685                 .hw.init = &(struct clk_init_data){
3686                         .name = "gcc_nss_port1_rx_clk",
3687                         .parent_names = (const char *[]){
3688                                 "nss_port1_rx_div_clk_src"
3689                         },
3690                         .num_parents = 1,
3691                         .flags = CLK_SET_RATE_PARENT,
3692                         .ops = &clk_branch2_ops,
3693                 },
3694         },
3695 };
3696
3697 static struct clk_branch gcc_nss_port1_tx_clk = {
3698         .halt_reg = 0x68244,
3699         .clkr = {
3700                 .enable_reg = 0x68244,
3701                 .enable_mask = BIT(0),
3702                 .hw.init = &(struct clk_init_data){
3703                         .name = "gcc_nss_port1_tx_clk",
3704                         .parent_names = (const char *[]){
3705                                 "nss_port1_tx_div_clk_src"
3706                         },
3707                         .num_parents = 1,
3708                         .flags = CLK_SET_RATE_PARENT,
3709                         .ops = &clk_branch2_ops,
3710                 },
3711         },
3712 };
3713
3714 static struct clk_branch gcc_nss_port2_rx_clk = {
3715         .halt_reg = 0x68248,
3716         .clkr = {
3717                 .enable_reg = 0x68248,
3718                 .enable_mask = BIT(0),
3719                 .hw.init = &(struct clk_init_data){
3720                         .name = "gcc_nss_port2_rx_clk",
3721                         .parent_names = (const char *[]){
3722                                 "nss_port2_rx_div_clk_src"
3723                         },
3724                         .num_parents = 1,
3725                         .flags = CLK_SET_RATE_PARENT,
3726                         .ops = &clk_branch2_ops,
3727                 },
3728         },
3729 };
3730
3731 static struct clk_branch gcc_nss_port2_tx_clk = {
3732         .halt_reg = 0x6824c,
3733         .clkr = {
3734                 .enable_reg = 0x6824c,
3735                 .enable_mask = BIT(0),
3736                 .hw.init = &(struct clk_init_data){
3737                         .name = "gcc_nss_port2_tx_clk",
3738                         .parent_names = (const char *[]){
3739                                 "nss_port2_tx_div_clk_src"
3740                         },
3741                         .num_parents = 1,
3742                         .flags = CLK_SET_RATE_PARENT,
3743                         .ops = &clk_branch2_ops,
3744                 },
3745         },
3746 };
3747
3748 static struct clk_branch gcc_nss_port3_rx_clk = {
3749         .halt_reg = 0x68250,
3750         .clkr = {
3751                 .enable_reg = 0x68250,
3752                 .enable_mask = BIT(0),
3753                 .hw.init = &(struct clk_init_data){
3754                         .name = "gcc_nss_port3_rx_clk",
3755                         .parent_names = (const char *[]){
3756                                 "nss_port3_rx_div_clk_src"
3757                         },
3758                         .num_parents = 1,
3759                         .flags = CLK_SET_RATE_PARENT,
3760                         .ops = &clk_branch2_ops,
3761                 },
3762         },
3763 };
3764
3765 static struct clk_branch gcc_nss_port3_tx_clk = {
3766         .halt_reg = 0x68254,
3767         .clkr = {
3768                 .enable_reg = 0x68254,
3769                 .enable_mask = BIT(0),
3770                 .hw.init = &(struct clk_init_data){
3771                         .name = "gcc_nss_port3_tx_clk",
3772                         .parent_names = (const char *[]){
3773                                 "nss_port3_tx_div_clk_src"
3774                         },
3775                         .num_parents = 1,
3776                         .flags = CLK_SET_RATE_PARENT,
3777                         .ops = &clk_branch2_ops,
3778                 },
3779         },
3780 };
3781
3782 static struct clk_branch gcc_nss_port4_rx_clk = {
3783         .halt_reg = 0x68258,
3784         .clkr = {
3785                 .enable_reg = 0x68258,
3786                 .enable_mask = BIT(0),
3787                 .hw.init = &(struct clk_init_data){
3788                         .name = "gcc_nss_port4_rx_clk",
3789                         .parent_names = (const char *[]){
3790                                 "nss_port4_rx_div_clk_src"
3791                         },
3792                         .num_parents = 1,
3793                         .flags = CLK_SET_RATE_PARENT,
3794                         .ops = &clk_branch2_ops,
3795                 },
3796         },
3797 };
3798
3799 static struct clk_branch gcc_nss_port4_tx_clk = {
3800         .halt_reg = 0x6825c,
3801         .clkr = {
3802                 .enable_reg = 0x6825c,
3803                 .enable_mask = BIT(0),
3804                 .hw.init = &(struct clk_init_data){
3805                         .name = "gcc_nss_port4_tx_clk",
3806                         .parent_names = (const char *[]){
3807                                 "nss_port4_tx_div_clk_src"
3808                         },
3809                         .num_parents = 1,
3810                         .flags = CLK_SET_RATE_PARENT,
3811                         .ops = &clk_branch2_ops,
3812                 },
3813         },
3814 };
3815
3816 static struct clk_branch gcc_nss_port5_rx_clk = {
3817         .halt_reg = 0x68260,
3818         .clkr = {
3819                 .enable_reg = 0x68260,
3820                 .enable_mask = BIT(0),
3821                 .hw.init = &(struct clk_init_data){
3822                         .name = "gcc_nss_port5_rx_clk",
3823                         .parent_names = (const char *[]){
3824                                 "nss_port5_rx_div_clk_src"
3825                         },
3826                         .num_parents = 1,
3827                         .flags = CLK_SET_RATE_PARENT,
3828                         .ops = &clk_branch2_ops,
3829                 },
3830         },
3831 };
3832
3833 static struct clk_branch gcc_nss_port5_tx_clk = {
3834         .halt_reg = 0x68264,
3835         .clkr = {
3836                 .enable_reg = 0x68264,
3837                 .enable_mask = BIT(0),
3838                 .hw.init = &(struct clk_init_data){
3839                         .name = "gcc_nss_port5_tx_clk",
3840                         .parent_names = (const char *[]){
3841                                 "nss_port5_tx_div_clk_src"
3842                         },
3843                         .num_parents = 1,
3844                         .flags = CLK_SET_RATE_PARENT,
3845                         .ops = &clk_branch2_ops,
3846                 },
3847         },
3848 };
3849
3850 static struct clk_branch gcc_nss_port6_rx_clk = {
3851         .halt_reg = 0x68268,
3852         .clkr = {
3853                 .enable_reg = 0x68268,
3854                 .enable_mask = BIT(0),
3855                 .hw.init = &(struct clk_init_data){
3856                         .name = "gcc_nss_port6_rx_clk",
3857                         .parent_names = (const char *[]){
3858                                 "nss_port6_rx_div_clk_src"
3859                         },
3860                         .num_parents = 1,
3861                         .flags = CLK_SET_RATE_PARENT,
3862                         .ops = &clk_branch2_ops,
3863                 },
3864         },
3865 };
3866
3867 static struct clk_branch gcc_nss_port6_tx_clk = {
3868         .halt_reg = 0x6826c,
3869         .clkr = {
3870                 .enable_reg = 0x6826c,
3871                 .enable_mask = BIT(0),
3872                 .hw.init = &(struct clk_init_data){
3873                         .name = "gcc_nss_port6_tx_clk",
3874                         .parent_names = (const char *[]){
3875                                 "nss_port6_tx_div_clk_src"
3876                         },
3877                         .num_parents = 1,
3878                         .flags = CLK_SET_RATE_PARENT,
3879                         .ops = &clk_branch2_ops,
3880                 },
3881         },
3882 };
3883
3884 static struct clk_branch gcc_port1_mac_clk = {
3885         .halt_reg = 0x68320,
3886         .clkr = {
3887                 .enable_reg = 0x68320,
3888                 .enable_mask = BIT(0),
3889                 .hw.init = &(struct clk_init_data){
3890                         .name = "gcc_port1_mac_clk",
3891                         .parent_names = (const char *[]){
3892                                 "nss_ppe_clk_src"
3893                         },
3894                         .num_parents = 1,
3895                         .flags = CLK_SET_RATE_PARENT,
3896                         .ops = &clk_branch2_ops,
3897                 },
3898         },
3899 };
3900
3901 static struct clk_branch gcc_port2_mac_clk = {
3902         .halt_reg = 0x68324,
3903         .clkr = {
3904                 .enable_reg = 0x68324,
3905                 .enable_mask = BIT(0),
3906                 .hw.init = &(struct clk_init_data){
3907                         .name = "gcc_port2_mac_clk",
3908                         .parent_names = (const char *[]){
3909                                 "nss_ppe_clk_src"
3910                         },
3911                         .num_parents = 1,
3912                         .flags = CLK_SET_RATE_PARENT,
3913                         .ops = &clk_branch2_ops,
3914                 },
3915         },
3916 };
3917
3918 static struct clk_branch gcc_port3_mac_clk = {
3919         .halt_reg = 0x68328,
3920         .clkr = {
3921                 .enable_reg = 0x68328,
3922                 .enable_mask = BIT(0),
3923                 .hw.init = &(struct clk_init_data){
3924                         .name = "gcc_port3_mac_clk",
3925                         .parent_names = (const char *[]){
3926                                 "nss_ppe_clk_src"
3927                         },
3928                         .num_parents = 1,
3929                         .flags = CLK_SET_RATE_PARENT,
3930                         .ops = &clk_branch2_ops,
3931                 },
3932         },
3933 };
3934
3935 static struct clk_branch gcc_port4_mac_clk = {
3936         .halt_reg = 0x6832c,
3937         .clkr = {
3938                 .enable_reg = 0x6832c,
3939                 .enable_mask = BIT(0),
3940                 .hw.init = &(struct clk_init_data){
3941                         .name = "gcc_port4_mac_clk",
3942                         .parent_names = (const char *[]){
3943                                 "nss_ppe_clk_src"
3944                         },
3945                         .num_parents = 1,
3946                         .flags = CLK_SET_RATE_PARENT,
3947                         .ops = &clk_branch2_ops,
3948                 },
3949         },
3950 };
3951
3952 static struct clk_branch gcc_port5_mac_clk = {
3953         .halt_reg = 0x68330,
3954         .clkr = {
3955                 .enable_reg = 0x68330,
3956                 .enable_mask = BIT(0),
3957                 .hw.init = &(struct clk_init_data){
3958                         .name = "gcc_port5_mac_clk",
3959                         .parent_names = (const char *[]){
3960                                 "nss_ppe_clk_src"
3961                         },
3962                         .num_parents = 1,
3963                         .flags = CLK_SET_RATE_PARENT,
3964                         .ops = &clk_branch2_ops,
3965                 },
3966         },
3967 };
3968
3969 static struct clk_branch gcc_port6_mac_clk = {
3970         .halt_reg = 0x68334,
3971         .clkr = {
3972                 .enable_reg = 0x68334,
3973                 .enable_mask = BIT(0),
3974                 .hw.init = &(struct clk_init_data){
3975                         .name = "gcc_port6_mac_clk",
3976                         .parent_names = (const char *[]){
3977                                 "nss_ppe_clk_src"
3978                         },
3979                         .num_parents = 1,
3980                         .flags = CLK_SET_RATE_PARENT,
3981                         .ops = &clk_branch2_ops,
3982                 },
3983         },
3984 };
3985
3986 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3987         .halt_reg = 0x56010,
3988         .clkr = {
3989                 .enable_reg = 0x56010,
3990                 .enable_mask = BIT(0),
3991                 .hw.init = &(struct clk_init_data){
3992                         .name = "gcc_uniphy0_port1_rx_clk",
3993                         .parent_names = (const char *[]){
3994                                 "nss_port1_rx_div_clk_src"
3995                         },
3996                         .num_parents = 1,
3997                         .flags = CLK_SET_RATE_PARENT,
3998                         .ops = &clk_branch2_ops,
3999                 },
4000         },
4001 };
4002
4003 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
4004         .halt_reg = 0x56014,
4005         .clkr = {
4006                 .enable_reg = 0x56014,
4007                 .enable_mask = BIT(0),
4008                 .hw.init = &(struct clk_init_data){
4009                         .name = "gcc_uniphy0_port1_tx_clk",
4010                         .parent_names = (const char *[]){
4011                                 "nss_port1_tx_div_clk_src"
4012                         },
4013                         .num_parents = 1,
4014                         .flags = CLK_SET_RATE_PARENT,
4015                         .ops = &clk_branch2_ops,
4016                 },
4017         },
4018 };
4019
4020 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
4021         .halt_reg = 0x56018,
4022         .clkr = {
4023                 .enable_reg = 0x56018,
4024                 .enable_mask = BIT(0),
4025                 .hw.init = &(struct clk_init_data){
4026                         .name = "gcc_uniphy0_port2_rx_clk",
4027                         .parent_names = (const char *[]){
4028                                 "nss_port2_rx_div_clk_src"
4029                         },
4030                         .num_parents = 1,
4031                         .flags = CLK_SET_RATE_PARENT,
4032                         .ops = &clk_branch2_ops,
4033                 },
4034         },
4035 };
4036
4037 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
4038         .halt_reg = 0x5601c,
4039         .clkr = {
4040                 .enable_reg = 0x5601c,
4041                 .enable_mask = BIT(0),
4042                 .hw.init = &(struct clk_init_data){
4043                         .name = "gcc_uniphy0_port2_tx_clk",
4044                         .parent_names = (const char *[]){
4045                                 "nss_port2_tx_div_clk_src"
4046                         },
4047                         .num_parents = 1,
4048                         .flags = CLK_SET_RATE_PARENT,
4049                         .ops = &clk_branch2_ops,
4050                 },
4051         },
4052 };
4053
4054 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
4055         .halt_reg = 0x56020,
4056         .clkr = {
4057                 .enable_reg = 0x56020,
4058                 .enable_mask = BIT(0),
4059                 .hw.init = &(struct clk_init_data){
4060                         .name = "gcc_uniphy0_port3_rx_clk",
4061                         .parent_names = (const char *[]){
4062                                 "nss_port3_rx_div_clk_src"
4063                         },
4064                         .num_parents = 1,
4065                         .flags = CLK_SET_RATE_PARENT,
4066                         .ops = &clk_branch2_ops,
4067                 },
4068         },
4069 };
4070
4071 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
4072         .halt_reg = 0x56024,
4073         .clkr = {
4074                 .enable_reg = 0x56024,
4075                 .enable_mask = BIT(0),
4076                 .hw.init = &(struct clk_init_data){
4077                         .name = "gcc_uniphy0_port3_tx_clk",
4078                         .parent_names = (const char *[]){
4079                                 "nss_port3_tx_div_clk_src"
4080                         },
4081                         .num_parents = 1,
4082                         .flags = CLK_SET_RATE_PARENT,
4083                         .ops = &clk_branch2_ops,
4084                 },
4085         },
4086 };
4087
4088 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
4089         .halt_reg = 0x56028,
4090         .clkr = {
4091                 .enable_reg = 0x56028,
4092                 .enable_mask = BIT(0),
4093                 .hw.init = &(struct clk_init_data){
4094                         .name = "gcc_uniphy0_port4_rx_clk",
4095                         .parent_names = (const char *[]){
4096                                 "nss_port4_rx_div_clk_src"
4097                         },
4098                         .num_parents = 1,
4099                         .flags = CLK_SET_RATE_PARENT,
4100                         .ops = &clk_branch2_ops,
4101                 },
4102         },
4103 };
4104
4105 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
4106         .halt_reg = 0x5602c,
4107         .clkr = {
4108                 .enable_reg = 0x5602c,
4109                 .enable_mask = BIT(0),
4110                 .hw.init = &(struct clk_init_data){
4111                         .name = "gcc_uniphy0_port4_tx_clk",
4112                         .parent_names = (const char *[]){
4113                                 "nss_port4_tx_div_clk_src"
4114                         },
4115                         .num_parents = 1,
4116                         .flags = CLK_SET_RATE_PARENT,
4117                         .ops = &clk_branch2_ops,
4118                 },
4119         },
4120 };
4121
4122 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4123         .halt_reg = 0x56030,
4124         .clkr = {
4125                 .enable_reg = 0x56030,
4126                 .enable_mask = BIT(0),
4127                 .hw.init = &(struct clk_init_data){
4128                         .name = "gcc_uniphy0_port5_rx_clk",
4129                         .parent_names = (const char *[]){
4130                                 "nss_port5_rx_div_clk_src"
4131                         },
4132                         .num_parents = 1,
4133                         .flags = CLK_SET_RATE_PARENT,
4134                         .ops = &clk_branch2_ops,
4135                 },
4136         },
4137 };
4138
4139 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4140         .halt_reg = 0x56034,
4141         .clkr = {
4142                 .enable_reg = 0x56034,
4143                 .enable_mask = BIT(0),
4144                 .hw.init = &(struct clk_init_data){
4145                         .name = "gcc_uniphy0_port5_tx_clk",
4146                         .parent_names = (const char *[]){
4147                                 "nss_port5_tx_div_clk_src"
4148                         },
4149                         .num_parents = 1,
4150                         .flags = CLK_SET_RATE_PARENT,
4151                         .ops = &clk_branch2_ops,
4152                 },
4153         },
4154 };
4155
4156 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4157         .halt_reg = 0x56110,
4158         .clkr = {
4159                 .enable_reg = 0x56110,
4160                 .enable_mask = BIT(0),
4161                 .hw.init = &(struct clk_init_data){
4162                         .name = "gcc_uniphy1_port5_rx_clk",
4163                         .parent_names = (const char *[]){
4164                                 "nss_port5_rx_div_clk_src"
4165                         },
4166                         .num_parents = 1,
4167                         .flags = CLK_SET_RATE_PARENT,
4168                         .ops = &clk_branch2_ops,
4169                 },
4170         },
4171 };
4172
4173 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4174         .halt_reg = 0x56114,
4175         .clkr = {
4176                 .enable_reg = 0x56114,
4177                 .enable_mask = BIT(0),
4178                 .hw.init = &(struct clk_init_data){
4179                         .name = "gcc_uniphy1_port5_tx_clk",
4180                         .parent_names = (const char *[]){
4181                                 "nss_port5_tx_div_clk_src"
4182                         },
4183                         .num_parents = 1,
4184                         .flags = CLK_SET_RATE_PARENT,
4185                         .ops = &clk_branch2_ops,
4186                 },
4187         },
4188 };
4189
4190 static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4191         .halt_reg = 0x56210,
4192         .clkr = {
4193                 .enable_reg = 0x56210,
4194                 .enable_mask = BIT(0),
4195                 .hw.init = &(struct clk_init_data){
4196                         .name = "gcc_uniphy2_port6_rx_clk",
4197                         .parent_names = (const char *[]){
4198                                 "nss_port6_rx_div_clk_src"
4199                         },
4200                         .num_parents = 1,
4201                         .flags = CLK_SET_RATE_PARENT,
4202                         .ops = &clk_branch2_ops,
4203                 },
4204         },
4205 };
4206
4207 static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4208         .halt_reg = 0x56214,
4209         .clkr = {
4210                 .enable_reg = 0x56214,
4211                 .enable_mask = BIT(0),
4212                 .hw.init = &(struct clk_init_data){
4213                         .name = "gcc_uniphy2_port6_tx_clk",
4214                         .parent_names = (const char *[]){
4215                                 "nss_port6_tx_div_clk_src"
4216                         },
4217                         .num_parents = 1,
4218                         .flags = CLK_SET_RATE_PARENT,
4219                         .ops = &clk_branch2_ops,
4220                 },
4221         },
4222 };
4223
4224 static struct clk_branch gcc_crypto_ahb_clk = {
4225         .halt_reg = 0x16024,
4226         .halt_check = BRANCH_HALT_VOTED,
4227         .clkr = {
4228                 .enable_reg = 0x0b004,
4229                 .enable_mask = BIT(0),
4230                 .hw.init = &(struct clk_init_data){
4231                         .name = "gcc_crypto_ahb_clk",
4232                         .parent_names = (const char *[]){
4233                                 "pcnoc_clk_src"
4234                         },
4235                         .num_parents = 1,
4236                         .flags = CLK_SET_RATE_PARENT,
4237                         .ops = &clk_branch2_ops,
4238                 },
4239         },
4240 };
4241
4242 static struct clk_branch gcc_crypto_axi_clk = {
4243         .halt_reg = 0x16020,
4244         .halt_check = BRANCH_HALT_VOTED,
4245         .clkr = {
4246                 .enable_reg = 0x0b004,
4247                 .enable_mask = BIT(1),
4248                 .hw.init = &(struct clk_init_data){
4249                         .name = "gcc_crypto_axi_clk",
4250                         .parent_names = (const char *[]){
4251                                 "pcnoc_clk_src"
4252                         },
4253                         .num_parents = 1,
4254                         .flags = CLK_SET_RATE_PARENT,
4255                         .ops = &clk_branch2_ops,
4256                 },
4257         },
4258 };
4259
4260 static struct clk_branch gcc_crypto_clk = {
4261         .halt_reg = 0x1601c,
4262         .halt_check = BRANCH_HALT_VOTED,
4263         .clkr = {
4264                 .enable_reg = 0x0b004,
4265                 .enable_mask = BIT(2),
4266                 .hw.init = &(struct clk_init_data){
4267                         .name = "gcc_crypto_clk",
4268                         .parent_names = (const char *[]){
4269                                 "crypto_clk_src"
4270                         },
4271                         .num_parents = 1,
4272                         .flags = CLK_SET_RATE_PARENT,
4273                         .ops = &clk_branch2_ops,
4274                 },
4275         },
4276 };
4277
4278 static struct clk_branch gcc_gp1_clk = {
4279         .halt_reg = 0x08000,
4280         .clkr = {
4281                 .enable_reg = 0x08000,
4282                 .enable_mask = BIT(0),
4283                 .hw.init = &(struct clk_init_data){
4284                         .name = "gcc_gp1_clk",
4285                         .parent_names = (const char *[]){
4286                                 "gp1_clk_src"
4287                         },
4288                         .num_parents = 1,
4289                         .flags = CLK_SET_RATE_PARENT,
4290                         .ops = &clk_branch2_ops,
4291                 },
4292         },
4293 };
4294
4295 static struct clk_branch gcc_gp2_clk = {
4296         .halt_reg = 0x09000,
4297         .clkr = {
4298                 .enable_reg = 0x09000,
4299                 .enable_mask = BIT(0),
4300                 .hw.init = &(struct clk_init_data){
4301                         .name = "gcc_gp2_clk",
4302                         .parent_names = (const char *[]){
4303                                 "gp2_clk_src"
4304                         },
4305                         .num_parents = 1,
4306                         .flags = CLK_SET_RATE_PARENT,
4307                         .ops = &clk_branch2_ops,
4308                 },
4309         },
4310 };
4311
4312 static struct clk_branch gcc_gp3_clk = {
4313         .halt_reg = 0x0a000,
4314         .clkr = {
4315                 .enable_reg = 0x0a000,
4316                 .enable_mask = BIT(0),
4317                 .hw.init = &(struct clk_init_data){
4318                         .name = "gcc_gp3_clk",
4319                         .parent_names = (const char *[]){
4320                                 "gp3_clk_src"
4321                         },
4322                         .num_parents = 1,
4323                         .flags = CLK_SET_RATE_PARENT,
4324                         .ops = &clk_branch2_ops,
4325                 },
4326         },
4327 };
4328
4329 static struct clk_hw *gcc_ipq8074_hws[] = {
4330         &gpll0_out_main_div2.hw,
4331         &gpll6_out_main_div2.hw,
4332         &pcnoc_clk_src.hw,
4333         &system_noc_clk_src.hw,
4334         &gcc_xo_div4_clk_src.hw,
4335         &nss_noc_clk_src.hw,
4336         &nss_ppe_cdiv_clk_src.hw,
4337 };
4338
4339 static struct clk_regmap *gcc_ipq8074_clks[] = {
4340         [GPLL0_MAIN] = &gpll0_main.clkr,
4341         [GPLL0] = &gpll0.clkr,
4342         [GPLL2_MAIN] = &gpll2_main.clkr,
4343         [GPLL2] = &gpll2.clkr,
4344         [GPLL4_MAIN] = &gpll4_main.clkr,
4345         [GPLL4] = &gpll4.clkr,
4346         [GPLL6_MAIN] = &gpll6_main.clkr,
4347         [GPLL6] = &gpll6.clkr,
4348         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4349         [UBI32_PLL] = &ubi32_pll.clkr,
4350         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4351         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4352         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4353         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4354         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4355         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4356         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4357         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4358         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4359         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4360         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4361         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4362         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4363         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4364         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4365         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4366         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4367         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4368         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4369         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4370         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4371         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4372         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4373         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4374         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4375         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4376         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4377         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4378         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4379         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4380         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4381         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4382         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4383         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4384         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4385         [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4386         [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4387         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4388         [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4389         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4390         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4391         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4392         [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4393         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4394         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4395         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4396         [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4397         [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4398         [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4399         [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4400         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4401         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4402         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4403         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4404         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4405         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4406         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4407         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4408         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4409         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4410         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4411         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4412         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4413         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4414         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4415         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4416         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4417         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4418         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4419         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4420         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4421         [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4422         [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4423         [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4424         [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4425         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4426         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4427         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4428         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4429         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4430         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4431         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4432         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4433         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4434         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4435         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4436         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4437         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4438         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4439         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4440         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4441         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4442         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4443         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4444         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4445         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4446         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4447         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4448         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4449         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4450         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4451         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4452         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4453         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4454         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4455         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4456         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4457         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4458         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4459         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4460         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4461         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4462         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4463         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4464         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4465         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4466         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4467         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4468         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4469         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4470         [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4471         [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4472         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4473         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4474         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4475         [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4476         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4477         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4478         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4479         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4480         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4481         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4482         [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4483         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4484         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4485         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4486         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4487         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4488         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4489         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4490         [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4491         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4492         [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4493         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4494         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4495         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4496         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4497         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4498         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4499         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4500         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4501         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4502         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4503         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4504         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4505         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4506         [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4507         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4508         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4509         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4510         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4511         [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4512         [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4513         [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4514         [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4515         [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4516         [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4517         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4518         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4519         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4520         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4521         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4522         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4523         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4524         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4525         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4526         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4527         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4528         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4529         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4530         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4531         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4532         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4533         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4534         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4535         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4536         [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4537         [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4538         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4539         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4540         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4541         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4542         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4543         [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4544         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4545         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4546         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4547         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4548         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4549         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4550         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4551         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4552         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4553         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4554         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4555         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4556         [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4557         [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4558         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4559         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4560         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4561         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4562         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4563         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4564 };
4565
4566 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4567         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4568         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4569         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4570         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4571         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4572         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4573         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4574         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4575         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4576         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4577         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4578         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4579         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4580         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4581         [GCC_SMMU_BCR] = { 0x12000, 0 },
4582         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4583         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4584         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4585         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4586         [GCC_PRNG_BCR] = { 0x13000, 0 },
4587         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4588         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4589         [GCC_WCSS_BCR] = { 0x18000, 0 },
4590         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4591         [GCC_NSS_BCR] = { 0x19000, 0 },
4592         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4593         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4594         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4595         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4596         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4597         [GCC_TCSR_BCR] = { 0x28000, 0 },
4598         [GCC_QDSS_BCR] = { 0x29000, 0 },
4599         [GCC_DCD_BCR] = { 0x2a000, 0 },
4600         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4601         [GCC_MPM_BCR] = { 0x2c000, 0 },
4602         [GCC_SPMI_BCR] = { 0x2e000, 0 },
4603         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4604         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4605         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4606         [GCC_TLMM_BCR] = { 0x34000, 0 },
4607         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4608         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4609         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4610         [GCC_USB0_BCR] = { 0x3e070, 0 },
4611         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4612         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4613         [GCC_USB1_BCR] = { 0x3f070, 0 },
4614         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4615         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4616         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4617         [GCC_SDCC2_BCR] = { 0x43000, 0 },
4618         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4619         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4620         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4621         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4622         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4623         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4624         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4625         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4626         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4627         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4628         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4629         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4630         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4631         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4632         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4633         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4634         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4635         [GCC_QPIC_BCR] = { 0x57018, 0 },
4636         [GCC_MDIO_BCR] = { 0x58000, 0 },
4637         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4638         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4639         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4640         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4641         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4642         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4643         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4644         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4645         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4646         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4647         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4648         [GCC_PCIE1_BCR] = { 0x76004, 0 },
4649         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4650         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4651         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4652         [GCC_DCC_BCR] = { 0x77000, 0 },
4653         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4654         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4655         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4656         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4657         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4658         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4659         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4660         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4661         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4662         [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4663         [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4664         [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4665         [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4666         [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4667         [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4668         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4669         [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4670         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4671         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4672         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4673         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4674         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4675         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4676         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4677         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4678         [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4679         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4680         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4681         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4682         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4683         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4684         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4685         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4686         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4687         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4688         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4689         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4690         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4691         [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4692         [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4693         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4694         [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4695         [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4696         [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4697         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4698 };
4699
4700 static const struct of_device_id gcc_ipq8074_match_table[] = {
4701         { .compatible = "qcom,gcc-ipq8074" },
4702         { }
4703 };
4704 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4705
4706 static const struct regmap_config gcc_ipq8074_regmap_config = {
4707         .reg_bits       = 32,
4708         .reg_stride     = 4,
4709         .val_bits       = 32,
4710         .max_register   = 0x7fffc,
4711         .fast_io        = true,
4712 };
4713
4714 static const struct qcom_cc_desc gcc_ipq8074_desc = {
4715         .config = &gcc_ipq8074_regmap_config,
4716         .clks = gcc_ipq8074_clks,
4717         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4718         .resets = gcc_ipq8074_resets,
4719         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4720 };
4721
4722 static int gcc_ipq8074_probe(struct platform_device *pdev)
4723 {
4724         int ret, i;
4725
4726         for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
4727                 ret = devm_clk_hw_register(&pdev->dev, gcc_ipq8074_hws[i]);
4728                 if (ret)
4729                         return ret;
4730         }
4731
4732         return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
4733 }
4734
4735 static struct platform_driver gcc_ipq8074_driver = {
4736         .probe = gcc_ipq8074_probe,
4737         .driver = {
4738                 .name   = "qcom,gcc-ipq8074",
4739                 .of_match_table = gcc_ipq8074_match_table,
4740         },
4741 };
4742
4743 static int __init gcc_ipq8074_init(void)
4744 {
4745         return platform_driver_register(&gcc_ipq8074_driver);
4746 }
4747 core_initcall(gcc_ipq8074_init);
4748
4749 static void __exit gcc_ipq8074_exit(void)
4750 {
4751         platform_driver_unregister(&gcc_ipq8074_driver);
4752 }
4753 module_exit(gcc_ipq8074_exit);
4754
4755 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4756 MODULE_LICENSE("GPL v2");
4757 MODULE_ALIAS("platform:gcc-ipq8074");