1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 * Author: Jian Hu <jian.hu@amlogic.com>
13 #include <linux/clk-provider.h>
14 #include <linux/init.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
18 #include "clk-input.h"
21 #include "clk-regmap.h"
22 #include "vid-pll-div.h"
23 #include "meson-eeclk.h"
26 static DEFINE_SPINLOCK(meson_clk_lock);
28 static struct clk_regmap g12a_fixed_pll_dco = {
29 .data = &(struct meson_clk_pll_data){
31 .reg_off = HHI_FIX_PLL_CNTL0,
36 .reg_off = HHI_FIX_PLL_CNTL0,
41 .reg_off = HHI_FIX_PLL_CNTL0,
46 .reg_off = HHI_FIX_PLL_CNTL1,
51 .reg_off = HHI_FIX_PLL_CNTL0,
56 .reg_off = HHI_FIX_PLL_CNTL0,
61 .hw.init = &(struct clk_init_data){
62 .name = "fixed_pll_dco",
63 .ops = &meson_clk_pll_ro_ops,
64 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
69 static struct clk_regmap g12a_fixed_pll = {
70 .data = &(struct clk_regmap_div_data){
71 .offset = HHI_FIX_PLL_CNTL0,
74 .flags = CLK_DIVIDER_POWER_OF_TWO,
76 .hw.init = &(struct clk_init_data){
78 .ops = &clk_regmap_divider_ro_ops,
79 .parent_names = (const char *[]){ "fixed_pll_dco" },
82 * This clock won't ever change at runtime so
83 * CLK_SET_RATE_PARENT is not required
89 * Internal sys pll emulation configuration parameters
91 static const struct reg_sequence g12a_sys_init_regs[] = {
92 { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 },
93 { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 },
94 { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
95 { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
96 { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
97 { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 },
100 static struct clk_regmap g12a_sys_pll_dco = {
101 .data = &(struct meson_clk_pll_data){
103 .reg_off = HHI_SYS_PLL_CNTL0,
108 .reg_off = HHI_SYS_PLL_CNTL0,
113 .reg_off = HHI_SYS_PLL_CNTL0,
118 .reg_off = HHI_SYS_PLL_CNTL0,
123 .reg_off = HHI_SYS_PLL_CNTL0,
127 .init_regs = g12a_sys_init_regs,
128 .init_count = ARRAY_SIZE(g12a_sys_init_regs),
130 .hw.init = &(struct clk_init_data){
131 .name = "sys_pll_dco",
132 .ops = &meson_clk_pll_ro_ops,
133 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
138 static struct clk_regmap g12a_sys_pll = {
139 .data = &(struct clk_regmap_div_data){
140 .offset = HHI_SYS_PLL_CNTL0,
143 .flags = CLK_DIVIDER_POWER_OF_TWO,
145 .hw.init = &(struct clk_init_data){
147 .ops = &clk_regmap_divider_ro_ops,
148 .parent_names = (const char *[]){ "sys_pll_dco" },
153 static struct clk_regmap g12a_sys_pll_div16_en = {
154 .data = &(struct clk_regmap_gate_data){
155 .offset = HHI_SYS_CPU_CLK_CNTL1,
158 .hw.init = &(struct clk_init_data) {
159 .name = "sys_pll_div16_en",
160 .ops = &clk_regmap_gate_ro_ops,
161 .parent_names = (const char *[]){ "sys_pll" },
164 * This clock is used to debug the sys_pll range
165 * Linux should not change it at runtime
170 static struct clk_fixed_factor g12a_sys_pll_div16 = {
173 .hw.init = &(struct clk_init_data){
174 .name = "sys_pll_div16",
175 .ops = &clk_fixed_factor_ops,
176 .parent_names = (const char *[]){ "sys_pll_div16_en" },
181 /* Datasheet names this field as "premux0" */
182 static struct clk_regmap g12a_cpu_clk_premux0 = {
183 .data = &(struct clk_regmap_mux_data){
184 .offset = HHI_SYS_CPU_CLK_CNTL0,
188 .hw.init = &(struct clk_init_data){
189 .name = "cpu_clk_dyn0_sel",
190 .ops = &clk_regmap_mux_ro_ops,
191 .parent_names = (const char *[]){ IN_PREFIX "xtal",
198 /* Datasheet names this field as "mux0_divn_tcnt" */
199 static struct clk_regmap g12a_cpu_clk_mux0_div = {
200 .data = &(struct clk_regmap_div_data){
201 .offset = HHI_SYS_CPU_CLK_CNTL0,
205 .hw.init = &(struct clk_init_data){
206 .name = "cpu_clk_dyn0_div",
207 .ops = &clk_regmap_divider_ro_ops,
208 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
213 /* Datasheet names this field as "postmux0" */
214 static struct clk_regmap g12a_cpu_clk_postmux0 = {
215 .data = &(struct clk_regmap_mux_data){
216 .offset = HHI_SYS_CPU_CLK_CNTL0,
220 .hw.init = &(struct clk_init_data){
221 .name = "cpu_clk_dyn0",
222 .ops = &clk_regmap_mux_ro_ops,
223 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
224 "cpu_clk_dyn0_div" },
229 /* Datasheet names this field as "premux1" */
230 static struct clk_regmap g12a_cpu_clk_premux1 = {
231 .data = &(struct clk_regmap_mux_data){
232 .offset = HHI_SYS_CPU_CLK_CNTL0,
236 .hw.init = &(struct clk_init_data){
237 .name = "cpu_clk_dyn1_sel",
238 .ops = &clk_regmap_mux_ro_ops,
239 .parent_names = (const char *[]){ IN_PREFIX "xtal",
246 /* Datasheet names this field as "Mux1_divn_tcnt" */
247 static struct clk_regmap g12a_cpu_clk_mux1_div = {
248 .data = &(struct clk_regmap_div_data){
249 .offset = HHI_SYS_CPU_CLK_CNTL0,
253 .hw.init = &(struct clk_init_data){
254 .name = "cpu_clk_dyn1_div",
255 .ops = &clk_regmap_divider_ro_ops,
256 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
261 /* Datasheet names this field as "postmux1" */
262 static struct clk_regmap g12a_cpu_clk_postmux1 = {
263 .data = &(struct clk_regmap_mux_data){
264 .offset = HHI_SYS_CPU_CLK_CNTL0,
268 .hw.init = &(struct clk_init_data){
269 .name = "cpu_clk_dyn1",
270 .ops = &clk_regmap_mux_ro_ops,
271 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
272 "cpu_clk_dyn1_div" },
277 /* Datasheet names this field as "Final_dyn_mux_sel" */
278 static struct clk_regmap g12a_cpu_clk_dyn = {
279 .data = &(struct clk_regmap_mux_data){
280 .offset = HHI_SYS_CPU_CLK_CNTL0,
284 .hw.init = &(struct clk_init_data){
285 .name = "cpu_clk_dyn",
286 .ops = &clk_regmap_mux_ro_ops,
287 .parent_names = (const char *[]){ "cpu_clk_dyn0",
293 /* Datasheet names this field as "Final_mux_sel" */
294 static struct clk_regmap g12a_cpu_clk = {
295 .data = &(struct clk_regmap_mux_data){
296 .offset = HHI_SYS_CPU_CLK_CNTL0,
300 .hw.init = &(struct clk_init_data){
302 .ops = &clk_regmap_mux_ro_ops,
303 .parent_names = (const char *[]){ "cpu_clk_dyn",
309 static struct clk_regmap g12a_cpu_clk_div16_en = {
310 .data = &(struct clk_regmap_gate_data){
311 .offset = HHI_SYS_CPU_CLK_CNTL1,
314 .hw.init = &(struct clk_init_data) {
315 .name = "cpu_clk_div16_en",
316 .ops = &clk_regmap_gate_ro_ops,
317 .parent_names = (const char *[]){ "cpu_clk" },
320 * This clock is used to debug the cpu_clk range
321 * Linux should not change it at runtime
326 static struct clk_fixed_factor g12a_cpu_clk_div16 = {
329 .hw.init = &(struct clk_init_data){
330 .name = "cpu_clk_div16",
331 .ops = &clk_fixed_factor_ops,
332 .parent_names = (const char *[]){ "cpu_clk_div16_en" },
337 static struct clk_regmap g12a_cpu_clk_apb_div = {
338 .data = &(struct clk_regmap_div_data){
339 .offset = HHI_SYS_CPU_CLK_CNTL1,
342 .flags = CLK_DIVIDER_POWER_OF_TWO,
344 .hw.init = &(struct clk_init_data){
345 .name = "cpu_clk_apb_div",
346 .ops = &clk_regmap_divider_ro_ops,
347 .parent_names = (const char *[]){ "cpu_clk" },
352 static struct clk_regmap g12a_cpu_clk_apb = {
353 .data = &(struct clk_regmap_gate_data){
354 .offset = HHI_SYS_CPU_CLK_CNTL1,
357 .hw.init = &(struct clk_init_data) {
358 .name = "cpu_clk_apb",
359 .ops = &clk_regmap_gate_ro_ops,
360 .parent_names = (const char *[]){ "cpu_clk_apb_div" },
363 * This clock is set by the ROM monitor code,
364 * Linux should not change it at runtime
369 static struct clk_regmap g12a_cpu_clk_atb_div = {
370 .data = &(struct clk_regmap_div_data){
371 .offset = HHI_SYS_CPU_CLK_CNTL1,
374 .flags = CLK_DIVIDER_POWER_OF_TWO,
376 .hw.init = &(struct clk_init_data){
377 .name = "cpu_clk_atb_div",
378 .ops = &clk_regmap_divider_ro_ops,
379 .parent_names = (const char *[]){ "cpu_clk" },
384 static struct clk_regmap g12a_cpu_clk_atb = {
385 .data = &(struct clk_regmap_gate_data){
386 .offset = HHI_SYS_CPU_CLK_CNTL1,
389 .hw.init = &(struct clk_init_data) {
390 .name = "cpu_clk_atb",
391 .ops = &clk_regmap_gate_ro_ops,
392 .parent_names = (const char *[]){ "cpu_clk_atb_div" },
395 * This clock is set by the ROM monitor code,
396 * Linux should not change it at runtime
401 static struct clk_regmap g12a_cpu_clk_axi_div = {
402 .data = &(struct clk_regmap_div_data){
403 .offset = HHI_SYS_CPU_CLK_CNTL1,
406 .flags = CLK_DIVIDER_POWER_OF_TWO,
408 .hw.init = &(struct clk_init_data){
409 .name = "cpu_clk_axi_div",
410 .ops = &clk_regmap_divider_ro_ops,
411 .parent_names = (const char *[]){ "cpu_clk" },
416 static struct clk_regmap g12a_cpu_clk_axi = {
417 .data = &(struct clk_regmap_gate_data){
418 .offset = HHI_SYS_CPU_CLK_CNTL1,
421 .hw.init = &(struct clk_init_data) {
422 .name = "cpu_clk_axi",
423 .ops = &clk_regmap_gate_ro_ops,
424 .parent_names = (const char *[]){ "cpu_clk_axi_div" },
427 * This clock is set by the ROM monitor code,
428 * Linux should not change it at runtime
433 static struct clk_regmap g12a_cpu_clk_trace_div = {
434 .data = &(struct clk_regmap_div_data){
435 .offset = HHI_SYS_CPU_CLK_CNTL1,
438 .flags = CLK_DIVIDER_POWER_OF_TWO,
440 .hw.init = &(struct clk_init_data){
441 .name = "cpu_clk_trace_div",
442 .ops = &clk_regmap_divider_ro_ops,
443 .parent_names = (const char *[]){ "cpu_clk" },
448 static struct clk_regmap g12a_cpu_clk_trace = {
449 .data = &(struct clk_regmap_gate_data){
450 .offset = HHI_SYS_CPU_CLK_CNTL1,
453 .hw.init = &(struct clk_init_data) {
454 .name = "cpu_clk_trace",
455 .ops = &clk_regmap_gate_ro_ops,
456 .parent_names = (const char *[]){ "cpu_clk_trace_div" },
459 * This clock is set by the ROM monitor code,
460 * Linux should not change it at runtime
465 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
471 * Internal gp0 pll emulation configuration parameters
473 static const struct reg_sequence g12a_gp0_init_regs[] = {
474 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
475 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
476 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
477 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
478 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
479 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
482 static struct clk_regmap g12a_gp0_pll_dco = {
483 .data = &(struct meson_clk_pll_data){
485 .reg_off = HHI_GP0_PLL_CNTL0,
490 .reg_off = HHI_GP0_PLL_CNTL0,
495 .reg_off = HHI_GP0_PLL_CNTL0,
500 .reg_off = HHI_GP0_PLL_CNTL1,
505 .reg_off = HHI_GP0_PLL_CNTL0,
510 .reg_off = HHI_GP0_PLL_CNTL0,
514 .range = &g12a_gp0_pll_mult_range,
515 .init_regs = g12a_gp0_init_regs,
516 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
518 .hw.init = &(struct clk_init_data){
519 .name = "gp0_pll_dco",
520 .ops = &meson_clk_pll_ops,
521 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
526 static struct clk_regmap g12a_gp0_pll = {
527 .data = &(struct clk_regmap_div_data){
528 .offset = HHI_GP0_PLL_CNTL0,
531 .flags = (CLK_DIVIDER_POWER_OF_TWO |
532 CLK_DIVIDER_ROUND_CLOSEST),
534 .hw.init = &(struct clk_init_data){
536 .ops = &clk_regmap_divider_ops,
537 .parent_names = (const char *[]){ "gp0_pll_dco" },
539 .flags = CLK_SET_RATE_PARENT,
544 * Internal hifi pll emulation configuration parameters
546 static const struct reg_sequence g12a_hifi_init_regs[] = {
547 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
548 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
549 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
550 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
551 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
552 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
555 static struct clk_regmap g12a_hifi_pll_dco = {
556 .data = &(struct meson_clk_pll_data){
558 .reg_off = HHI_HIFI_PLL_CNTL0,
563 .reg_off = HHI_HIFI_PLL_CNTL0,
568 .reg_off = HHI_HIFI_PLL_CNTL0,
573 .reg_off = HHI_HIFI_PLL_CNTL1,
578 .reg_off = HHI_HIFI_PLL_CNTL0,
583 .reg_off = HHI_HIFI_PLL_CNTL0,
587 .range = &g12a_gp0_pll_mult_range,
588 .init_regs = g12a_hifi_init_regs,
589 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
590 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
592 .hw.init = &(struct clk_init_data){
593 .name = "hifi_pll_dco",
594 .ops = &meson_clk_pll_ops,
595 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
600 static struct clk_regmap g12a_hifi_pll = {
601 .data = &(struct clk_regmap_div_data){
602 .offset = HHI_HIFI_PLL_CNTL0,
605 .flags = (CLK_DIVIDER_POWER_OF_TWO |
606 CLK_DIVIDER_ROUND_CLOSEST),
608 .hw.init = &(struct clk_init_data){
610 .ops = &clk_regmap_divider_ops,
611 .parent_names = (const char *[]){ "hifi_pll_dco" },
613 .flags = CLK_SET_RATE_PARENT,
618 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
619 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
620 * a strict register sequence to enable the PLL.
622 static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
623 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
624 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
625 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
626 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
627 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
628 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
629 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
630 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
631 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
632 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
633 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
634 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
637 /* Keep a single entry table for recalc/round_rate() ops */
638 static const struct pll_params_table g12a_pcie_pll_table[] = {
643 static struct clk_regmap g12a_pcie_pll_dco = {
644 .data = &(struct meson_clk_pll_data){
646 .reg_off = HHI_PCIE_PLL_CNTL0,
651 .reg_off = HHI_PCIE_PLL_CNTL0,
656 .reg_off = HHI_PCIE_PLL_CNTL0,
661 .reg_off = HHI_PCIE_PLL_CNTL1,
666 .reg_off = HHI_PCIE_PLL_CNTL0,
671 .reg_off = HHI_PCIE_PLL_CNTL0,
675 .table = g12a_pcie_pll_table,
676 .init_regs = g12a_pcie_pll_init_regs,
677 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
679 .hw.init = &(struct clk_init_data){
680 .name = "pcie_pll_dco",
681 .ops = &meson_clk_pcie_pll_ops,
682 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
687 static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
690 .hw.init = &(struct clk_init_data){
691 .name = "pcie_pll_dco_div2",
692 .ops = &clk_fixed_factor_ops,
693 .parent_names = (const char *[]){ "pcie_pll_dco" },
695 .flags = CLK_SET_RATE_PARENT,
699 static struct clk_regmap g12a_pcie_pll_od = {
700 .data = &(struct clk_regmap_div_data){
701 .offset = HHI_PCIE_PLL_CNTL0,
704 .flags = CLK_DIVIDER_ROUND_CLOSEST |
705 CLK_DIVIDER_ONE_BASED |
706 CLK_DIVIDER_ALLOW_ZERO,
708 .hw.init = &(struct clk_init_data){
709 .name = "pcie_pll_od",
710 .ops = &clk_regmap_divider_ops,
711 .parent_names = (const char *[]){ "pcie_pll_dco_div2" },
713 .flags = CLK_SET_RATE_PARENT,
717 static struct clk_fixed_factor g12a_pcie_pll = {
720 .hw.init = &(struct clk_init_data){
721 .name = "pcie_pll_pll",
722 .ops = &clk_fixed_factor_ops,
723 .parent_names = (const char *[]){ "pcie_pll_od" },
725 .flags = CLK_SET_RATE_PARENT,
729 static struct clk_regmap g12a_hdmi_pll_dco = {
730 .data = &(struct meson_clk_pll_data){
732 .reg_off = HHI_HDMI_PLL_CNTL0,
737 .reg_off = HHI_HDMI_PLL_CNTL0,
742 .reg_off = HHI_HDMI_PLL_CNTL0,
747 .reg_off = HHI_HDMI_PLL_CNTL1,
752 .reg_off = HHI_HDMI_PLL_CNTL0,
757 .reg_off = HHI_HDMI_PLL_CNTL0,
762 .hw.init = &(struct clk_init_data){
763 .name = "hdmi_pll_dco",
764 .ops = &meson_clk_pll_ro_ops,
765 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
768 * Display directly handle hdmi pll registers ATM, we need
769 * NOCACHE to keep our view of the clock as accurate as possible
771 .flags = CLK_GET_RATE_NOCACHE,
775 static struct clk_regmap g12a_hdmi_pll_od = {
776 .data = &(struct clk_regmap_div_data){
777 .offset = HHI_HDMI_PLL_CNTL0,
780 .flags = CLK_DIVIDER_POWER_OF_TWO,
782 .hw.init = &(struct clk_init_data){
783 .name = "hdmi_pll_od",
784 .ops = &clk_regmap_divider_ro_ops,
785 .parent_names = (const char *[]){ "hdmi_pll_dco" },
787 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
791 static struct clk_regmap g12a_hdmi_pll_od2 = {
792 .data = &(struct clk_regmap_div_data){
793 .offset = HHI_HDMI_PLL_CNTL0,
796 .flags = CLK_DIVIDER_POWER_OF_TWO,
798 .hw.init = &(struct clk_init_data){
799 .name = "hdmi_pll_od2",
800 .ops = &clk_regmap_divider_ro_ops,
801 .parent_names = (const char *[]){ "hdmi_pll_od" },
803 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
807 static struct clk_regmap g12a_hdmi_pll = {
808 .data = &(struct clk_regmap_div_data){
809 .offset = HHI_HDMI_PLL_CNTL0,
812 .flags = CLK_DIVIDER_POWER_OF_TWO,
814 .hw.init = &(struct clk_init_data){
816 .ops = &clk_regmap_divider_ro_ops,
817 .parent_names = (const char *[]){ "hdmi_pll_od2" },
819 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
823 static struct clk_fixed_factor g12a_fclk_div2_div = {
826 .hw.init = &(struct clk_init_data){
827 .name = "fclk_div2_div",
828 .ops = &clk_fixed_factor_ops,
829 .parent_names = (const char *[]){ "fixed_pll" },
834 static struct clk_regmap g12a_fclk_div2 = {
835 .data = &(struct clk_regmap_gate_data){
836 .offset = HHI_FIX_PLL_CNTL1,
839 .hw.init = &(struct clk_init_data){
841 .ops = &clk_regmap_gate_ops,
842 .parent_names = (const char *[]){ "fclk_div2_div" },
847 static struct clk_fixed_factor g12a_fclk_div3_div = {
850 .hw.init = &(struct clk_init_data){
851 .name = "fclk_div3_div",
852 .ops = &clk_fixed_factor_ops,
853 .parent_names = (const char *[]){ "fixed_pll" },
858 static struct clk_regmap g12a_fclk_div3 = {
859 .data = &(struct clk_regmap_gate_data){
860 .offset = HHI_FIX_PLL_CNTL1,
863 .hw.init = &(struct clk_init_data){
865 .ops = &clk_regmap_gate_ops,
866 .parent_names = (const char *[]){ "fclk_div3_div" },
871 static struct clk_fixed_factor g12a_fclk_div4_div = {
874 .hw.init = &(struct clk_init_data){
875 .name = "fclk_div4_div",
876 .ops = &clk_fixed_factor_ops,
877 .parent_names = (const char *[]){ "fixed_pll" },
882 static struct clk_regmap g12a_fclk_div4 = {
883 .data = &(struct clk_regmap_gate_data){
884 .offset = HHI_FIX_PLL_CNTL1,
887 .hw.init = &(struct clk_init_data){
889 .ops = &clk_regmap_gate_ops,
890 .parent_names = (const char *[]){ "fclk_div4_div" },
895 static struct clk_fixed_factor g12a_fclk_div5_div = {
898 .hw.init = &(struct clk_init_data){
899 .name = "fclk_div5_div",
900 .ops = &clk_fixed_factor_ops,
901 .parent_names = (const char *[]){ "fixed_pll" },
906 static struct clk_regmap g12a_fclk_div5 = {
907 .data = &(struct clk_regmap_gate_data){
908 .offset = HHI_FIX_PLL_CNTL1,
911 .hw.init = &(struct clk_init_data){
913 .ops = &clk_regmap_gate_ops,
914 .parent_names = (const char *[]){ "fclk_div5_div" },
919 static struct clk_fixed_factor g12a_fclk_div7_div = {
922 .hw.init = &(struct clk_init_data){
923 .name = "fclk_div7_div",
924 .ops = &clk_fixed_factor_ops,
925 .parent_names = (const char *[]){ "fixed_pll" },
930 static struct clk_regmap g12a_fclk_div7 = {
931 .data = &(struct clk_regmap_gate_data){
932 .offset = HHI_FIX_PLL_CNTL1,
935 .hw.init = &(struct clk_init_data){
937 .ops = &clk_regmap_gate_ops,
938 .parent_names = (const char *[]){ "fclk_div7_div" },
943 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
946 .hw.init = &(struct clk_init_data){
947 .name = "fclk_div2p5_div",
948 .ops = &clk_fixed_factor_ops,
949 .parent_names = (const char *[]){ "fixed_pll_dco" },
954 static struct clk_regmap g12a_fclk_div2p5 = {
955 .data = &(struct clk_regmap_gate_data){
956 .offset = HHI_FIX_PLL_CNTL1,
959 .hw.init = &(struct clk_init_data){
960 .name = "fclk_div2p5",
961 .ops = &clk_regmap_gate_ops,
962 .parent_names = (const char *[]){ "fclk_div2p5_div" },
967 static struct clk_fixed_factor g12a_mpll_50m_div = {
970 .hw.init = &(struct clk_init_data){
971 .name = "mpll_50m_div",
972 .ops = &clk_fixed_factor_ops,
973 .parent_names = (const char *[]){ "fixed_pll_dco" },
978 static struct clk_regmap g12a_mpll_50m = {
979 .data = &(struct clk_regmap_mux_data){
980 .offset = HHI_FIX_PLL_CNTL3,
984 .hw.init = &(struct clk_init_data){
986 .ops = &clk_regmap_mux_ro_ops,
987 .parent_names = (const char *[]){ IN_PREFIX "xtal",
993 static struct clk_fixed_factor g12a_mpll_prediv = {
996 .hw.init = &(struct clk_init_data){
997 .name = "mpll_prediv",
998 .ops = &clk_fixed_factor_ops,
999 .parent_names = (const char *[]){ "fixed_pll_dco" },
1004 static struct clk_regmap g12a_mpll0_div = {
1005 .data = &(struct meson_clk_mpll_data){
1007 .reg_off = HHI_MPLL_CNTL1,
1012 .reg_off = HHI_MPLL_CNTL1,
1017 .reg_off = HHI_MPLL_CNTL1,
1022 .reg_off = HHI_MPLL_CNTL1,
1026 .lock = &meson_clk_lock,
1028 .hw.init = &(struct clk_init_data){
1029 .name = "mpll0_div",
1030 .ops = &meson_clk_mpll_ops,
1031 .parent_names = (const char *[]){ "mpll_prediv" },
1036 static struct clk_regmap g12a_mpll0 = {
1037 .data = &(struct clk_regmap_gate_data){
1038 .offset = HHI_MPLL_CNTL1,
1041 .hw.init = &(struct clk_init_data){
1043 .ops = &clk_regmap_gate_ops,
1044 .parent_names = (const char *[]){ "mpll0_div" },
1046 .flags = CLK_SET_RATE_PARENT,
1050 static struct clk_regmap g12a_mpll1_div = {
1051 .data = &(struct meson_clk_mpll_data){
1053 .reg_off = HHI_MPLL_CNTL3,
1058 .reg_off = HHI_MPLL_CNTL3,
1063 .reg_off = HHI_MPLL_CNTL3,
1068 .reg_off = HHI_MPLL_CNTL3,
1072 .lock = &meson_clk_lock,
1074 .hw.init = &(struct clk_init_data){
1075 .name = "mpll1_div",
1076 .ops = &meson_clk_mpll_ops,
1077 .parent_names = (const char *[]){ "mpll_prediv" },
1082 static struct clk_regmap g12a_mpll1 = {
1083 .data = &(struct clk_regmap_gate_data){
1084 .offset = HHI_MPLL_CNTL3,
1087 .hw.init = &(struct clk_init_data){
1089 .ops = &clk_regmap_gate_ops,
1090 .parent_names = (const char *[]){ "mpll1_div" },
1092 .flags = CLK_SET_RATE_PARENT,
1096 static struct clk_regmap g12a_mpll2_div = {
1097 .data = &(struct meson_clk_mpll_data){
1099 .reg_off = HHI_MPLL_CNTL5,
1104 .reg_off = HHI_MPLL_CNTL5,
1109 .reg_off = HHI_MPLL_CNTL5,
1114 .reg_off = HHI_MPLL_CNTL5,
1118 .lock = &meson_clk_lock,
1120 .hw.init = &(struct clk_init_data){
1121 .name = "mpll2_div",
1122 .ops = &meson_clk_mpll_ops,
1123 .parent_names = (const char *[]){ "mpll_prediv" },
1128 static struct clk_regmap g12a_mpll2 = {
1129 .data = &(struct clk_regmap_gate_data){
1130 .offset = HHI_MPLL_CNTL5,
1133 .hw.init = &(struct clk_init_data){
1135 .ops = &clk_regmap_gate_ops,
1136 .parent_names = (const char *[]){ "mpll2_div" },
1138 .flags = CLK_SET_RATE_PARENT,
1142 static struct clk_regmap g12a_mpll3_div = {
1143 .data = &(struct meson_clk_mpll_data){
1145 .reg_off = HHI_MPLL_CNTL7,
1150 .reg_off = HHI_MPLL_CNTL7,
1155 .reg_off = HHI_MPLL_CNTL7,
1160 .reg_off = HHI_MPLL_CNTL7,
1164 .lock = &meson_clk_lock,
1166 .hw.init = &(struct clk_init_data){
1167 .name = "mpll3_div",
1168 .ops = &meson_clk_mpll_ops,
1169 .parent_names = (const char *[]){ "mpll_prediv" },
1174 static struct clk_regmap g12a_mpll3 = {
1175 .data = &(struct clk_regmap_gate_data){
1176 .offset = HHI_MPLL_CNTL7,
1179 .hw.init = &(struct clk_init_data){
1181 .ops = &clk_regmap_gate_ops,
1182 .parent_names = (const char *[]){ "mpll3_div" },
1184 .flags = CLK_SET_RATE_PARENT,
1188 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
1189 static const char * const clk81_parent_names[] = {
1190 IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
1191 "fclk_div3", "fclk_div5"
1194 static struct clk_regmap g12a_mpeg_clk_sel = {
1195 .data = &(struct clk_regmap_mux_data){
1196 .offset = HHI_MPEG_CLK_CNTL,
1199 .table = mux_table_clk81,
1201 .hw.init = &(struct clk_init_data){
1202 .name = "mpeg_clk_sel",
1203 .ops = &clk_regmap_mux_ro_ops,
1204 .parent_names = clk81_parent_names,
1205 .num_parents = ARRAY_SIZE(clk81_parent_names),
1209 static struct clk_regmap g12a_mpeg_clk_div = {
1210 .data = &(struct clk_regmap_div_data){
1211 .offset = HHI_MPEG_CLK_CNTL,
1215 .hw.init = &(struct clk_init_data){
1216 .name = "mpeg_clk_div",
1217 .ops = &clk_regmap_divider_ops,
1218 .parent_names = (const char *[]){ "mpeg_clk_sel" },
1220 .flags = CLK_SET_RATE_PARENT,
1224 static struct clk_regmap g12a_clk81 = {
1225 .data = &(struct clk_regmap_gate_data){
1226 .offset = HHI_MPEG_CLK_CNTL,
1229 .hw.init = &(struct clk_init_data){
1231 .ops = &clk_regmap_gate_ops,
1232 .parent_names = (const char *[]){ "mpeg_clk_div" },
1234 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
1238 static const char * const g12a_sd_emmc_clk0_parent_names[] = {
1239 IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1242 * Following these parent clocks, we should also have had mpll2, mpll3
1243 * and gp0_pll but these clocks are too precious to be used here. All
1244 * the necessary rates for MMC and NAND operation can be acheived using
1245 * g12a_ee_core or fclk_div clocks
1250 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
1251 .data = &(struct clk_regmap_mux_data){
1252 .offset = HHI_SD_EMMC_CLK_CNTL,
1256 .hw.init = &(struct clk_init_data) {
1257 .name = "sd_emmc_a_clk0_sel",
1258 .ops = &clk_regmap_mux_ops,
1259 .parent_names = g12a_sd_emmc_clk0_parent_names,
1260 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1261 .flags = CLK_SET_RATE_PARENT,
1265 static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
1266 .data = &(struct clk_regmap_div_data){
1267 .offset = HHI_SD_EMMC_CLK_CNTL,
1271 .hw.init = &(struct clk_init_data) {
1272 .name = "sd_emmc_a_clk0_div",
1273 .ops = &clk_regmap_divider_ops,
1274 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1276 .flags = CLK_SET_RATE_PARENT,
1280 static struct clk_regmap g12a_sd_emmc_a_clk0 = {
1281 .data = &(struct clk_regmap_gate_data){
1282 .offset = HHI_SD_EMMC_CLK_CNTL,
1285 .hw.init = &(struct clk_init_data){
1286 .name = "sd_emmc_a_clk0",
1287 .ops = &clk_regmap_gate_ops,
1288 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1290 .flags = CLK_SET_RATE_PARENT,
1295 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
1296 .data = &(struct clk_regmap_mux_data){
1297 .offset = HHI_SD_EMMC_CLK_CNTL,
1301 .hw.init = &(struct clk_init_data) {
1302 .name = "sd_emmc_b_clk0_sel",
1303 .ops = &clk_regmap_mux_ops,
1304 .parent_names = g12a_sd_emmc_clk0_parent_names,
1305 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1306 .flags = CLK_SET_RATE_PARENT,
1310 static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
1311 .data = &(struct clk_regmap_div_data){
1312 .offset = HHI_SD_EMMC_CLK_CNTL,
1316 .hw.init = &(struct clk_init_data) {
1317 .name = "sd_emmc_b_clk0_div",
1318 .ops = &clk_regmap_divider_ops,
1319 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1321 .flags = CLK_SET_RATE_PARENT,
1325 static struct clk_regmap g12a_sd_emmc_b_clk0 = {
1326 .data = &(struct clk_regmap_gate_data){
1327 .offset = HHI_SD_EMMC_CLK_CNTL,
1330 .hw.init = &(struct clk_init_data){
1331 .name = "sd_emmc_b_clk0",
1332 .ops = &clk_regmap_gate_ops,
1333 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1335 .flags = CLK_SET_RATE_PARENT,
1339 /* EMMC/NAND clock */
1340 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
1341 .data = &(struct clk_regmap_mux_data){
1342 .offset = HHI_NAND_CLK_CNTL,
1346 .hw.init = &(struct clk_init_data) {
1347 .name = "sd_emmc_c_clk0_sel",
1348 .ops = &clk_regmap_mux_ops,
1349 .parent_names = g12a_sd_emmc_clk0_parent_names,
1350 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1351 .flags = CLK_SET_RATE_PARENT,
1355 static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
1356 .data = &(struct clk_regmap_div_data){
1357 .offset = HHI_NAND_CLK_CNTL,
1361 .hw.init = &(struct clk_init_data) {
1362 .name = "sd_emmc_c_clk0_div",
1363 .ops = &clk_regmap_divider_ops,
1364 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1366 .flags = CLK_SET_RATE_PARENT,
1370 static struct clk_regmap g12a_sd_emmc_c_clk0 = {
1371 .data = &(struct clk_regmap_gate_data){
1372 .offset = HHI_NAND_CLK_CNTL,
1375 .hw.init = &(struct clk_init_data){
1376 .name = "sd_emmc_c_clk0",
1377 .ops = &clk_regmap_gate_ops,
1378 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1380 .flags = CLK_SET_RATE_PARENT,
1386 static const char * const g12a_vpu_parent_names[] = {
1387 "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
1388 "mpll1", "vid_pll", "hifi_pll", "gp0_pll",
1391 static struct clk_regmap g12a_vpu_0_sel = {
1392 .data = &(struct clk_regmap_mux_data){
1393 .offset = HHI_VPU_CLK_CNTL,
1397 .hw.init = &(struct clk_init_data){
1398 .name = "vpu_0_sel",
1399 .ops = &clk_regmap_mux_ops,
1400 .parent_names = g12a_vpu_parent_names,
1401 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
1402 .flags = CLK_SET_RATE_NO_REPARENT,
1406 static struct clk_regmap g12a_vpu_0_div = {
1407 .data = &(struct clk_regmap_div_data){
1408 .offset = HHI_VPU_CLK_CNTL,
1412 .hw.init = &(struct clk_init_data){
1413 .name = "vpu_0_div",
1414 .ops = &clk_regmap_divider_ops,
1415 .parent_names = (const char *[]){ "vpu_0_sel" },
1417 .flags = CLK_SET_RATE_PARENT,
1421 static struct clk_regmap g12a_vpu_0 = {
1422 .data = &(struct clk_regmap_gate_data){
1423 .offset = HHI_VPU_CLK_CNTL,
1426 .hw.init = &(struct clk_init_data) {
1428 .ops = &clk_regmap_gate_ops,
1429 .parent_names = (const char *[]){ "vpu_0_div" },
1431 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1435 static struct clk_regmap g12a_vpu_1_sel = {
1436 .data = &(struct clk_regmap_mux_data){
1437 .offset = HHI_VPU_CLK_CNTL,
1441 .hw.init = &(struct clk_init_data){
1442 .name = "vpu_1_sel",
1443 .ops = &clk_regmap_mux_ops,
1444 .parent_names = g12a_vpu_parent_names,
1445 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
1446 .flags = CLK_SET_RATE_NO_REPARENT,
1450 static struct clk_regmap g12a_vpu_1_div = {
1451 .data = &(struct clk_regmap_div_data){
1452 .offset = HHI_VPU_CLK_CNTL,
1456 .hw.init = &(struct clk_init_data){
1457 .name = "vpu_1_div",
1458 .ops = &clk_regmap_divider_ops,
1459 .parent_names = (const char *[]){ "vpu_1_sel" },
1461 .flags = CLK_SET_RATE_PARENT,
1465 static struct clk_regmap g12a_vpu_1 = {
1466 .data = &(struct clk_regmap_gate_data){
1467 .offset = HHI_VPU_CLK_CNTL,
1470 .hw.init = &(struct clk_init_data) {
1472 .ops = &clk_regmap_gate_ops,
1473 .parent_names = (const char *[]){ "vpu_1_div" },
1475 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1479 static struct clk_regmap g12a_vpu = {
1480 .data = &(struct clk_regmap_mux_data){
1481 .offset = HHI_VPU_CLK_CNTL,
1485 .hw.init = &(struct clk_init_data){
1487 .ops = &clk_regmap_mux_ops,
1489 * bit 31 selects from 2 possible parents:
1492 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1494 .flags = CLK_SET_RATE_NO_REPARENT,
1500 static const char * const g12a_vdec_parent_names[] = {
1501 "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
1502 "hifi_pll", "gp0_pll",
1505 static struct clk_regmap g12a_vdec_1_sel = {
1506 .data = &(struct clk_regmap_mux_data){
1507 .offset = HHI_VDEC_CLK_CNTL,
1510 .flags = CLK_MUX_ROUND_CLOSEST,
1512 .hw.init = &(struct clk_init_data){
1513 .name = "vdec_1_sel",
1514 .ops = &clk_regmap_mux_ops,
1515 .parent_names = g12a_vdec_parent_names,
1516 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1517 .flags = CLK_SET_RATE_PARENT,
1521 static struct clk_regmap g12a_vdec_1_div = {
1522 .data = &(struct clk_regmap_div_data){
1523 .offset = HHI_VDEC_CLK_CNTL,
1526 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1528 .hw.init = &(struct clk_init_data){
1529 .name = "vdec_1_div",
1530 .ops = &clk_regmap_divider_ops,
1531 .parent_names = (const char *[]){ "vdec_1_sel" },
1533 .flags = CLK_SET_RATE_PARENT,
1537 static struct clk_regmap g12a_vdec_1 = {
1538 .data = &(struct clk_regmap_gate_data){
1539 .offset = HHI_VDEC_CLK_CNTL,
1542 .hw.init = &(struct clk_init_data) {
1544 .ops = &clk_regmap_gate_ops,
1545 .parent_names = (const char *[]){ "vdec_1_div" },
1547 .flags = CLK_SET_RATE_PARENT,
1551 static struct clk_regmap g12a_vdec_hevcf_sel = {
1552 .data = &(struct clk_regmap_mux_data){
1553 .offset = HHI_VDEC2_CLK_CNTL,
1556 .flags = CLK_MUX_ROUND_CLOSEST,
1558 .hw.init = &(struct clk_init_data){
1559 .name = "vdec_hevcf_sel",
1560 .ops = &clk_regmap_mux_ops,
1561 .parent_names = g12a_vdec_parent_names,
1562 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1563 .flags = CLK_SET_RATE_PARENT,
1567 static struct clk_regmap g12a_vdec_hevcf_div = {
1568 .data = &(struct clk_regmap_div_data){
1569 .offset = HHI_VDEC2_CLK_CNTL,
1572 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1574 .hw.init = &(struct clk_init_data){
1575 .name = "vdec_hevcf_div",
1576 .ops = &clk_regmap_divider_ops,
1577 .parent_names = (const char *[]){ "vdec_hevcf_sel" },
1579 .flags = CLK_SET_RATE_PARENT,
1583 static struct clk_regmap g12a_vdec_hevcf = {
1584 .data = &(struct clk_regmap_gate_data){
1585 .offset = HHI_VDEC2_CLK_CNTL,
1588 .hw.init = &(struct clk_init_data) {
1589 .name = "vdec_hevcf",
1590 .ops = &clk_regmap_gate_ops,
1591 .parent_names = (const char *[]){ "vdec_hevcf_div" },
1593 .flags = CLK_SET_RATE_PARENT,
1597 static struct clk_regmap g12a_vdec_hevc_sel = {
1598 .data = &(struct clk_regmap_mux_data){
1599 .offset = HHI_VDEC2_CLK_CNTL,
1602 .flags = CLK_MUX_ROUND_CLOSEST,
1604 .hw.init = &(struct clk_init_data){
1605 .name = "vdec_hevc_sel",
1606 .ops = &clk_regmap_mux_ops,
1607 .parent_names = g12a_vdec_parent_names,
1608 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1609 .flags = CLK_SET_RATE_PARENT,
1613 static struct clk_regmap g12a_vdec_hevc_div = {
1614 .data = &(struct clk_regmap_div_data){
1615 .offset = HHI_VDEC2_CLK_CNTL,
1618 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1620 .hw.init = &(struct clk_init_data){
1621 .name = "vdec_hevc_div",
1622 .ops = &clk_regmap_divider_ops,
1623 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1625 .flags = CLK_SET_RATE_PARENT,
1629 static struct clk_regmap g12a_vdec_hevc = {
1630 .data = &(struct clk_regmap_gate_data){
1631 .offset = HHI_VDEC2_CLK_CNTL,
1634 .hw.init = &(struct clk_init_data) {
1635 .name = "vdec_hevc",
1636 .ops = &clk_regmap_gate_ops,
1637 .parent_names = (const char *[]){ "vdec_hevc_div" },
1639 .flags = CLK_SET_RATE_PARENT,
1645 static const char * const g12a_vapb_parent_names[] = {
1646 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
1647 "mpll1", "vid_pll", "mpll2", "fclk_div2p5",
1650 static struct clk_regmap g12a_vapb_0_sel = {
1651 .data = &(struct clk_regmap_mux_data){
1652 .offset = HHI_VAPBCLK_CNTL,
1656 .hw.init = &(struct clk_init_data){
1657 .name = "vapb_0_sel",
1658 .ops = &clk_regmap_mux_ops,
1659 .parent_names = g12a_vapb_parent_names,
1660 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
1661 .flags = CLK_SET_RATE_NO_REPARENT,
1665 static struct clk_regmap g12a_vapb_0_div = {
1666 .data = &(struct clk_regmap_div_data){
1667 .offset = HHI_VAPBCLK_CNTL,
1671 .hw.init = &(struct clk_init_data){
1672 .name = "vapb_0_div",
1673 .ops = &clk_regmap_divider_ops,
1674 .parent_names = (const char *[]){ "vapb_0_sel" },
1676 .flags = CLK_SET_RATE_PARENT,
1680 static struct clk_regmap g12a_vapb_0 = {
1681 .data = &(struct clk_regmap_gate_data){
1682 .offset = HHI_VAPBCLK_CNTL,
1685 .hw.init = &(struct clk_init_data) {
1687 .ops = &clk_regmap_gate_ops,
1688 .parent_names = (const char *[]){ "vapb_0_div" },
1690 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1694 static struct clk_regmap g12a_vapb_1_sel = {
1695 .data = &(struct clk_regmap_mux_data){
1696 .offset = HHI_VAPBCLK_CNTL,
1700 .hw.init = &(struct clk_init_data){
1701 .name = "vapb_1_sel",
1702 .ops = &clk_regmap_mux_ops,
1703 .parent_names = g12a_vapb_parent_names,
1704 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
1705 .flags = CLK_SET_RATE_NO_REPARENT,
1709 static struct clk_regmap g12a_vapb_1_div = {
1710 .data = &(struct clk_regmap_div_data){
1711 .offset = HHI_VAPBCLK_CNTL,
1715 .hw.init = &(struct clk_init_data){
1716 .name = "vapb_1_div",
1717 .ops = &clk_regmap_divider_ops,
1718 .parent_names = (const char *[]){ "vapb_1_sel" },
1720 .flags = CLK_SET_RATE_PARENT,
1724 static struct clk_regmap g12a_vapb_1 = {
1725 .data = &(struct clk_regmap_gate_data){
1726 .offset = HHI_VAPBCLK_CNTL,
1729 .hw.init = &(struct clk_init_data) {
1731 .ops = &clk_regmap_gate_ops,
1732 .parent_names = (const char *[]){ "vapb_1_div" },
1734 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1738 static struct clk_regmap g12a_vapb_sel = {
1739 .data = &(struct clk_regmap_mux_data){
1740 .offset = HHI_VAPBCLK_CNTL,
1744 .hw.init = &(struct clk_init_data){
1746 .ops = &clk_regmap_mux_ops,
1748 * bit 31 selects from 2 possible parents:
1751 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1753 .flags = CLK_SET_RATE_NO_REPARENT,
1757 static struct clk_regmap g12a_vapb = {
1758 .data = &(struct clk_regmap_gate_data){
1759 .offset = HHI_VAPBCLK_CNTL,
1762 .hw.init = &(struct clk_init_data) {
1764 .ops = &clk_regmap_gate_ops,
1765 .parent_names = (const char *[]){ "vapb_sel" },
1767 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1773 static struct clk_regmap g12a_vid_pll_div = {
1774 .data = &(struct meson_vid_pll_div_data){
1776 .reg_off = HHI_VID_PLL_CLK_DIV,
1781 .reg_off = HHI_VID_PLL_CLK_DIV,
1786 .hw.init = &(struct clk_init_data) {
1787 .name = "vid_pll_div",
1788 .ops = &meson_vid_pll_div_ro_ops,
1789 .parent_names = (const char *[]){ "hdmi_pll" },
1791 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1795 static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div",
1798 static struct clk_regmap g12a_vid_pll_sel = {
1799 .data = &(struct clk_regmap_mux_data){
1800 .offset = HHI_VID_PLL_CLK_DIV,
1804 .hw.init = &(struct clk_init_data){
1805 .name = "vid_pll_sel",
1806 .ops = &clk_regmap_mux_ops,
1808 * bit 18 selects from 2 possible parents:
1809 * vid_pll_div or hdmi_pll
1811 .parent_names = g12a_vid_pll_parent_names,
1812 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names),
1813 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1817 static struct clk_regmap g12a_vid_pll = {
1818 .data = &(struct clk_regmap_gate_data){
1819 .offset = HHI_VID_PLL_CLK_DIV,
1822 .hw.init = &(struct clk_init_data) {
1824 .ops = &clk_regmap_gate_ops,
1825 .parent_names = (const char *[]){ "vid_pll_sel" },
1827 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1831 static const char * const g12a_vclk_parent_names[] = {
1832 "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4",
1833 "fclk_div5", "fclk_div7"
1836 static struct clk_regmap g12a_vclk_sel = {
1837 .data = &(struct clk_regmap_mux_data){
1838 .offset = HHI_VID_CLK_CNTL,
1842 .hw.init = &(struct clk_init_data){
1844 .ops = &clk_regmap_mux_ops,
1845 .parent_names = g12a_vclk_parent_names,
1846 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
1847 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1851 static struct clk_regmap g12a_vclk2_sel = {
1852 .data = &(struct clk_regmap_mux_data){
1853 .offset = HHI_VIID_CLK_CNTL,
1857 .hw.init = &(struct clk_init_data){
1858 .name = "vclk2_sel",
1859 .ops = &clk_regmap_mux_ops,
1860 .parent_names = g12a_vclk_parent_names,
1861 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
1862 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1866 static struct clk_regmap g12a_vclk_input = {
1867 .data = &(struct clk_regmap_gate_data){
1868 .offset = HHI_VID_CLK_DIV,
1871 .hw.init = &(struct clk_init_data) {
1872 .name = "vclk_input",
1873 .ops = &clk_regmap_gate_ops,
1874 .parent_names = (const char *[]){ "vclk_sel" },
1876 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1880 static struct clk_regmap g12a_vclk2_input = {
1881 .data = &(struct clk_regmap_gate_data){
1882 .offset = HHI_VIID_CLK_DIV,
1885 .hw.init = &(struct clk_init_data) {
1886 .name = "vclk2_input",
1887 .ops = &clk_regmap_gate_ops,
1888 .parent_names = (const char *[]){ "vclk2_sel" },
1890 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1894 static struct clk_regmap g12a_vclk_div = {
1895 .data = &(struct clk_regmap_div_data){
1896 .offset = HHI_VID_CLK_DIV,
1900 .hw.init = &(struct clk_init_data){
1902 .ops = &clk_regmap_divider_ops,
1903 .parent_names = (const char *[]){ "vclk_input" },
1905 .flags = CLK_GET_RATE_NOCACHE,
1909 static struct clk_regmap g12a_vclk2_div = {
1910 .data = &(struct clk_regmap_div_data){
1911 .offset = HHI_VIID_CLK_DIV,
1915 .hw.init = &(struct clk_init_data){
1916 .name = "vclk2_div",
1917 .ops = &clk_regmap_divider_ops,
1918 .parent_names = (const char *[]){ "vclk2_input" },
1920 .flags = CLK_GET_RATE_NOCACHE,
1924 static struct clk_regmap g12a_vclk = {
1925 .data = &(struct clk_regmap_gate_data){
1926 .offset = HHI_VID_CLK_CNTL,
1929 .hw.init = &(struct clk_init_data) {
1931 .ops = &clk_regmap_gate_ops,
1932 .parent_names = (const char *[]){ "vclk_div" },
1934 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1938 static struct clk_regmap g12a_vclk2 = {
1939 .data = &(struct clk_regmap_gate_data){
1940 .offset = HHI_VIID_CLK_CNTL,
1943 .hw.init = &(struct clk_init_data) {
1945 .ops = &clk_regmap_gate_ops,
1946 .parent_names = (const char *[]){ "vclk2_div" },
1948 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1952 static struct clk_regmap g12a_vclk_div1 = {
1953 .data = &(struct clk_regmap_gate_data){
1954 .offset = HHI_VID_CLK_CNTL,
1957 .hw.init = &(struct clk_init_data) {
1958 .name = "vclk_div1",
1959 .ops = &clk_regmap_gate_ops,
1960 .parent_names = (const char *[]){ "vclk" },
1962 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1966 static struct clk_regmap g12a_vclk_div2_en = {
1967 .data = &(struct clk_regmap_gate_data){
1968 .offset = HHI_VID_CLK_CNTL,
1971 .hw.init = &(struct clk_init_data) {
1972 .name = "vclk_div2_en",
1973 .ops = &clk_regmap_gate_ops,
1974 .parent_names = (const char *[]){ "vclk" },
1976 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1980 static struct clk_regmap g12a_vclk_div4_en = {
1981 .data = &(struct clk_regmap_gate_data){
1982 .offset = HHI_VID_CLK_CNTL,
1985 .hw.init = &(struct clk_init_data) {
1986 .name = "vclk_div4_en",
1987 .ops = &clk_regmap_gate_ops,
1988 .parent_names = (const char *[]){ "vclk" },
1990 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1994 static struct clk_regmap g12a_vclk_div6_en = {
1995 .data = &(struct clk_regmap_gate_data){
1996 .offset = HHI_VID_CLK_CNTL,
1999 .hw.init = &(struct clk_init_data) {
2000 .name = "vclk_div6_en",
2001 .ops = &clk_regmap_gate_ops,
2002 .parent_names = (const char *[]){ "vclk" },
2004 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2008 static struct clk_regmap g12a_vclk_div12_en = {
2009 .data = &(struct clk_regmap_gate_data){
2010 .offset = HHI_VID_CLK_CNTL,
2013 .hw.init = &(struct clk_init_data) {
2014 .name = "vclk_div12_en",
2015 .ops = &clk_regmap_gate_ops,
2016 .parent_names = (const char *[]){ "vclk" },
2018 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2022 static struct clk_regmap g12a_vclk2_div1 = {
2023 .data = &(struct clk_regmap_gate_data){
2024 .offset = HHI_VIID_CLK_CNTL,
2027 .hw.init = &(struct clk_init_data) {
2028 .name = "vclk2_div1",
2029 .ops = &clk_regmap_gate_ops,
2030 .parent_names = (const char *[]){ "vclk2" },
2032 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2036 static struct clk_regmap g12a_vclk2_div2_en = {
2037 .data = &(struct clk_regmap_gate_data){
2038 .offset = HHI_VIID_CLK_CNTL,
2041 .hw.init = &(struct clk_init_data) {
2042 .name = "vclk2_div2_en",
2043 .ops = &clk_regmap_gate_ops,
2044 .parent_names = (const char *[]){ "vclk2" },
2046 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2050 static struct clk_regmap g12a_vclk2_div4_en = {
2051 .data = &(struct clk_regmap_gate_data){
2052 .offset = HHI_VIID_CLK_CNTL,
2055 .hw.init = &(struct clk_init_data) {
2056 .name = "vclk2_div4_en",
2057 .ops = &clk_regmap_gate_ops,
2058 .parent_names = (const char *[]){ "vclk2" },
2060 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2064 static struct clk_regmap g12a_vclk2_div6_en = {
2065 .data = &(struct clk_regmap_gate_data){
2066 .offset = HHI_VIID_CLK_CNTL,
2069 .hw.init = &(struct clk_init_data) {
2070 .name = "vclk2_div6_en",
2071 .ops = &clk_regmap_gate_ops,
2072 .parent_names = (const char *[]){ "vclk2" },
2074 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2078 static struct clk_regmap g12a_vclk2_div12_en = {
2079 .data = &(struct clk_regmap_gate_data){
2080 .offset = HHI_VIID_CLK_CNTL,
2083 .hw.init = &(struct clk_init_data) {
2084 .name = "vclk2_div12_en",
2085 .ops = &clk_regmap_gate_ops,
2086 .parent_names = (const char *[]){ "vclk2" },
2088 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2092 static struct clk_fixed_factor g12a_vclk_div2 = {
2095 .hw.init = &(struct clk_init_data){
2096 .name = "vclk_div2",
2097 .ops = &clk_fixed_factor_ops,
2098 .parent_names = (const char *[]){ "vclk_div2_en" },
2103 static struct clk_fixed_factor g12a_vclk_div4 = {
2106 .hw.init = &(struct clk_init_data){
2107 .name = "vclk_div4",
2108 .ops = &clk_fixed_factor_ops,
2109 .parent_names = (const char *[]){ "vclk_div4_en" },
2114 static struct clk_fixed_factor g12a_vclk_div6 = {
2117 .hw.init = &(struct clk_init_data){
2118 .name = "vclk_div6",
2119 .ops = &clk_fixed_factor_ops,
2120 .parent_names = (const char *[]){ "vclk_div6_en" },
2125 static struct clk_fixed_factor g12a_vclk_div12 = {
2128 .hw.init = &(struct clk_init_data){
2129 .name = "vclk_div12",
2130 .ops = &clk_fixed_factor_ops,
2131 .parent_names = (const char *[]){ "vclk_div12_en" },
2136 static struct clk_fixed_factor g12a_vclk2_div2 = {
2139 .hw.init = &(struct clk_init_data){
2140 .name = "vclk2_div2",
2141 .ops = &clk_fixed_factor_ops,
2142 .parent_names = (const char *[]){ "vclk2_div2_en" },
2147 static struct clk_fixed_factor g12a_vclk2_div4 = {
2150 .hw.init = &(struct clk_init_data){
2151 .name = "vclk2_div4",
2152 .ops = &clk_fixed_factor_ops,
2153 .parent_names = (const char *[]){ "vclk2_div4_en" },
2158 static struct clk_fixed_factor g12a_vclk2_div6 = {
2161 .hw.init = &(struct clk_init_data){
2162 .name = "vclk2_div6",
2163 .ops = &clk_fixed_factor_ops,
2164 .parent_names = (const char *[]){ "vclk2_div6_en" },
2169 static struct clk_fixed_factor g12a_vclk2_div12 = {
2172 .hw.init = &(struct clk_init_data){
2173 .name = "vclk2_div12",
2174 .ops = &clk_fixed_factor_ops,
2175 .parent_names = (const char *[]){ "vclk2_div12_en" },
2180 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2181 static const char * const g12a_cts_parent_names[] = {
2182 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2183 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2184 "vclk2_div6", "vclk2_div12"
2187 static struct clk_regmap g12a_cts_enci_sel = {
2188 .data = &(struct clk_regmap_mux_data){
2189 .offset = HHI_VID_CLK_DIV,
2192 .table = mux_table_cts_sel,
2194 .hw.init = &(struct clk_init_data){
2195 .name = "cts_enci_sel",
2196 .ops = &clk_regmap_mux_ops,
2197 .parent_names = g12a_cts_parent_names,
2198 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2199 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2203 static struct clk_regmap g12a_cts_encp_sel = {
2204 .data = &(struct clk_regmap_mux_data){
2205 .offset = HHI_VID_CLK_DIV,
2208 .table = mux_table_cts_sel,
2210 .hw.init = &(struct clk_init_data){
2211 .name = "cts_encp_sel",
2212 .ops = &clk_regmap_mux_ops,
2213 .parent_names = g12a_cts_parent_names,
2214 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2215 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2219 static struct clk_regmap g12a_cts_vdac_sel = {
2220 .data = &(struct clk_regmap_mux_data){
2221 .offset = HHI_VIID_CLK_DIV,
2224 .table = mux_table_cts_sel,
2226 .hw.init = &(struct clk_init_data){
2227 .name = "cts_vdac_sel",
2228 .ops = &clk_regmap_mux_ops,
2229 .parent_names = g12a_cts_parent_names,
2230 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2231 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2235 /* TOFIX: add support for cts_tcon */
2236 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2237 static const char * const g12a_cts_hdmi_tx_parent_names[] = {
2238 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2239 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2240 "vclk2_div6", "vclk2_div12"
2243 static struct clk_regmap g12a_hdmi_tx_sel = {
2244 .data = &(struct clk_regmap_mux_data){
2245 .offset = HHI_HDMI_CLK_CNTL,
2248 .table = mux_table_hdmi_tx_sel,
2250 .hw.init = &(struct clk_init_data){
2251 .name = "hdmi_tx_sel",
2252 .ops = &clk_regmap_mux_ops,
2253 .parent_names = g12a_cts_hdmi_tx_parent_names,
2254 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names),
2255 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2259 static struct clk_regmap g12a_cts_enci = {
2260 .data = &(struct clk_regmap_gate_data){
2261 .offset = HHI_VID_CLK_CNTL2,
2264 .hw.init = &(struct clk_init_data) {
2266 .ops = &clk_regmap_gate_ops,
2267 .parent_names = (const char *[]){ "cts_enci_sel" },
2269 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2273 static struct clk_regmap g12a_cts_encp = {
2274 .data = &(struct clk_regmap_gate_data){
2275 .offset = HHI_VID_CLK_CNTL2,
2278 .hw.init = &(struct clk_init_data) {
2280 .ops = &clk_regmap_gate_ops,
2281 .parent_names = (const char *[]){ "cts_encp_sel" },
2283 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2287 static struct clk_regmap g12a_cts_vdac = {
2288 .data = &(struct clk_regmap_gate_data){
2289 .offset = HHI_VID_CLK_CNTL2,
2292 .hw.init = &(struct clk_init_data) {
2294 .ops = &clk_regmap_gate_ops,
2295 .parent_names = (const char *[]){ "cts_vdac_sel" },
2297 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2301 static struct clk_regmap g12a_hdmi_tx = {
2302 .data = &(struct clk_regmap_gate_data){
2303 .offset = HHI_VID_CLK_CNTL2,
2306 .hw.init = &(struct clk_init_data) {
2308 .ops = &clk_regmap_gate_ops,
2309 .parent_names = (const char *[]){ "hdmi_tx_sel" },
2311 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2317 static const char * const g12a_hdmi_parent_names[] = {
2318 IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
2321 static struct clk_regmap g12a_hdmi_sel = {
2322 .data = &(struct clk_regmap_mux_data){
2323 .offset = HHI_HDMI_CLK_CNTL,
2326 .flags = CLK_MUX_ROUND_CLOSEST,
2328 .hw.init = &(struct clk_init_data){
2330 .ops = &clk_regmap_mux_ops,
2331 .parent_names = g12a_hdmi_parent_names,
2332 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names),
2333 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2337 static struct clk_regmap g12a_hdmi_div = {
2338 .data = &(struct clk_regmap_div_data){
2339 .offset = HHI_HDMI_CLK_CNTL,
2343 .hw.init = &(struct clk_init_data){
2345 .ops = &clk_regmap_divider_ops,
2346 .parent_names = (const char *[]){ "hdmi_sel" },
2348 .flags = CLK_GET_RATE_NOCACHE,
2352 static struct clk_regmap g12a_hdmi = {
2353 .data = &(struct clk_regmap_gate_data){
2354 .offset = HHI_HDMI_CLK_CNTL,
2357 .hw.init = &(struct clk_init_data) {
2359 .ops = &clk_regmap_gate_ops,
2360 .parent_names = (const char *[]){ "hdmi_div" },
2362 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2367 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
2368 * muxed by a glitch-free switch.
2371 static const char * const g12a_mali_0_1_parent_names[] = {
2372 IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5",
2373 "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"
2376 static struct clk_regmap g12a_mali_0_sel = {
2377 .data = &(struct clk_regmap_mux_data){
2378 .offset = HHI_MALI_CLK_CNTL,
2382 .hw.init = &(struct clk_init_data){
2383 .name = "mali_0_sel",
2384 .ops = &clk_regmap_mux_ops,
2385 .parent_names = g12a_mali_0_1_parent_names,
2387 .flags = CLK_SET_RATE_NO_REPARENT,
2391 static struct clk_regmap g12a_mali_0_div = {
2392 .data = &(struct clk_regmap_div_data){
2393 .offset = HHI_MALI_CLK_CNTL,
2397 .hw.init = &(struct clk_init_data){
2398 .name = "mali_0_div",
2399 .ops = &clk_regmap_divider_ops,
2400 .parent_names = (const char *[]){ "mali_0_sel" },
2402 .flags = CLK_SET_RATE_NO_REPARENT,
2406 static struct clk_regmap g12a_mali_0 = {
2407 .data = &(struct clk_regmap_gate_data){
2408 .offset = HHI_MALI_CLK_CNTL,
2411 .hw.init = &(struct clk_init_data){
2413 .ops = &clk_regmap_gate_ops,
2414 .parent_names = (const char *[]){ "mali_0_div" },
2416 .flags = CLK_SET_RATE_PARENT,
2420 static struct clk_regmap g12a_mali_1_sel = {
2421 .data = &(struct clk_regmap_mux_data){
2422 .offset = HHI_MALI_CLK_CNTL,
2426 .hw.init = &(struct clk_init_data){
2427 .name = "mali_1_sel",
2428 .ops = &clk_regmap_mux_ops,
2429 .parent_names = g12a_mali_0_1_parent_names,
2431 .flags = CLK_SET_RATE_NO_REPARENT,
2435 static struct clk_regmap g12a_mali_1_div = {
2436 .data = &(struct clk_regmap_div_data){
2437 .offset = HHI_MALI_CLK_CNTL,
2441 .hw.init = &(struct clk_init_data){
2442 .name = "mali_1_div",
2443 .ops = &clk_regmap_divider_ops,
2444 .parent_names = (const char *[]){ "mali_1_sel" },
2446 .flags = CLK_SET_RATE_NO_REPARENT,
2450 static struct clk_regmap g12a_mali_1 = {
2451 .data = &(struct clk_regmap_gate_data){
2452 .offset = HHI_MALI_CLK_CNTL,
2455 .hw.init = &(struct clk_init_data){
2457 .ops = &clk_regmap_gate_ops,
2458 .parent_names = (const char *[]){ "mali_1_div" },
2460 .flags = CLK_SET_RATE_PARENT,
2464 static const char * const g12a_mali_parent_names[] = {
2468 static struct clk_regmap g12a_mali = {
2469 .data = &(struct clk_regmap_mux_data){
2470 .offset = HHI_MALI_CLK_CNTL,
2474 .hw.init = &(struct clk_init_data){
2476 .ops = &clk_regmap_mux_ops,
2477 .parent_names = g12a_mali_parent_names,
2479 .flags = CLK_SET_RATE_NO_REPARENT,
2483 /* Everything Else (EE) domain gates */
2484 static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
2485 static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
2486 static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2);
2487 static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
2488 static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);
2489 static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);
2490 static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);
2491 static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);
2492 static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
2493 static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);
2494 static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);
2495 static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);
2496 static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);
2497 static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);
2498 static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
2499 static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);
2500 static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);
2501 static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);
2502 static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4);
2503 static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25);
2504 static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26);
2505 static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28);
2507 static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0);
2508 static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3);
2509 static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4);
2510 static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11);
2511 static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13);
2512 static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16);
2513 static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20);
2514 static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23);
2515 static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24);
2516 static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25);
2517 static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26);
2518 static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27);
2519 static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29);
2521 static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2522 static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2523 static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
2524 static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
2525 static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
2526 static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
2527 static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
2528 static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
2529 static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
2530 static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
2532 static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
2533 static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2);
2534 static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2535 static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2536 static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5);
2537 static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6);
2538 static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7);
2539 static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8);
2540 static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9);
2541 static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10);
2542 static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14);
2543 static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16);
2544 static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20);
2545 static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21);
2546 static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22);
2547 static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
2548 static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
2549 static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
2550 static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
2552 static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0);
2553 static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1);
2554 static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2);
2555 static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
2556 static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
2558 /* Array of all clocks provided by this provider */
2559 static struct clk_hw_onecell_data g12a_hw_onecell_data = {
2561 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
2562 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
2563 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
2564 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
2565 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
2566 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
2567 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
2568 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
2569 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
2570 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
2571 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
2572 [CLKID_CLK81] = &g12a_clk81.hw,
2573 [CLKID_MPLL0] = &g12a_mpll0.hw,
2574 [CLKID_MPLL1] = &g12a_mpll1.hw,
2575 [CLKID_MPLL2] = &g12a_mpll2.hw,
2576 [CLKID_MPLL3] = &g12a_mpll3.hw,
2577 [CLKID_DDR] = &g12a_ddr.hw,
2578 [CLKID_DOS] = &g12a_dos.hw,
2579 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
2580 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
2581 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
2582 [CLKID_ISA] = &g12a_isa.hw,
2583 [CLKID_PL301] = &g12a_pl301.hw,
2584 [CLKID_PERIPHS] = &g12a_periphs.hw,
2585 [CLKID_SPICC0] = &g12a_spicc_0.hw,
2586 [CLKID_I2C] = &g12a_i2c.hw,
2587 [CLKID_SANA] = &g12a_sana.hw,
2588 [CLKID_SD] = &g12a_sd.hw,
2589 [CLKID_RNG0] = &g12a_rng0.hw,
2590 [CLKID_UART0] = &g12a_uart0.hw,
2591 [CLKID_SPICC1] = &g12a_spicc_1.hw,
2592 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
2593 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
2594 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
2595 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
2596 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
2597 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
2598 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
2599 [CLKID_AUDIO] = &g12a_audio.hw,
2600 [CLKID_ETH] = &g12a_eth_core.hw,
2601 [CLKID_DEMUX] = &g12a_demux.hw,
2602 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
2603 [CLKID_ADC] = &g12a_adc.hw,
2604 [CLKID_UART1] = &g12a_uart1.hw,
2605 [CLKID_G2D] = &g12a_g2d.hw,
2606 [CLKID_RESET] = &g12a_reset.hw,
2607 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
2608 [CLKID_PARSER] = &g12a_parser.hw,
2609 [CLKID_USB] = &g12a_usb_general.hw,
2610 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
2611 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
2612 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
2613 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
2614 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
2615 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
2616 [CLKID_BT656] = &g12a_bt656.hw,
2617 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
2618 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
2619 [CLKID_UART2] = &g12a_uart2.hw,
2620 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
2621 [CLKID_GIC] = &g12a_gic.hw,
2622 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
2623 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
2624 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
2625 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
2626 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
2627 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
2628 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
2629 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
2630 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
2631 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
2632 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
2633 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
2634 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
2635 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
2636 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
2637 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
2638 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
2639 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
2640 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
2641 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
2642 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
2643 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
2644 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
2645 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
2646 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
2647 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
2648 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
2649 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
2650 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
2651 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
2652 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
2653 [CLKID_IEC958] = &g12a_iec958_gate.hw,
2654 [CLKID_ENC480P] = &g12a_enc480p.hw,
2655 [CLKID_RNG1] = &g12a_rng1.hw,
2656 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
2657 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
2658 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
2659 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
2660 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
2661 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
2662 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
2663 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
2664 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
2665 [CLKID_DMA] = &g12a_dma.hw,
2666 [CLKID_EFUSE] = &g12a_efuse.hw,
2667 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
2668 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
2669 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
2670 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
2671 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
2672 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
2673 [CLKID_VPU_0] = &g12a_vpu_0.hw,
2674 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
2675 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
2676 [CLKID_VPU_1] = &g12a_vpu_1.hw,
2677 [CLKID_VPU] = &g12a_vpu.hw,
2678 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
2679 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
2680 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
2681 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
2682 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
2683 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
2684 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
2685 [CLKID_VAPB] = &g12a_vapb.hw,
2686 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
2687 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
2688 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
2689 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
2690 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
2691 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
2692 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
2693 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
2694 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
2695 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
2696 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
2697 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
2698 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
2699 [CLKID_VCLK] = &g12a_vclk.hw,
2700 [CLKID_VCLK2] = &g12a_vclk2.hw,
2701 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
2702 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
2703 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
2704 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
2705 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
2706 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
2707 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
2708 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
2709 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
2710 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
2711 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
2712 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
2713 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
2714 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
2715 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
2716 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
2717 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
2718 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
2719 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
2720 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
2721 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
2722 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
2723 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
2724 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
2725 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
2726 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
2727 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
2728 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
2729 [CLKID_HDMI] = &g12a_hdmi.hw,
2730 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
2731 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
2732 [CLKID_MALI_0] = &g12a_mali_0.hw,
2733 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
2734 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
2735 [CLKID_MALI_1] = &g12a_mali_1.hw,
2736 [CLKID_MALI] = &g12a_mali.hw,
2737 [CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
2738 [CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
2739 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
2740 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
2741 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
2742 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
2743 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
2744 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
2745 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
2746 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
2747 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
2748 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
2749 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
2750 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
2751 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
2752 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
2753 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
2754 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
2755 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
2756 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
2757 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
2758 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
2759 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
2760 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
2761 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
2762 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
2763 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
2764 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
2765 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
2766 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
2767 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
2768 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
2769 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
2770 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
2771 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
2777 /* Convenience table to populate regmap in .probe */
2778 static struct clk_regmap *const g12a_clk_regmaps[] = {
2783 &g12a_mipi_dsi_host,
2824 &g12a_sd_emmc_a_clk0,
2825 &g12a_sd_emmc_b_clk0,
2826 &g12a_sd_emmc_c_clk0,
2828 &g12a_sd_emmc_a_clk0_div,
2829 &g12a_sd_emmc_b_clk0_div,
2830 &g12a_sd_emmc_c_clk0_div,
2832 &g12a_sd_emmc_a_clk0_sel,
2833 &g12a_sd_emmc_b_clk0_sel,
2834 &g12a_sd_emmc_c_clk0_sel,
2863 &g12a_vclk2_venclmmc,
2866 &g12a_fixed_pll_dco,
2915 &g12a_vclk_div12_en,
2917 &g12a_vclk2_div2_en,
2918 &g12a_vclk2_div4_en,
2919 &g12a_vclk2_div6_en,
2920 &g12a_vclk2_div12_en,
2940 &g12a_sys_pll_div16_en,
2941 &g12a_cpu_clk_premux0,
2942 &g12a_cpu_clk_mux0_div,
2943 &g12a_cpu_clk_postmux0,
2944 &g12a_cpu_clk_premux1,
2945 &g12a_cpu_clk_mux1_div,
2946 &g12a_cpu_clk_postmux1,
2949 &g12a_cpu_clk_div16_en,
2950 &g12a_cpu_clk_apb_div,
2952 &g12a_cpu_clk_atb_div,
2954 &g12a_cpu_clk_axi_div,
2956 &g12a_cpu_clk_trace_div,
2957 &g12a_cpu_clk_trace,
2963 &g12a_vdec_hevc_sel,
2964 &g12a_vdec_hevc_div,
2966 &g12a_vdec_hevcf_sel,
2967 &g12a_vdec_hevcf_div,
2971 static const struct meson_eeclkc_data g12a_clkc_data = {
2972 .regmap_clks = g12a_clk_regmaps,
2973 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
2974 .hw_onecell_data = &g12a_hw_onecell_data
2977 static const struct of_device_id clkc_match_table[] = {
2978 { .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data },
2982 static struct platform_driver g12a_driver = {
2983 .probe = meson_eeclkc_probe,
2985 .name = "g12a-clkc",
2986 .of_match_table = clkc_match_table,
2990 builtin_platform_driver(g12a_driver);