2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/of_address.h>
18 #include <linux/slab.h>
19 #include <linux/clkdev.h>
20 #include <linux/delay.h>
27 #define CON0_BASE_EN BIT(0)
28 #define CON0_PWR_ON BIT(0)
29 #define CON0_ISO_EN BIT(1)
30 #define PCW_CHG_MASK BIT(31)
32 #define AUDPLL_TUNER_EN BIT(31)
34 #define POSTDIV_MASK 0x7
36 /* default 7 bits integer, can be overridden with pcwibits. */
37 #define INTEGER_BITS 7
40 * MediaTek PLLs are configured through their pcw value. The pcw value describes
41 * a divider in the PLL feedback loop which consists of 7 bits for the integer
42 * part and the remaining bits (if present) for the fractional part. Also they
43 * have a 3 bit power-of-two post divider.
48 void __iomem *base_addr;
49 void __iomem *pd_addr;
50 void __iomem *pwr_addr;
51 void __iomem *tuner_addr;
52 void __iomem *tuner_en_addr;
53 void __iomem *pcw_addr;
54 void __iomem *pcw_chg_addr;
55 const struct mtk_pll_data *data;
58 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
60 return container_of(hw, struct mtk_clk_pll, hw);
63 static int mtk_pll_is_prepared(struct clk_hw *hw)
65 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
67 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
70 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
73 int pcwbits = pll->data->pcwbits;
79 /* The fractional part of the PLL divider. */
80 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
82 pcwfbits = pcwbits - ibits;
86 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
94 return ((unsigned long)vco + postdiv - 1) / postdiv;
97 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
101 if (pll->tuner_en_addr) {
102 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
103 writel(r, pll->tuner_en_addr);
104 } else if (pll->tuner_addr) {
105 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
106 writel(r, pll->tuner_addr);
110 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
114 if (pll->tuner_en_addr) {
115 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
116 writel(r, pll->tuner_en_addr);
117 } else if (pll->tuner_addr) {
118 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
119 writel(r, pll->tuner_addr);
123 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
129 __mtk_pll_tuner_disable(pll);
132 val = readl(pll->pd_addr);
133 val &= ~(POSTDIV_MASK << pll->data->pd_shift);
134 val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
136 /* postdiv and pcw need to set at the same time if on same register */
137 if (pll->pd_addr != pll->pcw_addr) {
138 writel(val, pll->pd_addr);
139 val = readl(pll->pcw_addr);
143 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
144 pll->data->pcw_shift);
145 val |= pcw << pll->data->pcw_shift;
146 writel(val, pll->pcw_addr);
147 chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
148 writel(chg, pll->pcw_chg_addr);
150 writel(val + 1, pll->tuner_addr);
152 /* restore tuner_en */
153 __mtk_pll_tuner_enable(pll);
159 * mtk_pll_calc_values - calculate good values for a given input frequency.
161 * @pcw: The pcw value (output)
162 * @postdiv: The post divider (output)
163 * @freq: The desired target frequency
164 * @fin: The input frequency
167 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
170 unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
171 const struct mtk_pll_div_table *div_table = pll->data->div_table;
176 if (freq > pll->data->fmax)
177 freq = pll->data->fmax;
180 if (freq > div_table[0].freq)
181 freq = div_table[0].freq;
183 for (val = 0; div_table[val + 1].freq != 0; val++) {
184 if (freq > div_table[val + 1].freq)
189 for (val = 0; val < 5; val++) {
191 if ((u64)freq * *postdiv >= fmin)
196 /* _pcw = freq * postdiv / fin * 2^pcwfbits */
197 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
198 _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
204 static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
205 unsigned long parent_rate)
207 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
211 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
212 mtk_pll_set_rate_regs(pll, pcw, postdiv);
217 static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
218 unsigned long parent_rate)
220 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
224 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
225 postdiv = 1 << postdiv;
227 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
228 pcw &= GENMASK(pll->data->pcwbits - 1, 0);
230 return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
233 static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
234 unsigned long *prate)
236 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
240 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
242 return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
245 static int mtk_pll_prepare(struct clk_hw *hw)
247 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
250 r = readl(pll->pwr_addr) | CON0_PWR_ON;
251 writel(r, pll->pwr_addr);
254 r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
255 writel(r, pll->pwr_addr);
258 r = readl(pll->base_addr + REG_CON0);
259 r |= pll->data->en_mask;
260 writel(r, pll->base_addr + REG_CON0);
262 __mtk_pll_tuner_enable(pll);
266 if (pll->data->flags & HAVE_RST_BAR) {
267 r = readl(pll->base_addr + REG_CON0);
268 r |= pll->data->rst_bar_mask;
269 writel(r, pll->base_addr + REG_CON0);
275 static void mtk_pll_unprepare(struct clk_hw *hw)
277 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
280 if (pll->data->flags & HAVE_RST_BAR) {
281 r = readl(pll->base_addr + REG_CON0);
282 r &= ~pll->data->rst_bar_mask;
283 writel(r, pll->base_addr + REG_CON0);
286 __mtk_pll_tuner_disable(pll);
288 r = readl(pll->base_addr + REG_CON0);
290 writel(r, pll->base_addr + REG_CON0);
292 r = readl(pll->pwr_addr) | CON0_ISO_EN;
293 writel(r, pll->pwr_addr);
295 r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
296 writel(r, pll->pwr_addr);
299 static const struct clk_ops mtk_pll_ops = {
300 .is_prepared = mtk_pll_is_prepared,
301 .prepare = mtk_pll_prepare,
302 .unprepare = mtk_pll_unprepare,
303 .recalc_rate = mtk_pll_recalc_rate,
304 .round_rate = mtk_pll_round_rate,
305 .set_rate = mtk_pll_set_rate,
308 static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
311 struct mtk_clk_pll *pll;
312 struct clk_init_data init = {};
314 const char *parent_name = "clk26m";
316 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
318 return ERR_PTR(-ENOMEM);
320 pll->base_addr = base + data->reg;
321 pll->pwr_addr = base + data->pwr_reg;
322 pll->pd_addr = base + data->pd_reg;
323 pll->pcw_addr = base + data->pcw_reg;
324 if (data->pcw_chg_reg)
325 pll->pcw_chg_addr = base + data->pcw_chg_reg;
327 pll->pcw_chg_addr = pll->base_addr + REG_CON1;
329 pll->tuner_addr = base + data->tuner_reg;
330 if (data->tuner_en_reg)
331 pll->tuner_en_addr = base + data->tuner_en_reg;
332 pll->hw.init = &init;
335 init.name = data->name;
336 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
337 init.ops = &mtk_pll_ops;
338 if (data->parent_name)
339 init.parent_names = &data->parent_name;
341 init.parent_names = &parent_name;
342 init.num_parents = 1;
344 clk = clk_register(NULL, &pll->hw);
352 void mtk_clk_register_plls(struct device_node *node,
353 const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
359 base = of_iomap(node, 0);
361 pr_err("%s(): ioremap failed\n", __func__);
365 for (i = 0; i < num_plls; i++) {
366 const struct mtk_pll_data *pll = &plls[i];
368 clk = mtk_clk_register_pll(pll, base);
371 pr_err("Failed to register clk %s: %ld\n",
372 pll->name, PTR_ERR(clk));
376 clk_data->clks[pll->id] = clk;