2 * arch/xtensa/kernel/coprocessor.S
4 * Xtensa processor configuration-specific table of coprocessor and
5 * other custom register layout information.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 * Copyright (C) 2003 - 2007 Tensilica Inc.
15 #include <linux/linkage.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/processor.h>
18 #include <asm/coprocessor.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm-uaccess.h>
21 #include <asm/unistd.h>
22 #include <asm/ptrace.h>
23 #include <asm/current.h>
24 #include <asm/pgtable.h>
26 #include <asm/signal.h>
27 #include <asm/tlbflush.h>
29 #if XTENSA_HAVE_COPROCESSORS
32 * Macros for lazy context switch.
35 #define SAVE_CP_REGS(x) \
36 .if XTENSA_HAVE_COPROCESSOR(x); \
38 .Lsave_cp_regs_cp##x: \
39 xchal_cp##x##_store a2 a4 a5 a6 a7; \
43 #define SAVE_CP_REGS_TAB(x) \
44 .if XTENSA_HAVE_COPROCESSOR(x); \
45 .long .Lsave_cp_regs_cp##x; \
49 .long THREAD_XTREGS_CP##x
52 #define LOAD_CP_REGS(x) \
53 .if XTENSA_HAVE_COPROCESSOR(x); \
55 .Lload_cp_regs_cp##x: \
56 xchal_cp##x##_load a2 a4 a5 a6 a7; \
60 #define LOAD_CP_REGS_TAB(x) \
61 .if XTENSA_HAVE_COPROCESSOR(x); \
62 .long .Lload_cp_regs_cp##x; \
66 .long THREAD_XTREGS_CP##x
86 .section ".rodata", "a"
88 .Lsave_cp_regs_jump_table:
98 .Lload_cp_regs_jump_table:
111 * coprocessor_flush(struct thread_info*, index)
114 * Save coprocessor registers for coprocessor 'index'.
115 * The register values are saved to or loaded from the coprocessor area
116 * inside the task_info structure.
118 * Note that this function doesn't update the coprocessor_owner information!
122 ENTRY(coprocessor_flush)
124 /* reserve 4 bytes on stack to save a0 */
128 movi a0, .Lsave_cp_regs_jump_table
139 ENDPROC(coprocessor_flush)
144 * a0: trashed, original value saved on stack (PT_AREG0)
146 * a2: new stack pointer, original in DEPC
148 * depc: a2, original value saved on stack (PT_DEPC)
149 * excsave_1: dispatch table
151 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
152 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
155 ENTRY(fast_coprocessor_double)
158 call0 unrecoverable_exception
160 ENDPROC(fast_coprocessor_double)
162 ENTRY(fast_coprocessor)
164 /* Save remaining registers a1-a3 and SAR */
166 s32i a3, a2, PT_AREG3
168 s32i a1, a2, PT_AREG1
172 s32i a2, a1, PT_AREG2
175 * The hal macros require up to 4 temporary registers. We use a3..a6.
178 s32i a4, a1, PT_AREG4
179 s32i a5, a1, PT_AREG5
180 s32i a6, a1, PT_AREG6
182 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
185 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
187 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
189 ssl a3 # SAR: 32 - coprocessor_number
197 /* Retrieve previous owner. (a3 still holds CP number) */
199 movi a0, coprocessor_owner # list of owners
200 addx4 a0, a3, a0 # entry for CP
203 beqz a4, 1f # skip 'save' if no previous owner
205 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */
207 l32i a5, a4, THREAD_CPENABLE
208 xor a5, a5, a2 # (1 << cp-id) still in a2
209 s32i a5, a4, THREAD_CPENABLE
212 * Get context save area and 'call' save routine.
213 * (a4 still holds previous owner (thread_info), a3 CP number)
216 movi a5, .Lsave_cp_regs_jump_table
217 movi a0, 2f # a0: 'return' address
218 addx8 a3, a3, a5 # a3: coprocessor number
219 l32i a2, a3, 4 # a2: xtregs offset
220 l32i a3, a3, 0 # a3: jump address
224 /* Note that only a0 and a1 were preserved. */
227 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
228 movi a0, coprocessor_owner
231 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */
233 1: GET_THREAD_INFO (a4, a1)
236 /* Get context save area and 'call' load routine. */
238 movi a5, .Lload_cp_regs_jump_table
241 l32i a2, a3, 4 # a2: xtregs offset
242 l32i a3, a3, 0 # a3: jump address
246 /* Restore all registers and return from exception handler. */
248 1: l32i a6, a1, PT_AREG6
249 l32i a5, a1, PT_AREG5
250 l32i a4, a1, PT_AREG4
253 l32i a3, a1, PT_AREG3
254 l32i a2, a1, PT_AREG2
256 l32i a0, a1, PT_AREG0
257 l32i a1, a1, PT_AREG1
261 ENDPROC(fast_coprocessor)
265 ENTRY(coprocessor_owner)
267 .fill XCHAL_CP_MAX, 4, 0
269 END(coprocessor_owner)
271 #endif /* XTENSA_HAVE_COPROCESSORS */